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13J21 Switch Operations for Central Function and Arbiter Control ........................22
14Switch Operations for Synchronous or Asynchronous Clock Control .................22
iv21555 PCI-to-PCI Bridge Ev aluation Board User’s Guide
Introduction1
This User’s Guide describes the 21555 PCI-to -PCI non transpar ent Bridge Evalu ation Board which
is referred to as the DE1B55503.
1.1Overview
The DE1B55503 is a PCI expansion board that is used to evaluate the o peration of the 21 555 when
it is used as a gateway to an intelligent subsystem. The subsystem can use a variety of PCI devices
and local processors. The DE1B55503 can be used to:
• Develop initialization code to configure the 21555 and associated logic and devices on the
local PCI bus as an intelligent controller.
• Evaluate the operation of the 21555 with a variety of PCI devices configured in an intelligent
subsystem.
• Build and evaluate a system using synchronous and asynchronous clocking.
• Test features:
— Intelligent Input/Output (I2O) transactions.
— Power management features.
— Vital Product Data (VPD) support.
1.2Features
The DE1B55503:
• Complies fully with the protocol and electrical standards of the PCI Local Bus Specification,
Revision 2.3.
• Includes a 21555 “nontransparent” PCI-to-PCI Bridge that provides bridging between two
processor domains.
• Includes a host PCI interface that plugs into any 5V PCI option card slot.
• Provides three local bus 5V PCI bus option card slots. Slot 1 (see Figure 1 on page 6) may be
Figure 1 on page6 shows the major components on the DE1B55503.
Figure 1. Major Components
2
1
OPTIONAL
SLOT
Parallel
ROM
Initialization
Switches
1.3.1Connectors
J8
J21
J20
J9
JTAG
Connector
L2
L1+
E9
E8
E7
1 2 3 4 5
1 2 3 4 5
1 2 3 4 5
SLOT 2
SLOT 1
Y1
E4
OPTIONAL SLOT
J4J6J2
E3
E2
21555
Clock Buffer
E5
J1
Serial
ROM
J7
J101
J102
J5
E1
PCI option and slot
PCI option and PICMG
slot
Mictor Connectors for
logic analyzers and
oscilloscopes
A8408-01
• J1 is the 10-pin JTAG connector. See Table A-5 on page 26.
• J7 and J101 (slot 2 and slot 1) are local (secondary bus) PCI option slots.
— J101 (slot 1) can be used for a local processor with the insertion of a PCI Indu strial
Computer Manufacturers Group
(PICMG) Single Board Computer. It is the PCI portion
of the PCI-ISA card edge connector. See Section 1.7 and Section 1.9.
• J102 (secondary bus) is the optional and connector-less slot. The optional slot is for a third
64-bit PCI connector. The through-holes are p rov id ed fo r ins talla ti on o f a local bus conn ect or.
The default build for this board is for two option cards on the local bus. 66MHz operation is
limited to two (2) loads on the PCI bus. All connectors are 64-bit.
• The J2 and J4 Mictor* (scope pod) connectors provide test points for the all the 64-bit S_AD
signals.
• The J5 and J6 Mictor connectors are for other PCI control signals, such as C/BE, REQ, and
GNT. J6 provides test points for parallel ROM data and address lines.
621555 PCI-to-PCI Bridge Ev aluation Board User’s Guide
Note:See Table A-2 on page 24 for Mictor pinouts.
1.3.2Switches and Jumper
The DE1B55503 uses a combination of DIP switch, stake-pin and zero ohm resistor jumpers to
control the various configuration options. See Section 1.4, Section 1.5, and Section 1.6 for
information.
• J8 is a single stake pin jumper. See Section 1.5 for information.
• J9, J20, and J21 are five-sw itch switch pack s. The du al-pole switch es are labeled S W1 through
SW5. They control the options at power up such as the d irection of the REQ# and GNT# lines,
the on-board parallel ROM functions, and the enabling of the asynchronous clock options for
the local bus. See Section 1.4 for informat ion.
• Figure 3 on page 10 identifies the location of each configuration jumper.
1.3.3Devices
• E1 is the voltage regulator that produces the 3.3 and 5 V clamping signal. See Section 1.6.2.
• E2 is the 21555 PCI-to-PCI Bridge.
Introduction
• E3 is the clock buffer.
• E4 is the serial ROM (SROM).
• Y1 is a 33.333 MHz crystal oscillator that can be used for an independent local clock signal.
• E5 is the Parallel ROM. This device is nonvolatile EEPROM. See Section 2.3.2,
“Programming the Flash ROM” on page 18.
• E7, E8, and E9 are address latches.
• E6 (not shown) is the empty socket for attaching a ROM emulator.
• L1 is a LED that indicates the status of the LOO bit (LED On or Off bit) which is switched
through software. This LED can light if jumper J8 is installed.
• L2 is a LED that indicates DE1B55503 5Vdc power status.
Figure 2 shows the th ree initialization switch packs, and Table 1 on page 9 gives a high-level
description of each switch. The switches are read at DE1B55503 power up. Further details on the
operation of these swi tches can b e found i n Chapter 3, “Optional Configurations”. Th e switches are
in dual-in-line (DIP) packs designated J9, J20, and J21. Each switch pack contains SW1 through
SW5.
Figure 2. Switches
Initialization
Switches
J8
J21
J20
J9
L2
L1+
E9
E8
E7
E5
1 2 3 4 5
1 2 3 4 5
1 2 3 4 5
SLOT 2
J7
J101
SLOT 1
J102
OPTIONAL SLOT
Y1
E3
E2
E4
J1
J4J6J2
J5
21555
E1
A8409-01
821555 PCI-to-PCI Bridge Ev aluation Board User’s Guide
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