Intel 21554 Hardware Reference Manual September 1998

21554 PCI-to-PCI Bridge for
Embedded Applications

Hardware Reference Manual

September 1998

Order Number: 278091-001

Information in this document is provided in connection with Intel products. No license, express or implied, by estoppel or otherwise, to any intellectual
property rights is granted by this document. Except as provided in Intel’s Terms and Conditions of Sale for such products, Intel assumes no liability
whatsoever, and Intel disclaims any express or implied warranty, relating to sale and/or use of Intel products including liability or warranties relating to
fitness for a particular purpose, merchantability, or infringement of any patent, copyright or other intellectual property right. Intel products are not
intended for use in medical, life saving, or life sustaining applications.

Intel may make changes to specifications and product descriptions at any time, without notice.

Designers must not rely on the absence or characteristics of any features or instructions marked "reserved" or "undefined." Intel reserves these for
future definition and shall have no responsibility whatsoever for conflicts or incompatibilities arising from future changes to them.

The 21554 may contain design defects or errors known as errata which may cause the product to deviate from published specifications. Current
characterized errata are available on request.

Contact your local Intel sales office or your distributor to obtain the latest specifications and before placing your product order.
Copies of documents which have an ordering number and are referenced in this document, or other Intel literature may be obtained by calling

1-800-548-4725 or by visiting Intel’s website at http://www.intel.com.

Copyright © Intel Corporation, 1998
*Third-party brands and names are the property of their respective owners.

21554 PCI-to-PCI Bridge for Embedded Applications Hardware Reference Manual

Contents

1 Preface........................................................................................................................1–1

1.1 Manual Organization .........................................................................................1–1

1.2 Conventions and Terminology...........................................................................1–2

1.2.1 Caution................................................................................................1–2

1.2.2 Data Units............................................................................................1–2

1.2.3 Note .....................................................................................................1–2

1.2.4 Numbering ..........................................................................................1–2

1.2.5 Signal Names......................................................................................1–2

1.2.6 SIGNAME#...........................................................................................1–3

2 Introduction..............................................................................................................2–1

2.1 Features............................................................................................................2–1

2.2 Comparing 21554 and Standard PCI-to-PCI Bridge .........................................2–4

2.3 Architectural Overview ......................................................................................2–7

3 Signal Pins........................... .....................................................................................3–1

3.1 Primary PCI Bus Interface Signals....................................................................3–2

3.2 Primary PCI Bus Interface 64-Bit Extension Signals.........................................3–5

3.3 Secondary PCI Bus Interface Signals...............................................................3–6

3.4 Secondary PCI Bus Interface 64-Bit Extension Signals....................................3–8

3.5 Secondary PCI Bus Arbitration Signals.............................................................3–9

3.6 Clock Signals.....................................................................................................3–9

3.7 Power Management, Hot Swap, and Reset Signals .......................................3–10

3.8 ROM Interface Signals ....................................................................................3–11

3.9 Miscellaneous Signals.....................................................................................3–12

3.10 Diagnostic Signals...........................................................................................3–13

4 PCI Bus Opera t ion................................................................................................ .4–1

4.1 PCI Bus Operation ............................................................................................4–1

4.1.1 Posted Write Transactions ...................................................................4–1

4.1.1.1 Memory Write Transactions ....................................................4–2

4.1.1.2 Memory Write and Invalidate Transactions.............................4–2

4.1.1.3 Posted Write Transactions Using the 64-bit Extension ...........4–3

4.1.1.4 Write Performance Tuning Options.........................................4–3

4.1.2 Delayed Write Transactions .................................................................4–4

4.1.3 Delayed Read Transactions.................................................................4–5

4.1.3.1 Nonprefetchable Reads...........................................................4–6

4.1.3.2 Prefetchable Reads.................................................................4–6

4.1.3.3 Prefetchable Read Transactions Using the

64-bit Extension...................................... ...... ...... .....................4–6

4.1.3.4 Read Performance Features and Tuning Options...................4–7

4.1.4 Target Terminations .............................................................................4–8

4.1.4.1 Target Terminations Returned by the 21554...........................4–8

4.1.4.2 Transaction Termination Errors on the Target Bus .................4–9

4.1.5 Ordering Rules .....................................................................................4–9

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5 Address Decoding.................................................................................................5–1

5.1 21554 CSR Address Decoding.........................................................................5–1

5.2 Expansion ROM Address Decoding..................................................................5–1

5.3 Memory Transaction Address Decoding...........................................................5–2

5.3.1 Using the BAR Setup Registers...........................................................5–2

5.3.2 Direct Address Translation...................................................................5–4

5.3.3 Lookup Table Based Address Translation ...........................................5–6

5.3.3.1 Lookup Table Entry Format.....................................................5–8

5.3.4 Forwarding of 64-Bit Address Memory Transactions...........................5–8

5.4 I/O Transaction Address Decoding ........................ ...... ....... ...... ...... ..................5 –9

5.4.1 Indirect I/O Transaction Generation..................................................5–10

5.4.2 Subtractive Decoding of I/O Transactions..........................................5–11

5.5 21554 Base Address Register Summary........................................................5–11

6 Configuration Accesses......................................................................................6–1

6.1 Type 0 Accesses to the 21554 Configuration Space ........................................6–1

6.2 Initiation of Configuration Transactions by 21554.............................................6–2

7 Configuration Space Registers........................................................................7–1

7.1 Configuration Space Address Map ...................................................................7–2

7.2 Configuration Register Description ...................................................................7–5

7.2.1 Shared Standard PCI Registers...........................................................7–5

7.2.1.1 Vendor ID Register..................................................................7–5

7.2.1.2 Device ID Register ..................................................................7–6

7.2.1.3 Revision ID (RevID) Register.................................................7–6

7.2.1.4 BiST Register ..........................................................................7–6

7.2.1.5 Header Type Register .............................................................7–7

7.2.1.6 Subsystem Vendor ID Register....................... ...... ....... ...... .....7–7

7.2.1.7 Subsystem ID Register.......... ....... ...... .....................................7–7

7.2.2 Primary and Secondary Standard PCI Registers.................................7–8

7.2.2.1 Primary and Secondary Command Registers.........................7–8

7.2.2.2 Primary and Secondary Status Registers .............................7–10

7.2.2.3 Primary and Secondary Class Code Registers.....................7–11

7.2.2.4 Primary and Secondary Cache Line Size Registers .............7–11

7.2.2.5 Primary Latency and Secondary Master

Latency Timer Registers .......................................................7–11

7.2.2.6 Primary and Secondary Interrupt Line Registers ..................7–12

7.2.2.7 Primary and Secondary Interrupt Pin Registers....................7–12

7.2.2.8 Primary and Secondary Minimum Grant Registers...............7–12

7.2.2.9 Primary and Secondary Maximum Latency Registers ..........7–13

7.2.2.10Enhanced Capabilities Pointer Register................................7–13

7.2.2.11Power Managemen t Capabili ty ID Regis ter ................. .........7–13

7.2.2.12Power Management Next Item Pointer Register...................7–13

7.2.2.13Power Management Capabilities Register............................7–14

7.2.2.14Power Management Control and Status Register.................7–15

7.2.2.15PMCSR Bridge Support Extensions......................................7–16

7.2.2.16Power Management Data Register.......................................7–16

7.2.2.17Vital Product Data (VPD) ECP Register................................7–16

7.2.2.18Vital Product Data (VPD) Next Pointer Register ...................7–16

7.2.2.19Vital Product Data (VPD) Address Register..........................7–17

7.2.2.20VPD Data Register................................................................7–17

7.2.2.21Compact PCI Hot-Swap Capability Identifier Register ..........7–17

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7.2.2.22Compact PCI Hot-Swap Next Pointer Register.....................7–18

7.2.2.23Compact PCI Hot-Swap Control Register .............................7–18

7.2.3 Primary and Secondary Address Registers .......................................7–19

7.2.3.1 Primary CSR and Downstream Memory 0

Base Address Register..........................................................7–19

7.2.3.2 Secondary CSR Memory Base Address Registers...............7–20

7.2.3.3 Primary and Secondary CSR I/O Base Address

Register................. ................................................................7–20

7.2.3.4 Downstream I/O or Memory 1 and Upstream

I/O or Memory 0 BAR ............................................................7–21

7.2.3.5 Downstream Memory 2 and 3 BAR, Upstream

Memory 1 BAR......................................................................7–22

7.2.3.6 Upper 32 Bits Downstream Memory 3 Base

Address Register...................................................................7–23

7.2.3.7 Upstream Memory 2 Base Address Register........................7–23

7.2.3.8 Primary Expansion ROM Base Address Register.................7–24

7.2.3.9 Downstream I/O or Memory 1 and Upstream

I/O or Memory 0 Translated Base Register...........................7–25

7.2.3.10Downstream Memory 0, 2, 3, and Upstream

Memory 1 Translated Base Register.....................................7–26

7.2.3.11Downstream I/O or Memory 1 and Upstream

I/O or Memory 0 Setup Registers..........................................7–27

7.2.3.12Downstream Memory 0, 2, 3, and Upstream

Memory 1 Setup Registers....................................................7–28

7.2.3.13Upper 32 Bits Downstream Memory 3 Setup Register..........7–29

7.2.3.14Primary Expansion ROM Setup Register..............................7–29

7.2.4 Configuration Transaction Generation Registers...............................7–30

7.2.4.1 Downstream and Upstream Configuration

Address Registers.................................................................7–30

7.2.4.2 Downstream Configuration Data and Upstream

Configuration Data Registers ............................. ....... ...... ......7–31

7.2.4.3 Configuration Own Bits Register ...........................................7–32

7.2.4.4 Configuration Control and Status Register............................7–33

7.2.5 Device-Specific Control and Status Registers....................................7–34

7.2.5.1 Chip Control 0 Register .........................................................7–34

7.2.5.2 Chip Control 1 Register .........................................................7–37

7.2.5.3 Reset Control Register..........................................................7–39

7.2.5.4 Chip Status Register .............................................................7–40

7.2.5.5 Arbiter Control Register............................................. ...... ......7–41

7.2.5.6 Primary SERR# Disable Register..........................................7–42

7.2.5.7 Secondary SERR# Disable Register.....................................7–43

7.3 Serial ROM Configuration Data Preload Format.............................................7–44

8 Control and Status Registers............................................................................8–1

8.1 CSR Address Map.............................................................................................8–2

8.2 CSR Descriptions..............................................................................................8–4

8.2.1 I/O and Configuration Transaction Generation Registers ....................8–4

8.2.1.1 Downstream /Upstream Configuration Address

and Data, Control, Status Registers........................................8–4

8.2.1.2 Downstream I/O Address and Upstream I/O

Address Registers...................................................................8–5

8.2.1.3 Downstream I/O Data and Upstream I/O Data

Registers .................................................................................8–5

8.2.1.4 I/O Own Bits Registers............................................................8–6

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8.2.1.5 I/O Control and Status Register .............................................8–7

8.2.1.6 Lookup Table Offset Register..................................................8–8

8.2.1.7 Lookup Table Data Register....................................................8–8

8.2.2 I2O Registers .......................................................................................8–9

8.2.2.1 I2O Inbound Queue.................................................................8–9

8.2.2.2 I2O Outbound Queue..............................................................8–9

8.2.2.3 I2O Outbound Post_List Status...............................................8–9

8.2.2.4 I2O Outbound Post_List Interrupt Mask................................8–10

8.2.2.5 I2O Inbound Post_List Status................................................8–10

8.2.2.6 I2O Inbound Post_List Interrupt Mask...................................8–10

8.2.2.7 I2O Inbound Free_List Head Pointer.....................................8–11

8.2.2.8 I2O Inbound Post_List Tail Pointer........................................8–11

8.2.2.9 I2O Outbound Free_List Tail Pointer.....................................8–11

8.2.2.10I2O Outbound Post_List Head Pointer..................................8–11

8.2.2.11I2O Inbound Post_List Counter.............................................8–12

8.2.2.12I2O Inbound Free_List Counter.............................................8–12

8.2.2.13I2O Outbound Post_List Counter..........................................8–13

8.2.2.14I2O Outbound Free_List Counter..........................................8–13

8.2.3 Address Registers..............................................................................8–14

8.2.3.1 Upstream Memory 2 Lookup Table.......................................8–14

8.2.4 Interrupt Registers..............................................................................8–15

8.2.4.1 Primary Clear IRQ and Secondary Clear IRQ

Registers ...............................................................................8–15

8.2.4.2 Primary Set IRQ and Secondary Set IRQ Registers.............8–15

8.2.4.3 Primary Clear IRQ Mask and Secondary Clear

IRQ Mask Registers........ ...... ....... .........................................8–16

8.2.4.4 Primary Set IRQ Mask and Secondary Set IRQ

Mask Registers................ ...... ....... .........................................8–16

8.2.4.5 Chip Status CSR ...................................................................8–17

8.2.4.6 Chip Set IRQ Mask Register.................................................8–17

8.2.4.7 Chip Clear IRQ Mask Register..............................................8–18

8.2.4.8 Upstream Page Boundary IRQ 0 Register ............................8–18

8.2.4.9 Upstream Page Boundary IRQ 1 Register ............................8–19

8.2.4.10Upstream Page Boundary IRQ Mask 0 Register...................8–19

8.2.4.11Upstream Page Boundary IRQ Mask 1 Register...................8–19

8.2.5 ROM Registers...................................................................................8–20

8.2.5.1 ROM Setup Register .............................................................8–20

8.2.5.2 ROM Data Register...............................................................8–20

8.2.5.3 ROM Address Register .........................................................8–21

8.2.5.4 ROM Control Register...........................................................8–22

8.2.6 Control and Miscellaneous Registers.................................................8–23

8.2.6.1 Scratchpad 0 Through Scratchpad 7 Registers ....................8–23

9 I2O Support ..............................................................................................................9–1

9.1 Inbound Message Passing..................................... ...... .....................................9–1

9.2 Outbound Message Passing.............................................................................9–3

9.3 Miscellaneous Notes .........................................................................................9–4

10 Interrupt and Scratchpad Registers.............................................................10–1

10.1 Interrupt Support .............................................................................................10–1

10.2 Doorbell Interrupts..................................... ............................................. ...... ...10–2

10.3 Scratchpad Registers......................................................................................10–2

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21554 PCI-to-PCI Bridge for Embedded Applications Hardware Reference Manual

11 Parallel ROM Interf ac e.......................................................................................11–1

11.1 Parallel ROM Read by CSR Access ...............................................................11–2

11.2 Parallel ROM Write by CSR Access................................................................11–4

11.3 Parallel ROM Dword Read..............................................................................11–5

11.4 Access Time and Strobe Control.....................................................................11–6

11.5 Attaching Additional Devices to the ROM Interface ........................................11–6

12 Serial ROM Interface...........................................................................................12–1

12.1 Serial ROM Preload Operation........................................................................12–1

12.2 Serial ROM Operation by CSR Access..................... ....... ...... ...... ...................12–2

13 Arbitration..................... ....... ...... ....... ............................................. ...... ....... ...... ......13–1

13.1 Primary PCI Bus Arbitration ............................................................................13–1

13.2 Secondary PCI Bus Arbitration........................................................................13–1

13.2.1 Secondary Bus Arbitration Using the Internal Arbiter.........................13–1

13.2.2 Secondary Bus Arbitration Using an External Arbiter.........................13–3

14 Error Handling.......................... ....... ...... ............................................. ....... ...... ......14–1

14.1 Parity Errors ....................................................................................................14–1

14.2 System Error (SERR#) Reporting ...................................................................14–4

15 Clocking...................................................................................................................15–1

15.1 21554 Secondary Clock Outputs.....................................................................15–1

16 Initialization Requirements..............................................................................17–1

16.1 Reset Behavior................................................................................................17–1

16.1.1 Central Function During Reset...........................................................17–2

16.2 21554 Initialization...........................................................................................17–3

16.2.1 Initialization with Serial ROM, Local Processor, and

Host Processor...................................................................................17–4

16.2.2 Initialization Without Serial Preload....................................................17–4

16.2.3 Initialization Without Local Processor.................................................17–5

16.2.4 Initialization Without Local Processor and Serial Preload..................17–5

16.2.5 Initialization Without Host Processor..................................................17–5

16.3 Power Management Support...........................................................................17–5

16.3.1 Transitions Between Power Management States ..............................17–6

16.3.2 PME# Support....................................................................................17–6

16.3.3 Power Management Data Register....................................................17–7

16.4 Compact PCI Hot-Swap Functionality.............................................................17–7

16.4.1 Add-In Card Insertion ................................................ ...... ....... ...... ......17–8

16.4.2 Add-In Card Removal...................... ....... ...... ....... ...............................17– 9

17 Diagnostic Mechanisms....................................................................................17–1

17.1 Test Access Port Controller.............................................................................17–1

17.1.1 Initialization.........................................................................................17–1

17.2 Instruction Register .........................................................................................17–2

17.3 Bypass Register ..............................................................................................17–2

17.4 Boundary-Scan Register .................................................................................17–2

18 VPD Support...........................................................................................................18–1

18.1 Reading VPD Information................................................................................18–1

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18.2 Writing VPD Information............................ ...... ....... ...... ....... ...... ...... ....... ...... ...18–2

19 Special Applications...........................................................................................19–1

19.1 Primary Bus VGA Support ..............................................................................19–1

19.2 Secondary Bus VGA Support..........................................................................19–1

20 Serial ROM and Register Rese t Summary.................................................20–1

20.1 Serial ROM Preload Sequence.......................................................................20–1

20.2 Register Reset and Access Summary ............................................................20–4

20.3 CSR Register Summary..................................................................................20–8

Figures

2-1 21554 Intelligent Controller Application.............................................................2–4

2-2 21554 Microarchitecture....................................................................................2–8

5-1 BAR Setup Register Example...........................................................................5–3

5-2 Address Format.................................................................................................5–4

5-3 Direct Offset Address Translation .....................................................................5–4

5-4 Downstream Address Translation Example ......................................................5–5

5-5 Address Translation Using Lookup Table .........................................................5–7

5-6 Upstream Lookup Table Address Translation...................................................5–7

5-7 Lookup Table Entry Format...............................................................................5–8

5-8 Dual-Address Transaction Forwarding..............................................................5–9

7-1 Primary Interface Configuration Space Address Map.......................................7–2

7-2 Secondary Interface Configuration Space Address Map ..................................7–3

7-3 Device-Specific Configuration Address Map.....................................................7–4

8-1 CSR Register Map (Sheet 1 of 2) .....................................................................8–2

8-2 CSR Register Map (Sheet 2 of 2) .....................................................................8–3

11-1 Parallel and Serial ROM Connections.............................................................11–2

11-2 Parallel ROM Read Timing .............................................................................11–3

11-3 Parallel ROM Write Timing..............................................................................11–5

11-4 Read and Write Strobe Timing........................................................................11–6

11-5 Attaching Multiple Devices on the ROM Interface...........................................11–7

12-1 Serial ROM Read Timing Diagram..................................................................12–3

12-2 Serial ROM Write Timing Diagram..................................................................12–4

12-3 Serial ROM Write All Timing Diagram.............................................................12–4

12-4 Serial ROM Write Enable Timing Diagram......................................................12–4

12-5 Serial ROM Write Disable Timing Diagram.....................................................12–5

12-6 Serial ROM Erase Timing Diagram.................................................................12–5

12-7 Serial ROM Erase All Operation .....................................................................12–5

12-8 Serial ROM Check Status Timing Diagram.....................................................12–6

13-1 Secondary Arbiter Example ............................................................................13–2

15-1 Synchronous Secondary Clock Generation ....................................................15–1

16-1 Compact PCI Hot-Swap Connections.............................................................17–7

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Tables

2-1 21554 and PPB Feature Comparison ...............................................................2–6

3-1 Signal Pin Functional Groups............................................................................3–1

3-2 Signal Type Abbreviations.................................................................................3–1

3-3 Primary PCI Bus Interface Signals....................................................................3–2

3-4 Primary PCI Bus Interface 64-Bit Extension Signals.........................................3–5

3-5 Secondary PCI Bus Interface Signals ...............................................................3–6

3-6 Secondary PCI Bus Interface 64-Bit Extension Signals....................................3–8

3-7 Secondary PCI Bus Arbitration Signals.............................................................3–9

3-8 Clock Signals.....................................................................................................3–9

3-9 Power Management, Hot Swap, and Reset Signals .......................................3–10

3-10 ROM Interface Signals........................... ...... ....... ...... ....... ...... ...... ....... ............3–11

3-11 Miscellaneous Signals.....................................................................................3–12

3-12 JTAG Signals ..................................................................................................3–13

4-1 Delayed Write Transaction Target Termination Returns...................................4–4

4-2 Delayed Read Transaction Target Termination Returns...................................4–5

4-3 Prefetch Boundaries..........................................................................................4–7

4-4 21554 Transaction Ordering Rules .................................................................4–10

5-1 Upstream Memory 2 Window Size....................................................................5–6

5-2 Base Address Register Summary...................................................................5–11

7-1 Register Access ................................................................................................7–5

7-2 Primary and Secondary Command Registers...................................................7–8

7-3 Primary and Secondary Status Registers .......................................................7–10

7-4 Primary and Secondary Class Code Registers...............................................7–11

7-5 Primary and Secondary Cache Line Size Registers .......................................7–11

7-6 Primary Latency and Secondary Master Latency Timer Registers .................7–11

7-7 Primary and Secondary Interrupt Line Registers ............................................7–12

7-8 Primary and Secondary Interrupt Pin Registers..............................................7–12

7-9 Primary and Secondary Minimum Grant Registers.........................................7–12

7-10 Primary and Secondary Maximum Latency Registers ....................................7–13

7-11 Enhanced Capabilities Pointer Register..........................................................7–13

7-12 Power Management Capability ID Register ....................................................7–13

7-13 Power Management Next Item Pointer Register.............................................7–13

7-14 Power Management Capabilities Register ......................................................7–14

7-15 Power Management Control and Status Register...........................................7–15

7-16 PMCSR Bridge Support Extensions................................................................7–16

7-17 Power Management Data Register .................................................................7–16

7-18 Vital Product Data (VPD) ECP Register..........................................................7–16

7-19 Vital Product Data (VPD) Next Pointer Register .............................................7–16

7-20 Vital Product Data (VPD) Address Register....................................................7–17

7-21 VPD Data Register..........................................................................................7–17

7-22 Compact PCI Hot-Swap Capability Identifier Register....................................7–17

7-23 Compact PCI Hot-Swap Next Pointer Register...............................................7–18

7-24 Compact PCI Hot-Swap Control Register .......................................................7–18

7-25 Primary CSR and Downstream Memory 0 Base Address Register ................7–19

7-26 Secondary CSR Memory Base Address Registers.........................................7–20

7-27 Primary and Secondary CSR I/O Base Address Register...............................7–20

7-28 Downstream I/O or Memory 1 and Upstream I/O or Memory 0 BAR..............7–21

7-29 Downstream Memory 2 and 3 BAR, Upstream Memory 1 BAR......................7–22

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7-30 Upper 32 Bits Downstream Memory 3 Base Address Register ......................7–23

7-31 Upstream Memory 2 Base Address Register..................................................7–23

7-32 Primary Expansion ROM Base Address Register...........................................7–24

7-33 Downstream I/O or Memory 1 and Upstream I/O or

Memory 0 Translated Base Register...............................................................7–25

7-34 Downstream Memory 0, 2, 3, and Upstream Memory 1

Translated Base Register................................................................................7–26

7-35 Downstream I/O or Memory 1 and Upstream I/O or

Memory 0 Setup Registers..............................................................................7–27

7-36 Downstream Memory 0, 2, 3, and Upstream

Memory 1 Setup Registers..............................................................................7–28

7-37 Upper 32 Bits Downstream Memory 3 Setup Register ...................................7–29

7-38 Primary Expansion ROM Setup Register........................................................7–29

7-39 Downstream and Upstream Configuration Address Registers........................7–30

7-40 Downstream Configuration Data and Upstream

Configuration Data Registers..........................................................................7–31

7-41 Configuration Own Bits Register.....................................................................7–32

7-42 Configuration Control and Status Register......................................................7–33

7-43 Chip Control 0 Register...................................................................................7–34

7-44 Chip Control 1 Register...................................................................................7–37

7-45 Reset Control Register....................................................................................7–39

7-46 Chip Status Register .......................................................................................7–40

7-47 Arbiter Control Register...................................................................................7–41

7-48 Primary SERR# Disable Register ...................................................................7–42

7-49 Secondary SERR# Disable Register...............................................................7–43

7-50 Autoload Sequence.........................................................................................7–44

7-51 Power Management and BiST Autoload Format.............................................7–45

8-1 Downstream I/O Address and Upstream I/O Address

Registers...........................................................................................................8–5

8-2 Downstream I/O Data and Upstream I/O Data Registers .................................8–5

8-3 I/O Own Bits Registers......................................................................................8–6

8-4 I/O Control and Status Register ........................................................................8–7

8-5 Lookup Table Offset Register ...........................................................................8–8

8-6 Lookup Table Data Register .............................................................................8–8

8-7 I2O Inbound Queue...........................................................................................8–9

8-8 I2O Outbound Queue........................................................................................8–9

8-9 I2O Outbound Post_List Status.........................................................................8–9

8-10 I2O Outbound Post_List Interrupt Mask..........................................................8–10

8-11 I2O Inbound Post_List Status .........................................................................8–10

8-12 I2O Inbound Post_List Interrupt Mask.............................................................8–10

8-13 I2O Inbound Free_List Head Pointer ..............................................................8–11

8-14 I2O Inbound Post_List Tail Pointer .................................................................8–11

8-15 I2O Outbound Free_List Tail Pointer ..............................................................8–11

8-16 I2O Outbound Post_List Head Pointer............................................................8–11

8-17 I2O Inbound Post_List Counter.......................................................................8–12

8-18 I2O Inbound Free_List Counter.......................................................................8–12

8-19 I2O Outbound Post_List Counter....................................................................8–13

8-20 I2O Outbound Free_List Counter....................................................................8–13

8-21 Upstream Memory 2 Lookup Table.................................................................8–14

8-22 Primary Clear IRQ and Secondary Clear IRQ Registers ................................8–15

8-23 Primary Set IRQ and Secondary Set IRQ Registers.......................................8–15

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8-24 Primary Clear IRQ Mask and Secondary Clear IRQ

Mask Registers................................................................................................8–16

8-25 Primary Set IRQ Mask and Secondary Set IRQ

Mask Registers................................................................................................8–16

8-26 Chip Status CSR.............................................................................................8–17

8-27 Chip Set IRQ Mask Register...........................................................................8–17

8-28 Chip Clear IRQ Mask Register........................................................................8–18

8-29 Upstream Page Boundary IRQ 0 Register ......................................................8–18

8-30 Upstream Page Boundary IRQ 1 Register ......................................................8–19

8-31 Upstream Page Boundary IRQ Mask 0 Register.............................................8–19

8-32 Upstream Page Boundary IRQ Mask 1 Register.............................................8–19

8-33 ROM Setup Register.............................. ...... ....... ...... ......................................8–20

8-34 ROM Data Register......................... ....... ...... ....... ............................................8–20

8-35 ROM Address Register .................................................... ...... ...... ....... ............8–21

8-36 ROM Control Registe................................... ....... ............................................8–22

8-37 Scratchpad 0 Through Scratchpad 7 Registers ..............................................8–23

11-1 Parallel ROM Interface Signals .......................................................................11–1

12-1 Serial ROM Interface Signals..........................................................................12–1

14-1 Parity Error Responses...................................................................................14–1

16-1 Reset Mechanisms..........................................................................................17–2

16-2 Power Management Actions ...........................................................................17–6

16-3 Hot-Swap Insertion from 21554 Viewpoint......................................................17–8

16-4 Add-In Card Removal from 21554 Viewpoint..................................................17–9

17-1 JTAG Signal Pins............................................................................................17–1

17-2 JTAG Instruction Register Options..................................................................17–2

20-1 Serial Preload Sequence.................................................................................20–1

20-2 Configuration Register Summary........... ...... ....... ...... ....... ...............................20– 4

20-3 CSR Summary ................................................................................................20–8

21554 PCI-to-PCI Bridge for Embedded Applications Hardware Reference Manual

xi

Preface

This manual provides a detailed functional and reg ister desc rip tion o f th e 2 1554 PCI-t o-PCI bridge
device for embedded applications. For pinouts, mechanical specifications, and electrical
specifications for this device, please refer to the 21554 PCI-to-PCI Bridge for Embedded
Applications Data Sheet.

1.1 Manual Organization

This manual contains the following chapters and an appendix:

Chapter 2, “Introduction”, provides an overview of the 21554 functionality and architecture.
Chapter 3, “Signal Pins”, describes the signal pins grouped by function.
Chapter 4, “PCI Bus Operation”, PCI transactions, transaction forwarding, and transact ion

termination.

Chapter 5, “Address Decoding”, contains details about how addresses are decoded.
Chapter 6, “Configuration Accesses”, explains how 21554 responds to Type 0 confi gurat ion

accesses.

1

Chapter 7, “Configuration Space Registers”, describes the 21554 configuration registers.
Chapter 8, “Control and Status Registers”, describes the 21554 CSRs.
Chapter 9, “I2O Support”, explains how the 21554 implements an I
Chapter 10, “Interrupt and Scratchpad Registers”, describes interrupt support and scrat chpad

registers.

Chapter 11, “Parallel ROM Interface”, describes the 21554 parallel ROM interface.
Chapter 12, “Serial ROM Interface”, describes the 21554 serial ROM interface.
Chapter 13, “Arbitration”, explains how 21554 implements primary and secondary PCI bus

arbitration.

Chapter 14, “Error Handling”, describes parity error responses and system error reporting.
Chapter 15, “Clocking”, describes clocking support in the 21554.
Chapter 16, “Initialization Requirements”, reset operation and initialization requirements for the

21554.

Chapter 17, “Diagnostic Mechanisms”, explains the implementation of the 21554’ s JTAG test port.
Chapter 18, “VPD Support” , 21554 Vital P roduct Data (VPD) support through seri al ROM interface.
Chapter 19, “Special Applications”, describes primary and secondary bus VGA support.

O messaging unit.

2

21554 PCI-to-PCI Bridge for Embedded Applica tio ns User’ s Ma nua l

1-1

Preface

Chapter 20, “Serial ROM and Register Reset Summary”, SROM preload sequence and register

reset and access.

Appendix A, “Support, Products , and Docu mentation ”, techn ical su pport and orderi ng info rmation .

1.2 Conventions and Terminology

This section describes the terminology and conventions used in this manual.

1.2.1 Caution

Cautions provide information to prevent damage to equipment or loss of data.

1.2.2 Data Units

This manual uses the following data-unit terminology.

Term Words Bytes Bits

Byte ½18
Word 1 2 16
Dword 2 4 32
Quadword 4 8 64

1.2.3 Note

Notes emphasize particularly important information.

1.2.4 Numbering

All numbers are decimal or hexadecimal unless otherwise indicated. In cases of ambiguity, a
subscript indicates the radix of nondecimal numbers. For examp l e, 19 is decimal, but 1 9h an d 1 9A
are hexadecimal.

1.2.5 Signal Names

Signal names are printed in lowercase type.
Signal names indicate whether a signal is low-asserted (the signal is active, or asserted, when it is

at a low voltage level) or high-asserted (the signal is asserted when it is at a high voltage level).
The names of low-asserted signals carry the suffix _l; the names of high-asserted signals have no
suffix. For example, p_idsel is a high-asserted signal, and p_frame_l is a low-asserted signal.

1-2

The prefix p_ denotes a primary bus signal; the prefix s_ denotes a secondary bus signal. For
example, p_ad is the primary interface address/data bus, and s_ad is the secondary interface
address/data bus.

21554 PCI-to-PCI Bridge for Embedded Applications User’s Manual

1.2.6 SIGNAME#

PCI signals that can be on either the primary interface or the secondary interface are printed in
uppercase, normal type. The names of low-asserted signals are followed by #. For example,

“asserting FRAME#” can refer to the assertion of the p_frame_l signal if the transaction is
occurring on the primary bus, or the assertion of the s_frame_ l signal if the transaction is occurr ing
on the secondary bus.

Preface

21554 PCI-to-PCI Bridge for Embedded Applica tio ns User’ s Ma nua l

1-3

Introduction

Intel’s 21554 is a PCI peripheral device that performs PCI bridging functions for embedded and
intelligent I/O applications. The 21554 has a 64-bit primary interface, a 64-bit secondary interface,
and 33-MHz capability.

The 21554 is a “nontransparent” PCI-to-PCI bridge that acts as a gateway to an intelligent
subsystem. It allows a local processor to independently configure and control the local subsystem.
The 21554 implements an I
intelligent I/O processor (IOP) in an I
independent, it works with any host and local processors that support a PCI bus. This architecture
independence enables vendors to leverage existing investments while moving products to PCI
technology.

Unlike a transparent PCI-to-PCI bridge, the 21554 is specifically designed to bridge between two
processor domains. The processor domain on the primary interface of the 21554 is also referred to
as the host domain, and its processor is the host processor. The secondary bus interfaces to the
local domain and the local processor. Special features include support of independent primary and
secondary PCI clocks, independent primary and secondary address spaces, and address translation
between the primary (host) and secondary (local) domains.

The 21554 enables add-in card vendors to present to the host system a higher level of abstraction
than is possible with a transparent PCI-to-PCI bridge. The 21554 uses a Type 0 configuration
header, which presents the entire subsystem as a single “device” to the host processor. This allows
loading of a single device driver for the entire subsystem, and independent local processor
initialization and control of the subsystem devices. Because the 21554 uses a Type 0 configuration
header, it does not require hierarchical PCI-to-PCI bridge configuration code.

O message unit that enables any local processor to function as an

2

O-capable system. Because the 21554 is architecture

2

2

The 21554 forwards transactions between the primary and secondary PCI buses as does a
transparent PCI-to-PCI bridge. In contr ast to a tran sparent PCI -to-PCI br idge, howev er, the 21554
can translate the address of a forwarded transaction from a system address to a local address, or
vice versa. This mechanism allows the 21 554 to hi de subsyst em resources fro m the host pro cessor
and to resolve any resource conflicts that may exist between the host and local subsystems.

The 21554 opera tes at 3.3 V, but is also 5.0-V I/O tolerant. Adapter cards designed us ing the
21554 can be keyed as universal, thus permitting use in eith er a 5-V or 3-V slot.

2.1 Features

The 21554 also supports the following features:
PCI Interfaces

• Full compliance with the PCI Local Bus Specification, Revision 2.1, plus :

— Vi t al Product Data (VPD) support
— Compact PCI Distributed Hot-Swap support

• 3.3-V operation with 5.0-V tolerant I/O

• Selectable asynchronous or synchronous primary and secondary interface clocks

21554 PCI-to-PCI Bridge for Embedded Applica tio ns User’ s Ma nua l

2-1

Introduction

• Concurrent primary and secondary bus operation

PCI Power Management

• Fully compliant with the Advanced Configuration Power Interface (ACPI) specification

• Fully compliant with the PCI Bus Power Management Specification

Buffer Architecture

• Queuing of multiple transactions in either direction

• 256 bytes of posted write (data and address) buffering in each direction:

— For forwarding of memory write (MW) and memory write and invalidate (MWI)

transactions

• 256 bytes of read data buffering in each direction

• Four delayed transaction entries in each direction:

— For forwarding of I/O write and all read transactions
— For configuration and I/O transaction generation

• Two dedicated I

Configuration Regis ters and CS Rs

O delayed transaction entries

2

• Two sets of standard PCI configuration registers corresponding to the primary and secondary

interface; each set is accessible from either the primary or secondary interface

• Four 32-bit base address conf iguration regis ters mapping the 21554 con trol and status re gisters

(CSRs):

— One for memory mapping of registers from the primary interface
— One for I/O mapping of registers from the primary interface
— One for memory mapping of registers from the secondary interface
— One for I/O mapping of registers from the secondary interface

Transaction Forwarding

• Four primary interface base address configuration registers for downstream forwarding, with

size and prefetchability programmable for all four address ranges:

— One programmable for forwarding of either I/O or memory transactions
— Three for forwarding of memory transactions:

*One shared with primary CSR memory mapping.

*One is configurable as a 64-bit address base address register (BAR) for downstream

dual-address cycles (DACs).

• Direct offset address translation for downstream memory and I/O transactions

• Three secondary interface address configuration registers specifying local address ranges for

upstream forwarding, with size and prefetchability programmable for all three address ranges:

— One programmable for forwarding of either I/ O or memo ry transact ions usin g direct of fset

address translation

2-2

— One for forwarding memory transactions using direct offset address translation

21554 PCI-to-PCI Bridge for Embedded Applications User’s Manual

Introduction

— One for forwarding memory transactions using lookup table (LUT) based address

translation

• Inverse decoding above the 4GB address boundary for upstream DACs

• Ability to generate Type 0 and Type 1 configuration commands on the primary or secondary

interface via configuration or I/O CSR accesses

• Ability to generate I/O commands on the primary or secondary interface via I/O CSR accesses

Intelligent I/O Support

• I

O message unit

2

— Standard I
— Queue size selectable between 256 and 32K entries, by powers of 2
— Hardware support for all primary (host-side) queue pointers
— Hardware support for queue-not-empty detection

O registers at 40h and 44h, with queue-not-empty interrupts

2

• Doorbell registers for sof tware generati on of primar y and sec ondary bu s inte rrupts , 16 bits per

interface

• Eight Dwords of scratchpad registers

ROM Interfaces

• Parallel flash ROM interface with primary bus expansion ROM base address register

— Read- and write-accessible by CSR access
— Programmable expansion ROM window size from 4KB to 16MB
— Programmable access times

• Serial ROM interface

— Read and write accessible through CSR access
— Enables preloading of selected configuration register fields to application-specific values

* Subsystem ID, subsystem vendor ID, and class code
* Numbers, sizes, and types of base address registers
* MIN_GNT and MAX_LAT for both interfaces
* Device-specific control bits

Miscellaneous Functions

• Secondary bus arbiter support for up to nine external devices (in addition to the 21554)

— Programmable two-level, rotating-priority arbi ter
— Hardware disable control for internal arbiter to allow use of an external arbiter

• Secondary bus clock output for synchronous operation

— May be buffered externally to support any number of secondary bus devices

* Buffered version is fed back to the 21554 secondary clock input

— Hardware and software disable control

• Hardware enable for secondary bus central functions

21554 PCI-to-PCI Bridge for Embedded Applica tio ns User’ s Ma nua l

2-3

Introduction

— Driving s_ad[31:0], s_cbe_l[3:0], and s_par during reset
— Asserting s_req64_l during reset

• IEEE Standard 1149.1 boundary-scan JTAG interface

2.2 Comparing 21554 and Standard PCI-to-PCI Bridge

The 21554 is functionally similar to a standard PCI-to-PC I bridge (PPB) in that both provide a
connection path between d evices attach ed to two independen t PCI buses . A 21554 and a PPB allow
the electrical loading of devices on one PCI bus to be iso lated from the other bus while permitting
concurrent operation on both buses. Because the PCI Local Bus Specification restricts PCI option
cards to a single electrical load, the ability of PPBs and the 21554 to spawn P CI bu ses enables the
design of multidevice PCI option cards. The key difference between a PPB and the 21554 is that
the presence of a PPB in a connection path between the host processor and a device is transparent
to devices and device drivers, while the presence of the 21554 is not. This difference enables the
21554 to provide features that better support the use of intelligent controllers in the subsystem.

It was a primary goal of the PCI-to-PCI bridge architecture that a PPB be transparent to devices
and device drivers. For example, no changes are needed to a device dr iver when a PCI periph eral is
located behind a PPB. Once configured during system initialization, a PPB operates without the aid
of a device driver. A PPB does not require a device driver of its own since it does not have any
resources that must be managed by software during run-time. This requirement for transparency
forced the usage of a flat addressing model across PCI-to-PCI bridges. This means that a given
physical address exists at only one location in the PCI bus hierarchy and that this location may be
accessed by any device attached at any point in the PCI bus hierarchy. As a consequence, it is not
possible for a PPB to isolate devices or address ranges from access by devices on the opposite
interface of a PPB. The PPB architecture assumes that the resources of any device in a PCI system
are configured and managed by the host processor.

However, there are applications where the transparency of a PCI-to-PCI bridge is not desired. For
example, Figure 2-1 shows a hypothetical PCI add-in card used for an intelligent subsystem
application.

Figure 2-1. 21554 Intelligent Controller Application

Intelligent Subsystem

Intelligent Subsystem

Local

CPU

DRAM/

ROM

PCI

Device

Local

CPU
Core

Logic

PCI

Device

PCI Bus

Assume that the local processor on the add-in card is used to manage the resources of the devices

attached to the add-in card’s local PCI bus. Assume also that it is desirable to restrict access to
these same resources from other PCI bus masters in the system and from the host processor. In

21554

PCI

Device

PCI Bus

Host
Core

Logic

Memory

Host

CPU

FM-06189.AI

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21554 PCI-to-PCI Bridge for Embedded Applications User’s Manual

Introduction

addition, there is a need to resolve address conflicts that may exist between the host system and the
local processor. The nontransparency of the 21554 i s per fect ly s uit ed t o thi s ki nd o f co nfi gu rati on ,
where a transparent PCI-to-PCI bridge would be problematic.

Because the 21554 is not transparent, the device driver for the add-in card must be aware of the
presence of the 21554 and manage its resources appropriately. The 21554 allows the entire
subsystem to appear as a single virtual device to the host. This enables configuration software to
identify the appropriate driver for the subsystem.

With a transparent PCI-to-PCI bridge, a driver does not need to know about the presence of the
bridge and manage its resources. The subsystem appears to the host system as individual PCI
devices on a secondary PCI bus, not as a single virtual device.

21554 PCI-to-PCI Bridge for Embedded Applica tio ns User’ s Ma nua l

2-5

Introduction

Table 2-1 shows a comparison between a 21554 and a standard transparent PCI-to-PCI bridge.

Table 2-1. 21554 and PPB Feature Comparison

Feature 21554 PCI-to-PCI Bridge

Transaction
forwarding

Address decoding

Address
translation

Configuration

Adheres to PPB ordering rules.

Uses posted writes and delayed
transactions.

Adheres to PPB transaction error and
parity error guidelines, although some
errors may be reported differently.

Base address registers are used to
define independent downstream and
upstream forwarding windows.

Inverse decoding is only used for
upstream transactions above the
4GB boundary.

Supported for both memory and I/O
transactions.

Downstream devices are not visible
to host.

Does not require hierarchical
configuration code (Type 0
configuration header).

Does not respond to Type 1
configuration transactions.

Adheres to PPB ordering rules.

Uses posted writes and delayed transactions.

Adheres to PPB transaction error and parity
error guidelines.

PPB base and limit address registers are
used to define downstream forwarding
windows.

Inverse decoding for all I/O and memory
upstream forwarding.

None. Flat address model is assumed.

Downstream devices are visible to host.

Requires hierarchical configuration code
(Type 1 configuration header).

Forwards and converts Type 1 configuration
transactions.

2-6

Run-time resources

Clocks

Secondary bus
central functions

Supports configuration access from
the secondary bus.

Implements separate set of
configuration registers for the
secondary interface.

Includes features such as doorbell
interrupts, I
on, that must be managed by the
device driver.

Generates secondary bus clock
output.

Asynchronous secondary clock input
is also supported.

Implements secondary bus arbiter.
This function can be disabled.

Drives secondary bus AD,
C/BE#, and PAR during reset. This

function can be disabled.

O message unit, and so

2

21554 PCI-to-PCI Bridge for Embedded Applications User’s Manual

Does not support configuration access from
the secondary bus. Same set of
configuration registers is used to control both
primary and secondary interfaces.

Typically has only configuration registers; no
device driver is required.

Generates one or more secondary bus clock
outputs.

Implements secondary bus arbiter. This
function can be disabled.

Drives secondary bus AD,
C/BE#, and PAR during reset.

2.3 Architectural Overview

The 21554 consists of the following function blocks:

Data Buffers

Data buffers include the buffers along with the associated data path control logic. Delayed
transaction buffers contain the compare functionality for completing delayed transactions. The
blocks also contain the watchdog timers associated with the buffers. The data buffers are as
follows:

• Four-entry downstream dela yed transacti on buffer

• Four-entry upst ream del ayed transaction buffer

• 256-byte downstream posted write buffer

• 256-byte upstream posted write buffer

• 256-byte downstream read data buffer

• 256-byte upstream read data buffer

Introduction

• Two downstream I

Registers

The following register blocks also contain address decode and translation logic, I
and interrupt control logic:

O delayed transaction entries

2

O message unit,

2

• Primary interface header Type 0 configuration registers

• Secondary interface header Type 0 configuration registers

• Device-specific configuration registers

• Memory and I/O mapped control and status registers

Control Logic

The 21554 has the following control logic:

• Primary PCI target control logic

• Primary PCI master control logic

• Secondary PCI target control logic

• Secondary PCI master control logic

• ROM interface control logic for both serial and parallel ROM connections (inter faces between

the ROM registers and ROM signals)

• Secondary PCI bus arbiter interface to secondary bus device request and grant lines, as well as

the 21554 secondary master control logic

• JTAG control logic

Figure 2-2 shows the 21554 microarchitecture.

21554 PCI-to-PCI Bridge for Embedded Applica tio ns User’ s Ma nua l

2-7

Introduction

Figure 2-2. 21554 Microarchitecture

21554

21554

Downstream Delayed Buffer

Downstream Posted Write Buffer

Upstream Read Data Buffer

Downstream Read Data Buffer

Upstream Posted Write Buffer

Primary

PCI
Bus

Primary

Target

Control

Primary

Master

Control

JTAG

JTAG Signals

Upstream Delayed Buffer

Primary

Config

Registers

Device­Specific

Config

Registers

ROM

Interface

Control

ROM Interface

Signals

CSR

Registers

Interrupt

Signals

Secondary

Config

Registers

Secondary

Target

Control

Secondary

Master
Control

Secondary

Bus

Arbiter

Secondary Arbiter

Signals

Secondary
PCI
Bus

FM-06188.AI4

2-8

21554 PCI-to-PCI Bridge for Embedded Applications User’s Manual

Signal Pins

This chapter provides detailed descriptions of the 21554 signal pins, grouped by function.

Table 3-1 describes these signal pin functional groups.

Table 3-1. Signal Pin Functional Groups

Function Description

3

Primary PCI bus
interface signal pins

Primary PCI bus
interface 64-bit
extension signal pins

Secondary PCI bus
interface signal pins

Secondary PCI bus
interface 64-bit
extension signal pins

Secondary PCI bus
arbitration signal pins

Clock signal pins

Power management,
hot swap, and reset
signal pins

ROM interface signal
pins

Miscellaneous signal
pins

Diagnostic signal pins IEEE Standard 1149.1 boundary-scan JTAG interface. Scan enable.

Table 3-2 defines the signal type abbreviations used in the signal tables.

All PCI pins required by the

All PCI 64-bit extension pins required by the

Revision 2.1.

All PCI pins required by the

All PCI 64-bit extension pins required by the

Revision 2.1.

Nine request/grant pairs of pins for the secondary PCI bus.
Two clock inputs (one for each PCI interface).

One secondary bus clock output.

Power management and hot-swap status and events. A primary interface reset input.
A secondary interface reset output.

8-bit multiplexed address/data bus plus control for parallel and serial ROM connection.

Two input voltage signaling level pins.

PCI Local Bus Specification, Revision 2.1.

PCI Local Bus Specification,

PCI Local Bus Specification, Revision 2.1.

PCI Local Bus Specification,

Table 3-2. Signal Type Abbreviations

Signal Type Description

I Standard input only.
O Standard output only.
TS Tristate bidirectional.

STS

OD Standard open drain.

Sustained tristate. Active low signal must be pulled high for one clock cycle when
deasserting.

Note: The _l signal name suffix indicates that the signal is asserted when it is at a low voltage level and

corresponds to the # suffix in the PCI Local Bus Specification, Revision 2.1. If this suffix is not
present, the signal is asserted when it is at a high voltage level.

21554 PCI-to-PCI Bridge for Embedded Applica tio ns User’ s Ma nua l

3-1

Signal Pins

3.1 Primary PCI Bus Interface Signals

Table 3-3 describes the primary PCI bus interface signals.

Table 3-3. Primary PCI Bus Interface Signals (Sheet 1 of 3)

Signal Name Type Description

Primary PCI interface address/data. These signals are a 32-bit multiplexed address and
data bus. During the address phase or phases of a transaction, the initiator drives a

p_ad[31:0] TS

p_cbe_l[3:0] TS

p_devsel_l STS

p_frame_l STS

p_gnt_l I

p_idsel I

p_inta_l

physical address on p_ad[31:0]. During the data phases of a transaction, the initiator
drives write data, or the target drives read data, on p_ad[31:0]. When the primary PCI
bus is idle, the 21554 drives p_ad to a valid logic level when p_gnt_l is asserted.

Primary PCI interface command/byte enables. These signals are a multiplexed
command field and byte enable field. During the address phase or phases of a
transaction, the initiator drives the transaction type on p_cbe_l[3:0]. When there are
two address phases, the first address phase carries the dual-address command and
the second address phase carries the transaction type. For both read and write
transactions, the initiator drives byte enables on p_cbe_l[3:0] during the data phases.
When the primary PCI bus is idle, the 21554 drives p_cbe_l to a valid logic level when
p_gnt_l is asserted.

Primary PCI interface DEVSEL#. Signal p_devsel_l is asserted by the target,
indicating that the device is responding to the transaction. As a target, the 21554
decodes the address of a transaction initiated on the primary bus to determine
whether to assert p_devsel_l. As an initiator of a transaction on the primary bus, the
21554 looks for the assertion of p_devsel_l within five clock cycles of p_frame_l
assertion; otherwise, the 21554 terminates the transaction with a master abort. Upon
completion of a transaction, p_devsel_l is driven to a deasserted state for one clock
cycle and is then sustained by an external pull-up resistor.

Primary PCI interface FRAME#. Signal p_frame_l is driven by the initiator of a
transaction to indicate the beginning and duration of an access on the primary PCI
bus. Signal p_frame_l assertion (falling edge) indicates the beginning of a PCI
transaction. While p_frame_l remains asserted, data transfers can continue. The
deassertion of p_frame_l indicates the final data phase requested by the initiator.
Upon completion of a transaction, p_frame_l is driven to a deasserted state for one
clock cycle and is then sustained by an external pull-up resistor.

Primary PCI bus GNT#. When asserted, p_gnt_l indicates to the 21554 that access to
the primary bus is granted. The 21554 can start a transaction on the primary bus
when the bus is idle and p_gnt_l is asserted. When the 21554 has not requested use
of the bus and p_gnt_l is asserted, the 21554 drives p_ad, p_cbe_l, and p_par to valid
logic levels.

Primary PCI interface IDSEL. Signal p_idsel is used as the chip select line for Type 0
configuration accesses to 21554 configuration space from the primary bus. When
p_idsel is asserted during the address phase of a Type 0 configuration transaction,
the 21554 responds to the transaction by asserting p_devsel_l.

Primary PCI bus interrupt. Signal p_inta_l is asserted by the 21554 when:

OD

• A primary doorbell register bit is set.

• The I

• The subsystem event bit is set.

All of these conditions are individually maskable. When the corresponding event bit is
cleared or the I
is pulled up through an external resistor.

O outbound queue is not empty.

2

O outbound queue is emptied, p_inta_l is deasserted. Signal p_inta_l

2

3-2

21554 PCI-to-PCI Bridge for Embedded Applications User’s Manual

Table 3-3. Primary PCI Bus Interface Signals (Sheet 2 of 3)

Signal Name Type Description

Primary PCI i nte rf ac e IR DY #. Si gna l p_i rd y_ l i s dr i ven b y t he i n it iat or o f a t r ans act io n to
indicate the initiator’s ability to complete the current data phase on the primary PCI bus.
During a write transaction, assertion of p_irdy_l indicates that valid write data is being

p_irdy_l STS

p_par TS

p_perr_l STS

p_req_l TS

p_serr_l OD

driven on the p_ad bus. During a read transaction, assertion of p_irdy_l indicates that
the initiator is able to accept read data for the current data phase. Once asserted during
a given data phase, p_irdy_l is not deasserted until the data phase completes. Upon
completion of a transaction, p_irdy_l is driven to a deasserted state for one clock cycle
and is then sustained by an external pull-up resistor.

Primary PCI interface parity. Signal p_par carries the even parity of the 36 bits of
p_ad[31:0] and p_cbe_l[3:0] for both address and data phases. Signal p_par is driven
by the same agent that drives the address (for address parity) or the data (for data
parity). Signal p_par contains valid parity one clock cycle after the address is valid
(indicated by assertion of p_frame_l), or one clock cycle after the data is valid
(indicated by assertion of p_irdy_l for write transactions and p_trdy_l for read
transactions). Signal p_par is tristated one clock cycle after the p_ad lines are
tristated. The device receiving data samples p_par as an input to check for possible
parity errors. When the primary PCI bus is idle, the 21554 drives p_par to a valid logic
level when p_gnt_l is asserted (one clock cycle after the p_ad bus is parked).

Primary PCI interface PERR#. Signal p_perr_l is asserted when a data parity error is
detected for data received on the primary interface. The timing of p_perr_l
corresponds to p_par driven one clock cycle earlier, and p_ad and p_cbe_l driven two
clock cycles earlier. Signal p_perr_l is asserted by the target during write transactions,
and by the initiator during read transactions. Upon completion of a transaction,
p_perr_l is driven to a deasserted state for one clock cycle and is then sustained by
an external pull-up resistor.

Primary PCI bus REQ#. Signal p_req_l is asserted by the 21554 to indicate to the
primary bus arbiter that it wants to start a transaction on the primary bus.

Primary PCI interface SERR#. Signal p_serr_l can be driven low by any device on the
primary bus to indicate a system error condition. The 21554 can conditionally assert
p_serr_l for the following reasons:

• Primary bus address parity error

• Downstream posted write data parity error on secondary bus

• Master abort during downstream posted write transaction

• Tar get abort during downstream posted write transaction

• Downstream posted write transaction discarded

• Downstream delayed write request discarded

• Downstream delayed read request discarded

• Downstream delayed transaction master timeout

• Secondary bus s_serr_l assertion

Signal p_serr_l is pulled up through an external resistor.

Signal Pins

21554 PCI-to-PCI Bridge for Embedded Applica tio ns User’ s Ma nua l

3-3

Signal Pins

Table 3-3. Primary PCI Bus Interface Signals (Sheet 3 of 3)

Signal Name Type Description

Primary PCI interface STOP#. Signal p_stop_l is driven by the target of a transaction,
indicating that the target is requesting the initiator to stop the transaction on the
primary bus.

• When p_stop_l is asserted in conjunction with p_trdy_l and p_devsel_l assertion,
a disconnect with data transfer is being signaled.

• When p_stop_l and p_devsel_l are asserted, but p_trdy_l is deasserted, a target

p_stop_l STS

p_trdy_l STS

disconnect without data transfer is being signaled. When this occurs on the first
data phase, that is, no data is transferred during the t ransaction, this is referred to
as a target retry.

• When p_stop_l is asserted and p_devsel_l is deasserted, the target is signaling a
target abort.

Upon completion of a transaction, p_stop_l is driven to a deasserted state for one
clock cycle and is then sustained by an external pull-up resistor.

Primary PCI interface TRDY#. Signal p_trdy_l is driven by the target of a transaction
to indicate the target's ability to complete the current data phase on the primary PCI
bus. During a write transaction, assertion of p_trdy_l indicates that the target is able to
accept write data for the current data phase. During a read transaction, assertion of
p_trdy_l indicates that the target is driving valid read data on the p_ad bus. Once
asserted during a given data phase, p_trdy_l is not deasserted until the data phase
completes. Upon completion of a transaction, p_trdy_l is driven to a deasserted state
for one clock cycle and is then sustained by an external pull-up resistor.

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21554 PCI-to-PCI Bridge for Embedded Applications User’s Manual

Signal Pins

3.2 Primary PCI Bus Interface 64-Bit Extension Signals

Table 3-4 describes the primary PCI bus interface 64-bit extension signals.

Table 3-4. Primary PCI Bus Interface 64-Bit Extension Signals

Signal Name Type Description

Primary PCI interface acknowledge 64-bit transfer. Signal p_ack64_l is asserted by

the target only when p_req64_l is asserted by the initiator, to indicate the target’s

p_ack64_l STS

p_ad[63:32] TS

p_cbe_l[7:4] TS

p_par64 TS

p_req64_l STS

ability to transfer data using 64 bits. Signal p_ack64_l has the same timing as
p_devsel_l. When deasserting, p_ack64_l is driven to a deasserted state for one clock
cycle and is then sustained by an external pull-up resistor.

Primary PCI interface address/data upper 32 bits. This multiplexed address and data
bus provides an additional 32 bits to the primary interface. During the address phase
or phases of a transaction, when the dual-address command is used and p_req64_l
is asserted, the initiator drives the upper 32 bits of a 64-bit address; otherwise, these
bits are undefined, and the initiator drives a valid logic level onto the pins. During the
data phases of a transaction, the initiator drives the upper 32 bits of 64-bit write data,
or the target drives the upper 32 bits of 64-bit read data, when p_req64_l and
p_ack64_l are both asserted. When not driven, signals p_ad[63:32] are pulled up to a
valid logic level through external resistors.

Primary PCI interface command/byte enables upper 4 bits. These signals are a
multiplexed command field and byte enable field. During the address phase or phases
of a transaction, when the dual-address command is used and p_req64_l is asserted,
the initiator drives the transaction type on p_cbe_l[7:4]; otherwise, these bits are
undefined, and the initiator drives a valid logic level onto the pins. For both read and
write transactions, the initiator drives byte enables for the p_ad[63:32] data bits on
p_cbe_l[7:4] during the data phases, when p_req64_l and p_ack64_l are both
asserted. When not driven, signals p_cbe_l[7:4] are pulled up to a valid logic level
through external resistors.

Primary PCI interface upper 32 bits parity. Signal p_par64 carries the even parity of
the 36 bits of p_ad[63:32] and p_cbe_l[7:4] for both address and data phases. Signal
p_par64 is driven by the initiator and is valid one clock cycle after the first address
phase when a dual-address command is used and p_req64_l is asserted. Signal
p_par64 is also valid one clock cycle after the second address phase of a
dual-address transaction when p_req64_l is asserted. Signal p_par64 is valid one
clock cycle after valid data is driven (indicated by assertion of p_irdy_l for write data
and p_trdy_l for read data), when both p_req64_l and p_ack64_l are asserted for that
data phase. Signal p_par64 is tristated by the device driving read or write data one
clock cycle after the p_ad lines are tristated. Devices receiving data sample p_par64
as an input to check for possible parity errors during 64-bit transactions. When not
driven, p_par64 is pulled up to a valid logic level through external resistors.

Primary PCI interface request 64-bit transfer. Signal p_req64_l is asserted by the
initiator to indicate that the initiator is requesting 64-bit data transfer. Signal p_req64_l
has the same timing as p_frame_l. When deasserting, p_req64_l is driven to a
deasserted state for one clock cycle and is then sustained by an external pull-up
resistor. The 21554 samples p_req64_l during primary bus reset to enable the 64-bit
extension signals. If p_req64_l is sampled high during reset, the primary 64-bit
extension is disabled and assumed not connected. The 21554 then drives
p_ad[63:32], p_cbe_l[7:4], and p_par64 to valid logic levels.

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Signal Pins

3.3 Secondary PCI Bus Interface Signals

Table 3-5 describes the secondary PCI bus interface signals.

Table 3-5. Secondary PCI Bus Interface Signals (Sheet 1 of 2)

Signal Name Type Description

Secondary PCI interface address/data. These signals are a 32-bit multiplexed
address and data bus. During the address phase or phases of a transaction, the

s_ad[31:0] TS

s_cbe_l[3:0] TS

s_devsel_l STS

s_frame_l STS

s_idsel I

s_inta_l OD

s_irdy_l STS

initiator drives a physical address on s_ad[31:0]. During the data phases of a
transaction, the initiator drives write data, or the target drives read data, on
s_ad[31:0]. When the secondary PCI bus is idle, the 21554 drives s_ad to a valid
logic level when its secondary bus grant is asserted.

Secondary PCI interface command/byte enables. These signals are a multiplexed
command field and byte enable field. During the address phase or phases of a
transaction, the initiator drives the transaction type on s_cbe_l[3:0]. When there are
two address phases, the first address phase carries the dual-address command and
the second address phase carries the transaction type. For both read and write
transactions, the initiator drives byte enables on s_cbe_l[3:0] during the data phases.
When the secondary PCI bus is idle, the 21554 drives s_cbe_l to a valid logic level
when its secondary bus grant is asserted.

Secondary PCI interface DEVSEL#. Signal s_devsel_l is asserted by the target,
indicating that the device is responding to the transaction. As a target, the 21554
decodes the address of a transaction initiated on the secondary bus to determine
whether to assert s_devsel_l. As an initiator of a transaction on the secondary bus,
the 21554 looks for the assertion of s_devsel_l within five clock cycles of s_frame_l
assertion; otherwise, the 21554 terminates the transaction with a master abort. Upon
completion of a transaction, s_devsel_l is driven to a deasserted state for one c lock
cycle and is then sustained by an external pull-up resistor.

Secondary PCI interface FRAME#. Signal s_frame_l is driven by the initiator of a
transaction to indicate the beginning and duration of an access on the secondary PCI
bus. Signal s_frame_l assertion (falling edge) indicates the beginning of a PCI
transaction. While s_frame_l remains asserted, data transfers can continue. The
deassertion of s_frame_l indicates the final data phase requested by the initiator.
Upon completion of a transaction, s_frame_l is driven to a deasserted state for one
clock cycle and is then sustained by an external pull-up resistor.

Secondary PCI interface IDSEL. Signal s_idsel is used as the chip select line for Type
0 configuration accesses to 21554 configuration space from the secondary bus. When
s_idsel is asserted during the address phase of a Type 0 configuration transaction, the
21554 responds to the transaction by asserting s_devsel_l.

Secondary PCI bus interrupt. Signal s_inta_l is asserted by the 21554 when:

• A secondary doorbell register bit is set.

• The I

• A page boundary is reached when performing lookup table address translation.

• The 21554 transitions from a D1 or D2 power state to a D0 power state.

All of these conditions are individually maskable. Signal s_inta_l is deasserted when
the corresponding event bit is cleared, or when the I
Signal s_inta_l is pulled up through an external resistor.

Secondary PCI interface IRDY#. Signal s_irdy_l is driven by the initiator of a
transaction to indicate the initiator's ability to complete the current data phase on the
secondary PCI bus. During a write transaction, assertion of s_irdy_l indicates that
valid write data is being driven on the s_ad bus. During a read transaction, assertion
of s_irdy_l indicates that the initiator is able to accept read data for the current data
phase. Once asserted during a given data phase, s_irdy_l is not deasserted until the
data phase completes. Upon completion of a transaction, s_irdy_l is driven to a
deasserted state for one clock cycle and is then sustained by an external pull-up
resistor.

O inbound queue is not empty.

2

O inbound queue is empty.

2

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21554 PCI-to-PCI Bridge for Embedded Applications User’s Manual

Table 3-5. Secondary PCI Bus Interface Signals (Sheet 2 of 2)

Signal Name Type Description

Secondary PCI interface parity. Signal s_par carries the even parity of the 36 bits of
s_ad[31:0] and s_cbe_l[3:0] for both address and data phases. Signal s_par is driven
by the same agent that drives the address (for address parity) or the data (for data
parity). Signal s_par contains valid parity one clock cycle after the address is valid
(indicated by assertion of s_frame_l), or one clock cycle after the data is valid

s_par TS

s_perr_l STS

s_serr_l OD

s_stop_l STS

s_trdy_l STS

(indicated by assertion of s_irdy_l for write transactions and s_trdy_l for read
transactions). Signal s_par is tristated one clock cycle after the s_ad lines are
tristated. The device receiving data samples s_par as an input to check for possible
parity errors. When the secondary PCI bus is idle, the 21554 drives s_par to a valid
logic level when its secondary bus grant is asserted (one clock cycle after the s_ad
bus is parked).

Secondary PCI interface PERR#. Signal s_perr_l is asserted when a data parity error
is detected for data received on the secondary interface. The timing of s_perr_l
corresponds to s_par driven one clock cycle earlier, and s_ad driven two clock cycles
earlier. Signal s_perr_l is asserted by the target during write transactions, and by the
initiator during read transactions. Upon completion of a transaction, s_perr_l is driven
to a deasserted state for one clock cycle and is then sustained by an external pull-up
resistor.

Secondary PCI interface SERR#. Signal s_serr_l can be driven low by any device on
the secondary bus to indicate a system error condition. The 21554 also samples
s_serr_l as an input and conditionally forwards it to the primary bus on p_serr_l. The
21554 can conditionally assert s_serr_l for the following reasons:

• Secondary bus address parity error

• Upstream posted write data parity error on primary bus

• Master abort during upstream posted write transaction

• Tar get abort during upstream posted write transaction

• Upstream posted write transaction discarded

• Upstream delayed write request discarded

• Upstream delayed read request discarded

• Upstream delayed transaction master timeout

Signal s_serr_l is pulled up through an external resistor.
Secondary PCI interface STOP#. Signal s_stop_l is driven by the target of a

transaction, indicating that the target is requesting the initiator to stop the transaction
on the secondary bus.

• When s_stop_l is asserted in conjunction with s_trdy_l and s_devsel_l assertion,
a disconnect with data transfer is being signaled.

• When s_stop_l and s_devsel_l are asserted, but s_trdy_l is deasserted, a target
disconnect without data transfer is being signaled. When this occurs on the first
data phase, that is, no data is transferred during the transaction, this is referred to
as a target retry.

• When s_stop_l is asserted and s_devsel_l is deasserted, the target is signaling a
target abort.

Upon completion of a transaction, s_stop_l is driven to a deasserted state for one
clock cycle and is then sustained by an external pull-up resistor.

Secondary PCI interface TRDY#. Signal s_trdy_l is driven by the target of a transaction
to indicate the target's ability to complete th e cur rent data phase on the secondary PCI
bus. During a write transaction, assertion of s_trdy_l indicates that the target is able to
accept write data for the current data phase. During a read transaction, assertion of
s_trdy_l indicates that the target is driving valid read data on the s_ad bus. Once
asserted during a given data phase, s_trdy_l is not deasserted until the data phase
completes. Upon completion of a transaction, s_trdy_l is driven to a deasserted state for
one clock cycle and is then sustained by an external pull-up resistor.

Signal Pins

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Signal Pins

3.4 Secondary PCI Bus Interface 64-Bit Extension
Signals

Table 3-6 describes the secondary PCI bus interface 64-bit extension signals.

Table 3-6. Secondary PCI Bus Interface 64-Bit Extension Signals

Signal Name Type Description

Secondary PCI interface acknowledge 64-bit transfer. Signal s_ack64_l is asserted

by the target only when s_req64_l is asserted by the initiator, to indicate the target’s

s_ack64_l STS

s_ad[63:32] TS

s_cbe_l[7:4] TS

s_par64 TS

s_req64_l STS

ability to transfer data using 64 bits. Signal s_ack64_l has the same timing as
s_devsel_l. When deasserting, s_ack64_l is driven to a deasserted state for one clock
cycle and is then sustained by an external pull-up resistor.

Secondary PCI interface address/data upper 32 bits. This multiplexed address and
data bus provides an additional 32 bits to the secondary interface. During the address
phase or phases of a transaction, when the dual-address command is used and
s_req64_l is asserted, the initiator drives the upper 32 bits of a 64 -bit address;
otherwise, these bits are undefined, and the initiator drives a valid logic level onto the
pins. During the data phases of a transaction, the initiator drives the upper 32 bits of
64-bit write data, or the target drives the upper 32 bits of 64-bit read data, when
s_req64_l and s_ack64_l are both asserted. When not driven, signals s_ad[63:32]
are pulled up to a valid logic level through external resistors.

Secondary PCI interface command/byte enables upper 4 bits. These signals are a
multiplexed command field and byte enable field. During the address phase or phases
of a transaction, when the dual-address command is used and s_req64_l is asserted,
the initiator drives the transaction type on s_cbe_l[7:4]; otherwise, these bits are
undefined, and the initiator drives a valid logic level onto the pins. For both read and
write transactions, the initiator drives byte enables for the s_ad[63:32] data bits on
s_cbe_l[7:4] during the data phases, when s_req64_l and s_ack64_l are both
asserted. When not driven, signals s_cbe_l[7:4] are pulled up to a valid logic level
through external resistors.

Secondary PCI interface upper 32 bits parity. Signal s_par64 carries the even parity
of the 36 bits of s_ad[63:32] and s_cbe_l[7:4] for both address and data phases.
Signal s_par64 is driven by the initiator and is valid one clock cycle after the first
address phase when a dual-address command is used and s_req64_l is asserted.
Signal s_par64 is also valid one clock cycle after the second address phase of a
dual-address transaction when s_req64_l is asserted. Signal s_par64 is valid one
clock cycle after valid data is driven (indicated by assertion of s_irdy_l for write data
and s_trdy_l for read data), when both s_req64_l and s_ack64_l are asserted for that
data phase. Signal s_par64 is tristated by the device driving read or write data one
clock cycle after the s_ad lines are tristated. Devices receiving data sample s_par64
as an input to check for possible parity errors during 64-bit transactions. When not
driven, s_par64 is pulled up to a valid logic level through external resistors.

Secondary PCI interface request 64-bit transfer. Signal s_req64_l is asserted by the
initiator to indicate that the initiator is requesting 64-bit data transfer . Signal s_req64_l
has the same timing as s_frame_l. If the 21554 is the secondary bus central function,
it will assert s_req64_l low during secondary bus reset to indicate that a 64-bit bus is
supported. When deasserting, s_req64_l is driven to a deasserted state for one clock
cycle and is then sustained by an external pull-up resistor. The 21554 samples
s_req64_l during secondary bus reset to enable the 64-bit extension signals. If
s_req64_l is sampled high during reset, the secondary 64-bit extension is disabled
and assumed not connected. The 21554 then drives s_ad[63:32], s_cbe_l[7:4], and
s_par64 to valid logic levels.

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21554 PCI-to-PCI Bridge for Embedded Applications User’s Manual

3.5 Secondary PCI Bus Arbitration Signals

Table 3-7 describes the secondary PCI bus arbitration signals.

Table 3-7. Secondary PCI Bus Arbitration Signals

Signal Name Type Description

Secondary PCI interface GNT#s. The 21554 secondary bus arbiter can assert one of
nine secondary bus grant outputs, s_gnt_l[8:0], to indicate that an initiator can start a
transaction on the secondary bus if the bus is idle. The 21554’s secondary bus grant

s_gnt_l[8:0] TS

s_req_l[8:0] I

is an internal signal. A programmable two-level rotating priority algorithm is used. If
the internal arbiter is disabled, s_gnt_l[0] is reconfigured to be an external secondary
bus request output for the 21554. The 21554 asserts this signal whenever it wants to
start a transaction on the secondary bus.

Secondary PCI interface REQ#s. The 21554 accepts nine request inputs,
s_req_l[8:0], into its secondary bus arbiter. The 21554 request input to the arbiter is
an internal signal. Each request input can be programmed to be in either a
high-priority rotating group or a low-priority rotating group. An asserted level on an
s_req_l pin indicates that the corresponding master wants to initiate a transaction on
the secondary PCI bus. If the internal arbiter is disabled, s_req_l[0] is reconfigured to
be an external secondary grant input for the 21554. In this case, an asserted level on
s_req_l[0] indicates that the 21554 can start a transaction on the secondary PCI bus if
the bus is idle.

Signal Pins

3.6 Clock Signals

Table 3-8 describ es the clock signal s.

Table 3-8. Clock Signals

Signal Name Type Description

Primary interface PCI CLK. This signal provides timing for all transactions on the

p_clk I

s_clk I

s_clk_o O

primary PCI bus. All primary PCI inputs are sampled on the rising edge of p_clk, and
all primary PCI outputs are driven from the rising edge of p_clk. Frequencies
supported by the 21554 range from 0 MHz to 33 MHz.

Secondary interface PCI CLK. This signal provides timing for all transactions on the
secondary PCI bus. All secondary PCI inputs are sampled on the rising edge of s_clk,
and all secondary PCI outputs are driven from the rising edge of s_clk. Frequencies
supported by the 21554 range from 0 MHz to 33 MHz.

Secondary interface PCI CLK output. This signal is generated from the primary
interface clock input, p_clk. This clock operates at the same frequency of p_clk and
may be externally buffered to create secondary bus device clock signals. When
buffered clocks are used, one of the clock outputs must be fed back to the secondary
clock input, s_clk. This clock output can be disabled by writing the secondary clock
disable bit in configuration space, or by pulling pr_ad[5] low during reset.

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Signal Pins

3.7 Power Management, Hot Swap, and Reset Signals

Table 3-9 describes the power management, hot swap, and reset signals.

Table 3-9. Power Management, Hot Swap, and Reset Signals

Signal Name Type Description

Compact PCI hot swap local status pin. As an input to the 21554, this signal indicates
the sense of the ejector switch and therefore the state of the LED in a Compact PCI

l_stat TS

p_enum_l OD

p_pme_l OD

p_rst_l I

s_pme_l I

s_rst_l O

card supporting distributed hot-swap. As an output from the 21554, it controls the LED.
If compact PCI hot swap is not supported by the add-in card, this signal should be tied

low through a resistor.
Primary bus compact PCI hot swap event. Conditionally asserted by the 21554, this

signal indicates either that the card has been inserted and is ready for configuration,
or that the card is about to be removed. This signal is deasserted when the
corresponding insertion or removal event bit is cleared.

This signal should be pulled up by an external resistor.
Primary bus power management event. Provides power management signaling

capability on behalf of the subsystem. The 21554 asserts p_pme_l when all of the
following are true:

• Signal s_pme_l is asserted low.

• Signal p_pme_l is supported in the current power state.

• PME_EN bit is set.

Once asserted, p_pme_l is deasserted when the PME status bit or the PME_EN bit is
cleared. If the PME# isolation circuitry is needed, it must be implemented externally.

Primary PCI bus RST#. Signal p_rst_l forces the 21554 to a known state. All register
state is cleared, and all PCI bus outputs are tristated, with the possible exception of
s_ad, s_cbe_l, s_par, and s_req64_l. Signal p_rst_l is asynchronous to p_clk.

Secondary bus power management event. The subsystem asserts this signal to the
21554 to indicate that it is signaling a power management event. The 21554
conditionally asserts p_pme_l when s_pme_l is asserted low.

If the subsystem does not generate power management events, this signal can also
be used for a subsystem status signal. A deasserting (rising) edge on this signal may
conditionally cause the 21554 to assert p_inta_l.

If this signal is not used, it should be tied high through a resistor.
Secondary PCI bus RST#. Signal s_rst_l is driven by the 21554 and acts as the PCI

reset for the secondary bus. The 21554 asserts s_rst_l when any of the following
conditions is met:

• Signal p_rst_l is asserted.

• The secondary reset bit in the reset control register in configuration space is set.

• The chip reset bit in the reset control register in configuration space is set.

• Power management transition from D3

When the 21554 asserts s_rst_l, it tristates all secondary control signals and, if
designated as the secondary bus central resource, asserts s_req64_l and drives
zeros on s_ad, s_cbe_l, and s_par. Signal s_rst_l remains asserted until p_rst_l is
deasserted, and the secondary reset bit is clear. Deassertion of s_rst_l occurs
automatically based on internal timers when s_rst_l assertion is caused by setting the
chip reset bit or a power management transition. Assertion of s_rst_l by itself does not
clear register state, and configuration registers are still accessible from the primary
PCI interface.

to D0 occurs.

hot

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21554 PCI-to-PCI Bridge for Embedded Applications User’s Manual

3.8 ROM Interface Signals

Table 3-10 describes the ROM interface signals.

Table 3-10. ROM Interface Signals (Sheet 1 of 2)

Signal Name Type Description

These signals interface to both the serial and parallel external ROM circuitry and have
multiple functions.

The signals pr_ad[7:0] serve as multiplexed address/data for the parallel ROM and
are latched externally in the following sequence:

• Address [23:16]

• Address [15:8]

• Address [7:0]

• Data [7:0]

The signals pr_ad[2:0] also serve as serial ROM signals, with no external logic
required:

• pr_ad[2] : sr_do, the serial ROM data output

• pr_ad[1] : sr_di, the serial ROM data input

• pr_ad[0] : sr_ck, the serial ROM clock output

During primary bus reset, external pull-up or pull-down resistors can be used on
signals pr_ad[7:2] to specify their state during reset. The values of these signals
during primary bus reset specify the following configuration options:

pr_ad[7]
During primary bus reset, pr_ad[7] specifies the arbiter enable configuration. If low,

the secondary bus arbiter is disabled, s_gnt_l[0] is used for 21554 secondary bus
request, and s_req_l[0] is used for 21554 secondary bus grant. If high, the internal
arbiter is enabled for use.

pr_ad[7:0] TS

pr_ad[6]
During primary bus reset, pr_ad[6] specifies the central function enable. If low, the

21554 asserts s_req64_l and drives s_ad, s_cbe_l, and s_par low during secondary
reset. If high, the 21554 tristates s_req64_l, s_ad, s_cbe_l, and s_par during
secondary reset.

pr_ad[5]
During primary bus reset, pr_ad[5] specifies the s_clk_o enable. If low, s_clk_o is

disabled and driven low. If high, s_clk_o is enabled and is a buffered version of p_clk.
pr_ad[4]
During primary bus reset, pr_ad[4] specifies synchronous enable. If high, the 21554

assumes asynchronous primary and secondary interfaces. If low, the 21554 assumes
synchronous primary and secondary interfaces.

pr_ad[3]
During primary bus reset, pr_ad[3] specifies the primary lockout bit reset value. If high,

the primary lockout bit is set high upon completion of chip reset, which causes the
21554 to return target retry to primary bus configuration transactions until the bit is
cleared. If low, the primary lockout bit is low upon completion of reset, which allows
immediate primary bus access to configuration registers.

pr_ad[2]
This signal should be biased high through a pull-up resistor. If the serial ROM is not

connected, the 21554 will not detect the pre-load enable sequence 10b. In this case,
the serial ROM preload is terminated after the first bit is read and the 21554 registers
remain at their reset values. This is not actually sampled at reset, but during the first
serial ROM read.

Signal Pins

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Signal Pins

Table 3-10. ROM Interface Signals (Sheet 2 of 2)

Signal Name Type Description

Parallel ROM address latch enable/chip select decoder enable. The signal pr_ale_l is
used to enable the parallel ROM address latches. The 21554 asserts pr_ale_l low
when it drives the first eight bits of the 24-bit address on pr_ad[7:0], and keeps it

pr_ale_l O

pr_clk O

pr_cs_l O/I

pr_rd_l O

pr_wr_l O

sr_cs O

asserted until the last eight bits of the address are driven. The upper bits of the
address are shifted through octal D-registers while pr_ale_l is low. When in multiple
device mode, pr_ale_l is also used for a chip select enable. When pr_ale_l is high,
the upper latched address lines are decoded with external circuitry to assert device
chip enables.

Parallel ROM address latch clock output. The signal pr_clk is used to clock the
address registers needed to de-multiplex the address, and is a buffered version of
p_clk divided by two.

Parallel ROM chip select or device ready. For a single device attachment, pr_cs_l is
used for the parallel ROM chip select. The 21554 asserts pr_cs_l low after the
address is shifted out and de-multiplexed through external octal registers. The 21554
deasserts pr_cs_l according to the access time specified in the ROM control CSR.
When in multiple device mode, pr_cs_l is reconfigured as a device ready (pr_rdy)
input. If pr_cs_l is driven low while the read or write strobe is asserted, the assertion
time of the read or write strobe is extended by the amount of time the device ready
signal is held low.

Parallel ROM read strobe. This signal controls the output enable signal of the parallel
ROM. The 21554 asserts pr_rd_l to enable the ROM to drive read data on pr_ad[7:0].
The 21554 samples this read data on the deasserting (rising) edge of pr_rd_l. The
timing of pr_rd_l with respect to the chip select is dictated by the read strobe mask.

Parallel RO M write strobe. This signal controls the write enable signal of the parallel
ROM. The 21554 asserts pr_wr_l when it drives write data to the ROM on pr_ad[7:0].
Write data is held stable until the deasserting (rising) edge of pr_wr_l. The timing of
pr_wr_l with respect to the chip select is dictated by the write strobe mask.

Serial ROM chip select. The 21554 drives this signal high to enable the serial ROM for
a read or write. The serial ROM operation uses pins pr_ad[2:0] for data in, data out,
and clock.

3.9 Miscellaneous Signals

Table 3-11. Miscellaneous Signals

3-12

Table 3-11 describes the miscellaneous signals.

Signal Name Type Description

Primary interface I/O voltage. This signal must be tied to either 3.3 V or 5.0 V,

p_vio I

s_vio I

corresponding to the signaling environment of the primary PCI bus as described in the

PCI Local Bus Specification, Revision 2.1

uses 5-V signaling levels, tie p_vio to 5.0 V. Signal p_vio is tied to 3.3 V only when all
the devices on the primary bus use 3.3-V signaling levels.

Secondary interface I/O voltage. This signal must be tied to either 3.3 V or 5.0 V ,
corresponding to the signaling environment of the secondary PCI bus as described in
the

PCI Local Bus Specification, Revision 2.1

bus uses 5-V signaling levels, tie s_vio to 5.0 V. Signal s_vio is tied to 3.3 V only when
all the devices on the secondary bus use 3.3-V signaling levels.

21554 PCI-to-PCI Bridge for Embedded Applications User’s Manual

. When any device on the primary PCI bus

. When any device on the secondary PCI

3.10 Diagnostic Signals

Table 3-12 describes JTAG and other diagnostic signals.

Table 3-12. JTAG Signals

Signal Name Type Description

Signal Pins

scan_ena I
tck I JTAG boundary-scan clock. Signal tck is the clock controlling the JTAG logic.

tdi I

tdo O

tms I

trst_l I

Scan enable input. This signal is used for chip test only and should be tied low
through an external resistor.

JTAG serial data in. Signal tdi is the serial input through which JTAG instructions and
test data enter the JTAG interface. The new data on tdi is sampled on the rising edge
of tck. An unterminated tdi produces the same result as if tdi were driven high.

JTAG serial data out . Signal tdo is the serial output through which test instructions and
data from the test logic leave the 21554.

JTAG test mode select. Signal tms causes state transitions in the test access port
(TAP) controller. An undriven tms has the same result as if it were driven high.

JTAG TAP reset. When asserted low, the TAP controller is asynchronously forced to
enter a reset state, which in turn asynchronously initializes other test logic. An
unterminated trst_l produces the same result as if trst_l were driven high.

21554 PCI-to-PCI Bridge for Embedded Applica tio ns User’ s Ma nua l

3-13

PCI Bus Operation

This chapter presents detailed information abo ut P CI transactions, transaction forwarding across
the 21554, and transaction termination.

4.1 PCI Bus Operation

The 21554 responds to transactions using the following commands as a target on both interfaces:

• All memory commands • Dual-address commands

• I/O read and write commands • Type 0 and Type 1 configuration commands

The 21554 does not respond to transactions using any other PCI commands.
The 21554 can initiate transactions using the following commands on either interface:

• All memory commands • Dual-address commands

• I/O read and write commands • Type 0 configuration com mands

The 21554 does not initiate transactions using any other PCI commands.

4

The 21554 responds to transactions by asserting DEVSEL# with medium timing. The 21554 may
also be enabled to subtractively decode I/O transactions in one direction only.

The 21554 supports linear increment address mode only, and disconnects memory transactions
whose low two address bits are not 00b after a single Dword.

4.1.1 Posted Write Transactions

The 21554 posts all memory write and memory write and invalidate (MWI) transactions that are to
be forwarded from one interface to the other. The 21554 accepts write data into its buffers without
wait states until the initiator ends the transaction, until an aligned address boundary is reached, or
until the posted write queue fills. Aligned address d isconnect boundaries for memory write and
MWI transactions are listed in Section 4.1.1.1 and Section 4.1.1.2, respectively.

The 21554 does not initiate a memory write transaction on the target bus until at least a cache line
amount of data is posted. If the transaction consists of less than a cache line, the 21554 waits until the
entire burst is posted. If the cache line size corresponding to the target bus is not set to a valid value, then
the 21554 uses a value of 8 Dwords for this purpose. Possible valid values are 4, 8, 16 and 32 Dwords.

The 21554 continues the transaction to the target as long as write data is availabl e or the transaction
has terminated on the initiator bus. Otherwise, the 21554 ends the transaction when a queue-empty
condition is detected or when all write data has been delivered for this transaction. The 21554 does
not insert master wait states when initiating posted writes.

21554 PCI-to-PCI Bridge for Embedded Applica tio ns User’ s Ma nua l

4-1

PCI Bus Operation

If the 21554 receives 224 consecutive target retries from the t ar get when att empt ing to deli ver post ed
write data, then the 21554 discards the posted write t ransacti on and condi t ionall y asse rts SER R# on
the initiator bus (see Chapter 14). The 21554 also conditionally asserts SERR # on the i nit i ator bus if
a target abort or master abort is detected on the target bus in response to the posted write.

4.1.1.1 Memory Write Transactions

As a target, the 21554 disconnects memory write transactions at the following address boundaries:

• An aligned 4KB address boundary

• An aligned page address boundary, for upstream transactions falling in the Upstream Memory

2 address range

• An aligned cache line boundary, when memory write Disconnect bit is set in configuration space

If the posted write queue fills before the master terminates the transaction, then the 21554 returns a
target disconnect when the last queue entry is filled.

As an initiator, when the 21554 has posted write data to deliver and the conditions listed in

Section 4.1.1.2 for initiating an MWI transaction are not met, the 21554 uses the memory write

command to deliver posted memory write data.

4.1.1.2 Memory Write and Invalidate T ransactions

As a target, the 21554 disconnects MWI transactions at the following address boundaries:

• An aligned 4 KB address boundary

• An aligned page address boundary, for upstream transactions falling in the Upstream Memory

2 address range

• An aligned cache line boundary, for MWI transactions when less than a cache line of available

space remains in the posted write queue

When a master initiates an MWI transaction, it guarantees that it will supply one full cache line of
data, or some multiple thereof. The 21554 initiates an MWI transaction on the target bus,
regardless of whether the bus command was a memory write or an MWI on the initiator bus,
whenever all of the following conditions are met:

• The MWI Enable bit is set in the Command register corresponding to the target interface.

• The target bus Cache Line Size is set to a valid value (4, 8, 16, or 32 Dwords).

• At least one aligned cache line of data has been posted.

• All byte enables for the posted cache line are turned on.

If any of these conditions is not met, the 21554 uses the memory write command.
The 21554 continues the MWI transaction as long as a full cache line (corresponding to the cache

line size of the target bus) is posted in the posted write queue. If this condition does not exist, then
the 21554 master terminates the transaction at the cache line boundary.

4-2

If the 21554 terminates an MWI transaction before all write data is delivered, then the 21554
initiates another write transaction to finish delivery of the write data. If a fraction of a cache line
remains, the 21554 initiates the transaction with the memory write command. If at least a complete
cache line was subsequently posted, then the 21554 once again initiates the transaction with an
MWI command.

21554 PCI-to-PCI Bridge for Embedded Applications User’s Manual

4.1.1.3 Posted Write Transactions Using the 64-bit Extension

The 21554 uses the 64-bit extension signals for accepting and delivering posted write data.

As a target, the 21554 asserts ACK64# in response to the initiator’s assertion of REQ64# for
memory writes and MWI commands if the address is quadword aligned (address bit AD[2] is zero).
The 21554 then accepts 64 bits of data per data phase without inserting target wait states.

As an initiator, the 21554 asserts REQ64# when delivering posted write data as long as the burst
consists of a minimum of 4 Dwords, and the original address is quadword aligned. If the target
asserts ACK64#, write data is delivered 64 bits per data phase without inserting master wait states.
If the burst ends on an odd Dword add ress b oundar y, the 21554 forces the hi gh fou r byt e enabl es of
the last data phase in the burst to be deasserted.

4.1.1.4 Write Performance Tuning Options

The 21554 implements several features and options that af fect write perfor mance when fo rwarding
posted write transactions.

Memory Write and Invalidate

When the MWI Enable bit in configuration space is set for that corresponding interface, the 21554
is enabled to initiate MWI transactions as described in Section 4.1.1.2.

PCI Bus Operation

Fast Back-to-Back

The 21554 may be enabled to initiate fast back-to-back transactions. The 21554 must have the bus
grant the clock cycle before it asserts FRAME# for the second transaction, and the Fast
Back-to-Back Enable bit must be set for the interface on which the 21554 is initiating the
transaction. If both of these conditions exist, the 21554 may initiate the second transaction with fast
back-to-back timing following a write transaction that is not terminated with STOP#.

Write Flow-Through

If the 21554 is able to obtain access to the target bus and start transferring write data to the target
before the transaction has been terminated on the initiator bus, then the 21554 automatically enters
flow-through mode. When in flow-through mode, the 21554 can sustain long write bursts as long
as a queue-empty condition is not detected, or until an aligned disconnect boundary is reached. If
the queue-empty condition is detected, the 21554 master terminates the transaction on the target
bus. If an aligned disconnect boundary is reached, the 21554 returns a target disconnect on the
initiator bus. Flow-through mode behavior is used for b oth m e mory write and MWI commands.

Memory Write Disconnect Mode

The 21554 implements a Memory Write Disconnect Mode bit in device specific configuration
space. When enabled, the 21554 disconnects memory writes on aligned cache line boundaries,
using the cache line size corresponding to the target bus.

Posted Write Queue Tuning

The 21554 implements a posted write queue management control bit for each posted write queue in the
Chip Control 1 configuration register . This bit specifies at what threshold the 21554 returns a target retry
instead of accepting write data. Setting this bit can minimize fragmentation of posted write transactions
and can prevent bursts from being broken into sub-cache line bursts. The tuning options are as follows:

• Target retry is returned when less then a cache line is free.

• T arget retry is returned when less then half a cache line is free, for CLS = 8, 16, or 32 Dwords.

A full cache line threshold is used for CLS = 4.

21554 PCI-to-PCI Bridge for Embedded Applica tio ns User’ s Ma nua l

4-3

PCI Bus Operation

4.1.2 Delayed Write Transactions

The 21554 uses delayed transactions when forwarding I/O writes from one PCI interface to the
other. Delayed transactions are also used for CSR or configuration register writes that cause the
21554 to initiate a transaction on the opposite interface, such as:

• CSR or configuration register write access that causes the 21554 to initiate a configuration

write transaction

• CSR write access that causes the 21554 to initiate an I/O write transaction

When an I/O write intended for the opposite PCI bus is first initiated, the 21554 returns a target
retry. If the delayed transaction queue is not full, the 21554 qu e ues the transaction information,
including address, bus command, write data, and byte enables.

If the transaction queued is a result of an I/O or Configuration Data register write, the 21554
queues the appropriate data based on the type of access desired, the address and data contained in
the corresponding registers, and the byte enables used for the register access. This phase of the
delayed transaction is called a delayed write request (DWR).

The 21554 requests the target bus and initiates the delayed write transaction as soon as the 21554
ordering rules allow (see Section 4.1.5). The 21554 always performs a single 32-bit data phase
when initiating a delayed write transaction. The 21554 completes the transaction on the target bus
and adds the completion status to the queue. Completion status contains the type of termination
(TRDY#, target abort, master abort) and whether PERR# assertion was detected. This phase of the
delayed transaction is called the delayed write completion (DWC).

If the 21554 receives 2
delayed write request and conditionally asserts SERR# on the initiator bus (see Chapter 14). If the
transaction is discarded before completion, the 21 554 returns a target abort to the initiator.

24

consecutive target retries from the target, then the 21554 discards the

When the initiator repeats the transaction using the same address, bus command, write data, and
byte enables, then the 21554 returns the appropriate target termination when ordering rules allow.
Otherwise, the 21554 continues to return target retry. The target terminations (Table 4-1) returned
are as follows:

Table 4-1. Delayed Write Transaction Target Termination Returns

Target Bus Response Initiator Bus Response

TRDY# TRDY# (and STOP# if multiple data phases requested)
Target abort Target abort

Master abort

TRDY# (if Master Abort Mode bit = 0)
Target abort (if Master Abort Mode bit = 1)

When the 21554 has a delayed completion to return to an initiator, and the initiator does not repeat
the transaction before the Master Time-Out Counter for that interface expires, then the 21554
discards the delayed completion transaction. If enabled to do so, the 21554 asserts SERR# on the
initiator bus. The Master Time-Out Counter expiration value is either 2
programmable in the Chip Control 0 configuration register. The Master Time-Out Counter is
disabled when the Master Time-Out Disable bit in the Chip Control 0 configuration register is zero.

10

or 215 PCI clock cycles,

4-4

21554 PCI-to-PCI Bridge for Embedded Applications User’s Manual

4.1.3 Delayed Read Transactions

The 21554 uses delayed transactions when forwarding any type of read (I/O, memory, memory
read line, and memory read multiple) from one PCI interface to the o ther. Delayed transactions are
also used for parallel ROM reads and CSR or configuration register reads that cause the 21554 to
initiate a PCI read transaction, such as:

• CSR or configuration register read access that causes the 21554 to initiate a configuration read

transaction

• CSR read access that causes the 21554 to initiate an I/O read transaction

The delayed read transaction protocol is similar to that of delayed write transactions, with the
exception that 64-bit transfers may be used for delayed-memory read tran saction s. When an I/O or
memory read intended for the other PCI bus is first initiate d, the 21554 returns a target retry. The
21554 queues the transaction information, including address, bus command, byte enables for
nonprefetchable reads, if the delayed transaction queue is not full.

If the transaction queued is a result of a CSR or configuration register read, the 21554 queues the
appropriate data based on the type of access desired, the address contained in the register, and the
byte enables used for the data register access. This phase of the delayed transaction is called a
delayed read request (DRR).

The 21554 requests the target bus and initiates the delayed read transaction as soon as the 21554
ordering rules allow. If the transaction is a nonprefetchable read as d escribed in Section 4.1.3.1, the
21554 requests on ly a s i ngle Dword of data. If the transaction is a memory read, the 21554 follows
the prefetch rules outlined in Section 4.1.3.2. The 21554 completes the transaction on the target bus
and adds the read data and parity to the read data queue and the completion status to the delayed
transaction queue. This phase of the delayed transaction is called the delayed read completion
(DRC). If the 21554 receives 2
the delayed read transaction and conditionally asserts SERR# on the initiator bus. If the transaction
is discarded before completion, the 21554 returns a target abort to the initiator.

24

consecutive target retries from the target, then the 21554 discards

PCI Bus Operation

When the initiator repeats the transaction using the same address, bus command, and byte enables,
then the 21554 returns the read data, parity, and appropriate target termination when ordering rul es
allow . For al l memory read t ype transacti on s, the 21554 alia ses the memory read, memory read l ine,
and memory read multiple commands when comparing a transacti on in the delayed t ransaction queue
to one initiated on the PCI bus. Therefore, regardless of the exact command us ed, if the address
matches, and both commands are any type of prefetchable memory read, then the 21554 consi ders it a
match. If there is no match or the ordering rules prevent returning the completion at that point , th e
21554 returns target retry. The target terminations (Table 4-2) returned are as follows:

Table 4-2. Delayed Read Transaction Target Termination Returns

Target Bus Response Initiator Bus Response

TRDY# TRDY# (and STOP# if returning last data and FRAME# is asserted)
Target abort Target abort

Master abort

TRDY# and FFFFFFFFh (if Master Abort Mode bit = 0)
Target abort (if Master Abort Mode bit = 1)

When the 21554 has a delayed completion to return to an initiator, and the initiator does not repeat
the transaction before the Master Time-out Counter for that interface expires, then the 21554
discards the delayed completion transaction. The Master Time-out Counter expiration value is
either 2

21554 PCI-to-PCI Bridge for Embedded Applica tio ns User’ s Ma nua l

10

or 215 PCI clock cycles, programmable in the Chip Control 0 configuration register.

4-5

PCI Bus Operation

4.1.3.1 Nonprefetchable Reads

The following transactions are considered by the 21554 to be nonprefetchable:

• I/O transactions

• Configuration transactions

• Transaction s using the m emory r ead co mmand th at add ress a rang e config ured as n onpre fetcha ble

• Primary bus memory reads to the Expansion ROM BAR

When initiating a nonprefetchable read, the 21554 requests only a single Dword of read data from
the target. The 21554 uses the same byte enables driven by the initiator of the transacti on.

When the 21554 returns the read data to the initiator, it target-disconnects at completion of the first
data phase if the initiator is requesting multiple Dwords.

4.1.3.2 Prefetchable Reads

The following transactions are considered by the 21554 to be prefetchable read transactions:

• Transactions using the memory read line command

• Transactions using the memory read multiple command

• Transactions using the memory read command that address a range configured as prefetchable

During a prefetchable read, the 21554 speculatively reads data from the target before the initiator
explicitly requests it. The amount of data read depends on the read command, the cache line size
corresponding to the initiator bus, and whether the 21554 is in flow-through mode, as described in

Table 4-3. The 21554 drives the byte enables to 0h for all data phases, regardless of the byte

enables driven by the initiator of the transaction.
When the 21554 returns prefetchable read data to the initiator, it continues to return read data until

the master deasserts FRAME# and IRDY# ending the transaction, or until the 21554 runs out of
read data and the target disconnect is returned. If the master terminates the transaction, the 21554
discards the unconsumed read data.

4.1.3.3 Prefetchable Read Transactions Using the 64-bit Extension

The 21554 uses the 64-bit extension signals when implemented, to initiate and complete
prefetchable read transactions.

As a target, the 21554 asserts ACK64# in response to the initiator’s assertion of REQ64# for
prefetchable memory read transactions where the 21554 has more than 1 Dword of data to return.
The 21554 returns 64 bits of data per data phase without inserting target wait states, with the
exception of a temporary queue-empty condition during flow-through. If the 21554 has an odd
number of Dwords to return to the initiator, it disconnects before delivering the last Dword. The
last Dword is discarded.

As an initiator, the 21554 asserts REQ64# for all prefetchable memory reads that have a starting
address on an aligned quadword boundary (that is, add ress bit AD[ 2] = 0). The 21554 then accepts
64 bits of read data per data phase without inserting master wa it states.

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21554 PCI-to-PCI Bridge for Embedded Applications User’s Manual

4.1.3.4 Read Performance Features and Tuning Options

The 21554 implements several features and options that affect read performance when forwarding
prefetchable read transactions.

Read Flow-Through

When the bandwidth of the initiator PCI interface is less than or equal to the bandwidth of the
target PCI interface, the 21554 may use f low-thro ugh , o r streaming , o peration when retu rning read
data. If the initiator of a delayed prefetchable read transaction repeats the transaction, and the
21554 starts delivering read data on the initiator bus while it is still accepting data for that
transaction on the target bus, the 21554 enters read flow-through mode. When in flow-through
mode, the 21554 can sustai n long read bu rsts up to a 4KB alig ned address bou ndary, or up to a page
address boundary for upstream transactions falling into Memory Range 2. If the read data queue
empties while the 21554 is in flow-through mode, the 21554 waits up to seven cycles and then
disconnects if read data is still not available.

Prefetching

The 21554 prefetches read data to the aligned address boundaries shown in Table 4-3.

Table 4-3. Prefetch Boundaries

PCI Bus Operation

Read Command

Memory Read 1 Dword 1 cache line

Memory Read Line 1 cache line 1 cache line

Memory Read
Multiple

Non-prefetchable
Range

2 cache lines 2 cache lines

Prefetchable
Range

In Flow-Through Mode

Page boundary for transactions in Upstream
Memory 2 range

4KB boundary
Initiator deasserts FRAME#
Page boundary for transactions in Upstream

Memory 2 range
4 KB boundary
Initiator deasserts FRAME#
Page boundary for transactions in Upstream

Memory 2 range
4 KB boundary
Initiator deasserts FRAME#

The cache line size corresponding to the initiator bus is used for determining prefetch boundaries.

Read Queue Full Threshold Tuning

The 21554 implements read queue management control bits for each read data queue in the Chip
Control 1 configuration register. These bits specify at what read-queue threshold the 21554
initiates a delayed prefetchable read transaction on the target bus. Use of these bits can minimize
fragmentation of prefetchable read bursts. The encoding and behavior of these bits are as follows:

• 00b: at least eight Dwords free in read data queue for all memory read commands

• 01b: at least eight Dwords free for all memory read commands (same as 00b)

• 10b: at least one cache line free for MRL and MRM, eight Dwords free for memory read

• 11b: at least one cache line free for all memory read commands

In these cases, the initiator bus cache line size is used. If the cache line size is not set to a valid
value, then 8 Dwords is used for the read queue threshold.

21554 PCI-to-PCI Bridge for Embedded Applica tio ns User’ s Ma nua l

4-7

PCI Bus Operation

4.1.4 Target Terminations

This section describes target retries, target disconnects, and target aborts received and returned by
the 21554.

4.1.4.1 Target Terminations Returned by the 21554

The 21554 returns a target retry under the following circumstances:

• Queue is full for posted memory writes.

• Delayed transaction is queued but response is not ready.

• Queue is full for delayed transactions (delayed transaction not queued).

• Serial preload is ongoing.

• Primary Lockout Bit is set.

• Transaction is in progress for CSR generation of I/O or Configuration Access (delayed

transaction not ready).

The 21554 returns a target disconnect under the following circumstances:

• Queue fills during posted write.

• Cache line boundary is reached for MWI transaction and the 21554 cannot buffer another.

• Cache line boundary is reached for memory write transaction and the Memory Write

Disconnect bit is set.

• The 21554 runs out of read data during completion of delay e d transaction to the initiator.

• Read transaction is nonprefetchable and multiple data ph ases are requested by the initiator.

• Multiple data phases requested by the initiator for an I/O or configuration access.

• Low two address bits are non-zero.

The 21554 returns a target abort and sets the Signaled Target Abort bit in the Primary or Secondary
Status register under the following circumstances:

• Target abort is detected during a delayed transaction completion on the target bus.

• Master abort is detected in response to a delayed transaction on the target bus when the Master

Abort Mode bit is set to a 1.

• Delayed transaction request is discarded after 2

24

target retries received from the target.

• Invalid lookup table entry is encountered wh en f orward ing upstream transactions in Upstream

Memory 2 range and the Master Abort Mode bit is set to a 1.

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21554 PCI-to-PCI Bridge for Embedded Applications User’s Manual

4.1.4.2 Transaction Termination Errors on the Target Bus

When the 21554 detects a target abort on the target bus, the 21554 sets the Target Abort Received in
the Primary or Secondary Status configuration regist er. In addition, the 21554 does the following:

• For delayed transactions, returns a target abort to the initiator and sets the Signaled Target

Abort bit in the Primary or Secondary Status configuration register

• For posted write transactions, asserts SERR# on the initiator bus if the SERR# Enable for that

interface is set, and sets the Signaled System Error bit in the Primary or Secondary Status
configuration register

When the 21554 detects a master abort on the target bus, the 21554 always sets Master Abort Received
bit in Primary or Secondary Status configuration register. In addition, the 21554 does the foll owing:

• For delayed transactions when the Master Abort Mode bit is 0, returns TRDY# and, for reads,

FFFFFFFFh to the initiator

• For delayed transactions when the Master Abort Mode bit is 1, returns a targ et abort and sets

the Signaled Target Abort bit in the Primary or Secondary Status configuration register

• For posted write transactions, if SERR# Enable is set on the initiator bus interface and if SERR#

Disable for Master Abort duri ng Posted Write is clear, then t he Signaled Syst em Error bit is set in
the Primary or Secondary Status register and SERR# is assert ed on t he in it iator b us.

PCI Bus Operation

4.1.5 Ordering Rules

The 21554 can queue and forward multiple transactions at once. Therefore, at any one time the 21554
may have multiple posted write and multiple delayed transaction requests and completions queued
and traveling in the same and opposite directions. The 21554 uses a set of orderi ng rules to dictate the
order in which it initiates posted writes, initiates delayed transaction requests, and returns delayed
transaction completion status. These rules reflect bot h the ordering constraints outlined in t he PCI
Local Bus Specification, Revision 2.1 as well as implementation choices specific to the 21554.

Independent transactions on the primary and secondary buses only have a relationship when those
transactions cross the 21554. General ordering guidelines for transactions crossing the 21554 are:

• The ordering relationship of a transaction with respect to other transactions is determined

when the transaction completes; that is, when a transaction ends with a termination other than
target retry.

• Requests terminated with target retry may be accepted and co mpleted in any or der with respect

to other transactions that have been terminated wi th target retry. If the order of completion of
delayed requests is important, the initiator should no t start a second delayed transaction until
the first one has been completed.

• Write transactions flowing in one direction have no ordering requirements with respect to

write transactions flowing in the other direction. The 21554 can accept posted writes on both
interfaces at the same time, as well as initiate posted writes on both interfaces at the same time.

• The acceptance of a posted memory write as a target can never be contingent on the

completion of a non-posted transaction as a master. This is true of the 21554 and must also be
true of other bus agents; otherwise, a deadlock can occur.

• The 21554 accepts posted writes regardless of the state of completion of any delayed

transactions being forwarded across the bridge.

• A target retry in response to a posted write is allowed, but only due to temporary conditions,

such as a buffer-full condition.

21554 PCI-to-PCI Bridge for Embedded Applica tio ns User’ s Ma nua l

4-9

PCI Bus Operation

The ordering rules apply to posted write, delayed write and read request, and delayed write and
read completion transactions crossing the bridge in the same direction. Note that delayed
completions cross the bridge in the opposite direction of its respective delayed request. Table 4-4
shows the 21554 transaction ordering rules.

Table 4-4. 21554 Transaction Ordering Rules

↓ Pass→

Posted Write No Yes Yes Yes Yes
Delayed Read

Request
Delayed Write

Request
Delayed Read

Completion
Delayed Write

Completion

Posted
Write

No Yes Yes Yes Yes

No Yes Yes Yes Yes

No Yes Yes Yes Yes

Yes Yes Yes Yes Yes

Delayed Read
Request

Delayed Write
Request

Delayed Read
Completion

Delayed Write
Completion

The only ordering res triction t he 21554 enforces is ordering with respect to po sted write s. No ot her
transaction other than a delayed write completion can pass a posted write. Posted writes are
delivered in the order in which they are accepted.

Delayed transactions m ay be in itiat ed by the 21554 in an y o rder, and are not necessarily in itiated in
the order in which they are received. When the 21554 initiates a delayed transaction, the 21554
can behave in one of two ways. If the Delayed Transaction Ordering Control configuration bit is
not set, the 21554 uses a rotating fairness algorithm to select which delayed transaction it initiates
next, regardless of the type of target termination is returned (retry, TRDY#, etc.). If the Delayed
Transaction Ordering Control configuration bit is set, the 21554 continues to initiate the same
transaction until a response other than target retry is received.

Delayed completions are returned to the initiator when ready, regardless of the order in which
corresponding delayed requests were queued. A delayed read completion may not be returned to
the initiator (the initiator receives a target retry) if a posted write is ahead of the delayed completion
in the queues. That is, the write was posted in the direction of the complet ion, but before the read
data was queued. In this case the write must be delivered before the read data can be returned to
the initiator.

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21554 PCI-to-PCI Bridge for Embedded Applications User’s Manual

Address Decoding

This chapter presents information about address decoding.
The 21554 supports independent primary and secondary address maps. The 21554 implements

separate base address registers (BARs) on both the primary and secondary interfaces that denote
address ranges for downstream and upstream forwarding, respectively . The 21 554 also has primary
and secondary BARs denoting ranges for CSR access. On the primary interface, the 21554 only
responds to those transactions whose addresses fall into one of its primary BAR ranges. All other
I/O and memory transactions on the primary bus are ignored by the 21554. Similarly, on the
secondary interface, the 21554 respon ds only to tho se transactions whose addr esses reside in one of
the secondary BAR ranges. All other transactions on the secondary bus are ignored by the 21554.

The address ranges defined by the primary BARs reside in the primary, or system, address map.
The address ranges defined by the secondary BARs reside in the secondary, or local, address map.
The 21554 supports address translations between the two address maps when forwarding
transactions upstream or downstream.

As a target, the 21554 ignores any transactions that it initiates as a master.

5.1 21554 CSR Address Decoding

5

The 21554 implements a set of control and status registers that may be mapped in either memory or
I/O space. The registers are mapped independently on the primary and secondary interfaces. The
following BARs are used to map the 21554 CSRs:

• Primary CSR and Downstream Memory 0 BAR for mapping in primary bus memory address space

— Lower 4KB of this range used to map the 21554 CSRs

• Primary CSR I/O BAR for mapping in primary bus I/O space

• Secondary CSR Memory BAR for mapping in secondary bus memory address space

• Secondary CSR I/O BAR for mapping in secondary bus I/O space

The primary BARs are located in the 21554 primary bus configuration space, and the secondary
BARs are located in the 21554 secondary bus configuration space. The memory BARs request
4 KB each (minimum size for Primary CSR and Downstream Memory 0 BAR), and the I/O BARs
request 256 bytes each.

5.2 Expansion ROM Address Decoding

The 21554 implements one BAR, the Primary Expansion ROM BAR, to map the expansion ROM
that may be attached to the 21554. The Expansion ROM can be mapped into primary bus address
space only, and is not accessible through a BAR from the secondary bus. The size of the Primary
Expansion ROM BAR is programmable through the Primary Expansion ROM Setup register in
device-specific configuration space. The size may vary from 4 KB to 16 MB by powers of 2. The
Primary Expansion ROM BAR may also be disabled through the setup register so that it requests
no space if the expansion ROM is not implemented.

21554 PCI-to-PCI Bridge for Embedded Applica tio ns User’ s Ma nua l

5-1

Address Decoding

5.3 Memory Transaction Address Decoding

The 21554 implements four BARs on the primary interface and three BARs on the secondary
interface that may be enabled to decode and forward memory tran sactions to the opposite interface.
These BARs are:

• Primary CSR and Downstream Memory 0 BAR, for addresses above the low 4 KB in this

address range

• Downstream I/O or Memory 1 BAR

• Downstream Memory 2 BAR

• Downstream Memory 3 BAR

• Upstream I/O or Memory 0 BAR

• Upstream Memory 1 BAR

• Upstream Memory 2 BAR

The downstream BARs are located in primary configuration space and are used to decode
transactions on the primary bus to be forwarded to the secondary bus. The upstream BARs are
located in secondary configuration space and are used to decode transactions on the secondary bus
to be forwarded to the primary bus.

5.3.1 Using the BAR Setup Registers

All downstream and upstream BARs have programmable sizes, and may be disabled so that they
request no space. The Primary CSR and Downstream Memory 0 BAR cannot be totally disabled,
as the 21554 CSRs are always mapped in the bottom 4 KB. The forwarding p art of the range m ay be
disabled by requesting only 4KB of memory. (Table 5-2 summarizes the minimum and maximum
range for each address range.) In addition, the Downstream Memory 3 BAR can be configured to
be mapped in 64-bit address space. The register then comprises two 32-bit registers and can be
used for forwarding DACs downstream. 64 -bit addressing support is discussed further in

Section 5.3.4. These BARs can also be programmed to be prefetchable or non-prefetchable.

Programming of all the forwarding BARs with the exception of the Upstream Memory 2 BAR is
done through corresponding device-specific setup configuration registers. The Primary Expansion
ROM BAR also has a setup register. Setup registers are preloaded by the serial ROM and are also
writeable from the secondary interface. Each b it of the setup re gister corresponds to the same bit of
its respective BAR. Bit 0 of the Downstream I/O or Memory 1 Setup register and the Upstream I/O
or Memory 0 Setup register should be written with a 0 to select a memory BAR or a 1 to select an
I/O BAR. Bits [2:1] are writeable to select the type of memory mapping. The Downstream
Memory 3 Setup registers bits [2:1] may be set to 10b to select 64-bit addressing.

5-2

21554 PCI-to-PCI Bridge for Embedded Applications User’s Manual

A mask is used to set the size of the BAR for the remaining read/write bits of the setup register.

Writing a 1 sets the corresponding bit in that setup register’s BAR to be read/write. Writing a 0 sets
the corresponding bit in that setup register’s BAR to be read only as 0. Therefore, the size is set by
writing the appropriate number of most significant bits to a 1, and the remain ing bits to a 0. If all
the zeros and ones in the size field are not contiguous, this is illegal and unpredictable results may
occur. If the most significant writeable bit of the setup register is a 0, then the corresponding BAR
is disabled and requests no space. Figure 5-1 shows an example of using a setup register to
program a BAR to request 1 MB of memory space.

Figure 5-1. BAR Setup Register Example

Address Decoding

31 20 19

111111111111

31 0

bbbbbb

R/W (Base Address)

bbbbbb

Setup Register

0000000000000001000

20 19

000000000000000010000

Read Only

Base Address Register

FM-06126.AI7

0

21554 PCI-to-PCI Bridge for Embedded Applica tio ns User’ s Ma nua l

5-3

Address Decoding

5.3.2 Direct Address T ranslation

With the exception of secondary bus transactions falling into the Upstream Memory 2 address
range and all dual address transactions, the 21554 uses direct add ress translation when forwarding
memory transactions from one interface to the other. Note that since transactions addressing the
bottom 4 KB of the Primary CSR and Downstream Memory 0 BAR are targeted at the 21554
CSRs, no forwarding and therefore no address translation is performed. Direct address translation
is used for transactions in that range above the low 4 KB boundary.

A memory address may be thought of as a base address (as programmed in the Downstream and
Upstream BARs) with an offset from the base address, as shown in Figure 5-2.

Figure 5-2. Address Format

Address Map

Offset

Base Address

When a memory transaction is forwarded downstream from the primary bus to the secondary bus,
the primary bus address may be mapped to another address in the secondary bus domain by
substituting a new base address for the base of the original address, as shown in Figure 5-3. This
new base address, also called the translated base address, references a new location in the
secondary bus address map. The offset is not affected. The process is similar for transactions
forwarded from the secondary bus to the primary bus.

Figure 5-3. Direct Offset Address Translation

Base

Address

Base Offset

Offset

Original Address

FM-06127.AI7

5-4

Translated Base

Offset

Translated Address

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21554 PCI-to-PCI Bridge for Embedded Applications User’s Manual

Each memory address range using direct of fset add ress translation has its own translated b ase. The
translated base addresses are programmable in registers corresponding to each BAR. These
registers are mapped both in device-specific conf iguratio n space and in CSR space. The nu mber of
bits of the translated base address corresponds to the number of writeable bits in the respective
BAR. Likewise, the number of bits of the offset also varies and depends on the size of the BAR.

Figure 5-4 gives an example of address translation of downstream memory transactions. Again,

upstream transactions are treated similarly.

Figure 5-4. Downstream Address Translation Example

Primary Address Map Secondary Address Map

Base + Offset

Address Decoding

Translated
Base + Offset

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21554 PCI-to-PCI Bridge for Embedded Applica tio ns User’ s Ma nua l

5-5

Address Decoding

5.3.3 Lookup Table Based Address Translation

As mentioned previously, Upstream Memory 2 address translation is treated differently than the
other ranges. The 21554 uses a page size based lookup table to perform address translation for
transactions falling i nto this range. A lookup table pr ovides a fl exible way of tr anslatin g secondar y
bus local addresses to primary bus system addresses.

The Upstream Memory 2 address range consist s of a fixed number (64) of pages. The page size is
programmable in the Chip Control 1 configuration register. Therefore, the size of the Upstream
Memory 2 BAR is dependent on the page size. The page size varies between 256 bytes to 4 MB by
powers of 2. This results in a win dow s i ze that var ies fr om 1 6 KB to 256 MB. This BAR can also
be disabled.

Each page of the upstream window has a corresponding translated base address.
The size of the translated base address varies with the page size and window size. The translated

base address replaces both the original base address and the lookup table index bits. The address
bits used for the original base address for a given page and window size are shown in Table 5-1.
Also shown are the locations of the six address bits needed to select one of the 64 entries in the
lookup table. Finally, the offset of the address, which is not translated, consists of the remaining
lower order address bits. Table 5-1 shows the Upstream Memory 2 window size, wit h base address,
index, and offset fields.

Table 5-1. Upstream Memory 2 Window Size

Page Size
(bytes)

256 16K [31:14] [13:8] [7:0]
512 32K [31:15] [14:9] [8:0]
1K 64K [31:16] [15:10] [9:0]
2K 128K [31:17] [16:11] [10:0]
4K 256K [31:18] [17:12] [11: 0]
8K 512K [31:19] [18:13] [12:0]
16K 1M [31:20] [19:14] [13:0]
32K 2M [31:21] [20:15] [14:0]
64K 4M [31:22] [21:16] [15:0]
128K 8M [31:23] [22:17] [16:0]
256K 16M [31:24] [23:18] [17:0]
512K 32M [31:25] [24:19] [18:0]
1M 64M [31:26] [25:20] [19:0]
2M 128M [31:27] [26:21] [20:0]
4M 256M [31:28] [27:22] [21:0]

Window Size
(bytes)

Figure 5-5 shows how a translated address is built using t he lookup table, assuming a page size of 4KB.

Base Address
(bits)

Lookup T able Index
(bits)

Offset
(bits)

5-6

21554 PCI-to-PCI Bridge for Embedded Applications User’s Manual

Figure 5-5. Address Translation Using Lookup Table

Translated Base Look-up Table

Translated Base Address [3F]

3F

Translated Base Address [3E]

3E
3D
3C
3B
3A
39

Translated Base Address [Index]

7
6
5
4
3
2

Translated Base Address [1]

1

Translated Base Address [0]

0

Address Decoding

31 18 17 0

Base Index Offset

31 0

Translated Base

12 11

12 11

Offset

FM-06130.AI7

Figure 5-6 shows an exam ple of how different address regions might be forwarded upstream using

the lookup table address translation.
The lookup table is part of the memory space that the 21554 r equest s with it s Pr imar y CSR Memo ry

BAR and Secondary CSR Memory BAR. The lookup table is indirectly accessible in I/O or memory
space at offsets 24h and 28h. This table i s impl emented on -si licon. No ext ernal memory i s needed.

Figure 5-6. Upstream Lookup Table Address Translation

Primary Address Map Secondary Address Map

Translated
Base + Offset

The 21554 conditionally asserts s_inta_l when an upstream memory transaction transfers data
addressing the last Dword in a page. This interrupt alerts the local processor that the page entry
may need updating. The 21554 implements an event bit and interrupt mask bit for each of the 64
pages (entries) in the upstream window.

Base + Offset

FM-06131.AI7

Note: The page entry of the lookup table should not be updated while the in itiator is still performing

transactions addressing that page.

21554 PCI-to-PCI Bridge for Embedded Applica tio ns User’ s Ma nua l

5-7

Address Decoding

5.3.3.1 Lookup Table Entry Format

Figure 5-7 shows the format for an entry in the lookup table. The number of bits of the entry used

for the new translated base address is variable. The maximum number of bits used are bits [31:8],
corresponding to a 256-byte page size, while the minimum number of bits used are bits [31:22],
corresponding to a 4 MB page size. The next 4 to 18 bits, depending on the number o f bit s used for
the base address, are reserved. The low 4 bits are used for control. T wo control bits are defined, one
indicating whether the entry is a valid entry, and one indicating whether prefetchable behavior
should be used on memory reads. If the entry is not valid, then the 21554 treats the transaction
addressing that page as if a master abort were detected on the target interface. For writes, the 21554
discards memory write data and, if the Secondary SERR# Disable for Master Abort during Posted
Write bit is 0 and the SERR# Enable bit is 1, asserts s_serr_l. For reads, the 21554 returns
FFFFFFFFh on reads if the Master Abort Mode bit is 0, or returns a target abort if the Master Abort
Mode bit is a 1.

Note: The lookup table is not cleared by reset. The lookup table must be initialized by the local processor

before the Upstream Memory 2 Address range is used.

Figure 5-7. Lookup Table Entry Format

31 18 17 8 7 3 2410

Translated Base Address Reserved

Translated Base Address

or Reserved

Prefetchable

Reserved
Reserved

Valid

FM-06132.AI7

5.3.4 Forwarding of 64-Bit Address Memory Transactions

The 21554 considers the host and local memory space ab ove the 4 GB boundary to be shared. This
means that the 21554 uses a flat address map in this space. Dual-address cycle (DAC) transactions
are used for addressing above the 4 GB boundary. The 21554 can forward dual-address cycle
transactions both upstream and downstream. The Downstr eam Memory 3 BAR is used to d esignate
the address range for downstream DACs. Inverse decoding is used for upstream DACs.

The Downstream Memory 3 BAR may be configured to be a 64-bit BAR by preloading the
Downstream Memory 3 Upper 32 Bits Setup register bit [31] to a one. The Downstream Memory
3 Setup register bits [2:1] should be set to 10b. This implies that the memory range can be located
anywhere in 64-bit address space. If this 64-bit addressing option is used, the maximum window
size changes from 2 GB (in the 32-bit case) to 2

If the preloaded window size for a 64-bit BAR is 2 GB or less, then the space requested may be
mapped either in 32-bit address space or 64-bit address sp ace. In the former case, the up per 32 bits
of the base address is zero and transactions are forwarded as described in the previous section u sing
direct offset address translation. If the upper 32-bit base address is non-zero, then the memory
range is located above the 4 GB boundary.

63

bytes.

5-8

If the Downstream Memory 3 Range is mapped above the 4 GB boundary, then primary bus
transactions falling into this address range are forwarded downstream with no address translation
performed. Any 64-bit address transactions on the secondary bus falling outside of the

21554 PCI-to-PCI Bridge for Embedded Applications User’s Manual

Downstream Memory 3 address range are forwarded upstream, again with no address translation.
This is similar to the forwarding mechanisms of a standard PCI-to-PCI bridge and is illustrated in

Figure 5-8.

Note that since the use of BARs restricts the alignment of the address rang e to the windo w size, the
Downstream Memory 3 address range can never straddle the 4 GB boundary.

Figure 5-8. Dual-Address Transaction Forwarding

Base + Offset

Address Decoding

64

Byte Boundary

2

4GB Boundary

Translated
Base + Offset

Primary Address Map Secondary Address Map

5.4 I/O Transaction Address Decoding

The 21554 provides a mechanism where one BAR on ea ch interface can b e config ured to be an I/O
BAR instead of a memory BAR. The Downstream I/O or Memory 1 BAR in primary configuration
space is used to decode primary bus I/O transactions for forwarding to the secondary bus. The
Upstream I/O or Memory 0 BAR in secondary configuration space is used to decode seco ndary bus
I/O transactions for forwarding to the primary bus.

The 21554 performs direct offset address translation when forwar ding I/O transa ctions in much the
same manner that it translates memory addresses. The size of the I/O BARs can be configured to be
64 bytes, 128 bytes, or 256 bytes. Accordingly, the base address can consist of 26, 25, or 24 bits.
The 21554 hardware does not r estrict s etting up larg er I/O windows, al though requ esting mor e than
256 bytes of I/O space is a violation of the PCI Local Bus Specification, Revision 2.1. The upper
bits comprising the base address of the I/O address on the primary bus is replaced with the base
address written in the Downstream I/O or Memory 1 Translated BAR when initiated on the
secondary bus. Similarly, the Upstream I/O or Memory 0 Translated BAR is used for upstream I/O
transactions. These translated base registers are mapped in both device-specific configuration
space and the 21554 CSR space.

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21554 PCI-to-PCI Bridge for Embedded Applica tio ns User’ s Ma nua l

5-9

Address Decoding

5.4.1 Indirect I/O Transaction Generation

The 21554 implements a CSR mechanism that allows access to any I/O address in the secondary or
local I/O address map from the primary interface, or any I/O address in the primary or host I/O
address map from the secondary interface. A pair of device-specific CSR registers contain the
address and data used to initiate the I/O transaction. O ne pair is used for downstream I/O
transactions and one pair is used for upstream I/O transactions. The downstream registers can only
be accessed from the primary interface, and the upstream registers can only be accessed from the
secondary interface. They function similarly, so only the downstream case is discussed.

The Downstream I/O Address register contains the address used when the transaction is initiated
on the secondary bus. When the Downstream I/O Data register is read or written from the primary
interface, the 21554 initiates the transaction on the secondary bus. For writes, the Downstream I/O
Data register contains the write data to be written. For reads, the read data is placed in this register
upon completion of the secondary bus I/O read.

The I/O Data register must be accessed with an I/O transaction on the primary interface to initiate
the secondary bus I/O transaction. Otherwise, this register appears as reserved for both memory
accesses or accesses from the secondary interface. In addition, the Downstream I/O Control bit in
the I/O Control and Status register must be set to enable downstream I/O transaction generation;
otherwise, I/O Data register accesses are treated as reserved accesses.

The 21554 uses the same byte enables that the initiator used to read or write the register.

Note: The low bits of the I/O address written in the I/O Address register must m a tch the byte enables

used during the data phase, as described in the PC I Loca l Bus Specification, Revision 2. 1. The
21554 will not correct discrepancies between b yte enables and address bits [1:0].

The 21554 responds to read or write access of Downstream I/O Data register with a target retry until the
I/O transaction is completed on the secondary bus. Thi s I/O access is treated as a delayed transaction by

the 21554. This delayed transaction is entered into the 21554’s downstream delayed transaction queue
and is ordered with respect to all other downstream transactions. When ordering rules permit, the 21554
initiates I/O write or read on the secondary bus. When the I/O transaction completes, then the 21554
returns target termination and, if a read, returns read data when the initiator repeats the transaction.

The 21554 provides a semaphore method that may be used to guarant ee atomicity of the Downst ream
I/O Address and Downstream I/O Data register accesses using the Downstream I/O Own bit.
Atomicity of these accesses is not hardware-enforced. An Upstream I/O Own bit is provided for
upstream I/O transactions. The following procedure should be used for downstream I/O transactions:

1. The initiator of the transaction reads the Downstream I/O Own bit. If the bit reads as zero, then
the initiator may proceed with the indirect I/O transaction sequence. If the bit reads as a 1, then
the initiator should not proceed until a subsequent read of the own bit returns a 0. The 21554
automatically sets the own bit to a 1 after it is read from the primary interface.

2. The initiator writes the target I/O address in the Downstream I/O Address register.

3. The initiator should write or read the data in the Downstream I/O Data register until a response
other than target retry is received.

4. Upon returning the completion of the I/O transaction to the initiator, the 21554 automatically
clears the bit to a 0.

The same procedure should be used for upstream I/O transactions using the Upstream I/O Address
register, Upstream I/O Data register, and Upstream I/O Own bit. To read the state of the
Downstream and Upstream I/O Own bits without side effects, a read-only copy of the I/O Own bit
states is kept in the I/O Control and Status register. Byte access of the I/O Own bits and their
read-only copies should be used to avoid setting the I/O Own bit for the opposite interface.

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21554 PCI-to-PCI Bridge for Embedded Applications User’s Manual

5.4.2 Subtractive Decoding of I/O Transactions

The 21554 can be enabled to subtractively decode I/O transactions and forward these transactions
to the opposite bus. No address translation is performed on subtractively decoded I/O transactions.
The transaction is treated by the 21554 as a delayed transaction. To enable subtractive decoding of
I/O transactions on the primary bus, the Subtractive Decode Enable bits in the Chip Control 1
configuration register must be set to 01b. T o enable subtractive decodi ng of I/O transactions on the
secondary bus, the Subtractive Decode Enable bits must be set to 10b.

Note: There can be only one subtractive decoding agent on a PCI bus. Subtractive decoding should not

be enabled for both the primary and secondary interfaces.

5.5 21554 Base Address Register Summary

Table 5-2 shows a summary of the 21554 BARs.

Table 5-2. Base Address Register Summary

Base Address Register Size Address Translation

Address Decoding

Primary CSR and Downstream Memory 0
BAR

Primary CSR I/O BAR 256 byte s —

Secondary CSR Memory BAR 4 KB —
Secondary CSR I/O BAR 256 bytes —
Primary Expansion ROM BAR 4 KB to 16 MB —

Downstream I/O or Memory 1 BAR

Downstream Memory 2 BAR 4 KB to 2 GB Direct Offset

Downstream Memory 3 BAR 4 KB to 2

Upstream I/O or Memory 0 BAR

Upstream Memory 1 BAR 4 KB to 2 GB Direct Offset
Upstream Memory 2 BAR 16 KB to 256 MB Lookup Table

4 KB to 2 GB

64 bytes to 256 bytes (I/O) or
4 KB to 2 GB (mem ory)

63

bytes

64 bytes to 256 bytes (I/O) or
4 KB to 2 GB (mem ory)

Low 4 KB: None
Above 4KB boundary:

Direct Offse t

Direct Offse t

Direct Offset ( < 4 GB)
None (≥4GB)

Direct Offse t

21554 PCI-to-PCI Bridge for Embedded Applica tio ns User’ s Ma nua l

5-11

Configuration Accesses

This chapter describes how the 21554 responds to Type 0 configuration transactions.
The 21554 implements two sets of configuration registers: one for the primary interface and one

for the secondary interface. Both sets are accessible from either interface. The 21554 can act as an
initiator of Type 0 or Type 1 configuration transactio ns on the primary or secondary bus using the
indirect configuration transaction mechanism.

As a target, the 21554 ignores any transactions that it initiates as a master.

6.1 Type 0 Accesses to the 21554 Configuration Space

The 21554 responds as a target to Type 0 configuration transactions on both its primary and
secondary interfaces when the IDSEL pin for that interface is asserted. The 21554 is a
single-function device and does not decode the function number. Because the 21554 is not a
transparent PCI-to-PCI bridge, it does not respond to Type 1 configuration transactions.

Access to the 21554 configuration space may be restricted during different phases of initialization:

• Reset:

No access to the 21554 configuration space from either interface.

6

• Serial preload:

No access to the 21554 configuration space from either interface. The 21554 returns target
retry.

• Optional primary lockout:

Access to the 21554 configuration space is allowed from the secondary interface only, until the
Primary Lockout Bit in the Chip Control 0 register is cleared. The 21554 returns target retry to
all accesses initiated on the primary bus, with the exception of accesses to the Reset Co ntrol
register at Dword D8h.

• Normal configuration and operation:

Access to the 21554 configuration space is allowed from both the primary and secondary

interfaces.
See Chapter 16 for a more detailed description of the initialization process.
Accesses to the 21554 configuration space are not ordered with respect to transactions in the 21554

queues. That is, the 21554 responds immediately to configuration transactions regardless of what
transactions exist in the upstream and downstream queues. Exceptions to this are configuration
accesses that result in the initiation of configuration and I/O transactions by the 21554. These
transactions are entered in the delayed transaction qu eue and ordered appropriately with respect to
other delayed transactions and posted writes in the 21554 queues.

21554 PCI-to-PCI Bridge for Embedded Applica tio ns User’ s Ma nua l

6-1

Configuration Accesses

6.2 Initiation of Configuration Transactions by 21554

Usually, the host processor configures primary bus devices and the local processor configures
secondary bus devices, so forwarding of configuration transactions across the 21554 is typically
not necessary. However, in order to support other configuration methods, the 21554 implements a
mechanism that enables initiation of Type 0 or Ty pe 1 configuration accesses on either the primary
bus or the secondary bus. This mechanism is different fro m the hierarchical mech anisms supported
by PCI-to-PCI bridges. Instead, two pairs of device-specific registers contain the address and data
that are used to initiate the configuration transaction. One pair is used to generate transactions on
the primary interface; the other is used to generate transactions on the secondary interface:

• The Upstream Configuration Address and Upstream Configuration Data registers contain the

address and data of the configuration transaction to be initiated on the primary bus.

• The Downstream Configuration Address and Downstream Configur ation Data regis ters co ntain

the address and data of the configurati on trans action t o be init i ated o n th e secondary b us.

In addition, the Configuration Control and Status register and Configuration Own Bits register are
used for configuration transaction generation. All of these registers are mapped into both
device-specific configuration space and the 21554 CSR space. The upstream address and data
registers can be written from the secondary interface only, and the downstream address and data
registers can be written from the primary interface only. Downstream and upstream configuration
address registers can be read from either interface.

In order to generate a configuration transaction, the corresponding Upstream or Downstream
Configuration Control bit in the Configuration Control and Status register must be set. Otherwise,
the corresponding Data registers are treated as reserved registers. The C onfigur ation Data registers
are also treated as reserved registers in memory space.

The Upstream or Downstream Configuration Add ress register must be written with the address to
be driven before the corresponding data register is accessed. This address is driven on the AD lines
exactly as written in the register. Therefore, a Type 0 format must be used to generate a Type 0
configuration transaction, and a Type 1 format must be used to generate a Type 1 configuration
transaction. The upper 21 bits of a Type 0 address format are used as IDSEL signals and are
specific to the motherboard or add-in card application.

The configuration transaction is initiated by the 21554 when the Upstream or Downstream
Configuration Data register is either read or written from the secondary or primary interface,
respectively. These registers must be accessed by either a configuration transaction or an I/O
transaction to initiate the transaction. The 21554 uses the same byte enables that the initiator used
to read or write the register. The 21554 responds to the access of the Upstream or Downstream
Configuration Data register with a target retry until the access is completed on the target bus.
When the access is completed, the 21554 returns the corresponding targ et terminat ion and, if a
read, the read data on a subsequent attempt of the transaction by the in itiator. If the Delayed
Transaction Target Retry Counter expires, that is, 2
then the 21554 returns a target abort to the initiator.

24

target retries are received from the target,

6-2

21554 PCI-to-PCI Bridge for Embedded Applications User’s Manual

Configuration Accesses

The 21554 provides a semaphore method that may be used to guarantee atomicity of the address
and data register accesses using the Upstream Configuration Own bit and Downstream
Configuration Own bit. Atomicity of these accesses is not guaranteed in hardware. If the
corresponding Configuration Control bit is not set, then the Own bit is treated as reserved. The
following procedure should be used for downstream transactions:

1. The initiator of the transaction should read the Downstream Configuration Own bit for
initiation of transactions on the second a ry bu s. If the bit reads as zero, then the initiator may
proceed with the configuration transaction sequence. If the bit reads as a 1, then the initiator
should not proc eed until a s ubseq uent read of the own bit ret urns a 0. The 215 54 aut omaticall y
sets the own bit to a 1 after it is read.

2. The initiator should write the target configuration address in the Downstream Configuration
Address regis t er.

3. The initiator should write or read the data in the Downstream Configuration Data register until
a response other than target retry is received.

4. Upon completion of the configuration transaction on the initiator bus, the 21554 automatically
clears the Downstream Configuration Own bit to a 0.

Upstream configuration transactions should use a similar process. To check the status of the own
bits without read side effects, read-only copies of these bits are located in the Configuration
Control and Status register. Byte access of the Configuration Own bits and their read-only copies
should be used to avoid setting the Configuration Own bit for the opposite interface.

21554 PCI-to-PCI Bridge for Embedded Applica tio ns User’ s Ma nua l

6-3

Configuration Space Registers

This chapter describes the 21554 configuration space registers.
The 21554 configuration space is divided into three parts: the primary interface configuration

registers, the secondary interface configuration registers, and the device-specific configuration
registers. Both the primary and secondary interface configuration headers contain the 64-byte
Type 0 configuration header corresponding to that interface. The device-specific configuration
registers are specific to the 21554, some of which apply to the primary interface, others to the
secondary interface, and some to other 21554 functions.

The 21554 provides very flexible configuration mechanisms. Access to the 21554 configuration
registers is supported from both the primary and secondary interfaces. Some configuration
parameters can be preloaded from the serial ROM attached to the 21554 prior to initialization. This
enables vendor-specific configuration parameters to be loaded into the 21554 configuration
registers, replacing default values specified by Intel. These vendor-specific parameters are loaded
before configuration of the 21554 by the local and/or host processors. Parameters that can be
preloaded include address mapping requirements, Class Code, Subsystem ID and Subsystem
Vendor ID, and others. Section 7.3 contains a description of the preload sequence and format.
During the preload operation, all accesses to the 21554 configuration registers receive a target
retry.

Subsequent to the serial ROM preload, the local processor may then access configuration registers
before the host processor is allowed access. The Primary Lock out configuration space bit can be set
to prevent access by the primary interface. The local processor can control this bit. When the
Primary Lockout is set, the 21554 returns a target retry to any configuration accesses by the host
processor, with the exception of the Reset Control register at Dword location D8h. When the bit is
cleared, the 21554 is then able to return TRDY# in response to host configuration accesses.
Optionally, the Primary Lockout bit may be cleared during the serial preload, permitting
simultaneous host and local access to configuration space. The Reset Control register is always
accessible to the host, except during chip reset.

7

Read accesses to reserved or unimplemented registers complete normally and return a data value of
zero when read. Writes to reserved registers are completed normally and the write data discarded.

Software must be careful when accessing registers that have bit fields reserved for future use. For
read accesses, software must use appropriate masks to extract the defined bits and may not rely on
reserved bits being any particular value. For write accesses, software must ensure that the values o f
reserved bit positions are preserved. That is, the values of the reserved bit positions must first be
read, merged with the new values for other bit positions, an d the merged data then written back.

21554 PCI-to-PCI Bridge for Embedded Applica tio ns User’ s Ma nua l

7-1

Configuration Space Registers

7.1 Configuration Space Address Map

Figure 7-1 shows an address map of the 21554 primary interface configuration space. Figure 7-2

shows an address map of the 21554 secondary interface configuration space. Figure 7-3 shows an
address map of the 21554 device-specific configuration space.

The first 64 bytes of the primary address map contain the primary interface co nfiguration registers.
The first 64 bytes of the secondary address map contain the secondary interface configuration
registers. Some of these registers are shared copies, such as the Device ID. Other registers are
separate, such as the Primary Cache Line Size and the Secondary Cache Line Size. Separate

registers have either “Primary” or “Secondary” preceding the register name. The secondary
configuration registers can be accessed in the second 64 bytes of the primary interface’s
configuration space map (primary addresses 40h - 7Fh). Similarly, the primary configuration
registers can be accessed in the second 64 bytes of the secondary interface’s configuration space
map (secondary addresses 40h - 7 Fh). Th e remaining device-specifi c registers are accessib le at the
same configuration address from both the primary and secondary interfaces.

Figure 7-1. Primary Interface Configuration Space Address Map

Byte 3 Byte 2 Byte 1 Byte 0

Device ID

Primary Status

1,2

BiST

Subsystem ID SubsystemVendor ID

Primary Primary Primary

MAX _LAT M IN_GNT

1.

Primary and secondary configuration registers are shared.

2.

Register or a portion of the register may be preloaded using the serial ROM interface.

11

Primary Class Code RevID

Header Type

Primary CSR and Downstream Memory 0 BAR

Primary CSR I/O BAR

Downstream I/O or Memory 1 BAR

Downstream Memory 2 BAR
Downstream Memory 3 BAR

Upper 32 Bits Downstream Memory 3 BAR

Primary Expansion ROM Base Address

Reserved

2

21

1

Reserved

Reserved

2

Interrupt Pin

Vendor ID

Primary Command

Primary CLSPrimary MLT

1,21,2

Capabilities

Pointer

Primary

Interrupt Line

Primary
Offset

00h 40h
04h 44h
08h 48h
0Ch 4Ch
10h 50h
14h 54h
18h 58h
1Ch 5Ch
20h 60h
24h 64h
28h 68h
2Ch 6Ch
30h 70h
34h 74h

1

38h 78h
3Ch 7Ch

Secondary
Offset

FM-06134.AI4

7-2

21554 PCI-to-PCI Bridge for Embedded Applications User’s Manual

Figure 7-2. Secondary Interface Configuration Space Address Map

Configuration Space Registers

Byte 3 Byte 2 Byte 1 Byte 0

Device ID Vendor ID

Device ID Vendor ID

Secondary Status

Secondary Class Code RevID

1,2

BiST

11

Secondary Command

Secondary

MLT

Secondary

CLS

Header Type

21

1

Secondary CSR Memory BAR

Secondary CSR I/O BAR

Upstream I/O or Memory 0 BAR

Upstream Memory 1 BAR
Upstream Memory 2 BAR

Reserved
Reserved

Subsystem ID Subsystem Vendor ID

1,2 1,2

Reserved

Reserved

Capabilities

1

Pointer

Reserved

SecondarySecondary Secondary

MAX _LAT M IN_GNT

1.

Primary and secondary configuration registers are shared.

2.

Register or a portion of the register may be preloaded using the serial ROM interface.

22

Secondary
Interrupt Pin

Interrupt Line

Primary
Offset

40h 00h
44h 04h
48h 08h
4Ch 0Ch

50h 10h
54h 14h
58h 18h
5Ch 1Ch
60h 20h
64h 24h
68h 28h
6Ch 2Ch
70h 30h
74h 34h

78h 38h
7Ch 3Ch

Secondary
Offset

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21554 PCI-to-PCI Bridge for Embedded Applica tio ns User’ s Ma nua l

7-3

Configuration Space Registers

Figure 7-3. Device-Specific Configuration Address Map

Byte 3 Byte 2 Byte 1 Byte 0

Primary
Offset

Downstream Configuration Address

Downstream Configuration Data

Upstream Configuration Address

Upstream Configuration Data

Configuration Control and Status Configuration Own Bits

11

Downstream Memory 0 Translated Base

Downstream I/O or Memory 1 Translated Base

Downstream Memory 2 Translated Base
Downstream Memory 3 Translated Base

Upstream I/O or Memory 0 Translated Base

Upstream Memory 1 Translated Base

Downstream Memory 0 Setup Register

Downstream I/O or Memory 1 Setup Register

Downstream Memory 2 Setup Register
Downstream Memory 3 Setup Register

Upper 32 Bits Downstream Memory 3 Setup Register

Primary Expansion ROM Setup Register

Upstream I/O or Memory 0 Setup Register

Upstream Memory 1 Setup Register

Chip Control 1

Arbiter Control

Reserved

2
2

Secondary

SERR#

Disables

Reset Control

2

Power Management Capabilities

2

PM Data PMCSR BSE

VPD Address

Next Item Ptr Capability ID

Power Management CSR

Next Item Ptr Capability ID

VPD Data

Reserved Hot Swap

Next Item Ptr Capability ID

1

1

1

1

1

1
1
1

1

1

2

2
2
2

2

2

2

2

Chip Control 0

2

Chip Status

Primary

22

SERR#

Disables

80h 80 h
84h 84 h
88h 88 h
8Ch 8Ch
90h 90 h
94h 94h
98h 98h
9Ch 9Ch
A0h A0h
A4h A4h
A8h A8h
ACh ACh
B0h B0h
B4h B4h
B8h B8h

BCh BCh
C0h C0h
C4h C4h
C8h C8h
CCh CC h
D0h D0 h
D4h D4h

D8h D8h
DCh DC h

2

E0h E0h
E4h E4h
E8h E8h

2

ECh ECh

Control

Reserved

1.

Shared mapping in the 21554 I/O or memory space.

2.

Register or a portion of the register may be preloaded using the serial ROM interface.

FF: F0h FF:F0h

Secondary
Offset

FM-06136.AI4

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21554 PCI-to-PCI Bridge for Embedded Applications User’s Manual

7.2 Configuration Register Description

The following subsections describe the 21554 configuration registers.

• Primary and secondary configuration head er r egisters, describing both the shared and separate

standard PCI configuration registers, with the exception of the base address registers

• Primary and secondary addressing registers, including base address registers, translation

registers, and setup reg isters

• Registers for upstream and downstream configuration tran saction generation

• Device-specific control and status registers

If a register is associate d with th e pr imar y in ter fac e, the n its n ame is pr eced ed wi th Primary. If a
register is associated with the secondary interface, then its name is preceded with Secondary. If a
register is shared by b oth interfaces, then it is not pr ece ded with Primary or Secondary. The byte
offsets at which each register can be accessed f rom each int erface are listed in each register de scription.

Table 7-1 shows the allowable access to each register.

Table 7-1. Register Access

Abbreviation Definition

R Read only. Writes have no effect.
R/W Read/write
R/W1TC Read. Write 1 to clear.
R/W1TS Read. Write 1 to set.
R0TS Read 0 to set.
R/(WS) Read. Write from secondary interface only. Primary bus writes have no effect.
R/(WP) Read. Write from primary interface only. Secondary bus writes have no effect.

Configuration Space Registers

7.2.1 Shared Standard PCI Registers

The registers described in this section are shared between the primary and secondary interfaces.

7.2.1.1 Vendor ID Register

Primary byte offset: 01:00h and 41:40h
Secondary byte offset: 41:40h and 01:00h

Bit Name R/W Description

15:0 VendorID R

21554 PCI-to-PCI Bridge for Embedded Applica tio ns User’ s Ma nua l

The Vendor ID identifies Intel as the vendor of this device and is internally
hardwired to be 1011 hex.

7-5

Configuration Space Registers

7.2.1.2 Device ID Regi ster

Primary byte offset: 03:02h and 43:42h
Secondary byte offset: 43:42h and 03:02h

Bit Name R/W Description

15:0 DeviceID R Device ID identifies this device as the 21554 and is internally hardwired to be 46h.

7.2.1.3 Revision ID (RevID) Register

Primary byte offset: 08h and 48h
Secondary byte offset: 08h and 48h

Bit Name R/W Description

7:0 RevisionID R

7.2.1.4 BiST Register

Primary byte offset: 0Fh and 4Fh
Secondary byte offset: 0Fh and 4Fh
The 21554 does not implement self-test internally and does not directly use the BiST register.

However, some form of self-test may be desired in the subsystem so mechanisms are provided by
the 21554 to support vendor -speci fic usage of the B iST register. The default value of this register is
00h after reset assert ion, whic h indicates t hat BiST is not su pported. However , afte r reset the 21554
allows this field to be automatically preloaded with a value from the serial ROM (if attached) or
programmed via the secondary interface by the local processor.

Bit Name R/W Description

3:0

5:4 Reserved R Reserved. Read only as 0.

6 Self Test R/W

7

Completion
Code

BiST
Supported

R/(WS)

R/(WS)

When read, the Revision ID indicates the revision number of this device. The
initial revision reads as 0. Subsequent revisions increment by 1.

The completion code can only be written by the secondary interface (at
secondary offset 0Fh or offset 4Fh). A Completion Code value of 0h indicates
that the device passed its self-test. Any non-zero value in the Completion
Code indicates that the device failed its self-test.

This bit can be written via the primary interface or secondary interface
configuration registers. Configuration code running on the host processor
sets this bit to 1 to invoke self-test. The local processor (or some other
device) on the secondary interface clears this bit to 0 to indicate the
completion of the self-test (after first updating the Completion Code bit field).

This bit can be written by the secondary interface (at secondary offset 0Fh or
offset 4Fh) or it may be preloaded using the serial ROM. A value of 1
indicates to configuration software that the device supports self-test. A value
of 0 indicates that the device does not support self-test.

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21554 PCI-to-PCI Bridge for Embedded Applications User’s Manual

7.2.1.5 Header Type Register

Primary byte offset: 0Eh and 4Eh
Secondary byte offset: 0Eh and 4Eh

Bit Name R/W Description

Configuration Space Registers

7:0

Header
Type

R

Defines the layout of addresses 00h through 3Fh in configuration space.
Reads as 00h indicating a Type 0 header format.

7.2.1.6 Subsystem Vendor ID Register

Primary byte offset: 2D:2Ch and 6D:6Ch
Secondary byte offset: 6D:6Ch and 2D :2Ch

Bit Name R/W Description

15:0

Subsystem
Vendor ID

R/(WS)

Identifies the vendor of the add-in card or subsystem. This register is
initialized by either the local processor or by serial ROM preload.

7.2.1.7 Subsystem ID Register

Primary byte offset: 2F:2Eh and 6F:6Eh
Secondary byte offset: 6F:6Eh and 2F:2Eh

Bit Name R/W Description

15:0

Subsystem
ID

R/(WS)

Identifies the vendor-specific device ID for subsystem. This register is
initialized by either the local processor or by serial ROM preload.

21554 PCI-to-PCI Bridge for Embedded Applica tio ns User’ s Ma nua l

7-7

Configuration Space Registers

7.2.2 Primary and Secondary Standard PCI Registers

The register types in this section have separate registers for the primary and secondary interfaces.
However, the register description is given once, and applies to both the primary and secondary
configuration registers. The primary register controls behavior on the primary interface only, and
the secondary register controls behavior on the secondary interface only.

7.2.2.1 Primary and Secondary Command Registers

Primary Command Secondary Command

Primary byte offset: 05:04h 45:44h
Secondary byte offset: 45:44h 05:04h

Table 7-2. Primary and Secondary Command Registers (Sheet 1 of 2)

Bit Name R/W Description

Controls 21554 response to I/O transactions on the corresponding interface.

0

1

2 Mas ter Enable R/W

3

4

5

6

I/O Space
Enable

Memory
Space Enable

Special Cycle
Enable

Memory Write
and Invalidate
Enable

VGA Snoop
Enable

Parity Error
Response

R/W

R/W

R

R/W

R

R/W

When 0:
When 1
Reset value

Controls response to memory transactions on the corresponding interface.

When 0:
When 1:
Reset value:

Controls 21554’s ability to initiate memory and I/O transactions on the
corresponding interface. Initiation of configuration transactions is not affected.

When 0:
When 1:
Reset value

The 21554 ignores special cycle transactions, so this bit is read only and
returns 0.

This bit controls the ability of the 21554 to generate M emory Write and
Invalidate (MWI) bus commands as a master on the corresponding
interface.

When 0:

Memory Write commands instead).

When 1:
Reset Value:

Reads only as 0 to indicate the 21554 does not respond to VGA palette
writes.

Controls the response of the 21554 when a parity error is detected on the
corresponding interface.

When 0:

Reported bit in the appropriate Primary or Secondary Status registers. The
21554 does not report address parity errors by asserting SERR#.

When 1:

Reported bit in the Primary or Secondary Status register when a data parity
error is detected. The 21554 allows SERR# assertion when address parity
errors are detected.

Reset value:

The 21554 does not respond to I/O transactions.

: The 21554 response to I/O transactions is enabled.

: 0

The 21554 does not respond to memory transactions.
The 21554 response to memory transactions is enabled.

0.

The 21554 does not initiate memory or I/O transactions.
The 21554 is enabled to operate as an initiator.

: 0.

Disables use of Memory Write and Invalidate bus commands (uses

Enables use of Memory Write and Invalidate bus commands.

0

The 21554 does not assert PERR#, nor does it set the Data Parity

The 21554 drives PERR# and conditionally sets the Data Parity

0.

7-8

21554 PCI-to-PCI Bridge for Embedded Applications User’s Manual

Configuration Space Registers

Table 7-2. Primary and Secondary Command Registers (Sheet 2 of 2)

Bit Name R/W Description

Wait Cycle

7

Control

SERR#

8

Enable

Fast

9

Back-to-Back
Enable

15:10 Reserved R Reserved. Returns 0 when read.

Reads as zero to indicate the 21554 does not perform address or data

R

stepping.
Controls the enable for SERR# on the corresponding interface.

When 0:

R/W

When 1:

described in Chapter 14.

Reset value:

Controls the ability of the 21554 to generate fast back-to-back transactions
on the corresponding bus.

When 0:

R/W

When 1:
Reset value:

SERR# cannot be driven by the 21554.
SERR# may be driven low by the 21554 under the conditions

0.

The 21554 does not generate back-to-back transactions.
The 21554 is enabled to generate back-to-back transactions.

0.

21554 PCI-to-PCI Bridge for Embedded Applica tio ns User’ s Ma nua l

7-9

Configuration Space Registers

7.2.2.2 Primary and Secondary Status Registers

Primary Status Secondary Status

Primary byte offset: 07:06h 47:46h
Secondary byte offset: 47:46h 07:06h

The bits described below reflect the status of the 21554 primary interface for the Primary Status
register, and of the secondary interface for the Secondary Status register. W1TC indicates that
writing a 1 to that bit clears the bit to 0. Writing a 0 has no effect.

Table 7-3. Primary and Secondary Status Registers

Bit Name R/W Description

3:0 Reserved R Reserved. Returns 0 when read.
4 ECP Support R

5 66 MHz Capable R

6 Reserv ed R Reserved. Returns 0 when read.

Enhanced Capabilities Support Indicator. Reads as 1 to indicate that
the Enhanced Capabilities Port is supported.

66 MHz Capable Indication.
Reads as 0 to indicate that the corresponding interface operates at a

maximum frequency of 33 MHz.

7

8

10:9 DEVSEL# timing R

11

12

13

14

15

Fast Back-to-Back
Capable

Data Parity
Detected

Signaled Target
Abort

Received Target
Abort

Received Master
Abort

Signaled System
Error

Detected Parity
Error

R

R/
W1TC

R/
W1TC

R/
W1TC

R/
W1TC

R/
W1TC

R/
W1TC

Reads as 1 to indicate that the 21554 is able to respond to fast
back-to-back transactions on the corresponding interface.

This bit is set to a 1 when all of the following are true:

• The 21554 is a master on the corresponding bus.

• PERR# is detected asserted for writes or a parity error is detected
for reads.

• Parity Error Response bit is set in the Primary or Secondary
Command register.

Reset value:

Indicates slowest response to a nonconfiguration command on the
corresponding interface. Reads as 01b to indicate that the 21554
responds no slower than with medium timing.

This bit is set to a 1 when the 21554 is acting as a target on the
corresponding bus and returns a target abort to the initiator.

Reset value:

This bit is set to a 1 when the 21554 is acting as an initiator on the
corresponding bus and receives a target abort.

Reset value:

This bit is set to a 1 when the 21554 is acting as an initiator on the
corresponding bus and detects a master abort.

Reset value:

This bit is set to a 1 when the 21554 has asserted SERR# on the
corresponding bus.

Reset value:

This bit is set to a 1 when the 21554 detects an address or data parity
error on the corresponding interface.

Reset value:

0.

0.

0.

0.

0.

0.

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21554 PCI-to-PCI Bridge for Embedded Applications User’s Manual

Configuration Space Registers

7.2.2.3 Primary and Secondary Class Code Registers

Primary Class Code Secondary Class Code

Primary byte offset: 0B:09h 4B:49h
Secondary byte offset: 4B:49h 0B:09h

These registers may be preloaded through the serial ROM. The Primary Class Code register may
also be programmed by the local processor.

Table 7-4. Primary and Secondary Class Code Registers

Bit Name R/W Description

7:0 ProgIF (PIF)

15:8 Sub-Class Code (SCC)

23:16 Base Class Code (BCC)

PPIF: R/(WS)
SPIF: R

PSCC: R/(WS)
SSCC: R

PBCC:R/(WS)
SBCC: R

Reads as zero.
Reads as 80 hex to indicate that this bridge device is

classified as “other”.
Reads as 06 hex to indicate device is a bridge device.

7.2.2.4 Primary and Secondary Cache Line Size Registers

Primary Cache Line Size Secondary Cache Line Size

Primary byte offset: 0Ch 4Ch
Secondary byte offset 4Ch 0Ch

Table 7-5. Primary and Secondary Cache Line Size Registers

Bit Name R/W Description

Designates the cache line size for the corresponding interface in units of
32-bit Dwords. Used for prefetching memory reads and for terminating

7:0 Cache Line Size R/W

memory write and invalidates. Valid cache line sizes are 4, 8, 16, and 32
Dwords. If the cache line size is set to any other value, the 21554 uses
the same behavior a s when the cache line size is set to 8.

Reset value:

00h.

7.2.2.5 Primary Latency and Secondary Master Latency Timer Registers

Primary MLT Secondary MLT

Primary byte offset: 0Dh 4Dh
Secondary byte offset: 4Dh 0Dh

Table 7-6. Primary Latency and Secondary Master Latency Timer Registers

Bit Name R/W Description

Master latency timer for the corresponding interface. Indicates the number of PCI
clock cycles from the assertion of FRAME# to the expiration of the timer when the
21554 is acting as a master. All bits are writeable, resulting in a granularity of 1 PCI
clock cycle.

R/W

When 0:

The 21554 relinquishes the bus after the first data transfer when the

21554’s PCI bus grant has been deasserted.

Reset value:

00h.

7:0

Master
Latency
Timer

21554 PCI-to-PCI Bridge for Embedded Applica tio ns User’ s Ma nua l

7-11

Configuration Space Registers

7.2.2.6 Primary and Secondary Interrupt Line Registers

Pr

Primary Interrupt Line Secondary Interrupt Line

Primary byte offset: 3Ch 7Ch
Secondary byte offset: 7Ch 3Ch

Table 7-7. Primary and Secondary Interrupt Line Registers

Bit Name R/W Description

This register is used to communicate interrupt line routing information for
the corresponding interface. This register must be initialized by

7:0 Interrupt Line R/W

initialization code so a default state after reset assertion is not specified.
Initialization code writes this register with a value indicating to which input
of the system interrupt controller the 21554 bus interrupt signal pin INTA#
is connected.

7.2.2.7 Primary and Secondary Interrupt Pin Registers

Primary Interrupt Pin Secondary Interrupt Pin

Primary byte offset: 3Dh 7Dh
Secondary byte offset: 7Dh 3Dh

Table 7-8. Primary and Secondary Interrupt Pin Registers

Bit Name R/W Description

7:0 Interrupt Pin R

This register indicates which PCI interrupt pin the 21554 uses on the
corresponding bus. This is a read-only register and always returns 1 when
read indicating that the 21554 uses INTA#.

7.2.2.8 Primary and Secondary Minimum Grant Registers

Primary Minimum Grant Secondary Minimum Grant

Primary byte offset: 3Eh 7Eh
Secondary byte offset: 7Eh 3Eh

These registers may be preloaded through the serial ROM. The Primary Minimum Grant register
may also be programmed by the local processor.

Table 7-9. Primary and Secondary Minimum Grant Registers

Bit Name R/W Description

7:0

MIN_GNT
(MG)

PMG: R/(WS)
SMG: R

Specifies how long of a burst period the 21554 needs on the
corresponding bus in units of 1/4 µsec. Reads as 0 before preload.

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21554 PCI-to-PCI Bridge for Embedded Applications User’s Manual

Configuration Space Registers

7.2.2.9 Primary and Secondary Maximum Latency Registers

Primary Maximum Latency Secondary Maximum Latency

Primary byte offset: 3Fh 7Fh
Secondary byte offset: 7Fh 3Fh

These registers may be preloaded through the ser ial ROM. The Primary Maximum Latency re gister
may also be programmed by the local processor.

Table 7-10. Primary and Secondary Maximum Latency Registers

Bit Name R/W D escription

7:0

MAX_LAT
(ML)

PML: R/(WS)
SML: R

Specifies how often the 21554 needs to gain access to the
corresponding bus in units of 1/4 µsec. Reads as 0 before preload.

7.2.2.10 Enhanced Capabilities Pointer Register

ECP

Primary byte offset: 34h and 74h
Secondary byte offset: 34h and 74h

Table 7-11. Enhanced Capabilities Pointer Register

Bit Name R/W Description

Pointer to the first set of ECP registers. Returns DCh to indicate that the first

7:0 ECP R

set of ECP registers begins at configuration offset DCh. For the 21554, this
points to the Power Management registers.

Reset value:

DCh

7.2.2.11 Power Management Capability ID Register

Primary byte offset: DCh
Secondary byte offset: DCh

Table 7-12. Power Management Capability ID Register

Bit Name R/W Description

7:0 PM ECP ID R

Power Management Enhanced Capabilities Port ID. Read only as 01h to identify
these ECP registers as Power Management registers.

7.2.2.12 Power Management Next Item Pointer Register

Primary byte offset: DDh
Secondary byte offset: DDh

Table 7-13. Power Management Next Item Pointer Register

Bit Name R/W Description

7:0 PM Next Ptr R

Pointer to next ECP registers. Reads as E4 to indicate the first register of the next
set of ECP registers, which support Vital Product Data, is located at offset E4h.

21554 PCI-to-PCI Bridge for Embedded Applica tio ns User’ s Ma nua l

7-13

Configuration Space Registers

7.2.2.13 Power Management Capabilities Register

Primary byte offset: DF:DEh
Secondary byte offset: DF:DEh

Bits [14:9,5,2:0] are loadable through the serial ROM or are programmable by the local processor.

Table 7-14. Power Management Capabilities Register

Bit Name R/W Description

Power Management Version. Loadable by serial ROM.

2:0 PM Version R/(WS)

3 PME Clock R

4APS R

5 DSI R/(WS)

8:6 Reserved R Reserved. Read only as 0.

9 D1 Support R/(WS)

10 D2 Support R/(WS)

15:11

PME
Support

R/(WS)

Reset value:

the PCI Power Management Interface Specification.
Clock Required for PME# Assertion. Reads as 1 to indicate that a clock is

required to assert PME#, if any of bits [15:11] in this register is asserted.
Read as 0 if bits [15:11] are all 0, indicating that the 21554 does not assert
PME#.

Auxiliary Power Source. Not defined since the 21554 does not have PME#
support from D3

Device-Specific Initialization. Loadable by serial ROM.

When 0:

requirements.

When 1:

requirements.

Reset value:

D1 Power State Support Indicator. Loadable by serial ROM.

When 0

management state.

When 1:
Reset value:

D2 Power State Support Indicator. Loadable by serial ROM.

When 0

management state.

When 1:
Reset value:

PME# support. Indicates whether the 21554 asserts p_pme_l when in a
given power state. Bit 11 corresponds to D0; bit 15 corresponds to D3
Bits [14:11] are loadable by serial ROM. Bit 15 always reads as 0 and is not
loaded by serial ROM nor writeable from the secondary interface, since the
21554 never asserts PME# when in D3

Reset value:

001b to indicate that this device is compliant to Revision 1.0 of

. Read only as 0.

cold

Indicates that the 21554 does not have device-specific initialization

Indicates that the 21554 has device-specific initialization

0

: Indicates that the 21554 does not support the D1 power

Indicates that the 21554 supports the D1 power management state.

0

: Indicates that the 21554 does not support the D2 power

Indicates that the 21554 supports the D2 power management state.

0

0 to indicate that the 21554 does not implement the PME# pin.

cold

.

cold

.

7-14

21554 PCI-to-PCI Bridge for Embedded Applications User’s Manual

Configuration Space Registers

7.2.2.14 Power Management Control and Status Register

Primary byte offset: E1:E 0h
Secondary byte offset: E1:E0h

Bits [14:13] are loadable by serial ROM or are programmable by the local processor.

Table 7-15. Power Management Control and Status Register

Bit Name R/W Description

Power State. Reflects the current power state of the 21554. If an
unimplemented power state is written to this register, the 21554 completes
the write transaction, ignores the write data, and does not change the value
of this field. D0 and D3 are always implemented. Support of D1 and D2 is
determined by serial ROM preload or local processor.

1:0 PWR State R/W

3:2 Reserved R Reserved. Read only as 00b.

4DYN DATAR

7:5 Reserved R Reserved. Read only as 000b.

8PME_ENR/W

12:9 DATA_SEL R/W

14:13 Data Scale R/(WS)

15 PME Status R/W1TC

00b: D0 (required)
01b: D1 (optional)
10b: D2 (optional)
11b: D3 (required)

Reset value:

Dynamic Data. Reads as 0 to indicate that the 21554 does not support
dynamic data reporting.

PME# Enable. Read only as 0 if the PME Support bits are all 0. Otherwise,
this is a read/write bit.

When 0:
When 1:
Reset value:

Data Select. This register is enabled by loading a “1” for the PM Data
Enable function in the serial ROM. For values of 7:0, selects one of eight
bytes of data loaded by serial ROM to be placed in the power management
data register. For values of 15:8, a 0 is returned in the data register.

If not enabled, this register always returns 0 when read.

Reset value:

Data Scale. Indicates the scaling factor of the value in the power
management data register. Loadable by serial ROM.

Reset value:

PME Status. The 21554 sets this bit to a 1 when s_pme_l is asserted and
the PME# Support bit for the current power state is a 1. This corresponds to
when the 21554 would normally assert p_pme_l, but regardless of the state
of the PME_En bit.

Writing a 1 clears this bit. Writing a 0 has no effect.

Reset value:

00b

The 21554 will not assert p_pme_l.
The 21554 is enabled to assert p_pme_l.

0

000b.

00b

0.

21554 PCI-to-PCI Bridge for Embedded Applica tio ns User’ s Ma nua l

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Configuration Space Registers

7.2.2.15 PMCSR Bridge Support Extensions

Primary byte offset: E2h
Secondary byte offset: E2h

Table 7-16. PMCSR Bridge Support Extensions

Bit Name R/W Description

7:0 BSE R Bridge Support Extensions. Read only as 00h.

7.2.2.16 Power Management Data Register

Primary byte offset: E3h
Secondary byte offset: E3h

Table 7-17. Power Management Data Register

Bit Name R/W Description

Power Management Data register. Reflects one of eight bytes loaded by

7:0 PM Data R

serial ROM, or reads as 0. Bytes are selected by the data select register.

Reset value:

00h

7.2.2.17 Vital Product Data (VPD) ECP Register

Primary byte offset: E4h
Secondary byte offset: E4h

Table 7-18. Vital Product Data (VPD) ECP Register

Bit Name R/W Description

7:0 50 R

VPD Enhanced Capabilities Port ID. Read only as 03h to identify these
ECP registers as VPD registers.

7.2.2.18 Vital Product Data (VPD) Next Pointer Register

Primary byte offset: E5h
Secondary byte offset: E5h

Table 7-19. Vital Product Data (VPD) Next Pointer Register

Bit Name R/W Description

7:0

VPD Next
Ptr

R

Pointer to next ECP registers. Reads as ECh to point to the next set of
ECP registers, supporting Compact PCI Hot Swap.

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21554 PCI-to-PCI Bridge for Embedded Applications User’s Manual

7.2.2.19 Vital Product Data (VPD) Address Register

Primary byte offset: E7:E 6h
Secondary byte offset: E7:E6h

Table 7-20. Vital Product Data (VPD) Address Register

Bit Name R/W Description

Vital Product Data Address. Contains the VPD byte address of the serial
ROM location to be accessed. Valid VPD byte addresses are 17F: 000h.

8:0 VPD Addr R/W

14:9 Reserved R Reserved. Read Only as 0.

15 VPD Flag R/W

VPD starts at base address 080h in the serial ROM. The VPD byte
address contained in this register is added to the VPD base address to
obtain the final serial ROM address.

VPD Flag. Starts a VPD serial ROM access and indicates completion of
the operation.

When written with a 0:

the VPD location indicated by bits [8:0]. Note that this operation is not
necessarily Dword aligned. When the read is complete, the 21554 sets
this bit to a 1.

When written with a 1:

the VPD location indicated by bits [8:0]. Note that this operation is not
necessarily Dword aligned. When the write is complete, the 21554 sets
this bit to a 0.

A 4-byte serial ROM read is performed starting at

A 4-byte serial ROM write is performed starting at

Configuration Space Registers

7.2.2.20 VPD Data Register

Primary byte offset: EB:E8h
Secondary byte offset: EB:E8h

Table 7-21. VPD Data Register

Bit Name R/W Description

VPD Data. Contains the VPD read or write data. For a read, t his register
should be read after a read operation was initiated and the 21554 has
returned the VPD Flag bit to a 1. For a write, this register should be
written with the write data before the operation is initiated with a write to

31:0 VPD Data R/W

the VPD Address and VPD Flag bits. VPD read and write operations are
always 4-byte operations.

Byte 0 contains the data corresponding to the starting VPD byte address.
Byte 1, 2, and 3 contain successive bytes. Note that Byte 0 is not
necessarily Dword aligned.

7.2.2.21 Compact PCI Hot-Swap Capability Identifier Register

Primary byte offset: ECh
Secondary byte offset: ECh

Table 7-22. Compact PCI Hot-Swap Capability Identifier Register

Bit Name R/W Description

7:0 HS ECP ID R

Enhanced capabilities ID. Reads only as 06h to indicate that these are
Compact PCI Hot-Swap registers.

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Configuration Space Registers

7.2.2.22 Compact PCI Hot- Swap Next Pointer Re gister

Primary byte offset: EDh
Secondary byte offset: EDh

Table 7-23. Compact PCI Hot-Swap Next Pointer Register

Bit Name R/W Description

7:0 HS NXT PTR R

Pointer to next set of ECP registers. Reads only as 0 to indicate
that these are the last ECP registers in this list.

7.2.2.23 Compact PCI Hot-Swap Control Register

Primary byte offset: EF:EEh
Secondary byte offset: EF:EEh

Table 7-24. Compact PCI Hot-Swap Control Register

Bit Name R/W Description

0 Reserv ed R Reserved. Read only as 0.

ENUM# Interrupt Mask.

When 0:

The 21554 asserts p_enum_l when an insertion or removal

1 ENUM _MA SK R/W

2 Reserv ed R Reserved. Read only as 0.

3 LED On/Off (LOO) R/W

5:4 Reserved R Returns 0 when read.

6REM STAT

7INS STAT

event occurs.

When 1:

The 21554 does not assert p_enum_l.

Reset value: 0

LED On/Off (LOO) Control. Allows software control of the l_stat pin
and therefore the state of the LED.

When 0:

The 21554 tristates l_stat. If REM STAT is low , the LED is of f if
the ejector handle is closed and on if the ejector handle is open. If
REM STAT is high, l_stat is not tristated but continues to be driven by
the 21554 (LED is off).

When 1:

The 21554 drives l_stat high and the LED is forced on.

Reset value:

Signal p_enum_l Removal Status. The 21554 sets this bit to a 1 when
l_stat is sampled high and p_rst_l is deasserted, signaling an impending
removal. This bit is cleared when software writes a 1. Clearing this bit

R/W1

causes the 21554 to tri-state l_stat. Writing a 0 has no effect.

TC

When 1:

about to be removed.
Reset value: 0

Signal p_enum_l Insertion Status. The 21554 sets this bit to a 1 when
l_stat is sampled low (ejector handle is closed), the serial preload is
complete and the Primary Lockout bit is cleared, indicating that the card
is ready for host initialization. This bit is cleared when software writes a

R/W1

1. Writing a 0 has no effect.

TC

When 1:

just been inserted.
Reset value: 0

0

The 21554 is asserting p_enum_l to indicate that the card is

The 21554 is asserting p_enum_l to indicate that the card has

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21554 PCI-to-PCI Bridge for Embedded Applications User’s Manual

Configuration Space Registers

7.2.3 Primary and Secondary Address Registers

This section contains descriptions of primary and secondary address registers.

7.2.3.1 Primary CSR and Downstream Memory 0 Base Address Register

Primary byte offset: 13:10h
Secondary byte offset: 53:50h

The Primary CSR and Downstream Memory 0 Base Address registers are us ed t o map the 21554
registers into primary memory space, and optionally to specify a memory range for downstream
forwarding of memory transactions. In order to speci fy a downs tream forwarding range, the
Downstream Memory 0 Setup Register must be loaded either from the serial ROM or by the local
processor before configuration software running on the host processor can access this register. Local
processor access of the setup register should be done before the Primary Lockout flag is cleared.

Table 7-25. Primary CSR and Downstream Memor y 0 Base Add ress Regi ster

Bit Name R/W Description

Space

0

Indicator

2:1 Type R

3 P refetchable R

11:4 R Returns 0 when read.

Base

31:12

Address

Type of address space requested. Reads as a 0 to indicate that memory

R

space is requested.
Indicates size and location of this address space.

Reset value:

32-bit memory.
Indicates whether the region is prefetchable. Accesses to the 21554 registers

are disconnected after the first data phase.

When 0:
When 1:

Reset value: 0

These bits are used to indicate the size of the requested address range and
to set the base address of the range. The low 4 KB of this address range map
the 21554 CSRs into primary memory space. The remaining space in this
range above 4 KB, if any, specifies a range for downstream forwarding of
memory transactions.

Bits [30:12] of the Downstream Memory 0 Setup register determine the
function of the corresponding bit in this register. If a bit in the setup register is

R/W

0 then the same bit in this register is a read-only bit and always returns 0
when read. If a bit in the setup register is 1 then the same bit in this register is
writeable and returns the value last written when read. If the setup register is
written to all zeros, the minimum size of 4 KB is requested (the 21554 CSR
access only, no forwarding range). The maximum size of this range is 2 GB;
therefore bit [31] is always writeable.

Reset value:

To 00 to indicate that this space can be mapped anywhere in

Nonprefetchable memory is requested.
Prefetchable memory is requested.

4 KB of nonprefetchable memory requested.

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Configuration Space Registers

7.2.3.2 Secondary CSR Memory Base Address Registers

Primary byte offset: 53:50h
Secondary byte offset: 13:10h

The Secondary CSR Memory Base Address register is used to map the 21554 registers into
secondary bus memory space.

Table 7-26. Secondary CSR Memory Base Address Registers

Bit Name R/W Description

0

2:1 Type R

3 Prefetchable R

11: 4 R Returns 0 when read.

31:12

Space
Indicator

Base
Address

R

R/W

Type of address space requested. Reads as a 0 to indicate that memory
space is requested.

Indicates size and location of the 21554 memory mapped registers. Reads
as 00 to indicate that the 21554 registers can be mapped anywhere in 32-bit
memory address space.

Indicates whether this space is prefetchable. Reads as 0 to indicate that
prefetching should not be used when reading the 21554 registers.

These bits are used to communicate to configuration software the size of the
requested memory address range and to set the base address of the range.
Since bits [31:12] are mappable, this indicates that the 21554 is requesting
4KB of memory space.

7.2.3.3 Primary and Secondary CSR I/O Base Address Register

Primary CSR I/O BAR Secondary CSR I/O BAR

Primary byte offset: 17:14h 57:54h
Secondary byte offset: 57:54h 17:14h

The Primary and Secondary CSR I/O Base Address registers are used to map the 21554 registers
into primary and secondary I/O space, respectively.

Table 7-27. Primary and Secondary CSR I/O Base Address Register

7-20

Bit Name R/W Description

0 Space Indicator R

7:1 Reserved R Reserved. Returns 0 when read.

31:8 Base Add ress R/W

Type of address space requested. Reads as a 1 to indicate that I/O
space is requested.

These bits are used to communicate to configuration software the size
of the requested I/O address range and to set the base address of the
range. Since bits [31:8] are mappable, this indicates that the 21554 is
requesting 256 bytes of I/O space.

21554 PCI-to-PCI Bridge for Embedded Applications User’s Manual

Configuration Space Registers

7.2.3.4 Downstream I/O or Memory 1 and Upstream I/O or Memory 0 BAR

Downstream I/O or Memory 1 BAR Upstream I/O or Memory 0 BAR

Primary byte offset: 1B:18h 5B:58h
Secondary byte offset: 5B:58h 1B:18h

These registers define address ranges in which either I/O or memory transactions can be forwarded
downstream or upstream. After reset, these registers are disabled and return all zeros when read.
This register may be enabled to request either 64, 128, or 256 bytes of I/O space (although
hardware does not restrict larger I/O windows), or 4 KB to 2 GB of memory space. The amount of
space requested is configured either by serial preload or by programming the Downstream I/O or
Memory 1 Setup register (for the downstream BAR) or the Upstream I/O or Memory 0 Setup
register (for the upstream BAR). Local processor access of the setup registers should be done
before the Primary Lockout flag is cleared.

Table 7-28. Downstream I/O or Memory 1 and Upstream I/O or Memory 0 BAR

Bit Name R/W Description

When read as a 0

0 Space Indicator R

2:1 Type R

3 Prefetchable R

5:4 R Read only. Returns 0 when read.

31:6 Base Address R/W

memory space.

When read as a 1:
Reset value:

Type indicator. If requesting I/O space, these bits read as zeros. If
requesting memory space, these bits indicate size and location of this
address range.

Reset value:

Prefetchable indicator. If requesting I/O or nonprefetchable memory,
reads as 0. If requesting prefetchable memory space, reads as 1.

Reset value:

These bits are used to indicate the size of the requested address range
and to set the base address of the range. Bits [30:6] of the
corresponding setup register determine the function of the
corresponding bit in this register. If a bit in the setup register is 0 then
the same bit in this register is a read-only bit and always return 0 when
read. If a bit in the setup register is 1, then the same bit in this register is
writeable and return the value last written when read. This base
address register may be disabled by writing bit [31] of the setup register
to zero. The minimum size for an I/O address range is 64 bytes and for
a memory range is 4 KB. The maximum size is 2 GB.

Reset value:

: Indicates that this BAR is disabled or is requesting

Indicates that I/O space is requested.

0

00b

0

This register is disabled (read only as 0).

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Configuration Space Registers

7.2.3.5 Downstream Memory 2 and 3 BAR, Upstream Memory 1 BAR

Because the description for these registers is very similar, they are discussed together.

Downstream
Memory 2 BAR

Primary byte offset: 1F:1Ch 23:20h 5F:5Ch
Secondary byte offset: 5F:5Ch 63:60h 1F:1Ch

Downstream
Memory 3 BAR

These registers define address ranges in which memory transactions on the primary in terface of the
21554 are forwarded to the secondary interface for the downstream BARs, and in which memory
transactions on the secondary interface are forwarded to the primary interface for the upstream
BAR. The setup registers corresponding to these BARs must be loaded either from the serial ROM
or by the local processor before configuration software running on the host processor can access
these registers. Local processor access of the setup registers should be done before the Primary
Lockout flag is cleared.

Table 7-29. Downstream Memory 2 and 3 BAR, Upstream Memory 1 BAR

Bit Name R/W Description

0 S pace Indicator R Reads only as 0 to indicate that memory space is requested.

Indicates size and location of this address space.

2:1 Type R

3 P refetchable R

11: 4 R Read only. Returns 0 when read.

31:12 Base Address R/W

Reset value:

32-bit memory.
Indicates whether the region is prefetchable.

When 0:

disabled).

When 1:

Reset value: 0

These bits are used to indicate the size of the requested address range
and to set the base address of the range. Bits [31:12] of the
corresponding setup register determine the function of the
corresponding bit in this register. If a bit in the setup register is 0, then
the same bit in this register is a read only bit and always returns 0
when read. If a bit in the setup register is 1, then the same bit in this
register is writeable and returns the value last written when read. This
base address register is disabled by writing bit [31] of the setup register
to zero. For the Downstream Memory 3 BAR, bit [31] of the Upper 32
Bits setup register must also be 0 to disable that range. The minimum
size for this address range is 4 K. The maximum size is 2GB, except
for the Downstream Memory 3 BAR which may use 64-bit addressing
and have a maximum window size of 2

Reset value:

00 to indicate that this space can be mapped anywhere in

Nonprefetchable memory is requested (or the range is

Prefetchable memory is requested.

63

Read only as 0 (range is disabled).

Upstream
Memory 1 BAR

bytes.

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21554 PCI-to-PCI Bridge for Embedded Applications User’s Manual

Configuration Space Registers

7.2.3.6 Upper 32 Bits Downstream Memory 3 Base Address Register

Primary byte offset: 27:24h
Secondary byte offset: 67:64h

Table 7-30. Upper 32 Bits Downstream Memory 3 Base Address Register

Bit Name R/W Description

This register defines the upper 32 bits of a memory r ang e for
downstream forwarding of memory transactions. The lower 32 bits are
contained in the Downstream Memory 3 Base Address register. These
bits are used to indicate the size of the requested address range and to
set the base address of the range. The value of each bit in the Upper 32
Bits Downstream Memory 3 Setup register determines the function of

31:0 Base Address R/W

the corresponding bit in this register. If a bit in the setup register is 0,
then the same bit in this register is a read-only bit a n d al ways return 0
when read. If a bit in the setup register is 1, then the same bit in th is
register is writeable and returns the value last written when read. This
base address register is disabled when bit [31] of the Upper 32 Bits
Downstream Memory 3 Base Address register is 0. The mi nimum size
for this address range is 4 K. The maximum size is 2

Reset value:

Read only as 0 (range is disabled).

63

bytes.

7.2.3.7 Upstream Memory 2 Base Address Register

Primary byte offset: 63:60h
Secondary byte offset: 23:20h

This register defines the memory range for ups tream forward ing of trans actio ns using look up tabl e
based address translation. The size of this register is programmed or disabled by setting the page
size in the Chip Control 1 configuration register.

Table 7-31. Upstream Memory 2 Base Address Register

Bit Name R/W Description

0 Space Indicator R Reads only as 0 to indicate that memory space is requested.

2:1 Type R

3 Prefetchable R

13:4 R Read Only. Returns 0 when read.

31:14 Base Address R/W

Indicates size and location of this address space. Reads as 00 to
indicate that this space can be mapped anywhere in 32-bit memory.

When this address range is enabled, read only as 1h to indicate
prefetchable memory. Page entries also may be individually
designated as prefetchable or nonprefetchable, where a
nonprefetchable entry overrides this prefetchable bit.

These bits are used to indicate the size of the requested address
range and to set the base address of the memory range for
upstream forwarding using lookup table based address translation.
The size of this window is a function of the page size, and can vary
from 16 KB to 4 MB increasing by powers of two. The number of
writeable bits is dependent on the window size, and varies from
[31:14] for a 16 KB window to [31:28] for a 256 MB window.

Reset value:

This address range is disabled (reads only as 0).

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Configuration Space Registers

7.2.3.8 Primary Expansion ROM Base Address Register

Primary byte offset: 33:30h
Secondary byte offset: 73:70h

This register defines an address rang e in which a mem ory r ead transaction on th e p rimary in terface
of the 21554 results in a read access to the parallel ROM interface. The Primary Expansion ROM
Setup register controls the size of the address range requested by the Primary Expansion ROM
Base Address register. The Primar y Ex pansion ROM Setup register m ust be load ed either from the
serial ROM or by the local processor before configuration software running on the host processor
can access this register. Local processor access should be done before the configuration lockout
flag is cleared.

Table 7-32. Primary Expansion ROM Base Address Register

Bit Name R/W Description

Enables the 21554 to respond to accesses to its expansion ROM
space. If this BAR is disabled this bit will return zero when read.

When 1:

0

11:1 Reserved R Reserved. Returns 0 when read.

31:12 Base Address R/W

Address Decode
Enable

R/W

The 21554 responds to memory accesses to expansion ROM

space if the Memory Enable bit is also set.

When 0:

The 21554 does not respond to accesses directed to this

address space.

Reset value:

These bits are used to indicate the size of the expansion ROM space
and to set the base address of the range. Bits [23:11] of the Primary
Expansion ROM Setup register determine the function of the
corresponding bit in this register. If a bit in the Primary Expansion ROM
Setup register is 0, the same bit in this register is a read-only bit and
always returns 0 when read. If a bit in the Primary Expansion ROM
Setup register is 1, then the same bit in this register is writeable and
returns the value last written when read. When this BAR is enabled, bits
[31:24] are always writeable. Writing a zero to bit [24] of the Primary
Expansion ROM Setup register disables this BAR. The minimum size
for this address range is 4 KB. The maximum size is 16 MB.

Reset value:

0.

0 (disabled).

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21554 PCI-to-PCI Bridge for Embedded Applications User’s Manual

Configuration Space Registers

7.2.3.9 Downstream I/O or Memory 1 and Upstream I/O or Memory 0
Translated Base Register

Dow

Downstream I/O or Memory 1
Translated Base

Primary byte offset: 9B:98h A7:A4h
Secondary byte offset: 9B:98h A7:A4h
CSR byte offset: 06 F:06Ch 07C:078h

Upstream I/O or Memory 0
Translated Base

These registers contain the translated ba se addresses for the ir respect ive downstream an d upstre am
BARs. The base address of the transaction on the ini tiator bus is r eplaced by t he ba se a ddress
contained in these registe rs. These register s are also mapp ed in the 2155 4 I/O and m emory CSR space.

Table 7-33. Downstream I /O or Memory 1 and Upstream I /O or Memory 0 T rans lated Base Regis ter

Bit Name R/W Description

5:0 Reserved R Reserved. Returns 0 when read.

Contains the translated base address for downstream or upstream
transactions whose initiator bus addresses fall into either the
Downstream I/O or Memory 1, or Upstream I/O or Memory 0 Base
Address range. The number of bits that are used for the translated base

31:6 XLAT_BASE R/W

is determined by the setup register corresponding to that base address
and also matches the number of writeable bits in the corresponding BAR.
The remaining bits may be written but are ignored when performing
address translation. When an I/O or memory transaction is initiated by the
21554 on the target bus, the original base address is replaced with the
value contained in this register.

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7-25

Configuration Space Registers

7.2.3.10 Downstream Memory 0, 2, 3, and Upstream Memory 1 Translated
Base Register

Downstream Memory 0
Translated Base

Primary byte offset: 97:94h 9F:9Ch A3:A0h
Secondary byte offset: 97:94h 9F:9Ch A3:A0h
CSR byte offset: 06B:068h 073:070h 077:074h

Upstream Memory 1
Translated Base

Primary byte offset: AB:A8h
Secondary byte offset: AB:A8h
CSR byte offset: 07F:07Ch

Downstream Memory 2
Translated Base

Downstream Memory 3
Translated Base

These registers contain the translated base addresses for their respective downstream and upstream
BARs. The base address of the transaction on the initiator bus is replaced by the base address
contained in these registers.

These registers are also mapped in the 21554 I/O and memory CSR space.

Table 7-34. Downstream Memory 0, 2, 3, an d Upstream Memory 1 T ranslated Base Register

Bit Name R/W Description

11:0 Reserved R Reserved. Returns 0 when read.

Contains the translated base address for downstream or upstream
transactions whose initiator bus addresses fall into one of the
following address ranges:

• Downstream Memory 0 (above low 4K boundary)

• Downstream Memory 2

• Downstream Memory 3

31:12 XLAT_BASE R/W

• Upstream Memory 1

The number of bits that are used for the translated base is
determined by the setup register corresponding to that base
address and also matches the number of writeable bits in the
corresponding BAR. The remaining bits can be written but are
ignored when performing address translation. When a memory
transaction is initiated by the 21554 on the target bus, the original
base address is replaced with the value contained in this register.

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21554 PCI-to-PCI Bridge for Embedded Applications User’s Manual

Configuration Space Registers

7.2.3.11 Downstream I/O or Memory 1 and Upstream I/O or Memory 0 Setup
Registers

Downstream I/O or Memory 1 Setup

Primary byte offset: B3:B0h C7:C4h
Secondary byte offset: B3:B0h C7:C4h

Upstream I/O or Memory 0
Setup

These registers may be preloaded by serial ROM or programmed by the local processor before host
configuration.

Table 7-35. Downstream I/O or Memory 1 and Upstream I/O or Memory 0 Setup Registers

Bit Name R/W Description

Type

0

Selector

2:1 Type R/(WS)

R/(WS)

When 0:

disabled.

When 1:
Reset value:

Type of space requested. Allowable values:

Other values may have unpredictable results.

The base address register is requesting memory space, or is

The base address register is requesting I/O space.

0

• 00b to indicate that the space requested by the BAR may be located
anywhere in memory space, must be used for I/O space

• 01b to indicate that memory space must be mapped below a 1MB
boundary

Reset value: 00h.

Indicates whether the space requested by the BAR is prefetchable.

When 0:

3 Prefetchable R/(WS)

5:4 Reserved R Read only as 0.

30:6 Size R/(WS)

31 BAR_Enable R/(WS)

space).

When 1:
Reset value

These bits specify the size of the address range requested by the BAR.
When a bit is 1, the corresponding bit in the BAR functions as a readable
and writeable bit. When a bit is 0, the corresponding bit in the BAR functions
as a read-only bit that always returns zero when read. The

Specification

not be greater than 256 bytes, although this is not enforced in hardware.
When configured as a memory range, bits [11:6] should be set to a 0 as the
minimum supported memory range is 4KB.

Reset value:

Base Address Register enable.

When 0:
When 1:

this setup register.

Reset value:

Not prefetchable (required, but not hardware enforced, for I/O

Prefetchable.

: 0

PCI Local Bus

states that the maximum value requested for I/O space should

0 (disabled).

The corresponding BAR is disabled and reads as 0.
The corresponding BAR is enabled, with size and type specified by

0

21554 PCI-to-PCI Bridge for Embedded Applica tio ns User’ s Ma nua l

7-27

Configuration Space Registers

7.2.3.12 Downstream Memory 0, 2, 3, and Upstream Memory 1 Setup
Registers

Downstream Memory 0
Setup

Primary byte offset: AF:ACh B7:B4h BB:B8h
Secondary byte offset: AF:ACh B7:B4h BB:B8h

Upstream Memory 1
Setup

Primary byte offset: CB:C8h
Secondary byte offset: CB:C8h

Downstream Memory 2
Setup

Downstream Memory 3
Setup

These registers are used to program the type and size of their respective upstream and downstream
base address registers.

Table 7-36. Downstream Memory 0, 2, 3, and Upstream Memory 1 Setup Registers

Bit Name R/W Description

0

2:1 Type R/(WS)

3 Prefetchable R/(WS)

11:4 Reserved R Read only as 0.

30:12 Size R/(WS)

31 BAR_Enable R/(WS)

Type
Selector

R

Read only as 0 to indicate memory space is requested by the corresponding
memory base address register.

Type of space requested. Allowable values are:

• 00b to indicate that the space requested by the base address register
may be located anywhere in memory space

• 01b to indicate that it must be mapped below a 1MB boundary

• 10b for Downstream Memory 3 Setup register to request a 64-bit BAR

Other values may yield unpredictable results.

Reset value:

Indicates whether the space requested by the base address register is
prefetchable.

When 0:
When 1:
Reset value

These bits specify the size of the address range requested by the base
address register. When a bit is 1, the corresponding bit in the BAR functions
as a readable and writeable bit. When a bit is 0, the corresponding bit in the
BAR functions as a read-only bit that always returns zero when read. Note:
If this field of the DS Memory 0 Setup is written to all zeros, the 21554 will
actually return 7FFFFh on reads (request 4 K ).

Reset value

whose reset value is 7FFFFh (request 4 KB).
Base Address Register enable. If the Upper 32 Bits Downstream Memory 3

Setup register bit [31] is a 1, then the corresponding BAR is enabled as a
64-bit register, and this bit is part of the size field for the 64-bit BAR.

When 0:

exception noted above.

When 1:

this setup register.

Reset value:

reset value is 1.

00b.

Not prefetchable.
Prefetchable.

: 0

: 0 (disabled), except for Downstream Memory 0 Setup register,

The corresponding BAR is disabled and reads as 0, with the

The corresponding BAR is enabled, with size and type specified by

0, except for Downstream Memory 0 Setup register, whose

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Configuration Space Registers

7.2.3.13 Upper 32 Bits Downstream Memory 3 Setup Register

Primary byte offset: BF:BCh
Secondary byte offset: BF:BCh

This register may be preloaded by serial ROM or programmed by the local processor before host
configuration.

Table 7-37. Upper 32 Bits Downstream Memory 3 Setup Register

Bit Name R/W Description

These bits specify upper 32 bits of the size of the address range requested by
Downstream M emory 3 Base Address register. When a bit is 1, the
corresponding bit in Downstream Memory 3 BAR functions as a readable and

30:0 Size R/(WS)

31 BAR_Enable R/(WS)

writeable bit. When a bit is 0, the corresponding bit in Downstream Memory 3
BAR functions as a read-only bit that always returns 0 when read. These bits
must be set to a non-zero value only when bits [2:1] of Downstream Memory 3
BAR are set to 10b (th is is not enforced in hardware).

Reset value:

64-bit Downstream Memory 3 BAR enable.

When 0:

a 32-bit BAR).

When 1:
Reset value:

0

The Downstream Memory 3 64-bit BAR is disabled (but may still be

The Downstream Memory 3 BAR is enabled as a 64-bit BAR.

0 (disabled)

7.2.3.14 Primary Expansion ROM Setup Register

Primary byte offset: C3:C0h
Secondary byte offset: C3:C0h

This register may be preloaded by serial ROM or programmed by the local processor before host

Table 7-38. Primary Expansion ROM Setup Register

configuration.

Bit Name R/W Description

11:0 Reserved R Reserved. Read only as 0.

These bits specify the size of the address range requested by the Primary
Expansion ROM Base Address register. When a bit is 1, the corresponding
bit in the Primary Expansion ROM Base Address register functions as a

23:12 Size R/(WS)

24 BAR_Enable R/(WS)

31:25 Reserved R Reserved. Returns 0 when read.

readable and writeable bit. When a bit is 0, the corresponding bit in the
Primary Expansion ROM Base Address register functions as a read-only bit
that always returns zero when read.

Reset value:

Base Address Register enable. Note the location of this bit in the preload
sequence, as shown in Section 7.3 and Chapter 20.

When 0:
When 1:

by this setup register.

Reset value:

0 (disabled).

The Primary Expansion ROM BAR is disabled and reads as 0.
The Primary Expansion ROM BAR is enabled, with size specified

0

21554 PCI-to-PCI Bridge for Embedded Applica tio ns User’ s Ma nua l

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Configuration Space Registers

7.2.4 Configuration Tr ansaction Generation Registers

This section contains descriptions of configuration transaction generation registers.

7.2.4.1 Downstream and Upstream Configuration Address Registers

Downstream Configuration Address Upstream Configuration Address

Primary byte offset: 83:80h 8B :88h (Reserved)
Secondary byte offset: 83:80h (Reserved) 8B:88h
CSR Space 003:000h 00B:008h

This description covers both the downstream and upstream versions of this register. These
registers are also mapped in memory and I/O space.

Table 7-39. Downstream and Upstream Configuration Address Registers

Bit Name R/W Description

This register contains the address for a configuration transaction to be
generated on the target bus. The address is driven exactly as written in this
register. This register should be written before the corresponding
Downstream or Upstream Configuration Data register is accessed. Once
the Downstream or Upstream Configuration Data register is accessed, the
transaction is initiated on the secondary or primary bus, respectively. If the
semaphore method is used, a master should not write to this register unless
the master has successfully read a 0 from the Downstream or Upstream
Configuration Own bit.

The Downstream Configuration Address register cannot be written from the
secondary interface. The Upstream Configuration Address register cannot
be written from the primary interface.

31:0

CFG_ADDR
(CA)

DCA:
R/(WP)

UCA:
R/(WS)

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Configuration Space Registers

7.2.4.2 Downstream Configuration Data and Upstream Configuration Data
Registers

Downstream Configuration Data Upstream Configuration Data

Primary byte offset: 87:84h 8F:8Ch (Reserved)
Secondary byte offset: 87:84h (Reserved) 8F:8Ch
CSR Space 007:004h 00F:00Ch

This description covers both the downstream and upstream versions of this register. These
registers are also mapped in memory and I/O space. This register is treated as a reserved register
for all memory accesses.

Table 7-40. Downstream Configuration Data and Upstream Configuration Data Registers

Bit Name R/W Description

This register contains the write data driven or the read data returned from a
configuration transaction initiated by the 21554. The Downstream or
Upstream Configuration Address register contains the address for this
transaction, depending on the direction of the transaction. The transaction
is initiated when this register is written (for a configuration write) or read (for
a configuration read) and the corresponding Configuration Control bit is a
one. The byte enables used for this register access are the same byte
enables used for the transaction driven on the target bus. A target retry is
returned to the initiator until the transaction has been completed on the
target bus. If the semaphore method is used, a master should not write to
this register unless the master has successfully read a 0 from the
Downstream or Upstream Configuration Own bit.

The Downstream Configuration Data register is reserved when accessed
from the secondary interface, or on either interface when the Downstream
Configuration Enable bit is not set. The Upstream Configuration Data
register is reserved when accessed from the primary interface, or on either
interface when the Upstream Configuration Enable bit is not set.

31:0

CFG_DATA
(CD)

DCD:
R/(WP)

UCD:
R/(WS)

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Configuration Space Registers

7.2.4.3 Configuration Own Bits Register

Primary byte offset: 91:90h
Secondary byte offset: 91:90h
CSR byte offs et 011:010h.

This register is also mapped in memory and I/O space.

Table 7-41. Configuration Own Bits Register

Bit Name R/W Description

Indicates ownership of the Downstream Configuration Address and
Downstream Configuration Data registers.

When 0:

Configuration Data registers are not owned. When read as a 0 from the

0

7:1 Reserved R Read only as 0.

8

15:9 Reserved R R ead only as 0.

Downstream
Configuration
Own Bit

Upstream
Configuration

Own Bit

R0TS(P)

R(S)

R0TS
(S)

R(P)

primary interface, this bit is subsequently set to a 1 by the 21554 if the
Downstream Configuration Control bit is a 1.

When 1:

Downstream Configuration Data registers. If this semaphore method is
used, other masters should not attempt to access these registers when this
bit is a 1. This bit is automatically cleared once the configuration
transaction has completed on the initiator bus.

Reset value:

Indicates ownership of the Upstream Configuration Address and Upstream
Configuration Data registers.

When 0:

Data registers are not owned. When read as a 0 from the secondary
interface, this bit is subsequently set to a 1 by the 21554 if the Upstream
Configuration Control bit is a 1.

When 1:

Configuration Data registers. If this semaphore method is used, other
masters should not attempt to access these registers when this bit is a 1.
This bit is automatically cleared once the configuration transaction has
completed on the initiator bus.

Reset value:

Downstream Configuration Address and Downstream

A master owns Downstream Configuration Address and

0.

Upstream Configuration Address and Upstream Configuration

A master owns Upstream Configuration Address and Upstream

0.

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21554 PCI-to-PCI Bridge for Embedded Applications User’s Manual

7.2.4.4 Configuration Control and Status Register

Primary byte offset: 93:92h
Secondary byte offset: 93:92h
CSR byte offset: 013:012h

This register is also mapped in memory and I/O space.

Table 7-42. Configuration Control and Status Register

Bit Name R/W Description

Configuration Space Registers

Downstream

0

Configuration
Own Status

Downstream

1

Configuration
Control

7:2 Reserved R Reserved. Returns 0 when read.

Upstream

8

Configuration
Own Status

Upstream

9

Configuration
Control

15:10 Reserved R Reserved. Reads only as 0.

R

R/W

R

R/W

Provides the current value of the Downstream Configuration Own bit. This
bit has no side effects when read.

Enables the 21554 to perform downstream indirect configuration
transactions.

When 0:

The 21554 will not initiate a configuration transac tion on the
secondary interface when the Downstream Configuration Data register is
accessed. The Downstream Configuration Data register is treated as a
reserved register.

When 1:

The 21554 is enabled to perform downstream configuration
transactions when the Downstream Configuration Data register is
accessed.

Reset value:

Provides the current value of the Upstream Configuration Own bit. This bit
has no side effects when read.

Enables the 21554 to perform upstream indirect configuration transactions.

When 0:

primary interface when the Upstream Configuration Data register is
accessed. The Upstream Configuration Data register is treated as a
reserved register.

When 1:

transactions when the Upstream Configuration Data register is accessed.

Reset value:

0

The 21554 will not initiate a configuration transac tion on the

The 21554 is enabled to perform upstream configuration

0

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Configuration Space Registers

7.2.5 Device-Specific Control and Status Registers

This section contains information about the device-specific control and status registers.

7.2.5.1 Chip Control 0 Register

Primary byte offset: CD:CCh
Secondary byte offset: CD:CCh

This register may be preloaded by serial ROM or programmed by the local processor before host
configuration.

Table 7-43. Chip Control 0 Register (Sheet 1 of 3)

Bit Name R/W Description

Controls the 21554’s behavior on the initiator bus when a master abort
termination occurs in response to a delayed transaction initiated by the
21554 on the target bus.

When 0:

0

1

2

3

Master Abort
Mode

Memory Write
Disconnect
Control

Primary
Master
Timeout

Secondary
Master
Timeout

R/W

R/W

R/W

R/W

The 21554 asserts TRDY# in response to a delayed transaction,

and returns FFFFFFFFh if a read.

When 1:

The 21554 returns a target abort in response to a delayed

transaction.

Reset value:

Controls the disconnect boundary for memory writes. This bit does not
apply to memory write and invalidate commands.

When 0:

boundary, a page boundary (Upstream Memory Range 2 only) or when the
posted write queue is full.

When 1:

boundary, or when the posted write queue is full.

Reset value:

Sets the maximum number of PCI clock cycles that the 21554 waits for an
initiator on the primary bus to repeat a delayed transaction request. The
counter starts when the delayed transaction completion is ready to be
returned to the initiator. If the initiator has not repeated the transaction at
least once before the counter expires, the 21554 discards the delayed
transaction from its queues.

When 0:

.983ms for a 33-MHz bus.

When 1:
Reset Value:

Sets the maximum number of PCI clock cycles that the 21554 waits for an
initiator on the secondary bus to repeat a delayed transaction request.
The counter starts when the delayed transaction completion is ready to be
returned to the initiator. If the initiator has not repeated the transaction at
least once before the counter expires, the 21554 discards the delayed
transaction from its queues.

When 0:

.983ms for a 33-MHz bus.

When 1:
Reset Value:

0

The 21554 disconnects memory writes either on an aligned 4KB

The 21554 disconnects memory write on an aligned cache line

0

The primary master timeout counter is 2

The value is 2

0

The secondary master timeout counter is 2

The value is 2

0

10

PCI clock cycles, or 30.7 µs for a 33-MHz bus.

10

PCI clock cycles, or 30.7 µs for a 33-MHz bus.

15

PCI clock cycles, or

15

PCI clock cycles, or

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21554 PCI-to-PCI Bridge for Embedded Applications User’s Manual

Table 7-43. Chip Control 0 Register (Sheet 2 of 3)

Bit Name R/W Description

Disables the primary master timeout counter.

When 0:

The primary master timeout counter is enabled and uses the

value specified by the Primary Master timeout bit.

When 1:

The primary master timeout counter is disabled. The 21554 waits

indefinitely for a primary bus initiator to repeat a delayed transaction.

Reset value:

Disables the secondary master timeout counter.

When 0:

The secondary master timeout counter is enabled and uses the

value specified by the Secondary Master Timeout bit.

When 1:

The secondary master timeout counter is disabled. The 21554
waits indefinitely for a secondary bus initiator to repeat a delayed
transaction.

Reset value:

Controls how the 21554 initiates delayed transactions on the target bus.

When 0:

which transaction is attempted. After receiving a target retry in response to
a delayed transaction, the 21554 can initiate a different queued delayed
transaction.

When 1:

transaction, the 21554 continues to attempt that same transaction until a
response other than target retry is received. The 21554 does not initiate
other delayed transactions until the above condition is satisfied.

The 21554 uses a round-robin arbitration scheme to determine

When a target retry is received in response to a delayed

Reset value: 0

SERR# forward enable.

When 0:

The 21554 does not assert p_serr_l as a result of s_serr_l
assertion.

When 1:

The 21554 asserts p_serr_l whenever s_serr_l is detected
asserted and the primary SERR# Enable bit is set.

Reset value:

Controls prefetching for upstream dual address transactions using the
memory read bus command.

When 0:
When 1:

prefetched; transactions are limited to a single Dword and byte enables are
preserved.

Prefetching is performed for upstream DAC memory reads.
Upstream DACs using the memory read bus command are not

Reset value:

Enables multiple devices to be attached to the ROM interface.

When 0:

Only the parallel and serial ROM can be attached to the ROM
interface. The parallel ROM chip select is driven on the pr_cs_l pin.

When 1:

Multiple devices may be attached to the ROM interface. All c hip
selects with the exception of the serial ROM are decoded from the upper
address lines of the ROM interface.

Reset value:

4

5

6

7

8

9

Primary
Master
Timeout
Disable

Secondary
Master
Timeout
Disable

Delayed
Transaction
Order Control

SERR#
Forward
Enable

Upstream
DAC Prefetch
Disable

Multiple
Device Enable

R/W

R/W

R/W

R/W

R/W

R/W

Configuration Space Registers

0

0

.

0

0

0

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Configuration Space Registers

Table 7-43. Chip Control 0 Register (Sheet 3 of 3)

Bit Name R/W Description

This bit prevents the primary bus from accessing configuration space. This
allows the local processor to access the 21554 registers before the host
processor accesses them.

This bit can be written from the secondary interface only. The local
processor must write this bit to a 0 to allow the 21554 to be configured by

10

11

13:12 Reserved R Reserved. Read only as 00b.

15:14 VGA Mode R/W

Primary
Access
Lockout

Secondary
Clock Disable

R/(WS)

R/W

the host processor, unless preloaded to 0 by serial ROM.

When 0:

The 21554 configuration space can be accessed from both

interfaces.

When 1:

The 21554 configuration space can only be accessed from the
secondary interface. Primary bus accesses, with the exception of the
Reset Control register, receive a target retry.

Reset value:

reset.
Secondary clock output disable.

When 0:

s_clk_o is driven as a buffered copy of p_clk.

When 1:

s_clk_o is disabled and driven low.

Reset value:

low during primary bus reset.

Enables address decoding and transaction forwarding of the following
VGA transactions:

• Frame buffer memory addresses 000BFFFF:000A0000h

• VGA I/O addresses 3BB:3B0h and 3DF:3C0h, where AD[31:16] =
0000h and AD[15:10] are not decoded.

The following values control how the 21554 decodes and forwards VGA
memory and I/O transactions:

• 00: VGA memory and I/O transactions on the primary and secondary
buses are ignored (unless decoded by some other mechanism).

• 01: VGA memory and I/O transactions on the primary bus are
forwarded to the secondary bus. VGA transactions on the secondary
bus are ignored.

• 10: VGA memory and I/O transactions on the secondary bus are
forwarded to the primary bus. VGA transactions on the primary bus
are ignored.

• 11: Illegal.The 21554 behavior is unpredictable.

Reset value

1 if pr_ad[3] is high during reset, 0 if pr_ad[3] is low during

0 if pr_ad[5] is high during primary bus reset; 1 if pr_ad[5] is

: 00b

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