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21153 (PCI-PCI Bridge)
Evaluation Board User Guide
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Intel 21153 (PCI-PCI Bridge) Evaluation Board User Guide

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21153 PCI-to- PCI Bridge Evaluation Board
User’s Guide
August 1998
Order Number: 278129-001
Intel may make changes to specifications and product descriptions at any time, without notice. Designers must not rely on the absence or characteristics of any features or instructions marked "reserved" or "undefined." Intel reserves these for
future definition and shall have no responsibility whatsoever for conflicts or incompatibilities arising from future changes to them. The 21153 may contain design defects or errors known as errata which may cause the product to deviate from published specifications. Current
characterized errata are available on request. Contact your local Intel sales office or your distributor to obtain the latest specifications and before placing your product order. Copies of documents which have an ordering number and are referenced in this document, or other Intel literature may be obtained by calling 1-800-
548-4725 or by visiting Intel’s website at http://www.intel.com.
Copyright © Intel Corporation, 1998 *Third-party brands and names are the property of their respective owners.
21153 PCI-to-PCI Brid ge Evaluation Board User’s Guide

Contents

1 Introduction.........................................................................................................................1
1.1 Overview...............................................................................................................1
1.2 Features................................................................................................................1
1.3 Major Components................................................................................................2
1.4 DIP Switches.........................................................................................................3
1.5 Optional Jumpers..................................................................................................4
1.6 Secondary Slot Numbering and IDSEL Mappin g .................................................. 5
1.7 Typical Conf igu r a tions...... ...................... ............................... .............................. ..5
2 Installa tion................... .............................. ............................... ............................... ......... ..1
2.1 Specifica tions............................. ............................... .............................. ..............1
2.2 Hardware Requirements .......................................................................................1
2.3 Software Requirements.........................................................................................1
2.4 Installation Procedure............................................................................................2
3 Interrupt Routing.................................................................................................................1
4 Optional Programmable Features......................................................................................1
4.1 Secondary PCI Bus Arbitra tion ..............................................................................1
4.2 Secondary Clock Control.......................................................................................3
A Kit Contents ........................................................................................................................1
Support, Products, and Documentation .......................................... ....... ..... ....... .. .......... ....3
21153 PCI-to-PCI Bridge Evaluation Board User’ s Gu id e iii

Figures

Tables

1-1 EB153 Major Components.................................................................. ....... ..... ......2
1-2 EB153 DIP Switches........... ...................... ............................... .............................3
1-3 Secondary PCI Slot Numbering............................................................................5
1-4 EB153 with One Secondary Bus Option Card ......................................................6
1-5 EB153 with Two Secondary Bus Option Cards....................................................6
1-6 Tri-Level with Two EB153s..................................................................................7
1-7 Four PCI Buses in a Tri-Level Hierarchy..............................................................7
4-1 Arbitration DIP Switches .......................................................................................2
4-2 Secondary Clock DIP Switch ................................................................................5
1-1 DIP Switch Operation............................................................................................4
1-2 Jumper Connections .............................................................................................4
3-1 Interrupt ORing......................... ............................... ............................... ...............1
3-2 Interrupts from Devices to EB153 Fingers............................................................2
4-1 Internal Arbitration DIP Switch Positions...............................................................2
4-2 External PAL Arbitration DIP Switch Positions......................................................3
4-3 gpio Serial Data Format........................................................................................4
4-4 Secondary Clock DIP Switch Positions.................................................................5
iv 21153 PCI-to-PCI Brid ge Evaluation Board User’s Guide
Introduction
This document describes the 21153 PCI-to-P CI Bridge Evaluation Boar d (also referred to as the EB153). The EB153 is an evalua tion and development board for systems based on the 21153 PCI-to-PCI Bridge chip (t he 21153).
Intel 21153 is a second-generation PCI-to-PCI bridge and is fully compliant with the electrical and protocol requi rements of th e PCI Local Bu s Specifi ca tio n, Revis ion 2. 1, a nd the P CI-to-PCI Bridge Architecture Specification, Revision 1.0. The 21153 provides full supp ort for delayed transactions, which enables the buffering of memory read, I/O, and configuration transactions. The 21153 has separate posted write, read data, and delayed trans action queues with significa ntly more buffering capability than first-generation bridges.
For detailed info rmation about the 21153, refer to the 21 153 PCI-to-PCI Bridge Data Sheet.

1.1 Overview

The EB153 is a unive rs al PCI exp ansi on board th at is used t o eval uate t he opera tion of t he 21153 in various configurations, and with a variety of PCI devices. The EB153 can be used to perform the following functions:
• Develop initia lization code to configu re a PCI-to-PCI bridge and the PCI devices behind the
bridge
1
• Evaluate the operation of a PCI-to-PCI bridge with a variety of PCI devices attached to the
secondary bus
• Build an d ev al u at e a fl ex i b le hi er ar c h y f or mu ltiple PCI bu ses

1.2 Features

The EB153 has the following features:
• Complies fully wit h the protocol and electrical standards of the PCI Local Bus Specification,
Revision 2 .1
• Includes a 21153 PCI-to-PCI Bridge that provide s bri dging between a 64-bit primary and
32-bit secondary bus.
• Includes a primary PCI bus that plugs into any 5-V or 3.3-V PCI option card slot.
• Provides four secondary 5-V PCI bus option card slots.
• May be built with 3.3-V secondary PCI card slots. If you are inter ested in this option, call the
Information Line (see Support, Products, and Documentati on).
• Supports an optional external secondary bus arbiter.
• Supports multi ple levels of PCI bus hierarchy.
21153 PCI-to-PCI Bridge Evaluation Board
User’s Guide 1-1
Introduction

1.3 Major Components

Figure 1-1 shows the major components on the EB153.
Figure 1-1. EB153 Major Components
Viewed from Side 1
J11_J12,J19_J21_Optional
Scope Jack Mounting Holes to Observe
s_clk_o<7:4>
J13 _ Optional
External Power Connector
E4 _ Socket for Optional PAL to Control Secondary Bus Arbitration
SW4 and SW2 _ DIP Switches to Control Internal/External Arbiter Options
SW3 _ DIP Switch to Control the gpio Secondary Clock Mask Control
J7
J21 J20 J19 J12 J11
J10
J17
J13
J9
E6
E5
SW4
SW3
SW1 _ DIP Switch Positions 1 through 4 and 6 Are Normally Closed; Position 5 Is Open
E4
SW2
SW1
J6
J5
J4
J8 J24
J23
J18
J3
E3
21153
PCI Option Card Slot (PCI Device 7)
PCI Option Card Slot (PCI Device 6)
PCI Option Card Slot (PCI Device 5)
PCI Option Card Slot (PCI Device 4)
J1, J3, J8, J9, J10, J17, J18, J22, J23,
J1
E1
E2
J22
J24 _ Logic Analyzer or Scope Monitoring Pods
E1 _ Standard 3.3-V Voltage Regulator (Supplies only the 21153 Device)
E2 _ Optional High-Current 3.3-V Voltage Regulator for Boards with 3.3-V Secondary Connectors
LJ-05474.AI4
1-2
21153 PCI-to-PCI Brid ge Evaluation Board
User’s Guide

1.4 DIP Switches

There are four 6-position DIP switches on the EB153. Figure 1-2 shows the locations of the DIP switches, and Table 1-1 describes their operation.
Figure 1-2. EB153 DIP Switches
J21 J20 J19 J12 J11
Introduction
Viewed from Side 1
J7
J6
J5
E4 _ Socket for Optional PAL to Control Secondary Bus Arbitration
SW4 and SW2 _ DIP Switches to Control Internal/External Arbiter Options
SW3 _ DIP Switch to Control the gpio Secondary Clock Mask Control
J10
J17
J13
J9
E6
E5
SW4
SW3
SW1 _ DIP Switch Positions 1 through 4 and 6 Are Normally Closed; Position 5 Is Open
E4
SW2
SW1
J4
J8 J24
J23
J18
J3
E3
21153
J1
E1
E2
J22
LJ-05475.AI4
21153 PCI-to-PCI Bridge Evaluation Board
User’s Guide 1-3
Introduction
Table 1-1 describes DIP switch operation. Set up DIP switches before powering up the system.
Table 1-1. DIP Switch Operation
DIP Switches
SW1
1
SW2
1
SW4
2
SW3
1
Table 4-1 and Table 4-2 provide detailed information about configuring this switch.
2
Table 4-2 and Table 4-4 provide detailed information about configuring this switch.
Description
Positions 1, 2, 3, 4, and 6 are closed and 5 is open for normal operation. To enab le all s_clk, open position 4 and close position 5.
Controls the arbiter. For internal arbiter, all positions are closed. For external arbiter, all positio ns are open.
Controls the arbiter. For internal arbiter, all positions are open For external arbit er, all positions are closed.
Controls the gpio clock ma sk sequence f or secondary clocks s_cl k_o<7:4>. For normal operat ion, all posit ions are ope n.
This disables the unused 21 153 s_clk_o<7:4> clocks.

1.5 Optional Jumpers

The EB153 provides optional jumpers as a special feature. T he jumpers can be used for d ebugging and for s p ecial evaluation tests.
To improve signal integrity, signal p_clk and signals s_clk< 3 :0> are not wired to scope pod positions for the default EB153 build. However, provis ion has been made in the design for viewing these sig n al s if ne ed e d.
Table 1-2 shows the connections required to allow observation of these signals at scope pod connector pin s.
Table 1-2. Jumper Connections
Jumper Description
R33 (0-Ω) resistor If installed, allows observation of p_clk at J9, pin 15. R44 (0-Ω) resistor If installed, allows observation of s_clk_o<0> at J17, pin 7. JW1-to-JW1 If connected with a wire, allows observation of s_clk_o<1 > at J17,
JW2-to-JW2 If connected with a wire, allows observation of s_clk_o<2> at J17,
JW3-to-JW3 If connected with a wire, allows observation of s_clk_o<3> at J17,
Note: The JW1, JW2, and JW3 holes are located on Side 2 of the EB153 They are labeled in etch. Intel
recommends that you use a meter to verify that the correct holes are used for jumper wires before connecting them.
A ground via has been placed to each of the JW1, JW2, and JW3 hole s so that a coaxi al wire can be used.
1-4
pin 5.
pin 3.
pin 1.
21153 PCI-to-PCI Brid ge Evaluation Board
User’s Guide
Introduction

1.6 Secondary Slot Numbering and IDSEL Mapping

The PCI secondary bus opt ion card s lots are mapped to PCI device number s 4, 5, 6, and 7 as shown in Figure 1-3. The secondary bus lines s_ad<20:23> are use d as secondary IDSEL lines.
Figure 1-3. Secondary PCI Slot Numbering
PCI Device Numbers
456
7

1.7 Typical Configurati ons

The EB153 support s various PCI config urat ion s with di f ferent types of devic es. Figure 1-4 through Figure 1-7 show examples of PCI configurations.
The primary bus connect or attaches to a PCI slot on the motherboard of the host system or to a secondary PCI bus slot on another EB153. A 5-V or universal PCI option card, or another EB153, can be plugged into any one of the four secondary bus option card slots.
PCI Option Card Slots
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21153 PCI-to-PCI Bridge Evaluation Board
User’s Guide 1-5
Introduction
Figure 1-4 shows the EB153 with one secondary bus option card.
Figure 1-4. EB153 with One Secondary Bus Optio n Card
Host System
Motherboard
21153
EB153
Figure 1-5 shows the EB153 with two secondary bus option card s.
Figure 1-5. EB153 with Two Seconda ry Bus Op tion Cards
Option Card
PCI
Device
LJ-05477.AI4
Host System
Motherboard
21153
EB153
Option Card
PCI
Device
Option Card
PCI
Device
LJ-05478.AI4
1-6
21153 PCI-to-PCI Brid ge Evaluation Board
User’s Guide
Figure 1-6 shows a tri-level bus with two EB153s.
Figure 1-6. Tri-Level with Two EB153s
Host System Motherboard
EB153
21153
Figure 1-7 shows four PCI buses in a tri-level hierarchy.
Option Card
PCI
Device
EB153
21153
Introduction
Option Card
PCI
Device
LJ-05479.AI4
Figure 1-7. Four PCI Buses in a Tri-Level Hierarchy
Host System
Motherboard
EB153
21153
21153
21153
EB153
EB153
Option Card
PCI
Device
Option Card
PCI
Device
LJ-05480.AI4
21153 PCI-to-PCI Bridge Evaluation Board
User’s Guide 1-7
Installation
This chapter provi des information about the EB153 speci f ications and the hardware and software requirements for using the EB153. It also describes how to install the EB153.

2.1 Specifications

The physical and power specifications for the EB153 are as follows: Dimensions:
• Height: 18.5 cm (7.3 in)
• Width: 16.7 cm (6.6 in)
Power Requirements:
• dc amps @ 5 V: 2.0 A (maximum)

2.2 Hardware Requirements

The following equipment is required to use the EB153:
• A computer system equipped with a PCI motherboard
2
• A PCI expansion slot on the motherboard that is equipped for the 5-V or 3.3-V environment

2.3 Software Requirements

To test the EB153 in x86 DOS or Windows systems, system BIOS must include autoconfiguration code for PCI-to-PCI bridges. If the system BIOS does not include this functionality, contact your BIOS vendor to obtain code with PCI-to-PCI bridge autoconfiguration support.
The EB153 kit provides a DOS utility that can be used to configure the PCI-to-PCI bridge. The diskette included in the EB153 kit contains the DOS utility and a README.TXT file that explains how to use it.
21153 PCI-to-PCI Bridge Evaluation Board
User’s Guide 2-1
Installation

2.4 Installation Procedure

Figure 1-1 illustrates the EB153 and shows the location of components r efe rred to in this section. Install the EB153 as f o llows:
1. Power down the host system that will contain the EB153.
2. Place the motherboard with the associated support devices on a bench if mechanical constrai nts do not allow testing of the EB153 and the expansion slots inside the syste m box.
3. Configure your system as follows:
a. Insert the card edge of the EB153 into a PCI slot. b. Insert a 5-V or unive rsal option P CI card i nto any or each of t he four s econdary bus option
card slots. Section 1.7 shows examples of typical PCI configurations.
4. Verify the DIP swit ch s ettings for SW1 through SW4 (for normal operat ion, SW1 positions 1 through 4 and position 6 are closed; posi tion 5 is open).
To enable all secondary clocks, open position 4 and clos e position 5.
5. Power up the system.
6. Verify autoc onfiguration of the 21153 and of any devices that are plugged in as fol lows :
a. Verify that system BIOS or firmware detects and configures the PCI devices downstream
of the 21153. If system BIOS is not available, use the DOS utility provided with the EB153 kit to configure the devices downstream of the 21153, and verify proper configuration.
b. Install de vice drivers for any PCI devices that are downs tream the 21153, and veri fy
proper configuration of those devices.
7. If desired, monit or bridge PCI c ont rol sig nals by conn ecti ng a logic analy zer to pod s J1, J3, J8, J9, J10, J17, J18, J22, J23, and J24.
2-2
21153 PCI-to-PCI Brid ge Evaluation Board
User’s Guide
Interrupt Routing
This chapter describes the way in which interrupts are routed. This information is provided as a reference for designers .
Because a total of 16 interrupts are connected to the secondary bus PCI slots (INTA#, INTB#, INTC#, and INTD# for each slot) and only four interrupts are driven to the card edge, the 16 incoming interrupts must be combined. This ORing of interrupts is perfo rmed in accordance with the PCI-to-PCI Bridge Architecture Specification.
Table 3-1 shows the ORing of interrupts .
Table 3-1. Interrupt ORing
3
Device Number Interrupt Pin
on Device
4 INTA#
INTB# INTC# INTD#
5INTA#
INTB# INTC# I INTD#
6INTA#
INTB# INTC# INTD#
7INTA#
INTB# INTC# INTD#
Interrupt Pin on Board Connector
INTA# INTB# INTC# INTD#
INTB# INTC# INTD# INTA#
INTC# INTD# INTA# INTB#
INTD# INTA# INTB# INTC#
In accordance with the PCI-to-PCI Bridge Arch itecture Specification, interrupts of the devices on the secondary slots are wire ORed and routed to PCI fingers of the EB153.
21153 PCI-to-PCI Bridge Evaluation Board
User’s Guide 3-1
Interrupt Routing
Table 3-2 lists the interrupts fro m the devices on the s econdary slots to the interrupts on the EB153 fingers.
Table 3-2. Interrupts from Devices to EB153 Fingers
Interrupts from Devices on Secondary Slots
INTA4 L INTD5 L INTC6 L INTB7 L
INTB4 L INTA5 L INTD6 L INTC7 L
INTC4 L INTB5 L iNTA6 L INTD7 L
INTD4 L INTC5 L INTB6 L INTA7 L
Interrupts on EB153 Fingers
INTA L
INTB L
INTC L
INTD L
Note: In the first column of Table 3-2, the number after each interrupt pin is the device number of the
devices in the s econdary slots. The L indicates that the assertion level is low.
3-2
21153 PCI-to-PCI Brid ge Evaluation Board
User’s Guide
Optional Programmable Features
This chapter desc ribes the use of DIP switches to test 21 153 secondary bus arbitrat ion and secondary clock control functions.

4.1 Secondary PCI Bus Arbitration

This section des cribes secondary bus arbitration and the arbitration DIP switche s. (For more detailed information about the 21153 arbiter, refer to the 21153 PCI-to-PCI Bridge Data Sheet).
The EB153 has two secondary bus arbiter systems:
• An internal arbit er that supports nine external masters in addition to the 21153
• An optional external arbiter implemented in an AMD MACH210A programmable device
The default setting is internal arbitration. The internal 21153 arbiter implements a 2-level programmable rotat ing mode algori thm. Secondary bus parking is done at the last mas ter to use the bus.
The internal arbiter can be disabled, and an external arbiter can be used instead for secondary bus arbitration. The EB153 provides a socket for an optional PAL (labeled E4 in Figure 4-1) to control secondary bus arbitration. If a different external arbiter is used where parking is done at one of the PCI slots, a PCI device must be ins talled in that slot. To change the default, configure the secondary bus arbiter system using DIP switches SW2, SW3, and SW4.
4
Figure 4-1 shows the location of the arbit rat ion DIP switch es, and Table 4-1 and Ta ble 4-2 describe their operation.
All DIP switch positions assume that th e E B153 is positioned with the components facing forward and the card edge facing down.
21153 PCI-to-PCI Bridge Evaluation Board
User’s Guide 4-1
Optional Programmable Features
Figure 4-1. Arbitration DIP Switches
J21 J20 J19 J12 J11
Viewed from Side 1
J7
J6
J5
E4 _ Socket for Optional PAL to Control Secondary Bus Arbitration
SW4 and SW2 _ DIP Switches to Control Internal/External Arbiter Options
J10
J17
J13
J9
E6
E4
E5
SW4
SW3
Table 4-1 describes the operation of internal arbitration jumpers.
Table 4-1. Internal Arbitration DIP Switch Positions
J8 J24
J23
J18
SW2
SW1
J4
J1
J3
E1
E2
J22
E3
21153
LJ-05481.AI4
4-2
DIP Switch Position Setting Description
SW2 1 Closed When closed, signal s_cfn_l is tied low to enable the
intern al arb iter.
2 Closed When closed, signal s_req_l<0> is tied to one of the
seconda ry PCI connectors for in clusion in the internal arbitration.
3–6 Closed When cl osed, sign als s_gnt_l<3:0> are connected from
the 21153 to the four secondary PCI connectors for use in the internal arbitration.
SW4 1–5 Open Disables connection of the s_gnt_l<3:0> and
s_req_l<0> signals between the 21153 and the external PAL.
21153 PCI-to-PCI Brid ge Evaluation Board
User’s Guide
Table 4-2 describes the operation of DIP switches for external arbitration with PAL.
Table 4-2. External PAL Arbitration DIP Switch Positions
DIP Switch Position Setting Description
Optional Programmable Features
SW2 1 Open Enables pullup for signal s_cfn_l to disable the internal
2 Open Disables the direct connection of signal s_req_l<0> to
3–6 Open Disables the direct connection of signals s_gnt_l<3:0>
SW4 1 Closed Connects signal s_req_l<0> to the external PAL.
2–5 Closed Connects signals s_gnt_l<3:0> from the four
SW3 5 Closed Enables signal s_clk_o<8> (by means of the gpio
arbiter.
a secondary PCI connector.
to the four secondary PCI connectors.
Because s_cfn is pulled high (SW2, position 1), this signal is used as the s_gnt_l to the 21153 by the external PAL.
secondary PCI connectors to the external PAL.
mask circuit) for use with the external PAL.

4.2 Secondary Clock Control

This section des cribes secondary clock control and the secondary clock DIP switch. The 21153 implements a 4-pin general-purpose I/O gpio interface. During normal operation, the
gpio interface is controlled by device-specific configuration registers. The gpio interface can be used during secondary interface reset to control secondary clocks on the
21153. The 21153 uses the gpio pins and the msk_in signal to input a 16-bit serial data stream. This data stream is shi f ted into the secondary clock control register and is used for selectively disabling sec ondary clock outputs.
The gpio clock mask inputs for the unused secondary clocks s_clk_o<8:4> are controlled by the secondary clock DIP switc h, SW3, as explained in Table 4-3. The gpio clock mask inputs for the used secondary clocks s_clk_o<3:0> are controlled by the state of the PCI PRSNT# signals from each of the four secondary PCI slots.
21153 PCI-to-PCI Bridge Evaluation Board
User’s Guide 4-3
Optional Programmable Features
T able 4-3 shows the format of the serial data stream.
Table 4-3. gpio Serial Data Format
Bit Description s_clk_o Output
<1:0> Slot 4 PRSNT#<1:0> or device 0 0 <3:2> Slot 5 PRSNT#<1:0> or device 1 1 <5:4> Slot 6 PRSNT#<1:0> or device 2 2 <7:6> Slot 7 PRSNT#<1:0> or device 3 3 <8> Device 4 <9> Device 5 <10> Device 6 <11> Device 7 <12> Device 8 <13> 21153 s_clk input 9 <14> Reserved Not applicable <15> Reserved Not applicable
1
Controlled by DIP switch SW3.
1 1 1 1 1
4 5 6 7 8
For more information about the format of the serial data stream, as presented in Table 4-3, and gpio mask implementation, see Section 10.2 in the 21153 PCI-to-PCI Bridge Data Sheet.
4-4
21153 PCI-to-PCI Brid ge Evaluation Board
User’s Guide
T abl e 4-4 describes the use of the DIP switch to control secondary clocks and Figu re 4-2 shows the location of the secondary clock DIP switch.
Table 4-4. Secondary Clock DIP Switch Positions
DIP Switch Position Setting Description
Optional Programmable Features
SW3 1–4 Open For normal operation, the open setting disables th e
1–4 Closed Positions 1–4 can be closed individually before
5 Open Disables s_clk_o<8> when the internal arbiter is used.
Figure 4-2. Secondary Clock DIP Switch
J11_J12,J19_J21_Optional
Scope Jack Mounting Holes to Observe
s_clk_o<7:4>
SW3 _ DIP Switch to
Control the gpio Secondary Clock Mask Control
unused 21153 s_clk _o<7:4> clocks.
powering up, to enable 21153 s_clk_o<7:4> clocks selectively for ch aracterization at sco pe jack locations J12–J15.
Viewed from Side 1
J7
J21
J17
SW4
SW3
J20 J19 J12 J11
J10
J13
J9
E6
E4
E5
SW2
SW1
J6
J5
J4
J8 J24
J23
J18
J3
E3
21153
J1
E1
E2
J22
21153 PCI-to-PCI Bridge Evaluation Board
LJ-05482.AI4
User’s Guide 4-5

Kit Contents A

This appendix lists the contents of the 21 153 PCI-to-PCI Bridge Evaluatio n Kit. The 21153 PCI-to-PCI Bridge Evaluation Kit contains the following material s:
• A 21153 PCI-to - P CI Bridge Evaluation Board (EB153)
• A diskette that con tains an MS-DOS utility for configuring the EB153
• A documentation package that includes the following:
— 21153 PCI-to-PCI Bridge Data Shee t — 21153 PCI-to-PCI Bridge Product Brief — 21153 PCI-to-PCI Bridge Configuration Application Note — 21153 PCI-to-PCI Bridge Hardware Implementation Application Note
— 21153 PCI-to-PCI Bridge Evaluation Boar d User’s Guide
— 21153 Evaluation System BIOS Letter — 21153 PCI Evaluation Board Schematics — 21153 Evaluation Board Vendor Parts List — SPICE model kit containing a Level 28 21153 S P I CE model and application note — Warranty Agreement/Registration Card
21153 PCI-to-PCI Bridge Evaluation Board
User’s Guide A-1

Support, Products, and Documentation

If you need technical support, a Pr odu ct Cat alog , or hel p deci din g which d ocume ntati on bes t meets your needs, visi t the Intel W orld Wide Web Internet site:
http://www. inte l.com
Copies of document s th at have an ordering number and are referenced in this document, or other Intel literature may be obtained by calling 1-800-332-2717 or by visiting Intel’s website for
developers at:
http://developer.intel.com
You can al so con ta ct the In tel Ma ssa chus et ts Inf or matio n Li ne or the Int el Mass achus et ts Cu st omer Technology Center. Please use the following information lines for support:
For documentation and general information:
Intel Massachusetts Information Line United States: 1–800–332–2717
Outside United States: 1–303-675-2148 Electronic mail address: techdoc@intel.co m
For technical support:
Intel Massachusetts Customer Technology Center Phone (U.S. and international): 1–978–568–7474 Fax: 1–978– 568–6698 Electronic mail address: techsup@intel.com
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