Information in this document is provided in connection with Intel products. No license, express or implied, by estoppel or otherwise, to any intellectual
property rights is granted by this document. Except as provided in Intel’s Terms and Conditions of Sale for such products, Intel assumes no liability
whatsoever, and Intel disclaims any express or implied warranty, relating to sale and/or use of Intel products including liability or warranties relating to
fitness for a particular purpose, merchantability, or infringement of any patent, copyright or other intellectual property right. Intel products are not
intended for use in medical, life saving, or life sustaining applications.
Intel may make changes to specifications and product descriptions at any time, without notice.
Designers must not rely on the absence or characteristics of any features or instructions marked "reserved" or "undefined." Intel reserves these for
future definition and shall have no responsibility whatsoever for conflicts or incompatibilities arising from future changes to them.
The 21152 may contain design defects or errors known as errata which may cause the product to deviate from published specifications. Current
characterized errata are available on request.
Contact your local Intel sales office or your distributor to obtain the latest specifications and before placing your product order.
Copies of documents which have an ordering number and are referenced in this document, or other Intel literature may be obtained by calling 1-800-
548-4725 or by visiting Intel’s website at http://www.intel.com.
4-2External PAL Arbitration Jumper Positions...........................................................3
iv21152 PCI-to-PCI Brid ge Evaluation Board User’s Guide
Introduction
This document describes the Intel 21152 PC I-to-PCI Bridge Evaluation Boar d (also referred to as
the EB152). The EB152 is an evaluation and development board for systems based on the Intel
21152 PCI-to-P CI Bridge chip (the 21152).
Intel’s 21152 is a second-generation PCI-to-PCI bridge an d is fully compliant with the electr ical
and protocol requirements of the PCI-to-PCI Bridge Architecture Specification, Revision 2.1, and
the PCI-to-PCI Bridge Archit ecture Specific ation, Revision 1.0. The 21152 provides full support
for delayed transactions, which enables the buffering of memory read, I/O, and configuration
transactions . The 21152 has separate posted write, read data, and delayed trans action queues with
significantly more buffering capability than first-generation bridges.
For detailed info rmation about the 21152, refer to the 21 152 PCI-to-PCI Bridge Data Sheet.
1.1Overview
This chapter provides an overview of the 21152 PCI-to-PCI Bridge Evaluation Board EB152 and
includes inf orm ation about the following topic s :
• Jumper location
1
• Secondary slot numbering and IDSEL mapping
• Typical configurations
The EB152 is a unive rs al PCI exp ansi on board th at is used t o eval uate t he opera tion of t he 21152 in
various configurations, and with a variety of PCI devices. The EB152 can be used to perform the
following functions:
• Develop initia lization code to configu re a PCI-to-PCI bridge and the PCI devices behind the
bridge
• Evaluate the operation of a PCI-to-PCI bridge with a variety of PCI devices attached to the
secondary bus
• Build an d ev al u at e a fl ex i b le hi er ar c h y f or mu ltiple PCI bu ses
1.2Features
The EB152 has the following features:
• Complies fully wit h the protocol and electrical standards of the PCI Local Bus Specification,
Revision 2.1.
• Includes a 21152 PCI-to-PCI Bridge that prov ides bridging between a primary and seco ndary
bus.
• Includes a primary PCI bus that plugs into any 5-V or 3.3-V PCI option card slot.
The EB152 provides 10 jumpe rs that can be used for debugging and for special evaluation tests.
The jumpers can be used for monit ori ng CLK sign als and 21 1 52 secondary PCI signal s. Addit ion al
optional jump ers control secondary bus arbitration.
Table 1-1 shows the connections required to allow observation of these signals at scope pod
connector pins.
Table 1-1. Jumper Connections
JumperDescription
J1This jumper monitors the foll owing signals:
J2, J8 through J12Logic analyzer pods can be plug ged into thes e jumpers for
W1, W4, J7These jumpers control secondary bus arbitration. Chapter 4, Secondary Bus
Introduction
p_clk (PCI clock)
s_clk_o<4:1> (four secondar y PCI clocks)
s_clk_o<0> (fed back to the s_clk input pin)
s_gnt_l<2> and s_gnt_l<3> .
monit oring 21152 secondary PCI sig nals.
Arbitration, provides information about configuring these jumpers.
1.5Secondary Slot Numbering and IDSEL Mapping
The PCI secondary bus opt ion card s lots are mapped to PCI device number s 4, 5, 6, and 7 as shown
in Figure 1-2. The secondary bus lines s_ad<20:23> are used as se co ndary IDSE L lines.