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Designers must not rely on the absence or characteristics of any features or instructions marked "reserved" or "undefined." Intel reserves these for
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The 21152 may contain design defects or errors known as errata which may cause the product to deviate from published specifications. Current
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4-2External PAL Arbitration Jumper Positions...........................................................3
iv21152 PCI-to-PCI Brid ge Evaluation Board User’s Guide
Introduction
This document describes the Intel 21152 PC I-to-PCI Bridge Evaluation Boar d (also referred to as
the EB152). The EB152 is an evaluation and development board for systems based on the Intel
21152 PCI-to-P CI Bridge chip (the 21152).
Intel’s 21152 is a second-generation PCI-to-PCI bridge an d is fully compliant with the electr ical
and protocol requirements of the PCI-to-PCI Bridge Architecture Specification, Revision 2.1, and
the PCI-to-PCI Bridge Archit ecture Specific ation, Revision 1.0. The 21152 provides full support
for delayed transactions, which enables the buffering of memory read, I/O, and configuration
transactions . The 21152 has separate posted write, read data, and delayed trans action queues with
significantly more buffering capability than first-generation bridges.
For detailed info rmation about the 21152, refer to the 21 152 PCI-to-PCI Bridge Data Sheet.
1.1Overview
This chapter provides an overview of the 21152 PCI-to-PCI Bridge Evaluation Board EB152 and
includes inf orm ation about the following topic s :
• Jumper location
1
• Secondary slot numbering and IDSEL mapping
• Typical configurations
The EB152 is a unive rs al PCI exp ansi on board th at is used t o eval uate t he opera tion of t he 21152 in
various configurations, and with a variety of PCI devices. The EB152 can be used to perform the
following functions:
• Develop initia lization code to configu re a PCI-to-PCI bridge and the PCI devices behind the
bridge
• Evaluate the operation of a PCI-to-PCI bridge with a variety of PCI devices attached to the
secondary bus
• Build an d ev al u at e a fl ex i b le hi er ar c h y f or mu ltiple PCI bu ses
1.2Features
The EB152 has the following features:
• Complies fully wit h the protocol and electrical standards of the PCI Local Bus Specification,
Revision 2.1.
• Includes a 21152 PCI-to-PCI Bridge that prov ides bridging between a primary and seco ndary
bus.
• Includes a primary PCI bus that plugs into any 5-V or 3.3-V PCI option card slot.
The EB152 provides 10 jumpe rs that can be used for debugging and for special evaluation tests.
The jumpers can be used for monit ori ng CLK sign als and 21 1 52 secondary PCI signal s. Addit ion al
optional jump ers control secondary bus arbitration.
Table 1-1 shows the connections required to allow observation of these signals at scope pod
connector pins.
Table 1-1. Jumper Connections
JumperDescription
J1This jumper monitors the foll owing signals:
J2, J8 through J12Logic analyzer pods can be plug ged into thes e jumpers for
W1, W4, J7These jumpers control secondary bus arbitration. Chapter 4, Secondary Bus
Introduction
p_clk (PCI clock)
s_clk_o<4:1> (four secondar y PCI clocks)
s_clk_o<0> (fed back to the s_clk input pin)
s_gnt_l<2> and s_gnt_l<3> .
monit oring 21152 secondary PCI sig nals.
Arbitration, provides information about configuring these jumpers.
1.5Secondary Slot Numbering and IDSEL Mapping
The PCI secondary bus opt ion card s lots are mapped to PCI device number s 4, 5, 6, and 7 as shown
in Figure 1-2. The secondary bus lines s_ad<20:23> are used as se co ndary IDSE L lines.
The EB152 suppor ts var ious PCI c onfi gurati ons with dif fe rent typ es of de vices. Figur e 1-3 through
Figure 1-6 show examples of PCI configurations.
The primary bus con nec tor attaches to a PCI slot on the mother board of the host system or to a
secondary PCI bus slot on another EB152. A 5-V or universal PCI option card, or another EB152,
can be plugged in to any one of the four secondary bus option card slot s.
Figure 1-3 shows the EB152 with one secondary bus option card.
Figure 1-3. EB152 with One Secondary Bus Option Card
Host System
Motherboard
EB152
Option Card
21152
Figure 1-4 shows the EB152 with two secondary bus option cards
Figure 1-4. EB152 with Two Secondary Bus Option Cards
This chapter provi des information about the EB152 speci f ications and the hardware and software
requirements for using the EB152. It also describes how to install the EB152.
2.1Specifications
The physical and power specifications for the EB152 are as follows:
Dimensions:
Height: 20.0 cm (7.90 in)
Width: 13.2 cm (5.20 in)
Power Requirements:
dc amps @ 5 V: 2.0 A (maximum)
2.2Hardware Requirements
The following equipment is required to use the EB152:
2
• A computer system equipped with a PCI motherboard
• A PCI expansion slot on the motherboard that is equipped for the 5 V or 3.3 V environment
2.3Software Requirements
To test the EB152 in x86 DOS or Windows systems, system BIOS must include autoconfiguration
code for PCI-to-PCI bridges. If the system BIOS does not include this functionality, contact your
BIOS vendor to obtain code with PCI-to-PCI bridge autoconfiguration support.
The EB152 kit provides a DOS utility that can be used to configure the PCI-to-PCI bridge. The
diskette included in the EB152 kit contains the DOS utility and a README.TXT file that explains
how to use it.
Figure 1-1 illustrates the EB152 and shows the location of components refe rred to in this section.
Install the EB152 as f o llows:
1. Power down the host system that will contain the EB152.
2. Place the motherboard with the associated support devices on a bench if mechanical
constrai nts do not allow testing of the EB152 and the expansion slots inside the syste m box.
3. Configure your system as follows:
a. Insert the card edge of the EB152 into a PCI slot.
b. Insert a 5-V or unive rsal option P CI card i nto any or each of t he four s econdary bus option
card slots. Section 1.4 shows examples of typical PCI configurations.
4. Power up the system.
5. Verify autoc onfiguration of the 21152 and of any devices that are plugged in as fol lows :
a. Verify that system BIOS or firmware detects and configures the PCI devices downstream
of the 21152. If system BIOS is not available, use the DOS utility provided with the
EB152 kit to configure the devices downstream of the 21152, and verify proper
configuration.
b. Install de vice drivers for any PCI devices that are downs tream the 21152, and veri fy
proper configuration of those devices.
6. If desired, moni tor bridge secondary PCI control signals by connecting a logic analyzer to
pods J2 and J8 through J12.
This chapter describes the way in which interrupts are routed. This information is provided as a
reference for designers .
Because a total of 16 interrupts are connected to the secondary bus PCI slots (INTA#, INTB#,
INTC#, and INTD# for each slot) and only four interrupts are driven to the card edge, the 16
incoming interrupts must be combined. This ORing of interrupts is perfo rmed in accordance with
the PCI-to-PCI Bridge Architecture Specification.
Table 3-1 shows the ORing of interrupts.
Table 3-1. Interrupt ORing
3
Device NumberInterrupt Pin
on Device
4 INTA#
INTB#
INTC#
INTD#
5INTA#
INTB#
INTC# I
INTD#
6INTA#
INTB#
INTC#
INTD#
7INTA#
INTB#
INTC#
INTD#
Interrupt Pin
on Board Connector
INTA#
INTB#
INTC#
INTD#
INTB#
INTC#
INTD#
INTA#
INTC#
INTD#
INTA#
INTB#
INTD#
INTA#
INTB#
INTC#
In accordance with the PCI-to-PCI Bridge Arch itecture Specification, Revision 1.0, interrupts of
the devices on the secondary slots are wire ORed and routed to PCI fingers of the EB152.
This chapter describes the use of jumpers to te st 21152 secondary bus arbitration, an optional
programmable feature. For more detailed information about the 21152 arbi ter, refer to the 21152
PCI-to-PCI Bridge Data Sheet.
The EB152 has two secondary bus arbiter systems:
• An internal arbiter implemented in the 21152 that supports four external masters in addition to
the 21152
• An optional external arbiter implemented in an AMD MACH210A programmable device
The default setting is internal arbitration. The internal 21152 arbiter implements a 2-level
programmable rotat ing mode algori thm. Second ary bus par king is don e at the las t master to use the
bus.
The internal arbiter can be disabled, and an external arbiter can be used instead for secondary bus
arbitration. The EB152 provides a socket for an optional PAL (labeled E3 in Figure 4-1) to control
secondary bus arbitration. If a different external arbiter is used where parking is done at one of the
PCI slots, a PCI devic e must be ins talle d in t hat slot. To change the def ault, configure the se condary
bus arbiter system using jumpers J7, W4, and W1.
Figure 4-1 shows t he l oca ti on o f t he a rbi tr at ion jum per s, an d Table 4-1 and Table 4-2 describe their
operation.
4
All jumper positions assume that the EB152 is positioned with the components fa cing forward and
the car d ed ge facing down.
Table 4-2 describes the operation of jumpers for external arbitration with PAL.
Table 4-2. External PAL Arbitrati on Jum per Positions
JumperPositionDesc ription
J7TopSelec ts the PAL as the source of secon dary grants.
W4RightSelects the board signal gt_out<4> (the external secondary grant to the
21152) to drive the 21152 s_req_l<0> input.
W1RightTies s_cfn_l high, which disables th e21152 internal arbiter and causes the
following reconfigurations:
Signal s_gnt_l<0> becomes the se condary bus req uest.
Signal s_req_l<0> becomes the secondary bus grant.
The PAL parks the secondary bus at the 21152.
— 21152 Evaluation System BIOS Letter
— 21152 PCI Evaluation Boar d S chematics
— 21152 Evaluation Board Vendor Parts List
— SPICE model kit containing a Level 28 21152 SPICE model and a pplication note
— Warranty Agr eement/Registration Card
If you need technical support, a Pr odu ct Cat alog , or hel p deci din g which d ocume ntati on bes t meets
your needs, visi t the Intel W orld Wide Web Internet site:
http://www. inte l.com
Copies of document s th at have an ordering number and are referenced in this document, or other
Intel literature may be obtained by calling 1-800-332-2717 or by visiting Intel’s website for
developers at:
http://developer.intel.com
You can al so con ta ct the In tel Ma ssa chus et ts Inf or matio n Li ne or the Int el Mass achus et ts Cu st omer
Technology Center. Please use the following information lines for support:
For documentation and general information:
Intel Massachusetts Information Line
United States:1–800–332–2717
Outside United States:1–303-675-2148
Electronic mail address:techdoc@intel.co m
For technical support:
Intel Massachusetts Customer Technology Center
Phone (U.S. and international):1–978–568–7474
Fax:1–978– 568–6698
Electronic mail address:techsup@intel.com
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