Intel 21143 User Manual
Intel® 21143 PCI/CardBus 10/
100Mb/s Ethernet LAN Controller
Design Guide
July 2002
Order Number: 278588-001
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Copyright © Intel Corporation, 2002
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2 Design Guide
Contents
Contents
1.0 Functional Overview........................................................................................................................5
1.1 21143 Overview....... ...... ....... ...... ....... ...................................... ....... ...... ....... ...... ....... ............5
1.2 Network Interface..................................................................................................................5
1.3 MII-Based PHY Block Diagram.............................................................................................6
1.4 SYM-Based PHY Block Diagram..........................................................................................6
2.0 21143 Ports .....................................................................................................................................7
3.0 Network Connection ........................................................................................................................9
3.1 10BASE-T Twisted-Pair Network Port..................................................................................9
3.2 100-Ready Designs ............................................................................................................12
3.2.1 Internal Optional Daughtercard..............................................................................13
3.2.2 Description of 100-Ready Daughtercard Block Diagram .......................................13
3.2.3 100-Ready External Module Design ......................................................................14
3.2.4 Description of 100-Ready External Module Block Diag ram...................................1 4
3.2.5 MII/SYM Pin Listing ...............................................................................................14
3.3 AUI Network Port................................................................................................................15
3.4 Media-Specific Components...............................................................................................18
4.0 21143 Requirements .....................................................................................................................19
4.1 Unused JTAG Port Requirements ......................................................................................19
4.2 Current Reference and Capacitor Input Requirements ......................................................19
4.3 Crystal and Crystal Oscillator Connections ........................................................................20
5.0 Signal Routing and Placement ......................................................................................................21
5.1 Ground and Power Planes..................................................................................................21
5.1.1 3.3 V Power Supply ...............................................................................................22
5.2 LED Status Signals.............................................................................................................22
6.0 Design Considerations ..................................................................................................................23
6.1 Designing the Ethernet Corner on Motherboards...............................................................23
6.2 Suggestions for FCC Compliance ......................................................................................23
6.2.1 Suggestions for Quiet Ground and Power Planes .................................................23
6.2.2 Suggestions for Routing ........................................................................................24
Figures
1 MII-Based PHY Design.................................................................................................................6
2 SYM-Based PHY Design..............................................................................................................7
3 10BASE-T Network Connection with Buffers..............................................................................10
4 10BASE-T Network Connection Without Buffers........................................................................11
5 Minimum Components Required for 10BASE-T........................................................................12
6 10BASE-T 100-Ready Daughtercard Block Diagram.................................................................13
7 10BASE-T 100-Ready External Module Block Diagram.............................................................14
8 AUI 10BASE5 Network and Pin Connections.............................................................................16
Design Guide 3
Contents
9 AUI 10BASE2 Network Connection............................................................................................17
10 21143 External Component Connections...................................................................................20
11 LED Time-Stretcher Circuit.........................................................................................................22
Tables
1 Signal gep<0>/aui_bnc Description..............................................................................................5
2 AUI Signals...................................................................................................................................7
3 Twisted-Pair Signals.....................................................................................................................7
4 MII Signals............. ...... ....................................... ....... ...... ...... ....... ...... ....... ...... ....... ..... .................8
5 SYM Signals.................................................................................................................................8
6 Internal vs. External Design Features .......................................................................................13
7 MII/SYM Pinout...........................................................................................................................14
8 10BASE-T Media-Specific Components.....................................................................................18
9 10BASE2 and 10BASE5 Media-Specific Components ..............................................................18
10 Pin Requirements When Not Using the JTAG Port ....................................................................19
11 Current Reference and Capacitor Inputs....................................................................................19
12 Crystal Specifications .................................................................................................................20
Revision History
Date Revision Description
July 2002 001 First release.
4 Design Guide
Intel® 21143 PCI/CardBus 10/100Mb/s Ethernet LAN Controller
This design guide prov ides a description of how to implement 100BASE-TX and 10BASE-T
network connections using the 21143 PCI/CardBus 10/100 Mb/s Ethernet LAN Controller
(referred to as the 21143).
While this document will not provide specific recommendations for physical layer devices, it will
provide design recommendations and layout recommendations.
This application note prov ides a description of how to implement 100BASE-TX and 10BASE-T
network connections using the 21143 PCI/CardBus 10/1 00 Mbs/s Ethernet LAN Controller
(referred to as the 21143).
1.0 Functional Overview
This section provides an overview of the 21143 and the implementation of 100 Mb/s and 10 Mb/s
network connections using MII-based or SYM-based PHY devices.
1.1 21143 Overview
The 21143 is a single-chip bus master Ethernet/Fast Ethernet device that supports direct memory
access (DMA) and has direct interfaces to both the CardB u s and the PCI local bus. The 21143
implements a direct interface to the CardBus or PCI bus through a single 50-pin connection, which
consists of the control and address/data signals.
The 21143 provides a complete implementation of the IEEE 802.3 Ethernet specification. This
includes the attachment unit interface (AUI), twisted-pair (10BASE-T) interface, MII SYM port
interface, and the interface through the media access control (MAC) layer that creates a direct
interface to the PCI bus.
The PCI interface utilizes only about 10% of the bus bandwidth during fully networked operation
for 100 Mb/s Fast Ethernet reception or transmission. This bus master design results in high
throughput between the system and the network.
1.2 Network Interface
The 21143 physical layer desi gn sup po rts AUI dro p cable Ethernet and 10BASE-T twisted-pair
(TP) Ethernet connections. The 21143 gep<0>/aui_bnc (pin 100), which is software controlled,
provides for a connection of either the AUI (10BASE5) or BNC (10BASE2) network connector.
Table 1 describes the function of this pin.
Table 1. Signal gep<0>/
Program State Function
0 AUI port enabled; BNC port disabled.
1 BNC transceiver (or DC-to-DC converter) enabled; AUI port disabled
AUI signals interface with the Manchester encoder/decoder portion of the 21143. The 21143
supports 10BASE5 thickwire and 10BASE2 ThinWire connections. The 10BASE2 connection
requires an external transceiver.
aui_bnc Description
Design Guide 5
Intel® 21143 PCI/CardBus 10/100Mb/s Ethernet LAN Controller
The 21143 implements the 100BASE-T MII layer and the 100/10 Mb/s Ethernet MAC layer. The
21143 provides a dual network interface for both a 100BASE-T and a 10 Mb/s Ethernet. At the
100BASE-T port, the 21143 supports the industry-standard MII for any 100BASE-T
implementation.
The 21143 is fully compl iant with the MII specifications (as defined in IEEE 802.3). The MII is a
nibblewide, general interface, that can be used with various physical interfaces, such as 100BASETX, 100BASE-T4, shielded twisted-pair (STP), and fiber. It also supports dual rates of speed
(10 Mb/s and 100 Mb/s).
The 21143 includes special support for 100BASE-TX networks by including the PCS section
(scrambler and 5B/4B coding/decoding). Integrati ng the 10BASE-T ENDEC with the 100 Mb/sonly SYM-based PHYs enables full support for a 10/100-implementation.
1.3 MII-Based PHY Block Diagram
Figure 1 is a block diagram of a 10BASE-T and 100BA SE-T singl e-connecto r network connectio n
using a MII-based PHY device with the 21143.
MII-based PHY devices are provided by Intel, Integrated Circuit Systems*, National
Semiconductor*, Seeq*, and TDK*.
Figure 1. MII-Based PHY Design
MII Port
of
21143
The MII-based PHY design includes the following components:
MII-Based
PHY
Devices
Magnetics
• The MII-based PHY devices, which have a direct interface to the MII port of the 21143 with
dual-rate option (as specified in the MII specification) and a full interface to the 10/100 Mb/s
magnetics module.
• The magnetics module, which is based on transfo rmers and serial cho kes enabling the networ k
connection to the 100 Mb/s network (100BASE-TX or 100BASE-T4) and to the 10 Mb/s
network (10BASE-T).
1.4 SYM-Based PHY Block Diagram
Figure 2 is a block diagram of a 100BA SE-TX sing l e-con nect or net work connection using a SYM-
based PHY device with the 21143. For a 10 Mb/s network connection, the network can be
connected directly to the 21143 through filters and chokes.
10/100 Mb/s
Network
Module
6 Design Guide
Intel® 21143 PCI/CardBus 10/100Mb/s Ethernet LAN Controller
SYM-based PHY devices are provided by GEC Plessey*, Quality Semiconductor*, and Micro
Linear*.
Figure 2. SYM-Based PHY Design
SYM Port
of
21143
The SYM-based PHY design includes the following component s :
• The SYM-based PHY devices, which have a direct interface to the SYM port of the 2114 3
with an interface to the 100 Mb/s magnetics module.
• The magnetics module, which is based on transformers and serial chokes enabling the network
connection to the 100 Mb/s-only network (100BASE-TX or 100BASE-T4).
2.0 21143 Ports
Table 2 lists the active AUI signals when the 21143 AUI port is selected.
Table 2. AUI Signals
Signal Pin Number
aui_cd– 138
aui_cd+ 137
aui_rd– 140
aui_rd+ 139
aui_td– 143
aui_td+ 142
SYM-Based
PHY
Devices
Magnetics
Module
100 Mb/s
Network
Table 3 lists the active twisted-pair signals when the 21143 10BASE-T port is selected.
Table 3. Twisted-Pair Signals
Signal Pin Number
tp_rd– 10
tp_rd+ 9
tp_td– 5
tp_td– – 4
tp_td+ 6
tp_td+ + 7
Table 4 lists the active MII signals when the 21143 MII port is selected.
Design Guide 7
Intel® 21143 PCI/CardBus 10/100Mb/s Ethernet LAN Controller
Table 4. MII Signals
Signal Pin Number
mii_clsn 118
mii_crs 117
mii_dv 129
mii_mdc 134
mii_mdio 135
mii_rclk 128
mii_rx_err 127
mii_rxd <3:0> 133:130
mii_tclk 124
mii_txd<3:0> 119:122
mii_txen 123
Table 5 lists the active SYM signals when the 21143 SYM port is selected.
Table 5. SYM Signals
Signal Pin Number
sd 117
sel10_100 127
sym_rclk 128
sym_rxd<0> 130
sym_rxd<1> 131
sym_rxd<2> 132
sym_rxd<3> 133
sym_rxd<4> 118
sym_tclk 124
sym_txd<0> 122
sym_txd<1> 121
sym_txd<2> 120
sym_txd<3> 119
sym_txd<4> 123
8 Design Guide
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