Intel 10 DX FPGA User Manual

Intel® Stratix® 10 DX FPGA

Development Kit User Guide

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	Contents
Contents
1. Getting Started...............................................................................................................	4
1.1. About this Document..............................................................................................	4
1.2. Installing the Intel Quartus® Prime Pro Edition Software.............................................	4
1.2.1. Activating Your License...............................................................................	4
1.3. Downloading the Board Package..............................................................................	4
1.4. Installing the Driver for Intel FPGA Download Cable II................................................	5
2. Development Kit Overview..............................................................................................	6
2.1. Supported Features...............................................................................................	7
2.2. Recommended Operating Conditions........................................................................	7
2.3. Handling the Board................................................................................................	8
3. Power Up the Development Kit.......................................................................................	9
3.1. Default Switch Settings..........................................................................................	9
3.2. Connectors and LEDs............................................................................................	12
3.3. Performing Board Restore through Board Test System (BTS) .....................................	13
3.4. Controlling On-board Clock....................................................................................	14
4. Board Test System (BTS)..............................................................................................	15
4.1. Preparing the Development Kit..............................................................................	16
4.2. Running the Board Test System.............................................................................	16
4.3. Using the Board Test System.................................................................................	17
4.3.1. Configure Menu.......................................................................................	17
4.3.2. Sys Info Tab............................................................................................	18
4.3.3. GPIO Tab................................................................................................	19
4.3.4. QSFP Tab................................................................................................	20
4.3.5. Component DDR4 CH0 Tab........................................................................	23
4.3.6. Component DDR4 CH1 Tab........................................................................	24
4.3.7. DDR4 DIMM CH0 Tab................................................................................	26
4.3.8. DDR4 DIMM CH1 Tab................................................................................	27
4.3.9. Power Monitor.........................................................................................	29
4.3.10. Clock Controller.....................................................................................	30
4.4. Smart VID Setting...............................................................................................	32
5. Development Kit Hardware and Configuration..............................................................	34
5.1. FPGA Configuration..............................................................................................	34
5.2. Programming the FPGA Over Intel FPGA Download Cable..........................................	34
5.3. Configuration Modes.............................................................................................	35
5.3.1. Avalon Streaming Interface x8 Mode..........................................................	35
5.3.2. JTAG Mode..............................................................................................	40

6. Document Revision History for Intel Stratix 10 DX FPGA Development Kit User Guide..42

A. Development Kit Components.......................................................................................	43
A.1. Components Overview..........................................................................................	44
A.2. Power, Thermal, and Mechanical Considerations.......................................................	47
A.2.1. Power Guidelines.....................................................................................	47
A.2.2. Thermal Requirements.............................................................................	53
A.2.3. Mechanical Requirements..........................................................................	54

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Contents
A.3. Clock Circuits......................................................................................................	56
A.4. Memory Interface................................................................................................	58
A.5. PCIe Interface.....................................................................................................	59
A.6. UPI Interface......................................................................................................	59
A.7. Transceiver Signals: PCIe and UPI Interface............................................................	60
A.8. SlimSAS Connector..............................................................................................	63
A.9. QSFP Network Interface........................................................................................	64
A.9.1. Dual Port Controller .................................................................................	65
A.10. I2C Interface.....................................................................................................	66
A.11. QSPI Flash Memory............................................................................................	67
A.11.1. Configuration QSPI Flash Memory.............................................................	67
A.11.2. NIOS QSPI Flash Memory........................................................................	67
B. Safety and Regulatory Information...............................................................................	69
B.1. Safety Warnings..................................................................................................	69
B.2. Safety Cautions...................................................................................................	71
C. Compliance and Conformity Information......................................................................	73

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1. Getting Started

1.1. About this Document

This document provides comprehensive guidelines for designing with Intel® Stratix® 10 DX FPGA Development Kit. It covers information about the software installation, board components, and configuration.

Table 1.		Ordering Information
		Product	Ordering Code	Device Part Number
	Intel Stratix 10 DX FPGA Development Kit		DK-DEV-1SDX-P-A	1SD280PT2F55E1VG
	(Production version)

1.2. Installing the Intel Quartus® Prime Pro Edition Software

The Intel Quartus® Prime Pro Edition software includes everything you need to design for Intel Stratix 10 FPGA from design entry and synthesis to optimization, verification, and simulation. For more information about downloading the Intel Quartus Prime Pro Edition software, refer to the Download Center for Intel FPGAs.

1.2.1. Activating Your License

Before using the Intel Quartus Prime Pro Edition software, you must activate your license. If you already have a licensed version installed, you can use that license file with this development kit. Otherwise, follow these steps:

1.Log into your My Intel account.

2.Click on the Intel FPGA Self Service Licensing Center.

3.Locate the serial number printed on the side of the development kit box below the bottom bar code. The number consists of alphanumeric characters and does not contain hyphens.

4.On the Intel FPGA Self Service Licensing Center page, click the Find it with your License Activation Code link.

5.In the Find/Activate Products dialog box, enter your development kit serial number and click Search.

1.3.Downloading the Board Package

Download the appropriate board package for your Intel Stratix 10 DX FPGA Development Kit from the Intel FPGA Development Kits webpage. Unzip the package.

	Intel Corporation. All rights reserved. Agilex, Altera, Arria, Cyclone, Enpirion, Intel, the Intel logo, MAX, Nios,
	Quartus and Stratix words and logos are trademarks of Intel Corporation or its subsidiaries in the U.S. and/or	ISO
	other countries. Intel warrants performance of its FPGA and semiconductor products to current specifications in
		9001:2015
	accordance with Intel's standard warranty, but reserves the right to make changes to any products and services
		Registered
	at any time without notice. Intel assumes no responsibility or liability arising out of the application or use of any
	information, product, or service described herein except as expressly agreed to in writing by Intel. Intel
	customers are advised to obtain the latest version of device specifications before relying on any published
	information and before placing orders for products or services.
	*Other names and brands may be claimed as the property of others.

1. Getting Started

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Figure 1.		Directory Structure
				<package rootdir>
					board_design_files
					demos
					documents
					examples
					factory_recovery
Table 2.		Directory Description
		Directory			Content Description
	board_design_files		Contains schematic, layout, assembly, and bill of material board design files. Use
			these files as a starting point for a new prototype board design.
	demos		Contains demonstration applications when available.
	documents		Contains documentation.
	examples		Contains sample design files for this development kit.
	factory_recovery		Contains the original data programmed onto the board before shipment. Use this
			data to restore the board to its original factory settings.

1.4. Installing the Driver for Intel FPGA Download Cable II

The development board includes integrated Intel FPGA Download Cable circuits for FPGA programming. However, for the host computer and board to communicate, you must install the Intel FPGA Download Cable II driver on the host computer.

Installation instructions for the Intel FPGA Download Cable II driver for your operating system are available on the Cable and Adapter Drivers Information webpage.

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2. Development Kit Overview

The Intel Stratix 10 DX FPGA Development Kit allows you to evaluate the performance, features, and operation of the Intel Stratix 10 DX device in the F2912 BGA package. It features P-tile transceivers with PCIe Gen4 x16 and Intel Ultra Path Interconnect (UPI) interfaces and E-tile transceivers with 25Gx4 or 56Gx2 quad small form-factor pluggable (QSFP) interfaces. It also supports 4xDDR4 x72 channels with two channels supporting the Intel Optane® DC Persistent memory module.

The UPI functionality is enabled by a combination of the appropriate P-Tile settings and UPI protocol IP core. The FPGA interface to Intel Optane DC Persistent memory module requires an Intel memory controller IP core. Both IP cores are available in Intel Quartus Prime Pro Edition software (additional licensing and enablement may apply).

Figure 2. Intel Stratix 10 DX FPGA Development Kit Block Diagram

SlimSAS x2

SlimSAS x2

UPI/PCle EP/RP

UPI/PCle EP/RP

x4

UPI_1

UPI_1

UPI_2

UPI_2

QSFP-2

TX

RX

TX

RX

25G x4 or 56G x2

x4

QSFP-1

x20

x20

x20

x20

25G x4 or 56G x2

TX

RX

TX

RX

DDR4_CH0

P-Tile

P-Tile

E-Tile

DDR4

9A

11B

11C

3I

512Mx16 X5

3D

3J

X72

QSPI

DIMM_CH0

X72

3C

3K

QSPI x4

2Gb Flash

DDR4/DDR-T

3B

3L

AVST x8

USB

USB

PHY

3A

JTAG

Intel

Intel Stratix 10 DX

3H

JTAG

JTAG HDR

Config

MAX 10

AVSTx8

FPGA Development Kit

I2C

SDM

2I

System

I2C

GPIO

Control

2J

Pwr Seq CTRL

Current

Current Sense

Sense

Inputs

2F

2N

NIOS

Temp

Temp Diodes

DIMM_CH1

Sense

X72

2C

2M

DDR4_CH1

FLASH

DDR4/DDR-T

DDR4

Clock

All Clocks

2B

2L

X72

P-Tile

P-Tile

512Mx16 X5

2A

2K

10A

10B

Voltage

All

RX

TX

RX

TX

Regulators &

x16

x20

Voltage Sense

Voltages

x16

x20

Discharge CKT

Inputs

PCIe Gen4 X16 Edge Conn

UPI_0

UPI_0

+12V

RX

TX

Aux_2

PWR in

+12V from PCle

12V

UPI/PCIe EP/RP

CTRL

Gold Finger

SlimSAS x2

	Intel Corporation. All rights reserved. Agilex, Altera, Arria, Cyclone, Enpirion, Intel, the Intel logo, MAX, Nios,
	Quartus and Stratix words and logos are trademarks of Intel Corporation or its subsidiaries in the U.S. and/or	ISO
	other countries. Intel warrants performance of its FPGA and semiconductor products to current specifications in
		9001:2015
	accordance with Intel's standard warranty, but reserves the right to make changes to any products and services
		Registered
	at any time without notice. Intel assumes no responsibility or liability arising out of the application or use of any
	information, product, or service described herein except as expressly agreed to in writing by Intel. Intel
	customers are advised to obtain the latest version of device specifications before relying on any published
	information and before placing orders for products or services.
	*Other names and brands may be claimed as the property of others.

2. Development Kit Overview

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2.1. Supported Features

Table 3.		Supported Features
		Category		Features
			• 0.85-0.89V/VID-adjustable VCC core, 2912 pin BGA package
	Intel Stratix 10 DX FPGA		•	P-Tile transceivers supporting PCIe Gen4 or UPI
			• E-Tile transceivers supporting 28Gbps NRZ and 56Gbps PAM4
			•	Partial reconfiguration support
			•	CVP configuration support
	FPGA configuration		•	2Gb QSPI Flash
			• Storage for one configuration image in flash
			• JTAG header for device programming
			• Built-in Intel FPGA Download Cable for device programming
			• 312.53125 Mhz and 156.25 MHz Differential LVDS for QSFP
			• 100 Mhz Differential LVDS for PCIe
	Programmable clock sources		•	133 Mhz Differential LVDS for Memory
			• 125 Mhz Configuration clock
			• 100 Mhz Differential LVDS for IO banks
			• PCIe x16 interface supporting Gen4 End-Point mode connected to a x16 PCIe edge
				connector (gold edge fingers)
	Transceiver interfaces		•	2x standard QSFP56 optical module interfaces connected to the E-tile transceivers
			• 3x UPI or PCIe interface supporting UPI x20 at 11.2Gbps or PCIe x16 at 16Gbps via
				SlimSAS connectors (cables shipped separately)
			• Two on-board independent single rank DDR4 x72 (ECC) channels operating at 1200 MHz
	Memory interfaces			(DDR4-2400)
			• Two DIMM sockets supporting DDR4 DIMM or Intel’s Optane DC Persistent memory
				module
			• 2xQSFP28 optical interface port
	Communication ports		•	JTAG header
			• USB (Micro USB) on-board Intel FPGA Download Cable II
			•	System I2C header
			• System Reset Push button
			• CPU Reset Push button
	Buttons, Switches, and LEDs		• PCIe Reset Push button
			• Four dedicated User LEDs
			• Link LED of each QSFP28 port to indicate the link and data transceiver
			• Two dedicated configuration status LEDs
	Heatsink and Fan		• Air-cooled heatsink assembly
			• Red Over-Temperature Warning LED Indicator
			• PCIe input power including required 2x4 AUX power connector
	Power		• Blue Power-On LED
			• On/Off Slide Power Switch for benchtop operation
			• On board power and temperature measurement circuitry
			• PCIe standard height form factor
	Mechanical		•	4.376” x 10.0” board size
			• 2 Slots height with heatsink

2.2. Recommended Operating Conditions

Follow these operating range or limit for different physical parameters:

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•Ambient operating temperature range: 0°C to 35°C

•Maximum ICC load current: 192 A

•Maximum ICC load transient percentage: 30%

•FPGA maximum power supported by the supplied heatsink/fan: 192 W

2.3.Handling the Board

When handling the board, it is important to observe static discharge precautions.

Caution: Without proper anti-static handling, the board can be damaged. Therefore, use antistatic handling precautions when touching the board.

Important: This development kit should not be operated in a vibrating environment.

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3. Power Up the Development Kit

The Intel Stratix 10 DX FPGA development kit is designed to operate in two modes:

•As a PCIe* add-in card

•Bench-top mode

When operating the card as a PCIe system, insert the card into an available PCIe slot and connect a 2x4 pin PCIe power cable from the system to power connectors at J42 of the board.

Note: When operating as a PCIe add-in card, the board does not power on unless power is supplied to J42.

In Bench-top mode, you must supply the board with 240 W of power supply connected to the power connector J42.

This development kit ships with its switches preconfigured to support the design examples in the kit. If you suspect that your board may not be correctly configured with the default settings, refer to the Default Switch and Jumper Settings section of this chapter.

Follow these instructions:

1.Connect the supplied power supply to an outlet and the DC Power Jack (J42) on the FPGA board.

Note: Use only the supplied power supply. Power regulation circuits on the board can be damaged by power supplies with greater voltage.

2.Set the power switch (SW31) to the ON position.

When the board powers up, the blue LED illuminates and the board is ready for use. The Orange LED (D56) should also illuminate indicating that all the power rails on the board are good. If the POWER GOOD LED (D56) is not illuminated, it indicates that the power supply is malfunctioned and the board will not power up.

Note: The standby powers are always present as soon as the AUX power is applied to J42. Use power switch SW31 to start the board.

3.1. Default Switch Settings

This development kit ships with its switches preconfigured to support the design examples in the kit. If you suspect that your board may not be correctly configured with the default settings, refer to the following table to return to its factory settings before proceeding.

	Intel Corporation. All rights reserved. Agilex, Altera, Arria, Cyclone, Enpirion, Intel, the Intel logo, MAX, Nios,
	Quartus and Stratix words and logos are trademarks of Intel Corporation or its subsidiaries in the U.S. and/or	ISO
	other countries. Intel warrants performance of its FPGA and semiconductor products to current specifications in
		9001:2015
	accordance with Intel's standard warranty, but reserves the right to make changes to any products and services
		Registered
	at any time without notice. Intel assumes no responsibility or liability arising out of the application or use of any
	information, product, or service described herein except as expressly agreed to in writing by Intel. Intel
	customers are advised to obtain the latest version of device specifications before relying on any published
	information and before placing orders for products or services.
	*Other names and brands may be claimed as the property of others.

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Table 4.

Default Switch Settings

Switch

Default Position

Description

Configuration mode setting bits:

Mode

MSEL0

MSEL1

MSEL2

QSPI_AVST

_SEL

SW1[1:4]

ON/OFF/OFF/X

JTAG

OFF (Open)

OFF (Open)

OFF (Open)

X

Avalon-ST

ON (Close)

OFF (Open)

OFF (Open)

X

JTAG, MAX10, UPI controls:

SW33

ON (Close)

OFF (Open)

1 - JTAG Debug

JTAG Header (J2)

Normal JTAG (Default)

dedicated for Max10

SW33[1:4]

OFF/X/ON/ON

2 - JTAG SOURCE

Not used

Not used

3 - UPI Mode

2 Sockets

4 Sockets

4 – M10 JTAG EN

M10 JTAG Enabled

M10 JTAG Disabled

PCIe PRSNT X1/x4/x8/x16 settings:

PCIe PRSNT X1

PCIe PRSNT X4

PCIe PRSNT X8

PCIe PRSNT

SW2[1:4]

ON/ON/ON/ON

X16

ON (Close)

ON (Close)

ON (Close)

ON (Close)

PCIe Edge connector PERSTn selection:

SW28

ON (Close)

•

ON: Endpoint (Default)

•

OFF: Root Port

Intel Stratix 10 DX PERSTn selection:

SW27

ON (Close)

•

ON: Endpoint (Default)

•

OFF: Root Port

UPI0 PERSTn selection - UPI0 connector side:

SW16

ON (Close)

•

ON: PERSTn from PCIe Edge connector to FPGA

• OFF: PERSTn from FPFA to CPU (Default)

UPI0 PERSTn selection - FPGA side:

SW24

ON (Close)

•

ON: PERSTn from FPGA to CPU (Default)

• OFF: PERSTn from PCIe Edge connector to FPGA

UPI1 PERSTn selection - UPI1 connector side:

SW17

ON (Close)

•

ON: PERSTn from PCIe Edge connector to FPGA

• OFF: PERSTn from FPFA to CPU (Default)

UPI1 PERSTn selection - FPGA side:

SW25

ON (Close)

•

ON: PERSTn from FPGA to CPU (Default)

• OFF: PERSTn from PCIe Edge connector to FPGA

UPI2 PERSTn selection - UPI2 connector side:

SW18

ON (Close)

•

ON: PERSTn from PCIe Edge connector to FPGA

• OFF: PERSTn from FPFA to CPU (Default)

SW26

ON (Close)

UPI2 PERSTn selection - FPGA side:

continued...

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	Switch	Default Position	Description
			• ON: PERSTn from FPGA to CPU (Default)
			• OFF: PERSTn from PCIe Edge connector to FPGA
			PCIe REFCLK source selection:
	SW14	ON (Close)	• ON: 100MHz REFCLK internal generated
			• OFF: 100MHz REFCLK from PCIe Edge Connector (Default)
			Power switch:
			• ON: Turn on power (set to this position for use in PCIe slot)
	SW31	ON (Close) or OFF (Open)	• OFF: Turn off power
			This switch must be ON when the card is plugged into a PCIe slot
			Note: (with 2x4 Aux power connected) or on the bench with external
			ATX power supply.

Figure 3.

Location of Switches and Push Buttons

SW25

SW24

SW26

S1

S2

SW20

SW18

SW20

SW27

SW16

SW19

SW1

S4

SW17

SW14

SW33

SW2

S3

SW28

Table 5.

Push Buttons

Push Buttons

Descriptions

S1

PCIe Reset

Push to reset PCIe bus

S2

MAX10 Reset

Push to reset Max10

S3

CPU Reset

Push to reset FPGA

S4

USER Push Button

Push button for user assigned function

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3.2. Connectors and LEDs

Figure 4.

Location of Connectors and LEDs

J2

D57

D56

J17

J73

J42

J38

J18

J40

J39

J15

J41

CN1

J55

J65

SW31

D9 D10 D14

D15 D18 D20 D22 D21 D13 D40

J9

J74

J24

Table 6.

Connectors

Connector

Description

J2

External JTAG connector

For use with Intel FPGA Download Cable

J42

AUX Power connector

For external 12V AUX power supply or power adapter

J97

I2C/PMBus connector

For accessing the core power controller

J17

I2C connector

To access I2C bus

J15

QSFP 1 connector

For using the QSFP interface

J18

QSFP 2 connector

CN1

USB connector

For programming FPGA using on-board Intel FPGA

Download Cable

J73

DIMM 0 connector

For DDR4/DDR-T memory channel 0

J74

DIMM 1 connector

For DDR4/DDR-T memory channel 1

J9

PCIe x16 Gold Finger

For using the PCIe interface

J38

UPI 1 Transmit

For UPI Link 1 connection from FPGA to CPU

J40

UPI 1 Receive

For UPI Link 1 connection from CPU to FPGA

J39

UPI 2 Transmit

For UPI Link 2 connection from FPGA to CPU

J41

UPI 2 Receive

For UPI Link 2 connection from CPU to FPGA

J55

UPI 0 Transmit

For UPI Link 0 connection from FPGA to CPU

J65

UPI 0 Receive

For UPI Link 0 connection from CPU to FPGA

J24

Fan connector

For connecting to the heatsink cooling fan

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Table 7.		LEDs
			LEDs		Description
				Green LED:
	D18		QSFP 1 Link LED for 25G	•	ON: link
				•	Blinks: Activities
				Yellow LED:
	D20		QSFP 1 Link LED for 10G	•	ON: link
				•	Blinks: Activities
				Green LED:
	D22		QSFP 2 Link LED for 25G	•	ON: link
				•	Blinks: Activities
				Yellow LED:
	D21		QSFP 2 Link LED for 10G	•	ON: link
				•	Blinks: Activities
	D9		USER LED 0	Green LED for USER LED 0
	D10		USER LED 1	Green LED for USER LED 1
	D14		USER LED 2	Green LED for USER LED 2
	D15		USER LED 3	Green LED for USER LED 3
				Yellow LED:
	D56		POWER GOOD LED	•	ON: All power is good
				•	OFF: Power failure
				Green LED:
	D57		CONFIG DONE LED	•	ON: FPGA configuration successful
				• OFF: FPGA configuration failed
				Green LED:
	D13		MAX10 CONFIG DONE LED	•	ON: MAX10 configuration successful
				• OFF: MAX10 configuration failed
				Red LED:
	D40		Over Temp LED	•	ON:
				•	OFF:
				Blue LED:
	D53		POWER LED	•	ON: Devkit power is on
				• OFF: Devkit power is off

3.3. Performing Board Restore through Board Test System (BTS)

The development kit ships with FPGA design examples stored in the QSPI flash device and pre-programmed Intel MAX® 10 system. If you want to restore the board QSPI flash with the default factory image, follow these steps:

1.Connect USB cable between CN1 USB connector and your computer.

2.Open Intel Quartus Prime Pro Edition Programmer.

3.Detect JTAG chain and attach factory default image on system Intel MAX 10 device.

4.Select programming options and click Program button.

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3.4. Controlling On-board Clock

The clock controller application can change the on-board Si53XX programmable oscillators to any customized frequency between 0.2 MHz and 800 MHz.

The clock control application (ClockControl.exe) runs as a stand-alone application and resides in the location <package dir>\examples\board_test_system.

The clock control application communicates with the system Intel MAX 10 device through either USB port CN1 or 10pin JTAG header J2. The system Intel MAX 10 device controls these programmable clock parts through a two-wire serial bus.

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4. Board Test System (BTS)

The Intel Stratix 10 DX FPGA Development Kit includes an application called Board Test System (BTS) to test the functionality of this board. The BTS provides an easy-to- use Graphical User Interface (GUI) to alter functional settings and observe results. You can use the BTS to test board components, modify functional parameters, observe performance, and measure power usage.

The BTS communicates over the JTAG bus to a test design running in the Intel Stratix 10 DX FPGA device. You can use the BTS to reconfigure the FPGA with test designs specific to the functionality that you are testing.

The BTS is also useful as a reference for designing systems.

Figure 5. BTS GUI Home

	Intel Corporation. All rights reserved. Agilex, Altera, Arria, Cyclone, Enpirion, Intel, the Intel logo, MAX, Nios,
	Quartus and Stratix words and logos are trademarks of Intel Corporation or its subsidiaries in the U.S. and/or	ISO
	other countries. Intel warrants performance of its FPGA and semiconductor products to current specifications in
		9001:2015
	accordance with Intel's standard warranty, but reserves the right to make changes to any products and services
		Registered
	at any time without notice. Intel assumes no responsibility or liability arising out of the application or use of any
	information, product, or service described herein except as expressly agreed to in writing by Intel. Intel
	customers are advised to obtain the latest version of device specifications before relying on any published
	information and before placing orders for products or services.
	*Other names and brands may be claimed as the property of others.

4. Board Test System (BTS)

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Figure 6. About BTS

4.1. Preparing the Development Kit

Several designs are provided to test the major board features. Each design provides data for one or more tabs in the application. The Configure Menu identifies the appropriate design to download to the FPGA for each tab.

After successful FPGA configuration, an appropriate tab appears that allows you to exercise the related board features. Highlights appear in the board picture around the corresponding components.

The BTS communicates over the JTAG bus to a test design running in the FPGA. The BTS and Power Monitor share the JTAG bus with other applications like the Nios® II debugger and the Signal Tap II Embedded Logic Analyzer. Because the BTS is designed based on the Intel Quartus Prime software, be sure to close other applications before you use the BTS.

The BTS relies on the Intel Quartus Prime software's specific library. Before running the BTS, open the Intel Quartus Prime software to automatically set the environment variable $QUARTUS_ROOTDIR. The BTS uses this environment variable to locate the Intel Quartus Prime library. The version of Intel Quartus Prime software set in the QUARTUS_ROOTDIR environment variable should be newer than version 14.1. For example, the Development Kit Installer version 15.1 requires that the Intel Quartus Prime software 14.1 or later version is installed.

Additionaly, to ensure that the FPGA is configured successfully, you should install the latest Intel Quartus Prime software that can support the silicon on the development kit. For this board, Intel recommends installing the Intel Quartus Prime version 19.3

b222.

Refer to the README.txt file under \examples\board_test_system directory.

4.2. Running the Board Test System

With the power to the board turned off, follow these steps:

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1.Connect the USB cable to your PC and the board.

2.Check whether the board switches and jumpers are set according to your preferences.

3.Turn on the power to the board.

To ensure operating stability, keep the USB cable connected and the board powered on when running the demonstration application. The BTS cannot run correctly unless the USB cable is attached and the board is powered on.

To run the BTS, navigate to the <package dir>\examples\board_test_system directory and run the BoardTestSystem.exe application. A GUI appears, displaying the application tab corresponding to the design running in the FPGA. If the design loaded in the FPGA is not supported by the BTS GUI, you will receive a message prompting you to configure your board with a valid BTS design. Refer to the Configure Menu on page 17 for configuring your board.

If some design is running in the FPGA, the BTS GUI loads the design file (.sof) in the image folder to check the current running design in the FPGA. Therefore, the design running in the FPGA must be the same as the design file in the image folder.

4.3. Using the Board Test System

This section describes each tab in the BTS.

4.3.1. Configure Menu

Use the Configure menu to select the design you want to use. Each design example tests different board features. Select a design from this menu and the corresponding tabs become active for testing.

Figure 7. Configure Menu

To configure the FPGA with a test system design, perform the following steps:

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1.On the Configure menu, click the configure command that corresponds to the functionality you want to test.

2.In the dialog box that appears, click Configure to download the corresponding design to the FPGA.

When configuration finishes, close the Intel Quartus Prime software GUI if it's already open. The design begins running in the FPGA. The corresponding GUI application tabs that interface with the design are now enabled.

Note: If you use the Intel Quartus Prime Programmer for configuration rather than the BTS GUI, you may need to restart the GUI.

4.3.2. Sys Info Tab

	The Sys Info tab shows the board's current configuration. The tab displays the
	contents of the Intel MAX 10 registers, the JTAG chain, the Ethernet port numbers,
	and other details stored on the board.
Figure 8.	Sys Info Tab

The following sections describe the controls of the Sys Info tab.

Board Information

Displays static information about your board:

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•Board Name: Indicates the official name of the board given by the BTS.

•Board P/N: Indicates the part number of the board.

•Serial Number: Indicates the serial number of the board.

•Board Revision: Indicates the revision of the board.

•MAX Version: Indicates the version of Intel MAX 10 code currently running on the board.

JTAG Chain

Shows devices which are currently in the JTAG chain.

4.3.3. GPIO Tab

The GPIO tab allows you to interact with all the genral purpose user I/O components on your board. You can turn LEDs on or off.

Figure 9. GPIO Tab

The following sections describe the controls on the GPIO tab:

User LEDs

Displays the current state of user LEDs. Toggle the LED buttons to turn the board LEDs on and off.

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Qsys Memory Map

Shows the memory map of the GPIO or FLASH Platform Designer system on your board.

4.3.4. QSFP Tab

This tab allows you to perform loopback tests on the QSFP ports.

Figure 10. QSFP Tab

The following sections describe the controls on the QSFP tab:

Status

Displays the following status information during a loopback test:

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•PLL Lock: Shows the PLL locked or unlocked state.

•Pattern sync: Shows the pattern synced or not synced state. The pattern is considered synced when the start of the data sequence is detected.

•Details: Shows the PLL lock and pattern sync status:

Figure 11. PLL and Pattern Status

Port

Allows you to specify which interface to test. The following port tests are available:

•QSFP x8

PMA Setting

Allows you to make changes to the PMA parameters that affect the active transceiver interface. The following settings are available for analysis:

•Serial Loopback: Routes signals between the transmitter and the receiver.

•VOD: Specifies the voltage output differential of the transmitter buffer.

•Pre-emphasis tap:

—Pre-tap 1: Specifies the amount of pre-emphasis on the first pre-tap of the transmitter buffer.

—Pre-tap 2: Specifies the amount of pre-emphasis on the second pre-tap of the transmitter buffer.

—Pre-tap 3: Specifies the amount of pre-emphasis on the third pre-tap of the transmitter buffer.

—Post-tap 1: Specifies the amount of pre-emphasis on the post-tap of the transmitter buffer.

•Equalizer: Specifies the RX tuning mode for receiver equalizer.

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Figure 12. PMA Setting

Data Type

Specifies the type of data contained in the transactions. The following data types are available for analysis:

•PRBS 7: Selects pseudo-random 7-bit sequences.

•PRBS 15: Selects pseudo-random 15-bit sequences.

•PRBS 23: Selects pseudo-random 23-bit sequences.

•PRBS 31: Selects pseudo-random 31-bit sequences.

•HF: Selects highest frequency divide-by-2 data pattern 10101010.

•LF: Selects lowest frequency divide-by-33 data pattern.

Error Control

Displays data errors detected during analysis and allows you to insert errors:

•Detected errors: Displays the number of data errors detected in the hardware.

•Inserted errors: Displays the number of errors inserted into the transmit data stream.

•Insert: Inserts a one-word error into the transmit data stream each time you click the button. Insert is only enabled during transaction performance analysis.

•Clear: Resets the detected errors and inserted errors counters to zero.

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