Integrated Silicon Solution IS62C1024AL, IS65C1024AL User Manual
IS62C1024AL
®
IS65C1024AL
128K x 8 LOW POWER CMOS
STATIC RAM
FEATURES
• High-speed access time: 35, 45 ns
• Low active power: 100 mW (typical)
• Low standby power: 20 µW (typical) CMOS
standby
• Output Enable (OE) and two Chip Enable
(CE1 and CE2) inputs for ease in applications
• Fully static operation: no clock or refresh
required
• TTL compatible inputs and outputs
• Single 5V (±10%) power supply
• Commercial, Industrial, and Automotive temperature ranges available
• Standard Pin Configuration:
—
32-pin SOP/ 32-pin TSOP (Type 1)
• Lead free available
ISSI
OCTOBER 2005
DESCRIPTION
The ISSI IS62C1024AL/IS65C1024AL is a low power, 131,072-
word by 8-bit CMOS static RAM. It is fabricated using highperformance CMO S technology. This highly reliable process coupled with innovative circuit design techniques,
yields higher performance and low power consumption
devices.
When CE1 is HIGH or CE2 is LOW (deselected), the device
assumes a standby mode at which the power dissipation
can be reduced by using CMOS input levels.
Easy memory expansion is provided by using two Chip
Enable inputs, CE1 and CE2. The active LOW Write Enable
(WE) controls both writing and reading of the memory.
FUNCTIONAL BLOCK DIAGRAM
A0-A16
V
DD
GND
I/O0-I/O7
CE1
CE2
OE
WE
Copyright © 2005 Integrated Silicon Solution, Inc. All rights reserved. ISSI reserves the right to make changes to this specification and its products at any time without notice. ISSI assumes no liability
arising out of the application or use of any information, products or services described herein. Customers are advised to obtain the latest version of this device specification before relying on any
published information and before placing orders for products.
Integrated Silicon Solution, Inc. — www.issi.com —
Rev. E
10/05/05
DECODER
I/O
DATA
CIRCUIT
CONTROL
CIRCUIT
1-800-379-4774
128K x 8
MEMORY ARRAY
COLUMN I/O
1
IS62C1024AL
1
IS65C1024AL
®
ISSI
PIN CONFIGURATION
32-Pin SOP
NC
A16
A14
A12
A7
A6
A5
A4
A3
A2
A1
A0
I/O0
I/O1
I/O2
GND
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
32
31
30
29
28
27
26
25
24
23
22
21
20
19
18
17
V
DD
A15
CE2
WE
A13
A8
A9
A11
OE
A10
CE
I/O7
I/O6
I/O5
I/O4
I/O3
PIN CONFIGURATION
32-Pin TSOP (Type 1)
A11
A9
A8
A13
WE
CE2
A15
DD
V
NC
A16
A14
A12
A7
A6
A5
A4
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
32
31
30
29
28
27
26
25
24
23
22
21
20
19
18
17
OE
A10
CE1
I/O7
I/O6
I/O5
I/O4
I/O3
GND
I/O2
I/O1
I/O0
A0
A1
A2
A3
PIN DESCRIPTIONS
A0-A16 Address Inputs
CE1 Chip Enable 1 Input
CE 2 Chip Enable 2 Input
OE Output Enable Input
WE Write Enable Input
I/O0-I/O7 Input/Output
OPERATING RANGE (IS62C1024AL)
Range Ambient Temperature VDD
Commercial 0°C to +70°C 5V ± 10%
Industrial -40°C to +85°C 5V ± 10%
VDD Power
GND Ground
OPERATING RANGE (IS65C1024AL)
Range Ambient Temperature VDD
Automotive -40°C to +125°C 5V ± 10%
TRUTH TABLE
Mode
WEWE
WE
WEWE
Not Selected X H X X High-Z ISB1, ISB2
(Power-down) X X L X High-Z ISB1, ISB2
Output Disabled H L H H High-Z ICC
Read H L H L DOUT ICC
Write L L H X DIN ICC
CE1CE1
CE1 CE2
CE1CE1
OEOE
OE I/O Operation VDD Current
OEOE
2
Integrated Silicon Solution, Inc. — www.issi.com —
1-800-379-4774
Rev. E
10/05/05
IS62C1024AL
IS65C1024AL
®
ISSI
ABSOLUTE MAXIMUM RATINGS
Symbol Parameter Value Unit
VTERM Terminal Voltage with Respect to GND –0.5 to +7.0 V
TSTG Storage Temperature –65 to +125 ° C
PT Power Dissipation 1.0 W
IOUT DC Output Current (LOW) 20 mA
Notes:
1. Stress greater than those listed under ABSOLUTE MAXIMUM RATINGS may cause permanent damage to the device. This is a
stress rating only and functional operation of the device at these or any other conditions above those indicated in the operational
sections of this specification is not implied. Exposure to absolute maximum rating conditions for extended periods may affect
reliability.
CAPACITANCE
Symbol Parameter Conditions Max. Unit
CIN Input Capacitance VIN = 0V 6 pF
COUT Output Capacitance VOUT = 0V 8 pF
Notes:
1. Tested initially and after any design or process changes that may affect these parameters.
2. Test conditions: T
(1,2)
A = 25°C, f = 1 MHz, VDD = 5.0V.
(1)
DC ELECTRICAL CHARACTERISTICS (Over Operating Range)
Symbol Parameter Test Conditions Options Min. Max. Unit
VOH Output HIGH Voltage VDD = Min., IOH = –1.0 mA 2.4 — V
VOL Output LOW Voltage VDD = Min., IOL = 2.1 mA — 0.4 V
VIH Input HIGH Voltage 2.2 VDD + 0.5 V
VIL Input LOW Voltage
ILI Input Leakage GND ≤ VIN ≤ VDD Com. -1 1 µA
ILO Output Leakage GND ≤ VOUT ≤ VDD Com. -1 1 µA
Note:
1. VIL (min.) = -0.3V DC; VIL (min.) = -2.0V AC (pulse width -2.0 ns). Not 100% tested.
VIH (max.) = VDD + 0.3V DC; VIH (max.) = VDD + 2.0V AC (pulse width -2.0 ns). Not 100% tested.
(1)
Ind. -2 2
Auto. -5 5
CE1 =
CE2 =
WE =
VIH
, or Ind. -2 2
VIL
, or OE =
VIL
VIH or
Auto. -5 5
-0.5 0.8 V
Integrated Silicon Solution, Inc. — www.issi.com —
Rev. E
10/05/05
1-800-379-4774
3
IS62C1024AL
IS65C1024AL
IS62C1024AL/IS65C1024AL
(1)
POWER SUPPLY CHARACTERISTICS
Symbol Parameter Test Conditions Min. Max. Min. Max. Unit
I
CC Average operating CE1 = VIL, CE2 = VIH Com. — 25 m A
Current VIN = VIH or VIL, Ind. — 30
I I/O= 0 mA Au t o. — 3 5
ICC1VDD Dynamic Operating VDD = Max., CE1 = VIL Com. — 30 m A
Supply Current IOUT = 0 mA, f = fMAX Ind. — 35
VIN = VIH or VIL Auto. — 40
CE2 = VIH typ.
SB1 TTL Standby Current VDD = Max., Com. — 1 m A
I
(TTL Inputs) VIN = VIH or VIL, CE1 ≥ VIH, Ind. — 1.5
or CE2 ≤ VIL, f = 0 Au to . — 2
I
SB2 CMOS Standby VDD = Max., Com. — 5 µ A
Current (CMOS Inputs) CE1 ≥ VDD – 0.2V, or Ind. — 10
CE2 ≤ 0.2V, VIN ≥ VDD – 0.2V, Auto. — 35
or VIN ≤ VSS + 0.2V, f = 0 typ.
Note:
1. At f = f
2. Typical Values are measured at V
MAX, address and data inputs are cycling at the maximum frequency, f = 0 means no input lines change.
DD = 5V, TA = 25
(Over Operating Range)
-35 ns -45 ns
(2)
(2)
o
C and not 100% tested.
—20
—4
ISSI
®
READ CYCLE SWITCHING CHARACTERISTICS
(1)
(Over Operating Range)
-35 ns -45 ns
Symbol Parameter Min. Max. Min. Max. Unit
tRC Read Cycle Time 35 — 45 — ns
tAA Address Access Time — 35 — 45 ns
tOHA Output Hold Time 3 — 3 — ns
tACE1 CE1 Access Time — 35 — 45 ns
tACE2 CE2 Access Time — 35 — 45 ns
tDOE OE Access Time — 10 — 20 ns
(2)
tLZOE
(2)
tHZOE
(2)
tLZCE1
(2)
tLZCE2
(2)
tHZCE
Notes:
1. Test conditions assume signal transition times of 5 ns or less, timing reference levels of 1.5V, input pulse levels of
0.6 to 2.4V and output loading specified in Figure 1a.
2. Tested with the load in Figure 1b. Transition is measured ±500 mV from steady-state voltage. Not 100% tested.
OE to Low-Z Output 3 — 5 — ns
OE to High-Z Output 0 10 0 1 5 ns
CE1 to Low-Z Output 3 — 5 — ns
CE2 to Low-Z Output 3 — 5 — ns
CE1 or CE2 to High-Z Output 0 1 0 0 1 5 ns
4
Integrated Silicon Solution, Inc. — www.issi.com —
1-800-379-4774
Rev. E
10/05/05
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