• Fully static operation: no clock or refresh
required
• Three state outputs
• Industrial temperature available
DD (IS62WV5128ALL)
DD (IS62WV5128BLL)
DESCRIPTION
The ISSI IS62WV5128ALL / IS62WV5128BLL are highspeed, 4M bit static RAMs organized as 512K words by 8
bits. It is fabricated using ISSI's high-performance CMOS
technology. This highly reliable process coupled with
innovative circuit design techniques, yields highperformance and low power consumption devices.
When CS1 is HIGH (deselected) the device assumes a
standby mode at which the power dissipation can be
reduced down with CMOS input levels.
Easy memory expansion is provided by using Chip Enable
and Output Enable inputs. The active LOW Write Enable
(WE) controls both writing and reading of the memory.
The IS62WV5128ALL and IS62WV5128BLL are packaged
in the JEDEC standard 32-pin TSOP (TYPE I), 32-pin
sTSOP (TYPE I), 32-pin TSOP (Type II), and 36-pin mini
BGA.
Commercial0°C to +70°C1.65V - 2.2V 2.5V - 3.6V
Industrial–40°C to +85°C1.65V - 2.2V 2.5V - 3.6V
®
ABSOLUTE MAXIMUM RATINGS
(1)
SymbolParameterValueUnit
VTERMTerminal Voltage with Respect to GND–0.2 to VDD+0.3V
VDDVDD Related to GND–0.2 to VDD+0.3V
TSTGStorage Temperature–65 to +150°C
PTPower Dissipation1.0W
Note:
1. Stress greater than those listed under ABSOLUTE MAXIMUM RATINGS may cause permanent damage to the device. This is
a stress rating only and functional operation of the device at these or any other conditions above those indicated in the
operational sections of this specification is not implied. Exposure to absolute maximum rating conditions for extended periods
may affect reliability.
DC ELECTRICAL CHARACTERISTICS (Over Operating Range)
OE to High-Z Output—20—25ns
OE to Low-Z Output5—5—ns
tHZCS1CS1 to High-Z Output020025ns
tLZCS1CS1 to Low-Z Output10—10—ns
Notes:
1. Test conditions assume signal transition times of 5 ns or less, timing reference levels of 0.9V/1.5V, input pulse levels of 0.4 to
VDD-0.2V/VDD-0.3V and output loading specified in Figure 1.
2. Tested with the load in Figure 2. Transition is measured ±500 mV from steady-state voltage. Not 100% tested.
AC WAVEFORMS
READ CYCLE NO. 1
ADDRESS
D
OUT
(1,2)
(Address Controlled) (CS1 = OE = VIL, WE = VIH)
t
RC
t
AA
t
OHA
PREVIOUS DATA VALID
t
OHA
DATA VALID
Integrated Silicon Solution, Inc. — www.issi.com —
Rev. C
05/02/05
1-800-379-4774
7
IS62WV5128ALL, IS62WV5128BLLISSI
AC WAVEFORMS
READ CYCLE NO. 2
ADDRESS
OE
CS1
(1,3)
(CS1, OE Controlled)
t
ACS1
t
RC
t
AA
t
t
LZOE
DOE
t
HZOE
t
OHA
®
t
LZCS1
DOUT
Notes:
1. WE is HIGH for a Read Cycle.
2. The device is continuously selected. OE, CS1= V
3. Address is valid prior to or coincident with CS1 LOW transition.
HIGH-Z
IL. WE=VIH.
t
HZCS
DATA VALID
8
Integrated Silicon Solution, Inc. — www.issi.com —
1-800-379-4774
Rev. C
05/02/05
IS62WV5128ALL, IS62WV5128BLLISSI
®
WRITE CYCLE SWITCHING CHARACTERISTICS
(1,2)
(Over Operating Range)
55 ns70 ns
SymbolParameterMin .Max. Min.Max.Unit
tWCWrite Cycle Time 55— 70—ns
tSCS1CS1 to Write End45— 60—ns
tAWAddress Setup Time to Write End4 5— 60—ns
tHAAddress Hold from Write End0— 0—ns
tSAAddress Setup Time0— 0—ns
tPWEWE Pulse Width40— 50—ns
tSDData Setup to Write End2 5— 30—ns
tHDData Hold from Write End 0— 0—ns
(3)
tHZWE
(3)
tLZWE
Notes:
1. Test conditions assume signal transition times of 5 ns or less, timing reference levels of 0.9V/1.5V, input pulse levels of 0.4V to
V
DD-0.2V/VDD-0.3V and output loading specified in Figure 1.
The internal write time is defined by the overlap of CS1 LOW and WE LOW. All signals must be in valid states to initiate a Write, but any one can go inactive to
2.
terminate the Write. The Data Input Setup and Hold timing are referenced to the rising or falling edge of the signal that terminates the write.
3. Tested with the load in Figure 2. Transition is measured ±500 mV from steady-state voltage. Not 100% tested.
WE LOW to High-Z Output—20 —20ns
WE HIGH to Low-Z Output5— 5—ns
AC WAVEFORMS
WRITE CYCLE NO. 1 (CS1 Controlled, OE = HIGH or LOW)
t
WC
ADDRESS
t
SCS1
CS1
t
AW
t
WE
DOUT
DIN
t
SA
DATA UNDEFINED
t
HZWE
PWE
HIGH-Z
t
SD
DATA-IN VALID
t
HA
t
LZWE
t
HD
Integrated Silicon Solution, Inc. — www.issi.com —
Rev. C
05/02/05
1-800-379-4774
9
IS62WV5128ALL, IS62WV5128BLLISSI
WRITE CYCLE NO. 2 (WE Controlled: OE is HIGH During Write Cycle)
t
WC
ADDRESS
OE
t
HA
t
t
LZWE
HD
CS1
WE
DOUT
t
SA
DATA UNDEFINED
t
AW
t
HZWE
t
SCS1
t
PWE
HIGH-Z
t
SD
®
DIN
DATA-IN VALID
WRITE CYCLE NO. 3 (WE Controlled: OE is LOW During Write Cycle)
t
WC
ADDRESS
OE
t
SCS1
CS1
t
AW
t
WE
PWE
t
HA
10
DOUT
DIN
t
SA
DATA UNDEFINED
t
HZWE
HIGH-Z
t
SD
DATA-IN VALID
t
LZWE
t
HD
Integrated Silicon Solution, Inc. — www.issi.com —
1-800-379-4774
Rev. C
05/02/05
IS62WV5128ALL, IS62WV5128BLLISSI
DATA RETENTION SWITCHING CHARACTERISTICS
SymbolParameterTest ConditionMin.Max.Unit
VDRVDD for Data RetentionSee Data Retention Waveform1.23.6V
IDRData Retention CurrentVDD = 1.2V, CS1≥ VDD – 0.2V—1 5µA
tSDRData Retention Setup TimeSee Data Retention Waveform0—ns
tRDRRecovery TimeSee Data Retention WaveformtRC—ns
®
DATA RETENTION WAVEFORM (
t
SDR
V
DD
V
DR
CS1
GND
CS1CS1
CS1 Controlled)
CS1CS1
Data Retention Mode
CS1≥ V
DD -
0.2V
t
RDR
Integrated Silicon Solution, Inc. — www.issi.com —
Rev. C
05/02/05
1-800-379-4774
11
IS62WV5128ALL, IS62WV5128BLLISSI
ORDERING INFORMATION
IS62WV5128ALL (1.65V-2.2V)
Industrial Range: –40°C to +85°C
Speed (ns)Order Part No.Package
70IS62WV5128ALL-70TITSOP, TYPE I
70IS62WV5128ALL-70T2ITSOP, TYPE II
70IS62WV5128ALL-70HIsTSOP, TYPE I
70IS62WV5128ALL-70BImini BGA (6mmx8mm)
ORDERING INFORMATION
IS62WV5128BLL (2.5V - 3.6V)
Commercial Range: 0°C to +70°C
®
Speed (ns)Order Part No.Package
55IS62WV5128BLL-55HsTSOP, TYPE I
Industrial Range: –40°C to +85°C
Speed (ns)Order Part No.Package
55IS62WV5128BLL-55TITSOP, TYPE I
55IS62WV5128BLL-55TLITSOP, TYPE I, Lead-free
55IS62WV5128BLL-55T2ITSOP, TYPE II
55IS62WV5128BLL-55T2LITSOP, TYPE II, Lead-free
55IS62WV5128BLL-55HIsTSOP, TYPE I
55IS62WV5128BLL-55HLIsTSOP, TYPE I, Lead-free
55IS62WV5128BLL-55BImini BGA (6mmx8mm)
55IS62WV5128BLL-55BLImini BGA (6mmx8mm), Lead-free
12
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