IS65C256AL
®
IS62C256AL
32K x 8 LOW POWER CMOS STATIC RAM
FEATURES
• Access time: 25 ns, 45 ns
• Low active power: 200 mW (typical)
• Low standby power
— 150 µW (typical) CMOS standby
— 15 mW (typical) operating
• Fully static operation: no clock or refresh
required
• TTL compatible inputs and outputs
• Single 5V power supply
• Lead-free available
• Industrial and Automotive temperatures available
DESCRIPTION
The ISSI IS62C256AL/IS65C256AL is a low power,
32,768 word by 8-bit CMOS static RAM. It is fabricated
using ISSI's high-performance, low power CMOS technology.
When CE is HIGH (deselected), the device assumes a
standby mode at which the power dissipation can be
reduced down to 150 µW (typical) at CMOS input levels.
Easy memory expansion is provided by using an active
LOW Chip Select (CE) input and an active LOW Output
Enable (OE) input. The active LOW Write Enable (WE)
controls both writing and reading of the memory.
The IS62C256AL/IS65C256AL is pin compatible with
other 32Kx8 SRAMs in plastic SOP or TSOP (Type I)
package.
ISSI
Preliminary Information
June 2005
FUNCTIONAL BLOCK DIAGRAM
A0-A14
VDD
GND
I/O0-I/O7
CE
OE
WE
DECODER
I/O
DATA
CIRCUIT
CONTROL
CIRCUIT
32K X 8
MEMORY ARRAY
COLUMN I/O
Copyright © 2005 Integrated Silicon Solution, Inc. All rights reserved. ISSI reserves the right to make changes to this specification and its products at any time without notice. ISSI assumes no liability
arising out of the application or use of any information, products or services described herein. Customers are advised to obtain the latest version of this device specification before relying on any
published information and before placing orders for products.
Integrated Silicon Solution, Inc. — www.issi.com —
Rev. 00A
06/01/05
1-800-379-4774
1
IS65C256AL
IS62C256AL
®
ISSI
PIN CONFIGURATION
28-Pin SOP
A7
A6
A5
A4
A3
A2
A1
A0
1
2
3
4
5
6
7
8
9
10
11
12
13
14
A14
A12
I/O0
I/O1
I/O2
GND
PIN DESCRIPTIONS
28
27
26
25
24
23
22
21
20
19
18
17
16
15
VDD
WE
A13
A8
A9
A11
OE
A10
CE
I/O7
I/O6
I/O5
I/O4
I/O3
PIN CONFIGURATION
28-Pin TSOP
OE
A11
A9
A8
A13
WE
VDD
A14
A12
A7
A6
A5
A4
A3
22
23
24
25
26
27
28
1
2
3
4
5
6
7
TRUTH TABLE
21
20
19
18
17
16
15
14
13
12
11
10
A10
CE
I/O7
I/O6
I/O5
I/O4
I/O3
GND
I/O2
I/O1
I/O0
A0
A1
9
A2
8
A0-A14 Address Inputs
CE Chip Select Input
OE Output Enable Input
WE Write Enable Input
Mode
Not Selected X H X High-Z ISB1, ISB2
(Power-down)
Output Disabled H L H High-Z ICC1, ICC2
WEWE
WE
WEWE
CECE
OEOE
CE
OE I/O Operation VDD Current
CECE
OEOE
Read H L L DOUT ICC1, ICC2
I/O0-I/O7 Input/Output
Write L L X DIN ICC1, ICC2
VDD Power
GND Ground
ABSOLUTE MAXIMUM RATINGS
(1)
Symbol Parameter Value Unit
VTERM Terminal Voltage with Respect to GND –0.5 to +7.0 V
TSTG Storage Temperature –65 to +150 °C
PT Power Dissipation 0.5 W
IOUT DC Output Current (LOW) 20 mA
Note:
1. Stress greater than those listed under ABSOLUTE MAXIMUM RATINGS may cause
permanent damage to the device. This is a stress rating only and functional operation of the
device at these or any other conditions above those indicated in the operational sections of
this specification is not implied. Exposure to absolute maximum rating conditions for extended
periods may affect reliability.
2
Integrated Silicon Solution, Inc. — 1-800-379-4774
Rev. 00A
06/01/05
IS65C256AL
IS62C256AL
OPERATING RANGE
Part No. Range Ambient Temperature VDD
IS62C256AL Commercial 0°C to +70°C 5V ± 10%
IS62C256AL Industrial –40°C to +85°C 5V ± 10%
IS65C256AL Automotive –40°C to +125°C 5V ± 10%
DC ELECTRICAL CHARACTERISTICS
Symbol Parameter Test Conditions Min. Max. Unit
VOH Output HIGH Voltage VDD = Min., IOH = –1.0 mA 2.4 — V
VOL Output LOW Voltage VDD = Min., IOL = 2.1 mA — 0.4 V
VIH Input HIGH Voltage 2.2 VDD + 0.5 V
VIL Input LOW Voltage
ILI Input Leakage GND ≤ VIN ≤ VDD Com. –1 1 µA
ILO Output Leakage GND ≤ VOUT ≤ VDD, Com. –1 1 µA
Note: 1. VIL = –3.0V for pulse width less than 10 ns.
(1)
Ind. –2 2
Auto. –10 10
Outputs Disabled Ind. –2 2
Auto. –10 10
–0.3 0.8 V
ISSI
®
Integrated Silicon Solution, Inc. — 1-800-379-4774
Rev. 00A
06/01/05
3
IS65C256AL
IS62C256AL
®
ISSI
POWER SUPPLY CHARACTERISTICS
Symbol Parameter Test Conditions Min. Max. Min. Max. Unit
ICC1 VDD Operating VDD = Max., CE = VIL Com. — 15 — 15 mA
Supply Current IOUT = 0 mA, f = 0 Ind. — 20 — 20
ICC2 VDD Dynamic Operating VDD = Max., CE = V IL Com. — 25 — 20 mA
Supply Current IOUT = 0 mA, f = fMAX Ind. — 30 — 25
ISB1 TTL Standby Current VDD = Max., Com. — 100 — 100
(TTL Inputs) VIN = VIH or VIL Ind. — 120 — 120
CE ≥ VIH, f = 0 Auto. — 150 — 150
ISB2 CMOS Standby VDD = Max., Com. — 15 — 15
Current (CMOS Inputs) CE ≥ VDD – 0.2V, Ind. — 20 — 20
VIN ≥ VDD – 0.2V, or Auto. — 50 — 50
VIN ≤ 0.2V, f = 0 typ.
Note:
1. At f = fMAX, address and data inputs are cycling at the maximum frequency, f = 0 means no input lines change.
2. Typical values are measured at VDD = 5.0V, TA = 25oC and not 100% tested.
(1)
(Over Operating Range)
Auto. — 25 — 25
Auto. — 35 — 30
(2)
typ.
15 12
(2)
-25 ns -45 ns
5 5
µA
µA
CAPACITANCE
Symbol Parameter Conditions Max. Unit
CIN Input Capacitance VIN = 0V 8 pF
COUT Output Capacitance VOUT = 0V 10 pF
Notes:
1. Tested initially and after any design or process changes that may affect these parameters.
2. Test conditions: T
(1,2)
A = 25°C, f = 1 MHz, VDD = 5.0V.
4
Integrated Silicon Solution, Inc. — 1-800-379-4774
Rev. 00A
06/01/05
IS65C256AL
IS62C256AL
®
ISSI
READ CYCLE SWITCHING CHARACTERISTICS
(1)
(Over Operating Range)
-25 ns -45 ns
Symbol Parameter Min. Max. Min. Max. Unit
tRC Read Cycle Time 2 5 — 4 5 — ns
tAA Address Access Time — 25 — 45 ns
tOHA Output Hold Time 2 — 2 — ns
tACS CE Access Time — 25 — 45 ns
tDOE OE Access Time — 13 — 25 ns
(2)
tLZOE
(2)
tHZOE
(2)
tLZCS
(2)
tHZCS
(3)
tPU
(3)
tPD
Notes:
1. Test conditions assume signal transition times of 5 ns or less, timing reference levels of 1.5V, input pulse levels of 0 to 3.0V and
output loading specified in Figure 1.
2. Tested with the load in Figure 2. Transition is measured ±500 mV from steady-state voltage. Not 100% tested.
3. Not 100% tested.
OE to Low-Z Output 0 — 0 — ns
OE to High-Z Output 0 12 0 20 ns
CE to Low-Z Output 3 — 3 — ns
CE to High-Z Output 0 12 0 20 ns
CE to Power-Up 0 — 0 — ns
CE to Power-Down — 2 0 — 30 ns
AC TEST CONDITIONS
Parameter Unit
Input Pulse Level 0V to 3.0V
Input Rise and Fall Times 3 ns
Input and Output Timing 1.5V
and Reference Levels
Output Load See Figures 1 and 2
AC TEST LOADS
480 Ω
5V
OUTPUT
100 pF
Including
jig and
scope
255 Ω
Figure 1. Figure 2.
OUTPUT
5V
5 pF
Including
jig and
scope
480 Ω
255 Ω
Integrated Silicon Solution, Inc. — 1-800-379-4774
Rev. 00A
06/01/05
5
IS65C256AL
IS62C256AL
AC WAVEFORMS
®
ISSI
READ CYCLE NO. 1
ADDRESS
D
OUT
READ CYCLE NO. 2
ADDRESS
OE
(1,2)
PREVIOUS DATA VALID
(1,3)
t
AA
t
OHA
t
RC
t
AA
DATA VALID
t
RC
t
OHA
t
OHA
READ1.eps
t
DOE
t
CE
t
LZCS
D
OUT
Notes:
1. WE is HIGH for a Read Cycle.
2. The device is continuously selected. OE, CE = V
3. Address is valid prior to or coincident with CE LOW transitions.
HIGH-Z
LZOE
t
ACS
IL.
DATA VALID
t
HZCS
t
HZOE
CS_RD2.eps
6
Integrated Silicon Solution, Inc. — 1-800-379-4774
Rev. 00A
06/01/05
IS65C256AL
IS62C256AL
®
ISSI
WRITE CYCLE SWITCHING CHARACTERISTICS
(1,3)
(Over Operating Range)
-25 ns -45 ns
Symbol Parameter Min. Max. Min. Max. Unit
tWC Write Cycle Time 2 5 — 45 — ns
tSCS CE to Write End 1 5 — 3 5 — ns
tAW Address Setup Time to Write End 1 5 — 2 5 — ns
tHA Address Hold from Write End 0 — 0 — ns
tSA Address Setup Time 0 — 0 — ns
tPWE1, WE Pulse Width 1 5 — 25 — ns
(4)
tPWE2
tSD Data Setup to Write End 12 — 20 — ns
tHD Data Hold from Write End 0 — 0 — ns
Notes:
1. Test conditions assume signal transition times of 5 ns or less, timing reference levels of 1.5V, input pulse levels of 0 to 3.0V and
output loading specified in Figure 1.
2. Tested with the load in Figure 2. Transition is measured ±500 mV from steady-state voltage. Not 100% tested.
3. The internal write time is defined by the overlap of CE LOW and WE LOW. All signals must be in valid states to initiate a Write,
but any one can go inactive to terminate the Write. The Data Input Setup and Hold timing are referenced to the rising or falling
edge of the signal that terminates the write.
4. Tested with OE HIGH.
AC WAVEFORMS
WRITE CYCLE NO. 1
ADDRESS
CE
WE
OUT
D
D
IN
(CE Controlled, OE is HIGH or LOW)
t
WC
VALID ADDRESS
t
SA
t
DATA UNDEFINED
t
HZWE
AW
t
t
t
PWE1
PWE2
SCS
(1 )
HIGH-Z
t
SD
DATA
IN
VALID
t
HA
t
LZWE
t
HD
CS_WR1.eps
Integrated Silicon Solution, Inc. — 1-800-379-4774
Rev. 00A
06/01/05
7
IS65C256AL
IS62C256AL
AC WAVEFORMS
®
ISSI
WRITE CYCLE NO. 2
ADDRESS
OE
LOW
CE
WE
t
SA
OUT
D
D
IN
(OE is HIGH During Write Cycle)
t
WC
VALID ADDRESS
t
AW
t
PWE1
t
HZWE
DATA UNDEFINED
(1,2)
HIGH-Z
t
SD
DATAIN VALID
t
HA
t
LZWE
t
HD
CS_WR2.eps
WRITE CYCLE NO. 3
ADDRESS
LOW
OE
CE
LOW
(OE is LOW During Write Cycle)
VALID ADDRESS
t
AW
t
WC
t
PWE2
(1)
t
HA
WE
t
D
OUT
D
IN
SA
DATA UNDEFINED
t
HZWE
HIGH-Z
t
SD
DATAIN VALID
t
t
HD
LZWE
CS_WR3.eps
Notes:
1. The internal write time is defined by the overlap of CE LOW and WE LOW. All signals must be in valid states to initiate a Write,
but any one can go inactive to terminate the Write. The Data Input Setup and Hold timing are referenced to the rising or falling
edge of the signal that terminates the write.
2. I/O will assume the High-Z state if OE = V
IH.
8
Integrated Silicon Solution, Inc. — 1-800-379-4774
Rev. 00A
06/01/05
IS65C256AL
IS62C256AL
DATA RETENTION SWITCHING CHARACTERISTICS
Symbol Parameter Test Condition Min. Typ. Max. Unit
VDR VDD for Data Retention See Data Retention Waveform 2.0 5.5 V
IDR Data Retention Current VDD = 2.0V, CE ≥ VDD – 0.2V Com. — — 15 µA
VIN ≥ VDD – 0.2V, or VIN ≤ VSS + 0.2V
tSDR Data Retention Setup Time See Data Retention Waveform 0 — ns
tRDR Recovery Time See Data Retention Waveform tRC —ns
Note:
1. Typical Values are measured at VDD = 5V, TA = 25oC and not 100% tested.
Ind. — — 20
Auto. — — 50
ISSI
®
DATA RETENTION WAVEFORM (
t
SDR
VDD
4.5V
2.2V
V
DR
CE
GND
CECE
CE Controlled)
CECE
Data Retention Mode
CE ≥ VDD
- 0.2V
t
RDR
Integrated Silicon Solution, Inc. — 1-800-379-4774
Rev. 00A
06/01/05
9
IS65C256AL
IS62C256AL
ORDERING INFORMATION
Commercial Range: 0°C to +70°C
Speed
(ns) Order Part No. Package
45 IS62C256AL-45T TSOP
IS62C256AL-45TL TSOP, Lead-free
IS62C256AL-45U Plastic SOP
IS62C256AL-45UL Plastic SOP, Lead-free
ORDERING INFORMATION
Industrial Range: –40°C to +85°C
Speed
(ns) Order Part No. Package
®
ISSI
25 IS62C256AL-25TI TSOP
IS62C256AL-25UI Plastic SOP
45 IS62C256AL-45TI TSOP
IS62C256AL-45TLI TSOP, Lead-free
IS62C256AL-45UI Plastic SOP
IS62C256AL-45ULI Plastic SOP, Lead-free
ORDERING INFORMATION
Automotive Range: –40°C to +125°C
Speed
(ns) Order Part No. Package
25 IS65C256AL-25TA3 TSOP
IS65C256AL-25TLA3 TSOP, Lead-free
IS65C256AL-25UA3 Plastic SOP
IS65C256AL-25ULA3 Plastic SOP, Lead-free
45 IS65C256AL-45TA3 TSOP
IS65C256AL-45TLA3 TSOP, Lead-free
IS65C256AL-45UA3 Plastic SOP
IS65C256AL-45ULA3 Plastic SOP, Lead-free
10
Integrated Silicon Solution, Inc. — 1-800-379-4774
Rev. 00A
06/01/05
PACKAGING INFORMATION
Plastic TSOP - 28-pins
Package Code: T (Type I)
1
®
ISSI
E
H
N
D
S
e
B
Plastic TSOP (T—Type I)
Millimeters Inches
Symbol Min Max Min Max
Ref. Std.
No. Leads 28
A 1.00 1.20 0.037 0.047
A1 0.05 0.20 0.002 0.008
B 0.16 0.27 0.006 0.011
C 0.10 0.20 0.004 0.008
D 7.90 8.10 0.308 0.316
E 11.70 11.90 0.456 0.465
H 13.20 13.60 0.515 0.531
e 0.55 BSC 0.022 BSC
L 0.30 0.70 0.011 0.027
α 0° 5° 0° 5°
A
SEATING PLANE
L
A1
Notes:
1. Controlling dimension: millimeters, unless otherwise specified.
2. BSC = Basic lead spacing between centers.
3. Dimensions D and E do not include mold flash protrusions and
should be measured from the bottom of the package
4. Formed leads shall be planar with respect to one another within
0.004 inches at the seating plane.
α
C
.
Integrated Silicon Solution, Inc.
PK13197T28 Rev. B 01/31/97
PACKAGING INFORMATION ISSI
C
S
330-mil Plastic SOP
Package Code: U (28-pin)
N
E1
E
1
D
SEATING PLANE
A
h x 45
o
®
e
MILLIMETERS INCHES
Sym. Min. Max. Min. Max.
No. Leads 28 28
A — 2.84 — 0.112
A1 0.10 — 0.004 —
B 0.36 0.51 0.014 0.020
C 0.25 — 0.010 —
D 17.98 18.24 0.708 0.718
E 11.51 12.12 0.453 0.477
E1 8.28 8.53 0.326 0.336
e 1.27 BSC 0.050 BSC
h 0.30 0.51 0.012 0.020
L 0.71 1.14 0.028 0.045
α 0
S 0.58 1.19 0.023 0.047
o
o
8
B
A1
o
0
o
8
L
Notes:
1. Controlling dimension: inches, unless
otherwise specified.
2. BSC = Basic lead spacing between
centers.
3. Dimensions D and E1 do not include
mold flash protrusions and should be
measured from the bottom of the
package.
4. Formed leads shall be planar with
respect to one another within 0.004
inches at the seating plane.
α
Copyright © 2003 Integrated Silicon Solution, Inc. All rights reserved. ISSI reserves the right to make changes to this specification and its products at any time
without notice. ISSI assumes no liability arising out of the application or use of any information, products or services described herein. Customers are advised to
obtain the latest version of this device specification before relying on any published information and before placing orders for products.
Integrated Silicon Solution, Inc. — www.issi.com — 1-800-379-4774
Rev. C
02/26/03
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