Integrated Silicon Solution IS61LV6416, IS61LV6416L User Manual
IS61LV6416
®
IS61LV6416L
64K x 16 HIGH-SPEED CMOS STATIC RAM
WITH 3.3V SUPPLY
FEATURES
• High-speed access time: 8, 10, 12 ns
• CMOS low power operation
— 61LV6416:
75 mW (typical) operating current
0.5 mW (typical) standby current
— 61LV6416L:
65 mW (typical) operating current
50 µW (typical) standby current
• TTL compatible interface levels
• Single 3.3V power supply
• Fully static operation: no clock or refresh
required
• Three state outputs
• Data control for upper and lower bytes
• Industrial temperature available
• Lead-free available
DESCRIPTION
The ISSI IS61LV6416/IS61LV6416L is a high-speed,
1,048,576-bit static RAM organized as 65,536 words by 16
bits. It is fabricated using ISSI's high-performance CMOS
technology. This highly reliable process coupled with
innovative circuit design techniques, yields access times
as fast as 8 ns with low power consumption.
When CE is HIGH (deselected), the device assumes a
standby mode at which the power dissipation can be
reduced down with CMOS input levels.
Easy memory expansion is provided by using Chip
Enable and Output Enable inputs, CE and OE. The active
LOW Write Enable (WE) controls both writing and reading
of the memory. A data byte allows Upper Byte (UB) and
Lower Byte (LB) access.
The IS61LV6416/IS61LV6416L is packaged in the JEDEC
standard 44-pin 400-mil SOJ, 44-pin TSOP-II, and 48-pin
mini BGA (6mm x 8mm).
ISSI
NOVEMBER 2005
FUNCTIONAL BLOCK DIAGRAM
A0-A15
DD
V
GND
I/O0-I/O7
Lower Byte
I/O8-I/O15
Upper Byte
CE
OE
WE
UB
LB
Copyright © 2005 Integrated Silicon Solution, Inc. All rights reserved. ISSI reserves the right to make changes to this specification and its products at any time without notice. ISSI assumes no liability
arising out of the application or use of any information, products or services described herein. Customers are advised to obtain the latest version of this device specification before relying on any
published information and before placing orders for products.
Integrated Silicon Solution, Inc.
Rev. I
11/22/05
DECODER
I/O
DATA
CIRCUIT
CONTROL
CIRCUIT
64K x 16
MEMORY ARRAY
COLUMN I/O
1
IS61LV6416
IS61LV6416L
PIN CONFIGURATIONS
®
ISSI
44-Pin SOJ (K)
1
A15
2
A14
3
A13
4
A12
5
A11
6
CE
7
I/O0
8
I/O1
9
I/O2
10
I/O3
11
VDD
I/O4
I/O5
I/O6
I/O7
WE
A10
A9
A8
A7
NC
12
13
14
15
16
17
18
19
20
21
22
GND
44
43
42
41
40
39
38
37
36
35
34
33
32
31
30
29
28
27
26
25
24
23
A0
A1
A2
OE
UB
LB
I/O15
I/O14
I/O13
I/O12
GND
VDD
I/O11
I/O10
I/O9
I/O8
NC
A3
A4
A5
A6
NC
44-Pin TSOP-II (T)
A15
A14
A13
A12
A11
CE
I/O0
I/O1
I/O2
I/O3
V
DD
GND
I/O4
I/O5
I/O6
I/O7
WE
A10
A9
A8
A7
NC
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
44
43
42
41
40
39
38
37
36
35
34
33
32
31
30
29
28
27
26
25
24
23
A0
A1
A2
OE
UB
LB
I/O15
I/O14
I/O13
I/O12
GND
V
DD
I/O11
I/O10
I/O9
I/O8
NC
A3
A4
A5
A6
NC
48-Pin mini BGA (6mm x 8mm) (B)
1 2 3 4 5 6
A1
OE
UB A3
I/O10A5
I/O
11
I/O12NC
A14
I/O
13
A12
NC
A8
A0
NC
A9
A
B
C
D
E
F
G
H
LB
I/O
I/O
GND
V
I/O
I/O
NC
8
9
DD
14
15
2
A15
A13
A4
A6
A7
NC
A10
A2
CE I/O
I/O1I/O
I/O
3
GND
I/O
4
I/O
I/O
5
WE
I/O
A11 NC
NC
0
2
V
DD
6
7
PIN DESCRIPTIONS
A0-A15 Address Inputs
I/O0-I/O15 Data Inputs/Outputs
CE Chip Enable Input
OE Output Enable Input
WE Write Enable Input
LB Lower-byte Control (I/O0-I/O7)
UB Upper-byte Control (I/O8-I/O15)
NC No Connection
VDD Power
GND Ground
Integrated Silicon Solution, Inc.
Rev. I
11/22/05
IS61LV6416
IS61LV6416L
TRUTH TABLE
I/O PIN
Mode
Not Selected X H X X X High-Z High-Z ISB1, ISB2
Output Disabled H L H X X High-Z High-Z ICC
Read H L L L H D
Write L L X L H DIN High-Z ICC
WEWE
WE
WEWE
X L X H H High-Z High-Z
H L L H L High-Z DOUT
HLLLL DOUT DOUT
L L X H L High-Z DIN
LLXLL DIN DIN
CECE
CE
CECE
OEOE
OE
OEOE
LBLB
LB
LBLB
UBUB
UB I/O0-I/O7 I/O8-I/O15 VDD Current
UBUB
OUT High-Z ICC
ISSI
®
1
2
3
ABSOLUTE MAXIMUM RATINGS
Symbol Parameter Value Unit
VTERM Terminal Voltage with Respect to GND –0.5 to VDD+0.5 V
TSTG Storage Temperature –65 to +150 °C
PT Power Dissipation 1.5 W
IOUT DC Output Current (LOW) 20 mA
Note:
1. Stress greater than those listed under ABSOLUTE MAXIMUM RATINGS may cause
permanent damage to the device. This is a stress rating only and functional operation of
the device at these or any other conditions above those indicated in the operational
sections of this specification is not implied. Exposure to absolute maximum rating
conditions for extended periods may affect reliability.
OPERATING RANGE
Range Ambient Temperature VDD (8,10 ns) VDD (12 ns)
Commercial 0°C to +70°C 3.3V+10%,-5% 3.3V ± 10%
Industrial –40°C to +85°C 3.3V+10%,-5% 3.3V ± 10%
(1)
4
5
6
7
8
9
DC ELECTRICAL CHARACTERISTICS (Over Operating Range)
Symbol Parameter Test Conditions Min. Max. Unit
VOH Output HIGH Voltage VDD = Min., IOH = –4.0 mA 2.4 — V
VOL Output LOW Voltage VDD = Min., IOL = 8.0 mA — 0.4 V
VIH Input HIGH Voltage 2 VDD + 0.3 V
VIL Input LOW Voltage
ILI Input Leakage GND ≤ VIN ≤ VDD –2 2 µA
ILO Output Leakage GND ≤ VOUT ≤ VDD, Outputs Disabled –2 2 µA
Notes:
1. VIL (min.) = –2.0V for pulse width less than 10 ns.
Integrated Silicon Solution, Inc.
Rev. I
11/22/05
(1)
–0.3 0.8 V
10
11
12
3
IS61LV6416
IS61LV6416L
IS61LV6416
POWER SUPPLY CHARACTERISTICS
Symbol Parameter Test Conditions Min. Max. Min. Max. Min. Max. Unit
ICC VDD Dynamic Operating VDD = Max., Com. — 140 — 120 — 100 mA
Supply Current IOUT = 0 mA, f = fMAX Ind. — 150 — 130 — 110
I
SB1 TTL Standby Current VDD = Max., Com. — 15 — 15 — 15 mA
(TTL Inputs) VIN = VIH or VIL Ind. — 20 — 20 — 20
CE ≥ VIH , f = 0
SB2 CMOS Standby VDD = Max., Com. — 5 — 5 — 5 mA
I
Current (CMOS Inputs) CE ≥ VDD – 0.2V, Ind. — 10 — 10 — 10
VIN ≥ VDD – 0.2V, or typ.
VIN ≤ 0.2V, f = 0
(1)
(Over Operating Range)
-8 ns -10 ns -12 ns
(2)
typ.
(2)
— 105 — 95—75
— 0.5 — 0.5 — 0.5
ISSI
®
Note:
1. At f = f
2. Typical values are measured at V
MAX, address and data inputs are cycling at the maximum frequency, f = 0 means no input lines change.
DD=3.3V, TA=25
o
C. Not 100% Tested.
IS61LV6416L
POWER SUPPLY CHARACTERISTICS
Symbol Parameter Test Conditions Min. Max. Min. Max. Unit
ICC VDD Dynamic Operating VDD = Max., Com. — 100 — 95mA
Supply Current IOUT = 0 mA, f = fMAX Ind. — 110 — 105
ISB1 TTL Standby Current VDD = Max., Com. — 15 — 15 mA
(TTL Inputs) VIN = VIH or VIL Ind. — 20 — 20
CE ≥ VIH , f = 0
ISB2 CMOS Standby VDD = Max., Com. — 1 — 1 mA
Current (CMOS Inputs) CE ≥ VDD – 0.2V, Ind. — 1.5 — 1.5
VIN ≥ VDD – 0.2V, or typ.
VIN ≤ 0.2V, f = 0
Note:
1. At f = f
2. Typical values are measured at V
MAX, address and data inputs are cycling at the maximum frequency, f = 0 means no input lines change.
DD=3.3V, TA=25
(1)
(Over Operating Range)
-8 ns -10 ns
(2)
typ.
(2)
o
C. Not 100% Tested.
—75 —70
— 0.05 — 0.05
CAPACITANCE
(1)
Symbol Parameter Conditions Max. Unit
CIN Input Capacitance VIN = 0V 6 pF
COUT Input/Output Capacitance VOUT = 0V 8 pF
Note:
1. Tested initially and after any design or process changes that may affect these parameters.
4
Integrated Silicon Solution, Inc.
Rev. I
11/22/05
IS61LV6416
IS61LV6416L
AC TEST CONDITIONS
Parameter Unit
Input Pulse Level 0V to 3.0V
Input Rise and Fall Times 3 ns
Input and Output Timing 1.5V
and Reference Level
Output Load See Figures 1a and 1b
AC TEST LOADS
®
ISSI
1
2
3
319 Ω
3.3V
OUTPUT
30 pF
Including
jig and
scope
Figure 1a. Figure 1b.
READ CYCLE SWITCHING CHARACTERISTICS
Symbol Parameter Min. Max. Min. Max. Min. Max. Unit
tRC Read Cycle Time 8 — 10 — 12 — ns
tAA Address Access Time — 8 — 10 — 12 ns
tOHA Output Hold Time 3 — 3 — 3 — n s
tACE CE Access Time — 8 — 10 — 12 n s
tDOE OE Access Time — 5 — 5 — 6 ns
(2)
tHZOE
tLZOE
tHZCE
tLZCE
tBA LB, UB Access Time — 6 — 6 — 6 ns
tHZB LB, UB to High-Z Output 0 4 0 5 0 6 ns
OE to High-Z Output — 5 — 5 — 6 ns
(2)
OE to Low-Z Output 0 — 0 — 0 — n s
(2
CE to High-Z Output 0 4 0 5 0 6 ns
(2)
CE to Low-Z Output 3 — 3 — 3 — n s
353 Ω
(1)
(Over Operating Range)
-8 ns -10 ns -12 ns
3.3V
OUTPUT
Including
319 Ω
5 pF
jig and
scope
353 Ω
4
5
6
7
8
9
10
11
tLZB LB, UB to Low-Z Output 0 — 0 — 0 — n s
Notes:
1. Test conditions assume signal transition times of 3 ns or less, timing reference levels of 1.5V, input pulse levels of 0 to 3.0V and
output loading specified in Figure 1a.
2. Tested with the load in Figure 1b. Transition is measured ±500 mV from steady-state voltage. Not 100% tested.
3. Not 100% tested.
Integrated Silicon Solution, Inc.
Rev. I
11/22/05
12
5
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