INTEGRAL IW4021BN, IW4021BDW Datasheet
8-Bit Shift Register
High-Voltage Silicon-Gate CMOS
The IW4021B is an Edge-Triggered 8-Bit Shift Register (Parallelto-Serial Converter) with a synchronous Serial Data Input (D
Clock Input (CP), an asynchronous active HIGH Parallel Load Input
(PL), eight asynchronous Parallel Data Inputs (P
Parallel Outputs from the last three stages (Q
5-Q7
) and Buffered
0-P7
).
Information on the Parallel Data Inputs (P0-P7) is asynchronously
loaded into the register while the Parallel Load Input (PL) is HIGH,
independent of the Clock (CP) and Serial Data (D
) inputs. Data
S
present in the register is stored on the HIGH-to-LOW transition of the
Parallel Load Input (PL).
When the Parallel Load Input is LOW, data on the Serial Data
Input (D
) is shifted into the first register position and all the data in
S
the register is shifted one position to the right on the LOW-to-HIGH
transition of the Clock Input (CP).
•
Operating Voltage Range: 3.0 to 18 V
•
Maximum input current of 1 µA at 18 V over full package-
temperature range; 100 nA at 18 V and 25°C
•
Noise margin (over full package temperature range):
1.0 V min @ 5.0 V supply
2.0 V min @ 10.0 V supply
2.5 V min @ 15.0 V supply
), a
S
TECHNICAL DATA
IW4021B
ORDERING INFORMATION
IW4021BN Plastic
IW4021BDW SOIC
TA = -55° to 125° C for all packages
PIN ASSIGNMENT
LOGIC DIAGRAM
PIN 16 =V
PIN 8 = GND
CC
FUNCTION TABLE
SERIAL OPERATION:
tCPD
S
PL
Q
t=n+6
n000
n+1 1 0 1 0
n+2 0 0 0 1 0
n+3 1 0 1 0 1
X0 Q5Q
PARALLEL OPERATION:
CP D
PL P5P6P7Q5Q6Q
S
X X 1 DDDDDD
X = don’t care
D = 1 or 0
Q
5
6
t=n+7
6
t=n+8
Q
7
Q
7
7
1
IW4021B
MAXIMUM RATINGS
*
Symbol Parameter Value Unit
V
CC
V
V
OUT
I
IN
P
P
DC Supply Voltage (Referenced to GND) -0.5 to +20 V
DC Input Voltage (Referenced to GND) -0.5 to VCC +0.5 V
IN
DC Output Voltage (Referenced to GND) -0.5 to VCC +0.5 V
DC Input Current, per Pin
Power Dissipation in Still Air, Plastic DIP+
D
SOIC Package+
Power Dissipation per Output Transistor 100 mW
D
±
10
750
500
Tstg Storage Temperature -65 to +150
T
Lead Temperature, 1 mm from Case for 10 Seconds
L
260
(Plastic DIP or SOIC Package)
*
Maximum Ratings are those values beyond which damage to the device may occur.
Functional operation should be restricted to the Recommended Operating Conditions.
+Derating - Plastic DIP: - 10 mW/°C from 65° to 125°C
SOIC Package: : - 7 mW/°C from 65° to 125°C
RECOMMENDED OPERATING CONDITIONS
Symbol Parameter Min Max Unit
V
VIN, V
T
CC
A
DC Supply Voltage (Referenced to GND) 3.0 18 V
DC Input Voltage, Output Voltage (Referenced to GND) 0 V
OUT
Operating Temperature, All Package Types -55 +125
CC
mA
mW
°
C
°
C
V
°
C
This device c ontains p rote ction ci rcuitr y to guard a gainst damage d ue to high st atic voltages or electr ic
fields. However, precautions must be taken to avoid applications of any voltage higher than maximum rated
voltages to this high-impedance circuit. For proper operation, V
GND≤(V
IN
or V
OUT
)≤VCC.
Unused inputs must always be tied to an appropriate logic voltage level (e.g., either GND or V
and V
IN
should be constrained to the range
OUT
CC
Unused outputs must be left open.
2
).
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