TB-FMCH-HDMI2 Hardware User Manual
1
Rev.1.05
TB-FMCH-HDMI2
Hardware User Manual
Rev.1.05
TB-FMCH-HDMI2 Hardware User Manual
2
Rev.1.05
Revision History
Version
Date
Description
Publisher
Rev.1.00
2011/02/01
Initial release
Yoshioka
Rev.1.01
2011/03/29
Modified Figure4-2, 4-3, 5-2, 5-3
Yoshioka
Rev.1.02
2012/10/18
Add Table5-6
Yanagisawa
Rev.1.03
2014/04/15
Add EC Declaration of Conformity
Amano
Rev.1.04
2014/08/13
Modify Table 5-7
Amano
Rev.1.05
2017/05/10
Modify Table 4-7
Goto
TB-FMCH-HDMI2 Hardware User Manual
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Table of Contents
1. Related Documents and Board Accessories ............................................................................... 8
2. Overview ...................................................................................................................................... 8
3. Feature ........................................................................................................................................ 9
4. TB-FMCH-HDMI2-RX ................................................................................................................ 10
4.1. Block Diagram ......................................................................................................................... 10
4.2. External View of the Board ....................................................................................................... 11
4.3. Board Specification .................................................................................................................. 12
4.4. Supplying Power to the Board ................................................................................................. 13
4.5. HDMI Receiver ........................................................................................................................ 14
4.6. FMC Connector ....................................................................................................................... 15
4.7. Other Interfaces ....................................................................................................................... 18
4.7.1. EEPROM Interface .......................................................................................................... 18
4.7.2. JTAG Interface ................................................................................................................. 18
4.7.3. General-Purpose Clock Interface .................................................................................... 18
4.8. LED Status ............................................................................................................................... 19
4.9. Control Function ...................................................................................................................... 19
4.10. FPGA Pin Assignment ......................................................................................................... 20
4.11. FPGA Output Data Phase ....................................................................................................... 27
4.12. Image Size ........................................................................................................................... 28
4.12.1. 2D Image Size ................................................................................................................. 28
4.12.2. 3D Image Size ................................................................................................................. 28
5. TB-FMCH-HDMI2-TX ................................................................................................................ 29
5.1. Block Diagram ......................................................................................................................... 29
5.2. External View of the Board ...................................................................................................... 30
5.3. Board Specification .................................................................................................................. 31
5.4. Power Supply to the Board ...................................................................................................... 32
5.5. HDMI Transmitter .................................................................................................................... 33
5.6. FMC Connector ....................................................................................................................... 34
5.7. Other Interfaces ....................................................................................................................... 37
5.7.1. JTAG Interface ................................................................................................................. 37
5.7.2. General-Purpose Clock Interface .................................................................................... 37
5.8. LED Status ............................................................................................................................... 38
5.9. Relation of ROM and Input Video Format ............................................................................... 38
5.10. Control Function .................................................................................................................. 39
5.11. FPGA Pin Assignment ............................................................................................................. 40
5.12. FPGA Input Data Phase ...................................................................................................... 47
5.13. Image Size ........................................................................................................................... 48
5.13.1. 2D Image Size ................................................................................................................. 48
5.13.2. 3D Image Size ................................................................................................................. 48
6. DDC Connection (Normal/ Through) ......................................................................................... 49
6.1. DDC Connection (Normal) ....................................................................................................... 49
6.2. DDC Connection (Through) ..................................................................................................... 50
7. Default Switch Setting ............................................................................................................... 51
8. Usage Example ......................................................................................................................... 55
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List of Figures
Figure 3-1 FMC Connector Pin Layout .............................................................................................. 9
Figure 4-1 TB-FMCH-HDMI2-RX Block Diagram............................................................................. 10
Figure 4-2 External View of TB-FMCH-HDMI2-RX (component side) .............................................. 11
Figure 4-3 External View of TB-FMCH-HDMI2-RX (solder side) ...................................................... 11
Figure 4-4 TB-FMCH-HDMI2-RX Board Dimensions ...................................................................... 12
Figure 4-5 TB-FMCH-HDMI2-RX Power Supply Structure .............................................................. 13
Figure 4-6 FPGA Output Data Timing .............................................................................................. 27
Figure 5-1 TB-FMCH-HDMI2-TX Block Diagram ............................................................................. 29
Figure 5-2 TB-FMCH-HDMI2-TX (component side) ........................................................................ 30
Figure 5-3 TB-FMCH-HDMI2-TX (solder side) ................................................................................. 30
Figure 5-4 TB-FMCH-HDMI2-TX Board Dimensions ....................................................................... 31
Figure 5-5 TB-FMCH-HDMI2-TX Power Supply Structure ............................................................... 32
Figure 5-6 FPGA Input Data Timing ................................................................................................. 47
Figure 6-1 DDC Connection Structure (Normal) .............................................................................. 49
Figure 6-2 DDC Connection Structure (Through) ............................................................................ 50
Figure 7-1 TB-FMCH-HDMI2-RX Default Switch Settings (component side) .................................. 51
Figure 7-2 TB-FMCH-HDMI2-TX Default Settings (component side) .............................................. 53
Figure 8-1 Usage Example .............................................................................................................. 55
List of Tables
Table 2-1 ROM data ........................................................................................................................... 8
Table 4-1 HDMI Connector (receiving side) ..................................................................................... 14
Table 4-2 SCL/SDA Jumper Setting ................................................................................................. 14
Table 4-3 JP1 Jumper Setting .......................................................................................................... 15
Table 4-4 FMC Connector Pin Assignment ...................................................................................... 16
Table 4-5 JTAG Connector ............................................................................................................... 18
Table 4-6 LED Status ........................................................................................................................ 19
Table 4-7 Switches ........................................................................................................................... 19
Table 4-8 FPGA Pin Assignment ...................................................................................................... 20
Table 5-1 HDMI Connector (transmit side) ....................................................................................... 33
Table 5-2 JP3 Jumper Setting .......................................................................................................... 34
Table 5-3 FMC Connector Pin Assignment ...................................................................................... 35
Table 5-4 JTAG Connector ............................................................................................................... 37
Table 5-5 LED Status ........................................................................................................................ 38
Table 5-6 Relation of ROM and Input Video Format ........................................................................ 38
Table 5-7 Switch Function ................................................................................................................ 39
Table 5-8 FPGA Pin Assignment ...................................................................................................... 40
Table 6-1 DDC Jumper Setting (Normal) ......................................................................................... 49
Table 6-2 DDC Jumper Setting (Through)........................................................................................ 50
Table 7-1 TB-FMCH-HDMI2-RX Default Settings (JP pin) ............................................................... 51
Table 7-2 TB-FMCH-HDMI2-RX Default Setting (DSW/RSW) ......................................................... 52
Table 7-3 TB-FMCH2-TX Default Settings (JP Pin) ......................................................................... 53
Table 7-4 TB-FMCH-HDMI2-TX Default Switch Settings (DSW/RSW)............................................ 54
Table 8-1 Setting Example ............................................................................................................... 55
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Introduction
Thank you for purchasing the TB-FMCH-HDMI2－RX/TB-FMCH-HDMI2-TX boards. Before using the
product, be sure to carefully read this user manual and fully understand how to correctly use the product.
First read through this manual, then always keep it handy.
SAFETY PRECAUTIONS Be sure to observe these precautions
Observe the precautions listed below to prevent injuries to you or other personnel or damage to property.
Before using the product, read these safety precautions carefully to assure correct use.
These precautions contain serious safety instructions that must be observed.
After reading through this manual, be sure to always keep it handy.
The following conventions are used to indicate the possibility of injury/damage and classify precautions if
the product is handled incorrectly.
Indicates the high possibility of serious injury or death if the product is handled
incorrectly.
Indicates the possibility of serious injury or death if the product is handled
incorrectly.
Indicates the possibility of injury or physical damage in connection with houses or
household goods if the product is handled incorrectly.
The following graphical symbols are used to indicate and classify precautions in this manual.
(Examples)
Turn off the power switch.
Do not disassemble the product.
Do not attempt this.
Danger
Warning
Caution
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In the event of a failure, disconnect the power supply.
If the product is used as is, a fire or electric shock may occur. Disconnect the power supply
immediately and contact our sales personnel for repair.
If an unpleasant smell or smoking occurs, disconnect the power supply.
If the product is used as is, a fire or electric shock may occur. Disconnect the power supply
immediately. After verifying that no smoking is observed, contact our sales personnel for
repair.
Do not disassemble, repair or modify the product.
Otherwise, a fire or electric shock may occur due to a short circuit or heat generation. For
inspection, modification or repair, contact our sales personnel.
Do not touch a cooling fan.
As a cooling fan rotates in high speed, do not put your hand close to it. Otherwise, it may
cause injury to persons. Never touch a rotating cooling fan.
Do not place the product on unstable locations.
Otherwise, it may drop or fall, resulting in injury to persons or failure.
If the product is dropped or damaged, do not use it as is.
Otherwise, a fire or electric shock may occur.
Do not touch the product with a metallic object.
Otherwise, a fire or electric shock may occur.
Do not place the product in dusty or humid locations or where water may
splash.
Otherwise, a fire or electric shock may occur.
Do not get the product wet or touch it with a wet hand.
Otherwise, the product may break down or it may cause a fire, smoking or electric shock.
Do not touch a connector on the product (gold-plated portion).
Otherwise, the surface of a connector may be contaminated with sweat or skin oil, resulting
in contact failure of a connector or it may cause a malfunction, fire or electric shock due to
static electricity.
Warning
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Do not use or place the product in the following locations.
Humid and dusty locations
Airless locations such as closet or bookshelf
Locations which receive oily smoke or steam
Locations exposed to direct sunlight
Locations close to heating equipment
Closed inside of a car where the temperature becomes high
Staticky locations
Locations close to water or chemicals
Otherwise, a fire, electric shock, accident or deformation may occur due to a short circuit or heat
generation.
Do not place heavy things on the product.
Otherwise, the product may be damaged.
■ Disclaimer
This product is HDMI interface for Xilinx FPGA evaluation boards. Tokyo Electron Device Limited
assumes no responsibility for any damages resulting from the use of this product for purposes other than
those stated.
Even if the product is used properly, Tokyo Electron Device Limited assumes no responsibility for any
damages caused by:
(1) Earthquake, thunder, natural disaster or fire resulting from the use beyond our responsibility, acts by
a third party or other accidents, the customer’s willful or accidental misuse or use under other
abnormal conditions.
(2) Secondary impact arising from use of this product or its unusable state (business interruption or
others)
(3) Use of this product against the instructions given in this manual.
(4) Malfunctions due to connection to other devices.
Tokyo Electron Device Limited assumes no responsibility or liability for:
(1) Erasure or corruption of data arising from use of this product.
(2) Any consequences or other abnormalities arising from use of this product, or
(3) Damage of this product not due to our responsibility or failure due to modification
This product has been developed by assuming its use for research, testing or evaluation. It is not
authorized for use in any system or application that requires high reliability.
Repair of this product is carried out by replacing it on a chargeable basis, not repairing the faulty devices.
However, non-chargeable replacement is offered for initial failure if such notification is received within
two weeks after delivery of the product.
The specification of this product is subject to change without prior notice.
The product is subject to discontinuation without prior notice.
Caution
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1. Related Documents and Board Accessories
All documents relating to this board can be downloaded from our website Club-X.
Accessories:
Interboard spacers and screws
Interboard jumper cable
2. Overview
The TB-FMCH-HDMI2 comes either with AnalogDevices’s HDMI Receiver "ADV7612BSWZ-P" or
HDMI Transmitter "ADV7511KSTZ-P".
(Collectively, there are called TB-FMCH-HDMI2. This document specifically describes these
optional boards in the RX and TX sections respectively).
Each board has two independent receivers/transmitters and is designed for high resolution
support.
It uses Samtec’s FMC connector and Molex’s HDMI connector for connection with a platform board
having High-Pin Count connectors.
This User Manual is refer to Initial ROM files.
TB-FMCH-HDMI2 boards need to download following ROM files.
Table 2-1 ROM data
No
Board name
FPGA ROM data
1
TB-FMCH-HDMI2-RX
rx_fpga_top.mcs
2
TB-FMCH-HDMI2-TX
tx_fpga_top.mcs
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3. Feature
HDMI Devices
Receiver : AnalogDevices’s ADV7612BSWZ-P
Transmitter : AnalogDevices’s ADV7511KSTZ-P
FMC Connector : Samtec’s ASP-134488-01
HDMI Connector (common) : Molex’s 5002541927
Power Supply (common) : Jumper switch selection
The RX board has an EEPROM for Display Data Channel (hereafter referred to as DDC) and allows
setting the AnalogDevices’s ADV7612BSWZ-P board operation via jumpers.
Figure 3-1 FMC Connector Pin Layout
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4. TB-FMCH-HDMI2-RX
4.1. Block Diagram
Figure 4-1 shows the TB-FMCH-HDMI2-RX block diagram.
The FMC-HPC connector is mounted on the solder side of the board.
XC6SLX45-3FGG484C
FPGAFMC-HPC
DEC#0
500254-1927
HDMI#0（RX)
ADV7612
RX#0_C、RX#0_0～2
RX#0_P[35:0]
RX#0_VS/HS/DE
RX#0_LLC
RX#0_DDCA_SCL
CEC#0
DET0
HPD#0
28.6363MHz
RX#0_SPDIF
RX#0_I2S[3:0]
RX#0_SCLK
RX#0_LRCLK
RX#0_MCLKOUT
RX#0_SCL
RX#0_INT1/CSN
RX#0_RESETN
PROM
ASP-134488-01
XCF16PFSG48C
LA[33:00]_P/N
HA[23:00]_P/N
CLK[3:0]_M2C_P/N
FPGA_D[7:0]
FPGA_DONE
FPGA_INITB
FPGA_PROGB
FPGA_CCLK
FPGA_TCK/TMS/TDI/TDO
EEPROM#0
24LCS22A
CLK
SYSCLK_P
RX#0_SDA
RX#0_DDCA_SDA
LED[7:0]
DSW[7:0]
RSW[3:0]
JTAG
87832-1420
KC5032C27.000
RX#0_HPD_IO
DDC0_GND
DDC0
DDC0_HPD
DDC0_5V
DDC0_SDA
RX#0_CEC
RX#0_DDCA_SDA_F
RX#0_DDCA_SCL_F
RX#0_DET1
DDC0_SCL
DDC_GND0
DEC#1
500254-1927
HDMI#1（RX)
ADV7612
RX#1_C、RX#1_0～2
RX#1_P[35:0]
RX#1_VS/HS/DE
RX#1_LLC
RX#1_DDCA_SCL
CEC#1
DET1
HPD#1
28.6363MHz
RX#1_SPDIF
RX#1_I2S[3:0]
RX#1_SCLK
RX#1_LRCLK
RX#1_MCLKOUT
RX#1_SCL
RX#1_INT1/CSN
RX#1_RESETN
EEPROM#1
24LCS22A
RX#1_SDA
RX#1_DDCA_SDA
RX#1_HPD_IO
DDC1_GND
DDC1
DDC1_HPD
DDC1_5V
DDC1_SDA
RX#1_CEC
RX#1_DDCA_SDA_F
RX#1_DDCA_SCL_F
RX#1_DET1
DDC1_SCL
DDC_GND1
Figure 4-1 TB-FMCH-HDMI2-RX Block Diagram
Main Functions:
1. HDMI receive function (ADV7612 => FPGA)
2. FMC connector interface (FPGA => FMC-HPC connector)
3. EEPROM interface
4. JTAG interface
5. General-purpose clock interface (27MHz)
6. General-purpose switch
7. General-purpose LED
8. DDC connection (Normal/ Through)
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4.2. External View of the Board
Figures 4-2 and 4-3 show the external view of the TB-FMCH-HDMI2-RX board.
Caution : This board has a plastic cover for protecting HDMI devices. Do not remove a plastic cover.
HDMI ConnectorHDMI ReceiverFPGA
Figure 4-2 External View of TB-FMCH-HDMI2-RX (component side)
FMC-HPC
Figure 4-3 External View of TB-FMCH-HDMI2-RX (solder side)
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4.3. Board Specification
The following shows TB-FMCH-HDMI2-RX board specifications.
External Dimensions : W:160mm x H:69mm
Number of Layers : 8 layers
Board Thickness : 1.6 mm
Material : FR-4
FPGA : Xilinx’s XC6SLX45-3FGG484C
FMC Connector : Samtec’s ASP-134488-01
HDMI Connector : Molex’s 5002541927
Figure 4-4 TB-FMCH-HDMI2-RX Board Dimensions
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4.4. Supplying Power to the Board
Figure 4-5 shows a TB-FMCH-HDMI2-RX power supply structure.
VCC_12V_IN VCC_5V
LT3503EDCB
VCC_1.8V0
LTC3026EMSE
VCC_1.8V1
LTC3026EMSE
ADV7612 : 449.7mA
VCC_3.3V
FPGA_VCAUX : 50mA FPGA_VCCIO : 29mA
ADV7612 : 312.5mA x2 = 625mA
1170mA
KC3225A: 6mA
NC7SZ125: 0.02mA x2 = 0.04mA
24LCS22A: 3mA x2 = 6mA
LTC1326: 0.04mA
135mA
VCC_2.5V
（2.926W）
750mA
(2.475W)
（0.677W）
562mA
LT3503EDCB
LT3568EDD
FPGA_VCCINT : 485mA
VCC_1.2V
FPGA_VCCIO : 261mA
XCF16 VCCINT : 10mA
ADV7612 : 449.7mA
XCF16 VCCIO : 40mA
LT3503EDCB
Figure 4-5 TB-FMCH-HDMI2-RX Power Supply Structure
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4.5. HDMI Receiver
HDMI Connector uses a 5002541927 (MOLEX).
HDMI Receiver uses an ADV7612BSWZ-P (Analog Devices).
The following device is used as ESD protection.
ESD protection: RCLAMP0524 and RCLAMP0504 (Semtech)
Table 4-1 shows the HDMI connector pin assignments.
Table 4-1 HDMI Connector (receiving side)
Pin #
Name
Description
1
TMDS DATA2+
TMDS receive data 2+
2
TMDS SHLD2
TMDS receive data 2 shield
3
TMDS DATA2-
TMDS receive data 2-
4
TMDS DATA1+
TMDS receive data 1+
5
TMDS SHLD1
TMDS receive data 1 shield
6
TMDS DATA1-
TMDS receive data 1-
7
TMDS DATA0+
TMDS receive data 0+
8
TMDS SHLD0
TMDS receive data 0 shield
9
TMDS DATA0-
TMDS receive data 0-
10
TMDS CLK+
TMDS receive clock+
11
TMDS CLK SHLD
TMDS receive clock shield
12
TMDS CLK-
TMDS receive clock-
13
CEC
CEC signal
14
RESERVED
Reserved
15
DDC_SCL
DDC serial clock
16
DDC_SDA
DDC serial data
17
DDC/CEC GND
DDC/CEC ground
18
DDC_+5V
+5V power supply
19
HOTPLUG_DET
Hot-plug detection
The receiver has an EEPROM (24LCS22A-SN: Micro Chip).
This EEPROM is used to store EDID data. The SCL signal can be switched by JP6/JP3 and the SDA
signal using JP7/JP4.
Note: At factory default settings, the EEPROM stores temporary data to enable output of image data
from an image output device. The ID used in the data is a dummy ID for evaluation purposes.
So, do not use it for actual products.
Table 4-2 SCL/SDA Jumper Setting
No
Purpose
Silk
Setting
1
DDC connection
(Normal)
JP6: SCL0, JP7: SDA0
JP3: SCL1,JP4: SDA1
JP6: 1-2 short JP7: 1-2 short
JP3: 1-2 short JP4: 1-2 short
2
DDC
connection(Through)
JP6: SCL0, JP7: SDA0
JP3: SCL1,JP4: SDA1
JP6: 2-3 short JP7: 2-3 short
JP3: 2-3 short JP4: 2-3 short
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4.6. FMC Connector
The FMC connector (High-Pin Count) connecting to the main board uses an ASP-134488-01 (SAMTEC).
Power to the TB-FMCH-HDMI2-RX is supplied from a +12V on the main board.
An external power source can also be used.
Table 4-3 shows JP1 jumper setting for power supply.
Table 4-3 JP1 Jumper Setting
No
Purpose
Silk
Setting
1
FMC connector
12VIN_SEL
JP1: 1-2 short
2
External power supply
12VIN_SEL
JP1: 2-3 short
To connect an external power source, use the following test pin:
TP14: 12VIN
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Table 4-4 shows the FMC connector pin assignment.
Table 4-4 FMC Connector Pin Assignment
Pin
A-row
B-row
C-row
D-row
E-row
1
GND
RES1
GND
PG_C2M
GND
2
DP1_M2C_P
GND
DP0_C2M_P
GND
HA01_P_CC
3
DP1_M2C_N
GND
DP0_C2M_N
GND
HA01_N_CC
4
GND
DP9_M2C_P
GND
GBTCLK0_M2C_P
GND
5
GND
DP9_M2C_N
GND
GBTCLK0_M2C_N
GND
6
DP2_M2C_P
GND
DP0_M2C_P
GND
HA05_P
7
DP2_M2C_N
GND
DP0_M2C_N
GND
HA05_N
8
GND
DP8_M2C_P
GND
LA01_P_CC
GND
9
GND
DP8_M2C_N
GND
LA01_N_CC
HA09_P
10
DP3_M2C_P
GND
LA06_P
GND
HA09_N
11
DP3_M2C_N
GND
LA06_N
LA05_P
GND
12
GND
DP7_M2C_P
GND
LA05_N
HA13_P
13
GND
DP7_M2C_N
GND
GND
HA13_N
14
DP4_M2C_P
GND
LA10_P
LA09_P
GND
15
DP4_M2C_N
GND
LA10_N
LA09_N
HA16_P
16
GND
DP6_M2C_P
GND
GND
HA16_N
17
GND
DP6_M2C_N
GND
LA13_P
GND
18
DP5_M2C_P
GND
LA14_P
LA13_N
HA20_P
19
DP5_M2C_N
GND
LA14_N
GND
HA20_N
20
GND
GBTCLK1_M2C_P
GND
LA17_P_CC
GND
21
GND
GBTCLK1_M2C_N
GND
LA17_N_CC
HB03_P
22
DP1_C2M_P
GND
LA18_P_CC
GND
HB03_N
23
DP1_C2M_N
GND
LA18_N_CC
LA23_P
GND
24
GND
DP2_C9M_P
GND
LA23_N
HB05_P
25
GND
DP2_C9M_N
GND
GND
HB05_N
26
DP2_C2M_P
GND
LA27_P
LA26_P
GND
27
DP2_C2M_N
GND
LA27_N
LA26_N
HB09_P
28
GND
DP2_C8M_P
GND
GND
HB09_N
29
GND
DP2_C8M_N
GND
TCK
GND
30
DP3_C2M_P
GND
SCL
TDI
HB13_P
31
DP3_C2M_N
GND
SDA
TDO
HB13_N
32
GND
DP2_C7M_P
GND
+3.3VAUX
GND
33
GND
DP2_C7M_N
GND
TMS
HB19_P
34
DP4_C2M_P
GND
GA0
TRST
HB19_N
35
DP4_C2M_N
GND
+12V
GA1
GND
36
GND
DP2_C6M_P
GND
+3.3V
HB21_P
37
GND
DP2_C6M_N
+12V
GND
HB21_N
38
DP5_C2M_P
GND
GND
+3.3V
GND
39
DP5_C2M_N
GND
+3.3V
GND
VADJ
40
GND
RES0
GND
+3.3V
GND
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Pin
F-row
G-row
H-row
J-row
K-row
1
PG_M2C
GND
VREF_A_M2C
GND
VREF_B_M2C
2
GND
CLK1_M2C_P
PRSNT_M2C_L
CLK3_M2C_P
GND
3
GND
CLK1_M2C_N
GND
CLK3_M2C_N
GND
4
HA00_P_CC
GND
CLK0_M2C_P
GND
CLK2_M2C_P
5
HA00_N_CC
GND
CLK0_M2C_N
GND
CLK2_M2C_N
6
GND
LA00_P_CC
GND
HA03_P
GND
7
GND
LA00_N_CC
LA02_P
HA03_N
HA02_P
8
HA04_P
GND
LA02_N
GND
HA02_N
9
HA04_N
LA03_P
GND
HA07_P
GND
10
GND
LA03_N
LA04_P
HA07_N
HA06_P
11
HA08_P
GND
LA04_N
GND
HA06_N
12
HA08_N
LA08_P
GND
HA11_P
GND
13
GND
LA08_N
LA07_P
HA11_N
HA10_P
14
HA12_P
GND
LA07_N
GND
HA10_N
15
HA12_N
LA12_P
GND
HA14_P
GND
16
GND
LA12_N
LA11_P
HA14_N
HA17_P_CC
17
HA15_P
GND
LA11_N
GND
HA17_N_CC
18
HA15_N
LA16_P
GND
HA18_P
GND
19
GND
LA16_N
LA15_P
HA18_N
HA21_P
20
HA19_P
GND
LA15_N
GND
HA21_N
21
HA19_N
LA20_P
GND
HA22_P
GND
22
GND
LA20_N
LA19_P
HA22_N
HA23_P
23
HB02_P
GND
LA19_N
GND
HA23_N
24
HB02_N
LA22_P
GND
HB01_P
GND
25
GND
LA22_N
LA21_P
HB01_N
HB00_P_CC
26
HB04_P
GND
LA21_N
GND
HB00_N_CC
27
HB04_N
LA25_P
GND
HB07_P
GND
28
GND
LA25_N
LA24_P
HB07_N
HB06_P_CC
29
HB08_P
GND
LA24_N
GND
HB06_N_CC
30
HB08_N
LA29_P
GND
HB11_P
GND
31
GND
LA29_N
LA28_P
HB11_N
HB10_P
32
HB12_P
GND
LA28_N
GND
HB10_N
33
HB12_N
LA31_P
GND
HB15_P
GND
34
GND
LA31_N
LA30_P
HB15_N
HB14_P
35
HB16_P
GND
LA30_N
GND
HB14_N
36
HB16_N
LA33_P
GND
HB18_P
GND
37
GND
LA33_N
LA32_P
HB18_N
HB17_P_CC
38
HB20_P
GND
LA32_N
GND
HB17_N_CC
39
HB20_N
VADJ
GND
VIO_B_M2C
GND
40
VADJ
GND
VADJ
GND
VIO_B_M2C
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Rev.1.05
4.7. Other Interfaces
The board also has the following interfaces.
4.7.1. EEPROM Interface
I2C interface used to control the EEPROM from the FPGA
EEPROM device: 24LCS22A-SN (Micro Chip)
4.7.2. JTAG Interface
JTAG connector for FPGA configuration
JTAG connector: 87832-1420 (Molex)
Table 4-5 JTAG Connector
Pin
Signal
Pin
Signal
1
GND
2
3.3V
3
GND
4
TMS
5
GND
6
TCK
7
GND
8
TDO
9
GND
10
TDI
11
GND
12
NC
13
GND
14
NC
4.7.3. General-Purpose Clock Interface
General-purpose clock for FPGA (27MHz crystal oscillator)
KC5032C027.0000C30E00 (Kyocera)
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19
Rev.1.05
4.8. LED Status
Table 4-6 shows the onboard LEDs.
Table 4-6 LED Status
No
Circuit #
Silk
Purpose
Description
1
DS1
LED0
General-purpose LED0
[RX0]I2C config state
Off: CFG done / On: CFG active
2
DS2
LED1
General-purposeLED1
[RX0]I2C read back
Off: Error / On: No error
3
DS3
LED2
General-purposeLED2
[RX1]I2C config state
Off: CFG done / On: CFG active
4
DS4
LED3
General-purposeLED3
[RX1]I2C read back
Off: Error / On: No error
5
DS5
LED4
General-purposeLED4
Unused (On)
6
DS6
LED5
General-purposeLED5
[RX0] Input video image clock monitor
Flashing: Clock / Off: No clock
7
DS7
LED6
General-purposeLED6
[RX1] Input video image clock monitor
Flashing: Clock / Off: No clock
8
DS8
LED7
General-purposeLED7
System reset monitor
On: Reset active / Off: Reset released
9
DS10
HPD0
RX0 hot-plug display
On: Connected state
10
DS9
HPD1
RX1 hot-plug display
On: Connected state
11
DS11
DONE
Config display
On: Config done
12
DS12
12VLED
12V display
On: 12V active
4.9. Control Function
Table 4-7 shows the onboard switch function.
Table 4-7 Switches
No
Circuit #
Silk
Function
1
S1-1
DSW
ADV7612 config ROM selection
*Should set all On
2
S1-2
DSW
3
S1-3
DSW
4
S1-4
DSW
5
S1-5
DSW
On 6 S1-6
DSW
Unused
7
S1-7
DSW
Unused
8
S1-8
DSW
Unused
9
S2
RSW
Unused
10
S3
RST
FPGA reconfig (long push: 3 seconds)
FPGA reset (short push)
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Rev.1.05
4.10. FPGA Pin Assignment
Table 4-8 shows the FPGA pin assignment.
In case of 8-bit signal format, active bits are assigned to MSB 8-bit of each RGB pin of FMC. LSB 2-bit
are always 2'b00 in 8-bit signal format.
Table 4-8 FPGA Pin Assignment
Pin Name
No.
IO
Spec
Description
CLK0_M2C_P
B10
O
LVCMOS25
RX#0_LLC signal (FPGA to FMC)
CLK1_M2C_P
C11
O
LVCMOS25
RX#1_LLC signal (FPGA to FMC)
LA00_P_CC
D6 O LVCMOS25
RX#0_VSYNC signal (FPGA to FMC)
LA01_P_CC
C7 O LVCMOS25
RX#0_HSYNC signal (FPGA to FMC)
LA02_P
D9 O LVCMOS25
RX#0_DE signal (FPGA to FMC)
LA03_P
D7 O LVCMOS25
RX#0_P0 signal (FPGA to FMC) [B0]
LA04_P
C13
O
LVCMOS25
RX#0_P1 signal (FPGA to FMC) [B1]
LA05_P
B14
O
LVCMOS25
RX#0_P2 signal (FPGA to FMC) [B2]
LA06_P
D15
O
LVCMOS25
RX#0_P3 signal (FPGA to FMC) [B3]
LA07_P
C17
O
LVCMOS25
RX#0_P4 signal (FPGA to FMC) [B4]
LA08_P
E16
O
LVCMOS25
RX#0_P5 signal (FPGA to FMC) [B5]
LA09_P
G16
O
LVCMOS25
RX#0_P6 signal (FPGA to FMC) [B6]
LA10_P
B21
O
LVCMOS25
RX#0_P7 signal (FPGA to FMC) [B7]
LA11_P
K16
O
LVCMOS25
RX#0_P8 signal (FPGA to FMC) [B8]
LA12_P
D19
O
LVCMOS25
RX#0_P9 signal (FPGA to FMC) [B9]
LA13_P
D21
O
LVCMOS25
RX#0_P10 signal (FPGA to FMC) [G0]
LA14_P
G19
O
LVCMOS25
RX#0_P11 signal (FPGA to FMC) [G1]
LA15_P
E20
O
LVCMOS25
RX#0_P12 signal (FPGA to FMC) [G2]
LA16_P
F21
O
LVCMOS25
RX#0_P13 signal (FPGA to FMC) [G3]
LA17_P_CC
G20
O
LVCMOS25
RX#0_P14 signal (FPGA to FMC) [G4]
LA18_P_CC
H21
O
LVCMOS25
RX#0_P15 signal (FPGA to FMC) [G5]
LA19_P
J20
O
LVCMOS25
RX#0_P16 signal (FPGA to FMC) [G6]
LA20_P
L20
O
LVCMOS25
RX#0_P17 signal (FPGA to FMC) [G7]
LA21_P
N20
O
LVCMOS25
RX#0_P18 signal (FPGA to FMC) [G8]
LA22_P
R20
O
LVCMOS25
RX#0_P19 signal (FPGA to FMC) [G9]
LA23_P
U20
O
LVCMOS25
RX#0_P20 signal (FPGA to FMC) [R0]
LA24_P
M19
O
LVCMOS25
RX#0_P21 signal (FPGA to FMC) [R1]
LA25_P
M16
O
LVCMOS25
RX#0_P22 signal (FPGA to FMC) [R2]
LA26_P
P19
O
LVCMOS25
RX#0_P23 signal (FPGA to FMC) [R3]
LA27_P
W20
O
LVCMOS25
RX#0_P24 signal (FPGA to FMC) [R4]
LA28_P
L17
O
LVCMOS25
RX#0_P25 signal (FPGA to FMC) [R5]
LA29_P
U19
O
LVCMOS25
RX#0_P26 signal (FPGA to FMC) [R6]
LA30_P
M17
O
LVCMOS25
RX#0_P27 signal (FPGA to FMC) [R7]
LA31_P
P17
O
LVCMOS25
RX#0_P28 signal (FPGA to FMC) [R8]
LA32_P
P18
O
LVCMOS25
RX#0_P29 signal (FPGA to FMC) [R9]
LA33_P
T19
IO
LVCMOS25
Unused
CLK0_M2C_N
A10
IO
LVCMOS25
Unused
CLK1_M2C_N
A11
IO
LVCMOS25
Unused
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21
Rev.1.05
Pin Name
No.
IO
Spec
Description
LA00_N_CC
C6 O LVCMOS25
RX#1_VSYNC signal (FPGA to FMC)
LA01_N_CC
A7 O LVCMOS25
RX#1_HSYNC signal (FPGA to FMC)
LA02_N
C8 O LVCMOS25
RX#1_DE signal (FPGA to FMC)
LA03_N
D8 O LVCMOS25
RX#1_P0 signal (FPGA to FMC) [B0]
LA04_N
A13
O
LVCMOS25
RX#1_P1 signal (FPGA to FMC) [B1]
LA05_N
A14
O
LVCMOS25
RX#1_P2 signal (FPGA to FMC) [B2]
LA06_N
C16
O
LVCMOS25
RX#1_P3 signal (FPGA to FMC) [B3]
LA07_N
A17
O
LVCMOS25
RX#1_P4 signal (FPGA to FMC) [B4]
LA08_N
D17
O
LVCMOS25
RX#1_P5 signal (FPGA to FMC) [B5]
LA09_N
G17
O
LVCMOS25
RX#1_P6 signal (FPGA to FMC) [B6]
LA10_N
B22
O
LVCMOS25
RX#1_P7 signal (FPGA to FMC) [B7]
LA11_N
J16
O
LVCMOS25
RX#1_P8 signal (FPGA to FMC) [B8]
LA12_N
D20
O
LVCMOS25
RX#1_P9 signal (FPGA to FMC) [B9]
LA13_N
D22
O
LVCMOS25
RX#1_P10 signal (FPGA to FMC) [G0]
LA14_N
F20
O
LVCMOS25
RX#1_P11 signal (FPGA to FMC) [G1]
LA15_N
E22
O
LVCMOS25
RX#1_P12 signal (FPGA to FMC) [G2]
LA16_N
F22
O
LVCMOS25
RX#1_P13 signal (FPGA to FMC) [G3]
LA17_N_CC
G22
O
LVCMOS25
RX#1_P14 signal (FPGA to FMC) [G4]
LA18_N_CC
H22
O
LVCMOS25
RX#1_P15 signal (FPGA to FMC) [G5]
LA19_N
J22
O
LVCMOS25
RX#1_P16 signal (FPGA to FMC) [G6]
LA20_N
L22
O
LVCMOS25
RX#1_P17 signal (FPGA to FMC) [G7]
LA21_N
N22
O
LVCMOS25
RX#1_P18 signal (FPGA to FMC) [G8]
LA22_N
R22
O
LVCMOS25
RX#1_P19 signal (FPGA to FMC) [G9]
LA23_N
U22
O
LVCMOS25
RX#1_P20 signal (FPGA to FMC) [R0]
LA24_N
N19
O
LVCMOS25
RX#1_P21 signal (FPGA to FMC) [R1]
LA25_N
L15
O
LVCMOS25
RX#1_P22 signal (FPGA to FMC) [R2]
LA26_N
P20
O
LVCMOS25
RX#1_P23 signal (FPGA to FMC) [R3]
LA27_N
W22
O
LVCMOS25
RX#1_P24 signal (FPGA to FMC) [R4]
LA28_N
K18
O
LVCMOS25
RX#1_P25 signal (FPGA to FMC) [R5]
LA29_N
V20
O
LVCMOS25
RX#1_P26 signal (FPGA to FMC) [R6]
LA30_N
M18
O
LVCMOS25
RX#1_P27 signal (FPGA to FMC) [R7]
LA31_N
N16
O
LVCMOS25
RX#1_P28 signal (FPGA to FMC) [R8]
LA32_N
R19
O
LVCMOS25
RX#1_P29 signal (FPGA to FMC) [R9]
LA33_N
T20
IO
LVCMOS25
Unused
CLK2_M2C_P
D11
IO
LVCMOS25
Unused
CLK3_M2C_P
B12
IO
LVCMOS25
Unused
HA00_P_CC
B6
IO
LVCMOS25
Unused
HA01_P_CC
B8
IO
LVCMOS25
Unused
HA02_P
C9
IO
LVCMOS25
Unused
HA03_P
D10
IO
LVCMOS25
Unused
HA04_P
D14
IO
LVCMOS25
Unused
HA05_P
C15
IO
LVCMOS25
Unused
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22
Rev.1.05
Pin Name
No.
IO
Spec
Description
HA06_P
B16
IO
LVCMOS25
Unused
HA07_P
B18
IO
LVCMOS25
Unused
HA08_P
C19
IO
LVCMOS25
Unused
HA09_P
F16
IO
LVCMOS25
Unused
HA10_P
A20
IO
LVCMOS25
Unused
HA11_P
H16
IO
LVCMOS25
Unused
HA12_P
F18
IO
LVCMOS25
Unused
HA13_P
C20
IO
LVCMOS25
Unused
HA14_P
H19
IO
LVCMOS25
Unused
HA15_P
J17
IO
LVCMOS25
Unused
HA16_P
H20
IO
LVCMOS25
Unused
HA17_P_CC
K20
IO
LVCMOS25
Unused
HA18_P
M20
IO
LVCMOS25
Unused
HA19_P
K21
IO
LVCMOS25
Unused
HA20_P
M21
IO
LVCMOS25
Unused
HA21_P
P21
IO
LVCMOS25
Unused
HA22_P
T21
IO
LVCMOS25
Unused
HA23_P
V21
IO
LVCMOS25
Unused
CLK2_M2C_N
C12
IO
LVCMOS25
Unused
CLK3_M2C_N
A12
IO
LVCMOS25
Unused
HA00_N_CC
A6
IO
LVCMOS25
Unused
HA01_N_CC
A8
IO
LVCMOS25
Unused
HA02_N
A9
IO
LVCMOS25
Unused
HA03_N
C10
IO
LVCMOS25
Unused
HA04_N
C14
IO
LVCMOS25
Unused
HA05_N
A15
IO
LVCMOS25
Unused
HA06_N
A16
IO
LVCMOS25
Unused
HA07_N
A18
IO
LVCMOS25
Unused
HA08_N
B20
IO
LVCMOS25
Unused
HA09_N
F17
IO
LVCMOS25
Unused
HA10_N
A21
IO
LVCMOS25
Unused
HA11_N
H17
IO
LVCMOS25
Unused
HA12_N
F19
IO
LVCMOS25
Unused
HA13_N
C22
IO
LVCMOS25
Unused
HA14_N
H18
IO
LVCMOS25
Unused
HA15_N
K17
IO
LVCMOS25
Unused
HA16_N
J19
IO
LVCMOS25
Unused
HA17_N_CC
K19
IO
LVCMOS25
Unused
HA18_N
L19
IO
LVCMOS25
Unused
HA19_N
K22
IO
LVCMOS25
Unused
HA20_N
M22
IO
LVCMOS25
Unused
HA21_N
P22
IO
LVCMOS25
Unused
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23
Rev.1.05
Pin Name
No.
IO
Spec
Description
HA22_N
T22
IO
LVCMOS25
Unused
HA23_N
V22
IO
LVCMOS25
Unused
RX#0_P35
T18
I
LVCMOS33
RX#0 Video data 35 (RX to FPGA)
RX#0_P34
T17
I
LVCMOS33
RX#0 Video data 34 (RX to FPGA)
RX#0_P33
Y19
I
LVCMOS33
RX#0 Video data 33 (RX to FPGA)
RX#0_P32
AB19
I
LVCMOS33
RX#0 Video data 32 (RX to FPGA)
RX#0_P31
W18
I
LVCMOS33
RX#0 Video data 31 (RX to FPGA)
RX#0_P30
Y18
I
LVCMOS33
RX#0 Video data 30 (RX to FPGA)
RX#0_P29
T16
I
LVCMOS33
RX#0 Video data 29 (RX to FPGA)
RX#0_P28
T15
I
LVCMOS33
RX#0 Video data 28 (RX to FPGA)
RX#0_P27
U17
I
LVCMOS33
RX#0 Video data 27 (RX to FPGA)
RX#0_P26
U16
I
LVCMOS33
RX#0 Video data 26 (RX to FPGA)
RX#0_P25
V19
I
LVCMOS33
RX#0 Video data 25 (RX to FPGA)
RX#0_P24
V18
I
LVCMOS33
RX#0 Video data 24 (RX to FPGA)
RX#0_P23
R16
I
LVCMOS33
RX#0 Video data 23 (RX to FPGA)
RX#0_P22
R15
I
LVCMOS33
RX#0 Video data 22 (RX to FPGA)
RX#0_P21
V17
I
LVCMOS33
RX#0 Video data 21 (RX to FPGA)
RX#0_P20
W17
I
LVCMOS33
RX#0 Video data 20 (RX to FPGA)
RX#0_P19
V15
I
LVCMOS33
RX#0 Video data 19 (RX to FPGA)
RX#0_P18
AA18
I
LVCMOS33
RX#0 Video data 18 (RX to FPGA)
RX#0_P17
AB18
I
LVCMOS33
RX#0 Video data 17 (RX to FPGA)
RX#0_P16
Y17
I
LVCMOS33
RX#0 Video data 16 (RX to FPGA)
RX#0_P15
AB17
I
LVCMOS33
RX#0 Video data 15 (RX to FPGA)
RX#0_P14
AA14
I
LVCMOS33
RX#0 Video data 14 (RX to FPGA)
RX#0_P13
AB14
I
LVCMOS33
RX#0 Video data 13 (RX to FPGA)
RX#0_P12
Y16
I
LVCMOS33
RX#0 Video data 12 (RX to FPGA)
RX#0_P11
W15
I
LVCMOS33
RX#0 Video data 11 (RX to FPGA)
RX#0_P10
V13
I
LVCMOS33
RX#0 Video data 10 (RX to FPGA)
RX#0_P9
W13
I
LVCMOS33
RX#0 Video data 9 (RX to FPGA)
RX#0_P8
AA16
I
LVCMOS33
RX#0 Video data 8 (RX to FPGA)
RX#0_P7
AB16
I
LVCMOS33
RX#0 Video data 7 (RX to FPGA)
RX#0_P6
W14
I
LVCMOS33
RX#0 Video data 6 (RX to FPGA)
RX#0_P5
Y14
I
LVCMOS33
RX#0 Video data 5 (RX to FPGA)
RX#0_P4
Y15
I
LVCMOS33
RX#0 Video data 4 (RX to FPGA)
RX#0_P3
AB15
I
LVCMOS33
RX#0 Video data 3 (RX to FPGA)
RX#0_P2
T12
I
LVCMOS33
RX#0 Video data 2 (RX to FPGA)
RX#0_P1
U12
I
LVCMOS33
RX#0 Video data 1 (RX to FPGA)
RX#0_P0
T14
I
LVCMOS33
RX#0 Video data 0 (RX to FPGA)
RX#0_DE
R13
I
LVCMOS33
RX#0 data enable (RX to FPGA)
RX#0_LLC
W12
I
LVCMOS33
RX#0 LLC signal (RX to FPGA)
RX#0_SCLK
Y13
I
LVCMOS33
RX#0 Audio serial clock (RX to FPGA)
RX#0_MCLKOUT
AA12
I
LVCMOS33
RX#0 Audio master clock (RX to FPGA)
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Rev.1.05
Pin Name
No.
IO
Spec
Description
SYSCLK_P
Y11
I
LVCMOS33
System Clock (27MHz)
RX#0_HSYNC
R11
I
LVCMOS33
RX#0 HSYNC (RX to FPGA)
RX#0_VSYNC
T11 I LVCMOS33
RX#0 VSYNC (RX to FPGA)
RX#0_SPDIF
AA10
I
LVCMOS33
RX#0 SPDIF Digital Audio (RX to FPGA)
RX#0_I2S0
AB10
I
LVCMOS33
RX#0 I2S Audio Signal 0 (RX to FPGA)
RX#0_I2S1
V11
I
LVCMOS33
RX#0 I2S Audio Signal 1 (RX to FPGA)
RX#0_I2S2
W11
I
LVCMOS33
RX#0 I2S Audio Signal 2 (RX to FPGA)
RX#0_I2S3
Y9 I LVCMOS33
RX#0 I2S Audio Signal 3 (RX to FPGA)
RX#0_LRCLK
AB9
I
LVCMOS33
RX#0 LRCLK Signal (RX to FPGA)
RX#0_SCL
W10
O
LVCMOS33
RX#0 I2C Serial Clock (FPGA to RX)
RX#0_SDA
Y10
IO
LVCMOS33
RX#0 I2C Serial Data (RX to/from FPGA)
RX#0_INT1
AA8
I
LVCMOS33
RX#0 Interrupt Input 1 (RX to FPGA)
RX#0_RESETN
AB8
O
LVCMOS33
RX#0 Reset (FPGA to RX)
RX#0_CSN
W8 O LVCMOS33
RX#0 CS Output (FPGA to RX)
RX#0_CEC
V7
IO
LVCMOS33
RX#0 CEC Signal (RX to/from FPGA)
RX#0_DDCA_SCL_F
W9 I LVCMOS33
RX#0 DDC Serial Clock (RX to FPGA)
RX#0_DDCA_SDA_F
Y8
IO
LVCMOS33
RX#0 DDC Serial Data (RX to/from FPGA)
RX#0_HPD_IO
U9 O LVCMOS33
RX#0 Hot Plug Control (FPGA to RX)
RX#0_DET1
V9 I LVCMOS33
RX#0 Detect Signal (RX to FPGA)
FPGA_SRSTN
AA2
I
LVCMOS33
FPGA Reset
RX#1_P35
Y2 I LVCMOS33
RX#1 Video Data 35 (RX to FPGA)
RX#1_P34
Y1 I LVCMOS33
RX#1 Video Data 34 (RX to FPGA)
RX#1_P33
W3 I LVCMOS33
RX#1 Video Data 33 (RX to FPGA)
RX#1_P32
W1 I LVCMOS33
RX#1 Video Data 32 (RX to FPGA)
RX#1_P31
P8 I LVCMOS33
RX#1 Video Data 31 (RX to FPGA)
RX#1_P30
P7 I LVCMOS33
RX#1 Video Data 30 (RX to FPGA)
RX#1_P29
P6 I LVCMOS33
RX#1 Video Data 29 (RX to FPGA)
RX#1_P28
P5 I LVCMOS33
RX#1 Video Data 28 (RX to FPGA)
RX#1_P27
T4 I LVCMOS33
RX#1 Video Data 27 (RX to FPGA)
RX#1_P26
T3 I LVCMOS33
RX#1 Video Data 26 (RX to FPGA)
RX#1_P25
U4 I LVCMOS33
RX#1 Video Data 25 (RX to FPGA)
RX#1_P24
V3 I LVCMOS33
RX#1 Video Data 24 (RX to FPGA)
RX#1_P23
N6 I LVCMOS33
RX#1 Video Data 23 (RX to FPGA)
RX#1_P22
N7 I LVCMOS33
RX#1 Video Data 22 (RX to FPGA)
RX#1_P21
M7 I LVCMOS33
RX#1 Video Data 21 (RX to FPGA)
RX#1_P20
M8 I LVCMOS33
RX#1 Video Data 20 (RX to FPGA)
RX#1_P19
R4 I LVCMOS33
RX#1 Video Data 19 (RX to FPGA)
RX#1_P18
P4 I LVCMOS33
RX#1 Video Data 18 (RX to FPGA)
RX#1_P17
M6 I LVCMOS33
RX#1 Video Data 17 (RX to FPGA)
RX#1_P16
L6 I LVCMOS33
RX#1 Video Data 16 (RX to FPGA)
RX#1_P15
P3 I LVCMOS33
RX#1 Video Data 15 (RX to FPGA)
RX#1_P14
N4 I LVCMOS33
RX#1 Video Data 14 (RX to FPGA)
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Rev.1.05
Pin Name
No.
IO
Spec
Description
RX#1_P13
M5 I LVCMOS33
RX#1 Video Data 13 (RX to FPGA)
RX#1_P12
M4 I LVCMOS33
RX#1 Video Data 12 (RX to FPGA)
RX#1_P11
V2 I LVCMOS33
RX#1 Video Data 11 (RX to FPGA)
RX#1_P10
V1 I LVCMOS33
RX#1 Video Data 10 (RX to FPGA)
RX#1_P9
U3 I LVCMOS33
RX#1 Video Data 9 (RX to FPGA)
RX#1_P8
U1 I LVCMOS33
RX#1 Video Data 8 (RX to FPGA)
RX#1_P7
T2 I LVCMOS33
RX#1 Video Data 7 (RX to FPGA)
RX#1_P6
T1 I LVCMOS33
RX#1 Video Data 6 (RX to FPGA)
RX#1_P5
R3 I LVCMOS33
RX#1 Video Data 5 (RX to FPGA)
RX#1_P4
R1 I LVCMOS33
RX#1 Video Data 4 (RX to FPGA)
RX#1_P3
P2 I LVCMOS33
RX#1 Video Data 3 (RX to FPGA)
RX#1_P2
P1 I LVCMOS33
RX#1 Video Data 2 (RX to FPGA)
RX#1_P1
N3 I LVCMOS33
RX#1 Video Data 1 (RX to FPGA)
RX#1_P0
N1 I LVCMOS33
RX#1 Video Data 0 (RX to FPGA)
RX#1_DE
M2 I LVCMOS33
RX#1 Data Enable (RX to FPGA)
RX#1_LLC
J3 I LVCMOS33
RX#1 LLC Signal (RX to FPGA)
RX#1_SCLK
M3 I LVCMOS33
RX#1 Audio Serial Clock (RX to FPGA)
RX#1_MCLKOUT
K5 I LVCMOS33
RX#1 Audio Master Clock (RX to FPGA)
RX#1_HSYNC
M1 I LVCMOS33
RX#1 HSYNC (RX to FPGA)
RX#1_VSYNC
L3 I LVCMOS33
RX#1 VSYNC (RX to FPGA)
RX#1_SPDIF
L1 I LVCMOS33
RX#1 SPDIF Digital Audio (RX to FPGA)
RX#1_I2S0
K2 I LVCMOS33
RX#1 I2S Audio Signal 0 (RX to FPGA)
RX#1_I2S1
K1 I LVCMOS33
RX#1 I2S Audio Signal 1 (RX to FPGA)
RX#1_I2S2
K6 I LVCMOS33
RX#1 I2S Audio Signal 2 (RX to FPGA)
RX#1_I2S3
J6 I LVCMOS33
RX#1 I2S Audio Signal 3 (RX to FPGA)
RX#1_LRCLK
H4 I LVCMOS33
RX#1 LRCLK Signal (RX to FPGA)
RX#1_SCL
H3 O LVCMOS33
RX#1 I2C Serial Clock (FPGA to RX)
RX#1_SDA
H2
IO
LVCMOS33
RX#1 I2C Serial Data (RX to/from FPGA)
RX#1_INT1
H1 I LVCMOS33
RX#1 Interrupt Input 1 (RX to FPGA)
RX#1_RESETN
G3 O LVCMOS33
RX#1 Reset (FPGA to RX)
RX#1_CSN
G1 O LVCMOS33
RX#1 CS Output (FPGA to RX)
RX#1_CEC
H6
IO
LVCMOS33
RX#1 CEC Signal (RX to/from FPGA)
RX#1_DDCA_SCL_F
H5 I LVCMOS33
RX#1 DDC Serial Clock (RX to FPGA)
RX#1_DDCA_SDA_F
F2
IO
LVCMOS33
RX#1 DDC Serial Data (RX<=>FPGA)
RX#1_HPD_IO
F1 O LVCMOS33
RX#1 Hot Plug Control (FPGA to RX)
RX#1_DET1
G4 I LVCMOS33
RX#1 Detect Signal (RX to FPGA)
RSW0
D2 I LVCMOS33
Rotary Switch 0
RSW1
D1 I LVCMOS33
Rotary Switch 1
RSW2
C3 I LVCMOS33
Rotary Switch 2
RSW3
C1 I LVCMOS33
Rotary Switch 3
DSW0
F5 I LVCMOS33
DIP Switch 0
DSW1
K7 I LVCMOS33
DIP Switch 1
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Rev.1.05
Pin Name
No.
IO
Spec
Description
DSW2
K8 I LVCMOS33
DIP Switch 2
DSW3
D5 I LVCMOS33
DIP Switch 3
DSW4
E4 I LVCMOS33
DIP Switch 4
DSW5
J7 I LVCMOS33
DIP Switch 5
DSW6
H8 I LVCMOS33
DIP Switch 6
DSW7
B2 I LVCMOS33
DIP Switch 7
LED0
G7 O LVCMOS33
LED0
LED1
F7 O LVCMOS33
LED1
LED2
D3 O LVCMOS33
LED2
LED3
C4 O LVCMOS33
LED3
LED4
E5 O LVCMOS33
LED4
LED5
E6 O LVCMOS33
LED5
LED6
A2 O LVCMOS33
LED6
LED7
B3 O LVCMOS33
LED7
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Rev.1.05
4.11. FPGA Output Data Phase
Figure 4-6 shows the output data phase of FPGA on TB-FMCH-HDMI2-RX.
FPGA to FMC data is output at the falling edge of the video clock.
The data should be latched at the rising edge on the main board side.
FPGA=>FMC
HDMIRX_CLK
VSYNC,HSYNC,
DE,DATA
Output data are synchronous with down
edge of HDMIRX_CLK.
Figure 4-6 FPGA Output Data Timing
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Rev.1.05
4.12. Image Size
4.12.1. 2D Image Size
TB-FMCH-HDMI2-RX supports HDMI1.4-compliant primary format and part of secondary format
(1080p@60Hz).
Supported image size:
640x480p@59.94/60Hz
1280x720p@59.94/60Hz
1920x1080i@59.94/60Hz
720x480p @ 59.94/60Hz
720(1440)x480i@59.94/60Hz
1280x720@50Hz
1920x1080i@50Hz
720x576p@50Hz
720(1440)x576i@50Hz
1920x1080p@59.94/60Hz
1920x1080p@50Hz
4.12.2. 3D Image Size
TB-FMCH-HDMI2-RX supports HDMI1.4-compliant primary format.
Supported image size:
1280x720p@59.94/60Hz (Frame Packing, Side-by-Side(Half), Top-and-Bottom)
1280x720p@50Hz (Frame Packing, Side-by-Side(Half), Top-and-Bottom)
1280x720p@23.98/24Hz (Frame Packing)
1280x720p@23.97/30Hz (Frame Packing)
1920x1080i@59.94/60Hz (Frame Packing, Side-by-Side(Half))
1920x1080i@50Hz (Frame Packing, Side-by-Side(Half))
1920x1080p@23.98/24Hz (Frame Packing, Side-by-Side(Half), Top-and-Bottom)
1920x1080p@29.97/30Hz (Frame Packing, Top-and-Bottom)
1920x1080p@59.94/60Hz (Top-and-Bottom)
1920x1080p@50Hz (Top-and-Bottom)
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Rev.1.05
5. TB-FMCH-HDMI2-TX
5.1. Block Diagram
Figure 5-1 shows a TB-FMCH-HDMI2-TX block diagram.
The FMC-HPC connector is mounted on the solder side of the board.
FPGA
XC6SLX45-3FGG484C
FMC-HPC
ENC#0
500254-1927
HDMI#0（TX)
ADV7511
TX#0_C、TX#0_0～2
TX#0_D[35:0]
TX#0_VS/HS/DE
TX#0_CLK
TX#0_DDCA_SCL
CEC#0
HEAC#0+/-
TX#0_DSD[5:0]
TX#0_DSDCLK
TX#0_SPDIF
TX#0_MCLK
TX#0_I2S[3:0]
TX#0_SCLK
TX#0_LRCLK
TX#0_PD
TX#0_INT
PROM
ASP-134488-01
XCF16PFSG48C
LA[33:00]_P/N
HA[23:00]_P/N
CLK[3:0]_M2C_P/N
FPGA_D[7:0]
FPGA_DONE
FPGA_INITB
FPGA_PROGB
FPGA_CCLK
FPGA_TCK/TMS/TDI/TDO
TX#0_SCL/SDA
HPD#0
CLK
SYSCLK_P
LED[7:0]
DSW[7:0]
RSW[3:0]
JTAG
KC5032C27.000
KC5032C12.000
CLK
TX#0_HPD_IO
TX#0_DDCA_SDA
DDC0_GND
DDC0
DDC0_HPD
DDC0_5V
DDC0_SDA
DDC0_SCL
T_SHLD0
VCC_5V
ENC#1
500254-1927
HDMI#1（TX)
ADV7511
TX#1_C、TX#0_0～2
TX#1_D[35:0]
TX#1_VS/HS/DE
TX#1_CLK
TX#1_DDCA_SCL
CEC#1
HEAC#1+/-
TX#1_DSD[5:0]
TX#1_DSDCLK
TX#1_SPDIF
TX#1_MCLK
TX#1_I2S[3:0]
TX#1_SCLK
TX#1_LRCLK
TX#1_PD
TX#1_INT
TX#1_SCL/SDA
HPD#1
KC5032C12.000
CLK
TX#1_HPD_IO
TX#1_DDCA_SDA
DDC1_GND
DDC1
DDC1_HPD
DDC1_5V
DDC1_SDA
DDC1_SCL
T_SHLD1
VCC_5V
Figure 5-1 TB-FMCH-HDMI2-TX Block Diagram
Main Function:
1. HDMI Transmit (FPGA to ADV7511)
2. FMC Connector Interface (FMC-HPC to FPGA)
3. JTAG Interface
4. General-purpose Clock Interface (27MHz)
5. General-purpose Switch
6. General-purpose LED
7. DDC Connection (Normal/ Through)
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Rev.1.05
5.2. External View of the Board
Figures 5-2 and 5-3 show the external view of the TB-FMCH-HDMI2-TX board.
HDMI ConnectorHDMI TransmitterFPGA
Figure 5-2 TB-FMCH-HDMI2-TX (component side)
FMC-HPC
Figure 5-3 TB-FMCH-HDMI2-TX (solder side)
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Rev.1.05
5.3. Board Specification
Figure 5-4 shows the TB-FMCH-HDMI2-TX board specification.
External Dimensions : W:160mm x H:69mm
Number of Layers : 8 Layers
Board Thickness : 1.6 mm
Material : FR-4
FPGA : Xilinx’s XC6SLX45-3FGG484C
FMC Connector : Samtec’s ASP-134488-01
HDMI Connector : Molex’s 5002541927
Figure 5-4 TB-FMCH-HDMI2-TX Board Dimensions
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Rev.1.05
5.4. Power Supply to the Board
Figure 5-5 shows the TB-FMCH-HDMI2-TX power supply structure.
VCC_12V_IN VCC_5V
LT3503EDCB
VCC_1.8V0
LTC3026EMSE
VCC_1.8V1
LTC3026EMSE
ADV7511 : 196mA
VCC_3.3V
FPGA_VCAUX : 68mA FPGA_VCCIO : 311mA
ADV7511 : 0.3mA x2 = 0.6mA
663mA
KC3225A: 6mA x3 = 18mA
LTC1326: 0.04mA
134mA
VCC_2.5V
（1.6575W）
437mA
(1.442W)
（0.671W）
349mA
LT3503EDCB
LT3568EDD
FPGA_VCCINT : 503mA
VCC_1.2V
FPGA_VCCIO : 261mA
XCF16 VCCINT : 10mA
XCF16 VCCIO : 40mA
LT3503EDCB
ADG702: 0.001mA x2 = 0.002mA
ADV7511 : 196mA
Figure 5-5 TB-FMCH-HDMI2-TX Power Supply Structure
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Rev.1.05
5.5. HDMI Transmitter
The HDMI connector uses MOLEX’s 5002541927.
The HDMI transmitter uses Analog Devices’s ADV7511KSTZ-P.
The following device is used for ESD protection:
ESD protection: Semtech’s RCLAMP0524 and RCLAMP0504
Table 5-1 shows the HDMI connector pin assignment.
Table 5-1 HDMI Connector (transmit side)
Pin #
Name
Description
1
TMDS DATA2+
TMDS Transmit Data 2+
2
TMDS SHLD2
TMDS Transmit Data 2 Shield
3
TMDS DATA2-
TMDS Transmit Data 2-
4
TMDS DATA1+
TMDS Transmit Data 1+
5
TMDS SHLD1
TMDS Transmit Data 1 Shield
6
TMDS DATA1-
TMDS Transmit Data 1-
7
TMDS DATA0+
TMDS Transmit Data 0+
8
TMDS SHLD0
TMDS Transmit Data 0 Shield
9
TMDS DATA0-
TMDS Transmit Data 0-
10
TMDS CLK+
TMDS Transmit Clock+
11
TMDS CLK SHLD
TMDS Transmit Clock Shield
12
TMDS CLK-
TMDS Transmit Clock-
13
CEC
CEC Signal
14
UTILITY/HEAC+
HEAC+ Signal
15
DDC_SCL
DDC Serial Clock
16
DDC_SDA
DDC Serial Data
17
DDC/CEC GND
DDC/CEC Ground
18
DDC_+5V
+5V
19
HPD/HEAC-
Hot Plug Detection/HEAC-Signal
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Rev.1.05
5.6. FMC Connector
The FMC connector connecting to the High-Pin Count uses SAMTEC’s ASP-134488-01.
Power to the TB-FMCH-HDMI2-TX is supplied from a +12V on the main board.
An external power source can also be used.
Table 5-2 shows JP3 jumper setting for power supply.
Table 5-2 JP3 Jumper Setting
No
Purpose
Silk
Jumper Setting
1
FMC Connector
12VIN_SEL
JP3: 1-2 short
2
External Power Source
12VIN_SEL
JP3: 2-3 short
The following test pin is used to connect an external power source.
TP14: 12VIN
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Rev.1.05
Table 5-3 shows the FMC connector pin assignment.
Table 5-3 FMC Connector Pin Assignment
Pin
A-row
B-row
C-row
D-row
E-row
1
GND
RES1
GND
PG_C2M
GND
2
DP1_M2C_P
GND
DP0_C2M_P
GND
HA01_P_CC
3
DP1_M2C_N
GND
DP0_C2M_N
GND
HA01_N_CC
4
GND
DP9_M2C_P
GND
GBTCLK0_M2C_P
GND
5
GND
DP9_M2C_N
GND
GBTCLK0_M2C_N
GND
6
DP2_M2C_P
GND
DP0_M2C_P
GND
HA05_P
7
DP2_M2C_N
GND
DP0_M2C_N
GND
HA05_N
8
GND
DP8_M2C_P
GND
LA01_P_CC
GND
9
GND
DP8_M2C_N
GND
LA01_N_CC
HA09_P
10
DP3_M2C_P
GND
LA06_P
GND
HA09_N
11
DP3_M2C_N
GND
LA06_N
LA05_P
GND
12
GND
DP7_M2C_P
GND
LA05_N
HA13_P
13
GND
DP7_M2C_N
GND
GND
HA13_N
14
DP4_M2C_P
GND
LA10_P
LA09_P
GND
15
DP4_M2C_N
GND
LA10_N
LA09_N
HA16_P
16
GND
DP6_M2C_P
GND
GND
HA16_N
17
GND
DP6_M2C_N
GND
LA13_P
GND
18
DP5_M2C_P
GND
LA14_P
LA13_N
HA20_P
19
DP5_M2C_N
GND
LA14_N
GND
HA20_N
20
GND
GBTCLK1_M2C_P
GND
LA17_P_CC
GND
21
GND
GBTCLK1_M2C_N
GND
LA17_N_CC
HB03_P
22
DP1_C2M_P
GND
LA18_P_CC
GND
HB03_N
23
DP1_C2M_N
GND
LA18_N_CC
LA23_P
GND
24
GND
DP2_C9M_P
GND
LA23_N
HB05_P
25
GND
DP2_C9M_N
GND
GND
HB05_N
26
DP2_C2M_P
GND
LA27_P
LA26_P
GND
27
DP2_C2M_N
GND
LA27_N
LA26_N
HB09_P
28
GND
DP2_C8M_P
GND
GND
HB09_N
29
GND
DP2_C8M_N
GND
TCK
GND
30
DP3_C2M_P
GND
SCL
TDI
HB13_P
31
DP3_C2M_N
GND
SDA
TDO
HB13_N
32
GND
DP2_C7M_P
GND
+3.3VAUX
GND
33
GND
DP2_C7M_N
GND
TMS
HB19_P
34
DP4_C2M_P
GND
GA0
TRST
HB19_N
35
DP4_C2M_N
GND
+12V
GA1
GND
36
GND
DP2_C6M_P
GND
+3.3V
HB21_P
37
GND
DP2_C6M_N
+12V
GND
HB21_N
38
DP5_C2M_P
GND
GND
+3.3V
GND
39
DP5_C2M_N
GND
+3.3V
GND
VADJ
40
GND
RES0
GND
+3.3V
GND
TB-FMCH-HDMI2 Hardware User Manual
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Rev.1.05
Pin
F-row
G-row
H-row
J-row
K-row
1
PG_M2C
GND
VREF_A_M2C
GND
VREF_B_M2C
2
GND
CLK1_M2C_P
PRSNT_M2C_L
CLK3_M2C_P
GND
3
GND
CLK1_M2C_N
GND
CLK3_M2C_N
GND
4
HA00_P_CC
GND
CLK0_M2C_P
GND
CLK2_M2C_P
5
HA00_N_CC
GND
CLK0_M2C_N
GND
CLK2_M2C_N
6
GND
LA00_P_CC
GND
HA03_P
GND
7
GND
LA00_N_CC
LA02_P
HA03_N
HA02_P
8
HA04_P
GND
LA02_N
GND
HA02_N
9
HA04_N
LA03_P
GND
HA07_P
GND
10
GND
LA03_N
LA04_P
HA07_N
HA06_P
11
HA08_P
GND
LA04_N
GND
HA06_N
12
HA08_N
LA08_P
GND
HA11_P
GND
13
GND
LA08_N
LA07_P
HA11_N
HA10_P
14
HA12_P
GND
LA07_N
GND
HA10_N
15
HA12_N
LA12_P
GND
HA14_P
GND
16
GND
LA12_N
LA11_P
HA14_N
HA17_P_CC
17
HA15_P
GND
LA11_N
GND
HA17_N_CC
18
HA15_N
LA16_P
GND
HA18_P
GND
19
GND
LA16_N
LA15_P
HA18_N
HA21_P
20
HA19_P
GND
LA15_N
GND
HA21_N
21
HA19_N
LA20_P
GND
HA22_P
GND
22
GND
LA20_N
LA19_P
HA22_N
HA23_P
23
HB02_P
GND
LA19_N
GND
HA23_N
24
HB02_N
LA22_P
GND
HB01_P
GND
25
GND
LA22_N
LA21_P
HB01_N
HB00_P_CC
26
HB04_P
GND
LA21_N
GND
HB00_N_CC
27
HB04_N
LA25_P
GND
HB07_P
GND
28
GND
LA25_N
LA24_P
HB07_N
HB06_P_CC
29
HB08_P
GND
LA24_N
GND
HB06_N_CC
30
HB08_N
LA29_P
GND
HB11_P
GND
31
GND
LA29_N
LA28_P
HB11_N
HB10_P
32
HB12_P
GND
LA28_N
GND
HB10_N
33
HB12_N
LA31_P
GND
HB15_P
GND
34
GND
LA31_N
LA30_P
HB15_N
HB14_P
35
HB16_P
GND
LA30_N
GND
HB14_N
36
HB16_N
LA33_P
GND
HB18_P
GND
37
GND
LA33_N
LA32_P
HB18_N
HB17_P_CC
38
HB20_P
GND
LA32_N
GND
HB17_N_CC
39
HB20_N
VADJ
GND
VIO_B_M2C
GND
40
VADJ
GND
VADJ
GND
VIO_B_M2C
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5.7. Other Interfaces
The board also provides the following interfaces.
5.7.1. JTAG Interface
The board has a JTAG connector FPGA configuration.
JTAG Connector: Molex’s 87832-1420
Table 5-4 JTAG Connector
Pin
Signal
Pin
Signal Name
1
GND
2
3.3V
3
GND
4
TMS
5
GND
6
TCK
7
GND
8
TDO
9
GND
10
TDI
11
GND
12
NC
13
GND
14
NC
5.7.2. General-Purpose Clock Interface
The board has a general-purpose clock on FPGA (27MHz crystal oscillator)
KC5032C027.0000C30E00 (Kyocera)
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5.8. LED Status
Table 5-5 shows the onboard LED function.
Table 5-5 LED Status
No
Circuit #
Silk
Purpose
Description
1
DS3
LED0
General-purpose LED0
[TX0]I2C config state
Off: CFG done / On: CFG active
2
DS4
LED1
General-purpose LED1
[TX0]I2C read back
Off: Error / On: No error
3
DS5
LED2
General-purpose LED2
[TX1]I2C config state
Off: CFG done / On: CFG active
4
DS6
LED3
General-purpose LED3
[TX1]I2C read back
Off: Error / On: No error
5
DS7
LED4
General-purpose LED4
Unused (On)
6
DS8
LED5
General-purpose LED5
[TX0] input video image clock monitor
Flashing: Active clock / Off: No clock
7
DS9
LED6
General-purpose LED6
[TX1] input video image clock monitor
Flashing: Active clock / Off: No clock
8
DS10
LED7
General-purpose LED7
System Reset Monitor
On: Reset active / Off: Reset release
9
DS1
HPD0
TX0 hot plug display
On: Connected state
10
DS2
HPD1
TX1 hot plug display
On: Connected state
11
DS11
DONE
Config display
On: Config complete
12
DS12
12VLED
12V display
On: 12V active
5.9. Relation of ROM and Input Video Format
TB-FMCH-HDMI2-RX and TB-FMCH-HDMI2-TX have 3 types of FPGA ROM.
Relation between ROM and Input Format is below.
Table 5-6 Relation of ROM and Input Video Format
ROM
HDMI
RX
ADV
7612
To FMC
Carria
Board
To FMC
ADV
7511
HDMI
TX
2in/2out
(initial ROM)
YCbCr
/RGB
>
RGB
>
RGB
>
RGB
1in/1out+
Audio
YCbCr
/RGB
YCbCr/
RGB
YCbCr/
RGB
YCbCr
/RGB
2in/2out
Up Grade
YCbCr
/RGB
YCbCr/
RGB
YCbCr/
RGB
YCbCr
/RGB
※ROM of “2in/2out(initial ROM)” convert YCbCr to RGB in ADV7612(RX).
This is true for ADV7511(TX).
※ROM of "1in/1out+Audio", "2in/2out up grade" go through ADV7612(RX) as input format.
This is true for ADV7511(TX).
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5.10. Control Function
Table 5-7 shows the onboard switch function.
Table 5-7 Switch Function
No
Circuit #
Silk
Description
1
S1-1
DSW
ADV7511 config ROM selection:
8bit Output : S1-1 OFF, S1-2 ON, S1-3 ON, S1-4 ON
10bit Output : S1-1 ON, S1-2 ON, S1-3 OFF, S1-4 ON
2
S1-2
DSW
3
S1-3
DSW
4
S1-4
DSW
5
S1-5
DSW
OFF 6 S1-6
DSW
Unused
7
S1-7
DSW
Unused
8
S1-8
DSW
Unused
9
S2
RSW
Unused
10
S3
RST
FPGA reconfig (long push – 3 seconds)
FPGA reset (short push)
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Rev.1.05
5.11. FPGA Pin Assignment
Table 5-8 shows the FPGA pin assignment.
In case of 8-bit signal format, active bits are assigned to MSB 8-bit of each RGB pin of FMC. LSB 2-bit
are always 2'b00 in 8-bit signal format.
Table 5-8 FPGA Pin Assignment
Pin Name
No.
IO
Spec.
Description
CLK0_M2C_P
B10
I
LVCMOS25
TX#0_DCLK Signal (FMC to FPGA)
CLK1_M2C_P
C11
IO
LVCMOS25
Unused
LA00_P_CC
D6 I LVCMOS25
TX#0_VSYNC Signal (FMC to FPGA)
LA01_P_CC
C7 I LVCMOS25
TX#0_HSYNC Signal (FMC to FPGA)
LA02_P
D9 I LVCMOS25
TX#0_DE Signal (FMC to FPGA)
LA03_P
D7 I LVCMOS25
TX#0_D0 Signal (FMC to FPGA) [B0]
LA04_P
C13
I
LVCMOS25
TX#0_D1 Signal (FMC to FPGA) [B1]
LA05_P
B14
I
LVCMOS25
TX#0_D2 Signal (FMC to FPGA) [B2]
LA06_P
D15
I
LVCMOS25
TX#0_D3 Signal (FMC to FPGA) [B3]
LA07_P
C17
I
LVCMOS25
TX#0_D4 Signal (FMC to FPGA) [B4]
LA08_P
E16
I
LVCMOS25
TX#0_D5 Signal (FMC to FPGA) [B5]
LA09_P
G16
I
LVCMOS25
TX#0_D6 Signal (FMC to FPGA) [B6]
LA10_P
B21
I
LVCMOS25
TX#0_D7 Signal (FMC to FPGA) [B7]
LA11_P
K16
I
LVCMOS25
TX#0_D8 Signal (FMC to FPGA) [B8]
LA12_P
D19
I
LVCMOS25
TX#0_D9 Signal (FMC to FPGA) [B9]
LA13_P
D21
I
LVCMOS25
TX#0_D10 Signal (FMC to FPGA) [G0]
LA14_P
G19
I
LVCMOS25
TX#0_D11 Signal (FMC to FPGA) [G1]
LA15_P
E20
I
LVCMOS25
TX#0_D12 Signal (FMC to FPGA) [G2]
LA16_P
F21
I
LVCMOS25
TX#0_D13 Signal (FMC to FPGA) [G3]
LA17_P_CC
G20
I
LVCMOS25
TX#0_D14 Signal (FMC to FPGA) [G4]
LA18_P_CC
H21
I
LVCMOS25
TX#0_D15 Signal (FMC to FPGA) [G5]
LA19_P
J20 I LVCMOS25
TX#0_D16 Signal (FMC to FPGA) [G6]
LA20_P
L20 I LVCMOS25
TX#0_D17 Signal (FMC to FPGA) [G7]
LA21_P
N20
I
LVCMOS25
TX#0_D18 Signal (FMC to FPGA) [G8]
LA22_P
R20
I
LVCMOS25
TX#0_D19 Signal (FMC to FPGA) [G9]
LA23_P
U20
I
LVCMOS25
TX#0_D20 Signal (FMC to FPGA) [R0]
LA24_P
M19
I
LVCMOS25
TX#0_D21 Signal (FMC to FPGA) [R1]
LA25_P
M16
I
LVCMOS25
TX#0_D22 Signal (FMC to FPGA) [R2]
LA26_P
P19
I
LVCMOS25
TX#0_D23 Signal (FMC to FPGA) [R3]
LA27_P
W20
I
LVCMOS25
TX#0_D24 Signal (FMC to FPGA) [R4]
LA28_P
L17 I LVCMOS25
TX#0_D25 Signal (FMC to FPGA) [R5]
LA29_P
U19
I
LVCMOS25
TX#0_D26 Signal (FMC to FPGA) [R6]
LA30_P
M17
I
LVCMOS25
TX#0_D27 Signal (FMC to FPGA) [R7]
LA31_P
P17
I
LVCMOS25
TX#0_D28 Signal (FMC to FPGA) [R8]
LA32_P
P18
I
LVCMOS25
TX#0_D29 Signal (FMC to FPGA) [R9]
LA33_P
T19
IO
LVCMOS25
Unused
CLK0_M2C_N
A10
I
LVCMOS25
TX#1_DCLK Signal (FMC to FPGA)
CLK1_M2C_N
A11
IO
LVCMOS25
Unused
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Rev.1.05
Pin Name
No.
IO
Spec.
Description
LA00_N_CC
C6 I LVCMOS25
TX#1_VSYNC Signal (FMC to FPGA)
LA01_N_CC
A7 I LVCMOS25
TX#1_HSYNC Signal (FMC to FPGA)
LA02_N
C8 I LVCMOS25
TX#1_DE Signal (FMC to FPGA)
LA03_N
D8 I LVCMOS25
TX#1_D0 Signal (FMC to FPGA) [B0]
LA04_N
A13
I
LVCMOS25
TX#1_D1 Signal (FMC to FPGA) [B1]
LA05_N
A14
I
LVCMOS25
TX#1_D2 Signal (FMC to FPGA) [B2]
LA06_N
C16
I
LVCMOS25
TX#1_D3 Signal (FMC to FPGA) [B3]
LA07_N
A17
I
LVCMOS25
TX#1_D4 Signal (FMC to FPGA) [B4]
LA08_N
D17
I
LVCMOS25
TX#1_D5 Signal (FMC to FPGA) [B5]
LA09_N
G17
I
LVCMOS25
TX#1_D6 Signal (FMC to FPGA) [B6]
LA10_N
B22
I
LVCMOS25
TX#1_D7 Signal (FMC to FPGA) [B7]
LA11_N
J16 I LVCMOS25
TX#1_D8 Signal (FMC to FPGA) [B8]
LA12_N
D20
I
LVCMOS25
TX#1_D9 Signal (FMC to FPGA) [B9]
LA13_N
D22
I
LVCMOS25
TX#1_D10 Signal (FMC to FPGA) [G0]
LA14_N
F20
I
LVCMOS25
TX#1_D11 Signal (FMC to FPGA) [G1]
LA15_N
E22
I
LVCMOS25
TX#1_D12 Signal (FMC to FPGA) [G2]
LA16_N
F22
I
LVCMOS25
TX#1_D13 Signal (FMC to FPGA) [G3]
LA17_N_CC
G22
I
LVCMOS25
TX#1_D14 Signal (FMC to FPGA) [G4]
LA18_N_CC
H22
I
LVCMOS25
TX#1_D15 Signal (FMC to FPGA) [G5]
LA19_N
J22 I LVCMOS25
TX#1_D16 Signal (FMC to FPGA) [G6]
LA20_N
L22 I LVCMOS25
TX#1_D17 Signal (FMC to FPGA) [G7]
LA21_N
N22
I
LVCMOS25
TX#1_D18 Signal (FMC to FPGA) [G8]
LA22_N
R22
I
LVCMOS25
TX#1_D19 Signal (FMC to FPGA) [G9]
LA23_N
U22
I
LVCMOS25
TX#1_D20 Signal (FMC to FPGA) [R0]
LA24_N
N19
I
LVCMOS25
TX#1_D21 Signal (FMC to FPGA) [R1]
LA25_N
L15 I LVCMOS25
TX#1_D22 Signal (FMC to FPGA) [R2]
LA26_N
P20
I
LVCMOS25
TX#1_D23 Signal (FMC to FPGA) [R3]
LA27_N
W22
I
LVCMOS25
TX#1_D24 Signal (FMC to FPGA) [R4]
LA28_N
K18
I
LVCMOS25
TX#1_D25 Signal (FMC to FPGA) [R5]
LA29_N
V20
I
LVCMOS25
TX#1_D26 Signal (FMC to FPGA) [R6]
LA30_N
M18
I
LVCMOS25
TX#1_D27 Signal (FMC to FPGA) [R7]
LA31_N
N16
I
LVCMOS25
TX#1_D28 Signal (FMC to FPGA) [R8]
LA32_N
R19
I
LVCMOS25
TX#1_D29 Signal (FMC to FPGA) [R9]
LA33_N
T20
IO
LVCMOS25
Unused
CLK2_M2C_P
D11
IO
LVCMOS25
Unused
CLK3_M2C_P
B12
IO
LVCMOS25
Unused
HA00_P_CC
B6
IO
LVCMOS25
Unused
HA01_P_CC
B8
IO
LVCMOS25
Unused
HA02_P
C9
IO
LVCMOS25
Unused
HA03_P
D10
IO
LVCMOS25
Unused
HA04_P
D14
IO
LVCMOS25
Unused
HA05_P
C15
IO
LVCMOS25
Unused
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Rev.1.05
Pin Name
No.
IO
Spec.
Description
HA06_P
B16
IO
LVCMOS25
Unused
HA07_P
B18
IO
LVCMOS25
Unused
HA08_P
C19
IO
LVCMOS25
Unused
HA09_P
F16
IO
LVCMOS25
Unused
HA10_P
A20
IO
LVCMOS25
Unused
HA11_P
H16
IO
LVCMOS25
Unused
HA12_P
F18
IO
LVCMOS25
Unused
HA13_P
C20
IO
LVCMOS25
Unused
HA14_P
H19
IO
LVCMOS25
Unused
HA15_P
J17
IO
LVCMOS25
Unused
HA16_P
H20
IO
LVCMOS25
Unused
HA17_P_CC
K20
IO
LVCMOS25
Unused
HA18_P
M20
IO
LVCMOS25
Unused
HA19_P
K21
IO
LVCMOS25
Unused
HA20_P
M21
IO
LVCMOS25
Unused
HA21_P
P21
IO
LVCMOS25
Unused
HA22_P
T21
IO
LVCMOS25
Unused
HA23_P
V21
IO
LVCMOS25
Unused
CLK2_M2C_N
C12
IO
LVCMOS25
Unused
CLK3_M2C_N
A12
IO
LVCMOS25
Unused
HA00_N_CC
A6
IO
LVCMOS25
Unused
HA01_N_CC
A8
IO
LVCMOS25
Unused
HA02_N
A9
IO
LVCMOS25
Unused
HA03_N
C10
IO
LVCMOS25
Unused
HA04_N
C14
IO
LVCMOS25
Unused
HA05_N
A15
IO
LVCMOS25
Unused
HA06_N
A16
IO
LVCMOS25
Unused
HA07_N
A18
IO
LVCMOS25
Unused
HA08_N
B20
IO
LVCMOS25
Unused
HA09_N
F17
IO
LVCMOS25
Unused
HA10_N
A21
IO
LVCMOS25
Unused
HA11_N
H17
IO
LVCMOS25
Unused
HA12_N
F19
IO
LVCMOS25
Unused
HA13_N
C22
IO
LVCMOS25
Unused
HA14_N
H18
IO
LVCMOS25
Unused
HA15_N
K17
IO
LVCMOS25
Unused
HA16_N
J19
IO
LVCMOS25
Unused
HA17_N_CC
K19
IO
LVCMOS25
Unused
HA18_N
L19
IO
LVCMOS25
Unused
HA19_N
K22
IO
LVCMOS25
Unused
HA20_N
M22
IO
LVCMOS25
Unused
HA21_N
P22
IO
LVCMOS25
Unused
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Rev.1.05
Pin Name
No.
IO
Spec.
Description
HA22_N
T22
IO
LVCMOS25
Unused
HA23_N
V22
IO
LVCMOS25
Unused
TX#0_D35
Y18
O
LVCMOS33
TX#0 Video data 35 (FPGA to TX)
TX#0_D34
T16
O
LVCMOS33
TX#0 Video data 34 (FPGA to TX)
TX#0_D33
T15
O
LVCMOS33
TX#0 Video data 33 (FPGA to TX)
TX#0_D32
U17
O
LVCMOS33
TX#0 Video data 32 (FPGA to TX)
TX#0_D31
U16
O
LVCMOS33
TX#0 Video data 31 (FPGA to TX)
TX#0_D30
V19
O
LVCMOS33
TX#0 Video data 30 (FPGA to TX)
TX#0_D29
V18
O
LVCMOS33
TX#0 Video data 29 (FPGA to TX)
TX#0_D28
R16
O
LVCMOS33
TX#0 Video data 28 (FPGA to TX)
TX#0_D27
R15
O
LVCMOS33
TX#0 Video data 27 (FPGA to TX)
TX#0_D26
V17
O
LVCMOS33
TX#0 Video data 26 (FPGA to TX)
TX#0_D25
W17
O
LVCMOS33
TX#0 Video data 25 (FPGA to TX)
TX#0_D24
V15
O
LVCMOS33
TX#0 Video data 24 (FPGA to TX)
TX#0_D23
AA18
O
LVCMOS33
TX#0 Video data 23 (FPGA to TX)
TX#0_D22
AB18
O
LVCMOS33
TX#0 Video data 22 (FPGA to TX)
TX#0_D21
Y17
O
LVCMOS33
TX#0 Video data 21 (FPGA to TX)
TX#0_D20
AB17
O
LVCMOS33
TX#0 Video data 20 (FPGA to TX)
TX#0_D19
AA14
O
LVCMOS33
TX#0 Video data 19 (FPGA to TX)
TX#0_D18
AB14
O
LVCMOS33
TX#0 Video data 18 (FPGA to TX)
TX#0_D17
Y16
O
LVCMOS33
TX#0 Video data 17 (FPGA to TX)
TX#0_D16
W15
O
LVCMOS33
TX#0 Video data 16 (FPGA to TX)
TX#0_D15
V13
O
LVCMOS33
TX#0 Video data 15 (FPGA to TX)
TX#0_D14
W13
O
LVCMOS33
TX#0 Video data 14 (FPGA to TX)
TX#0_D13
AA16
O
LVCMOS33
TX#0 Video data 13 (FPGA to TX)
TX#0_D12
AB16
O
LVCMOS33
TX#0 Video data 12 (FPGA to TX)
TX#0_D11
W14
O
LVCMOS33
TX#0 Video data 11 (FPGA to TX)
TX#0_D10
Y14
O
LVCMOS33
TX#0 Video data 10 (FPGA to TX)
TX#0_D9
Y15
O
LVCMOS33
TX#0 Video data 9 (FPGA to TX)
TX#0_D8
AB15
O
LVCMOS33
TX#0 Video data 8 (FPGA to TX)
TX#0_D7
T12
O
LVCMOS33
TX#0 Video data 7 (FPGA to TX)
TX#0_D6
U12
O
LVCMOS33
TX#0 Video data 6 (FPGA to TX)
TX#0_D5
T14
O
LVCMOS33
TX#0 Video data 5 (FPGA to TX)
TX#0_D4
R13
O
LVCMOS33
TX#0 Video data 4 (FPGA to TX)
TX#0_D3
R11
O
LVCMOS33
TX#0 Video data 3 (FPGA to TX)
TX#0_D2
T11
O
LVCMOS33
TX#0 Video data 2 (FPGA to TX)
TX#0_D1
AA10
O
LVCMOS33
TX#0 Video data 1 (FPGA to TX)
TX#0_D0
AB10
O
LVCMOS33
TX#0 Video data 0 (FPGA to TX)
TX#0_DCLK
W12
O
LVCMOS33
TX#0 DCLK signal (FPGA to TX)
SYSCLK_P
Y11
I
LVCMOS33
System clock (27MHz)
TX#0_DE
W11
O
LVCMOS33
TX#0 data enable (FPGA to TX)
TX#0_HSYNC
Y9 O LVCMOS33
TX#0 HSYNC (FPGA to TX)
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Rev.1.05
Pin Name
No.
IO
Spec.
Description
TX#0_VSYNC
AB9
O
LVCMOS33
TX#0 VSYNC (FPGA to TX)
TX#0_DSD0
W10
O
LVCMOS33
TX#0 DSD Audio data 0 (FPGA to TX)
TX#0_DSD1
Y10
O
LVCMOS33
TX#0 DSD Audio data 1 (FPGA to TX)
TX#0_DSD2
AA8
O
LVCMOS33
TX#0 DSD Audio data 2 (FPGA to TX)
TX#0_DSD3
AB8
O
LVCMOS33
TX#0 DSD Audio data 3 (FPGA to TX)
TX#0_DSD4
W8 O LVCMOS33
TX#0 DSD Audio data 4 (FPGA to TX)
TX#0_DSD5
V7 O LVCMOS33
TX#0 DSD Audio data 5 (FPGA to TX)
TX#0_DSD_CLK
W9 O LVCMOS33
TX#0 DSD clock (FPGA to TX)
TX#0_SPDIF
Y8 O LVCMOS33
TX#0 SPDIF Digital Audio (FPGA to TX)
TX#0_MCLK
AB7
O
LVCMOS33
TX#0 Audio Master Clock (FPGA to TX)
TX#0_I2S0
U9 O LVCMOS33
TX#0 I2S Audio Signal 0 (FPGA to TX)
TX#0_I2S1
V9 O LVCMOS33
TX#0 I2S Audio Signal 1 (FPGA to TX)
TX#0_I2S2
T8 O LVCMOS33
TX#0 I2S Audio Signal 2 (FPGA to TX)
TX#0_I2S3
U8 O LVCMOS33
TX#0 I2S Audio Signal 3 (FPGA to TX)
TX#0_SCLK
T10
O
LVCMOS33
TX#0 Audio Serial Clock (FPGA to TX)
TX#0_LRCLK
U10
O
LVCMOS33
TX#0 LRCLK Signal (FPGA to TX)
TX#0_HPD_IO
W6 O LVCMOS33
TX#0 Hot Plug Control (FPGA to TX)
TX#0_PD
T18
O
LVCMOS33
TX#0 Power Down (FPGA to TX)
TX#0_INT
Y19
I
LVCMOS33
TX#0 Interrupt (TX to FPGA)
TX#0_SCL
AB19
O
LVCMOS33
TX#0 Serial Clock (FPGA to TX)
TX#0_SDA
W18
IO
LVCMOS33
TX#0 Serial Data (FPGA to TX)
FPGA_SRSTN
AA2
O
LVCMOS33
FPGA Reset
TX#1_D35
W3 O LVCMOS33
TX#1 Video data 35 (FPGA to TX)
TX#1_D34
W1 O LVCMOS33
TX#1 Video data 34 (FPGA to TX)
TX#1_D33
P8 O LVCMOS33
TX#1 Video data 33 (FPGA to TX)
TX#1_D32
P7 O LVCMOS33
TX#1 Video data 32 (FPGA to TX)
TX#1_D31
P6 O LVCMOS33
TX#1 Video data 31 (FPGA to TX)
TX#1_D30
P5 O LVCMOS33
TX#1 Video data 30 (FPGA to TX)
TX#1_D29
T4 O LVCMOS33
TX#1 Video data 29 (FPGA to TX)
TX#1_D28
T3 O LVCMOS33
TX#1 Video data 28 (FPGA to TX)
TX#1_D27
U4 O LVCMOS33
TX#1 Video data 27 (FPGA to TX)
TX#1_D26
V3 O LVCMOS33
TX#1 Video data 26 (FPGA to TX)
TX#1_D25
N6 O LVCMOS33
TX#1 Video data 25 (FPGA to TX)
TX#1_D24
N7 O LVCMOS33
TX#1 Video data 24 (FPGA to TX)
TX#1_D23
M7 O LVCMOS33
TX#1 Video data 23 (FPGA to TX)
TX#1_D22
M8 O LVCMOS33
TX#1 Video data 22 (FPGA to TX)
TX#1_D21
R4 O LVCMOS33
TX#1 Video data 21 (FPGA to TX)
TX#1_D20
P4 O LVCMOS33
TX#1 Video data 20 (FPGA to TX)
TX#1_D19
M6 O LVCMOS33
TX#1 Video data 19 (FPGA to TX)
TX#1_D18
L6 O LVCMOS33
TX#1 Video data 18 (FPGA to TX)
TX#1_D17
P3 O LVCMOS33
TX#1 Video data 17 (FPGA to TX)
TX#1_D16
N4 O LVCMOS33
TX#1 Video data 16 (FPGA to TX)
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Pin Name
No.
IO
Spec.
Description
TX#1_D15
M5 O LVCMOS33
TX#1 Video data 15 (FPGA to TX)
TX#1_D14
M4 O LVCMOS33
TX#1 Video data 14 (FPGA to TX)
TX#1_D13
V2 O LVCMOS33
TX#1 Video data 13 (FPGA to TX)
TX#1_D12
V1 O LVCMOS33
TX#1 Video data 12 (FPGA to TX)
TX#1_D11
U3 O LVCMOS33
TX#1 Video data 11 (FPGA to TX)
TX#1_D10
U1 O LVCMOS33
TX#1 Video data 10 (FPGA to TX)
TX#1_D9
T2 O LVCMOS33
TX#1 Video data 9 (FPGA to TX)
TX#1_D8
T1 O LVCMOS33
TX#1 Video data 8 (FPGA to TX)
TX#1_D7
R3 O LVCMOS33
TX#1 Video data 7 (FPGA to TX)
TX#1_D6
R1 O LVCMOS33
TX#1 Video data 6 (FPGA to TX)
TX#1_D5
P2 O LVCMOS33
TX#1 Video data 5 (FPGA to TX)
TX#1_D4
P1 O LVCMOS33
TX#1 Video data 4 (FPGA to TX)
TX#1_D3
N3 O LVCMOS33
TX#1 Video data 3 (FPGA to TX)
TX#1_D2
N1 O LVCMOS33
TX#1 Video data 2 (FPGA to TX)
TX#1_D1
M2 O LVCMOS33
TX#1 Video data 1 (FPGA to TX)
TX#1_D0
M1 O LVCMOS33
TX#1 Video data 0 (FPGA to TX)
TX#1_DCLK
J3 O LVCMOS33
TX#1 DCLK signal (FPGA to TX)
TX#1_DE
L1 O LVCMOS33
TX#1 data enable (FPGA to TX)
TX#1_HSYNC
K2 O LVCMOS33
TX#1 HSYNC (FPGA to TX)
TX#1_VSYNC
K1 O LVCMOS33
TX#1 VSYNC (FPGA to TX)
TX#1_DSD0
M3 O LVCMOS33
TX#1 DSD Audio data 0 (FPGA to TX)
TX#1_DSD1
L4 O LVCMOS33
TX#1 DSD Audio data 1 (FPGA to TX)
TX#1_DSD2
K5 O LVCMOS33
TX#1 DSD Audio data 2 (FPGA to TX)
TX#1_DSD3
K4 O LVCMOS33
TX#1 DSD Audio data 3 (FPGA to TX)
TX#1_DSD4
K3 O LVCMOS33
TX#1 DSD Audio data 4 (FPGA to TX)
TX#1_DSD5
J4 O LVCMOS33
TX#1 DSD Audio data 5 (FPGA to TX)
TX#1_DSD_CLK
K6 O LVCMOS33
TX#1 DSD clock (FPGA to TX)
TX#1_SPDIF
J6 O LVCMOS33
TX#1 SPDIF Digital Audio (FPGA to TX)
TX#1_MCLK
H4 O LVCMOS33
TX#1 Audio Master Clock (FPGA to TX)
TX#1_I2S0
H3 O LVCMOS33
TX#1 I2S Audio signal 0 (FPGA to TX)
TX#1_I2S1
H2 O LVCMOS33
TX#1 I2S Audio signal 1 (FPGA to TX)
TX#1_I2S2
H1 O LVCMOS33
TX#1 I2S Audio signal 2 (FPGA to TX)
TX#1_I2S3
G3 O LVCMOS33
TX#1 I2S Audio signal 3 (FPGA to TX)
TX#1_SCLK
G1 O LVCMOS33
TX#1 Audio serial clock (FPGA to TX)
TX#1_LRCLK
H6 O LVCMOS33
TX#1 LRCLK signal (FPGA to TX)
TX#1_HPD_IO
H5 O LVCMOS33
TX#1 hot plug control (FPGA to TX)
TX#1_PD
G4 O LVCMOS33
TX#1 power down (FPGA to TX)
TX#1_INT
F2 I LVCMOS33
TX#1 interrupt (TX to FPGA)
TX#1_SCL
Y2 O LVCMOS33
TX#1 serial clock (FPGA to TX)
TX#1_SDA
Y1
IO
LVCMOS33
TX#1 serial data (FPGA to/from TX)
RSW0
D2 I LVCMOS33
Rotary switch 0
RSW1
D1 I LVCMOS33
Rotary switch 1
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Pin Name
No.
IO
Spec.
Description
RSW2
C3 I LVCMOS33
Rotary switch 2
RSW3
C1 I LVCMOS33
Rotary switch 3
DSW0
F5 I LVCMOS33
DIP switch 0
DSW1
K7 I LVCMOS33
DIP switch 1
DSW2
K8 I LVCMOS33
DIP switch 2
DSW3
D5 I LVCMOS33
DIP switch 3
DSW4
E4 I LVCMOS33
DIP switch 4
DSW5
J7 I LVCMOS33
DIP switch 5
DSW6
H8 I LVCMOS33
DIP switch 6
DSW7
B2 I LVCMOS33
DIP switch 7
LED0
G7 O LVCMOS33
LED0
LED1
F7 O LVCMOS33
LED1
LED2
D3 O LVCMOS33
LED2
LED3
C4 O LVCMOS33
LED3
LED4
E5 O LVCMOS33
LED4
LED5
E6 O LVCMOS33
LED5
LED6
A2 O LVCMOS33
LED6
LED7
B3 O LVCMOS33
LED7
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5.12. FPGA Input Data Phase
Figure 5-6 shows the input data phase of the FPGA on the TB-FMCH-HDMI2-TX.
FMC connector to FPGA data is captured by the FPGA at the rising edge of a video clock. Data
from the main board is transferred at the falling edge of a video clock.
HDMITX_CLK
VSYNC,HSYNC,
DE,DATA
FMC=>FPGA
Output data are synchronous with down
edge of HDMITX_CLK.
Figure 5-6 FPGA Input Data Timing
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5.13. Image Size
5.13.1. 2D Image Size
TB-FMCH-HDMI2-TX supports HDMI1.4-compliant primary format and part of secondary format
(1080p@60Hz).
Supported image size:
640x480p@59.94/60Hz
1280x720p@59.94/60Hz
1920x1080i@59.94/60Hz
720x480p @ 59.94/60Hz
720(1440)x480i@59.94/60Hz
1280x720@50Hz
1920x1080i@50Hz
720x576p@50Hz
720(1440)x576i@50Hz
1920x1080p@59.94/60Hz
1920x1080p@50Hz
5.13.2. 3D Image Size
TB-FMCH-HDMI2-RX supports HDMI1.4-compliant primary format.
Supported image size:
1280x720p@59.94/60Hz (Frame Packing, Side-by-Side(Half), Top-and-Bottom)
1280x720p@50Hz (Frame Packing, Side-by-Side(Half), Top-and-Bottom)
1280x720p@23.98/24Hz (Frame Packing)
1280x720p@23.97/30Hz (Frame Packing)
1920x1080i@59.94/60Hz (Frame Packing, Side-by-Side(Half))
1920x1080i@50Hz (Frame Packing, Side-by-Side(Half))
1920x1080p@23.98/24Hz (Frame Packing, Side-by-Side(Half), Top-and-Bottom)
1920x1080p@29.97/30Hz (Frame Packing, Top-and-Bottom)
1920x1080p@59.94/60Hz (Top-and-Bottom)
1920x1080p@50Hz (Top-and-Bottom)
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6. DDC Connection (Normal/ Through)
Two types of DDC connections are supported:
6.1. DDC Connection (Normal)
Table 6-1 shows DDC connection jumper setting (Normal) and Figure 6-1 shows DDC connection
structure.
Table 6-1 DDC Jumper Setting (Normal)
TB-FMCH-HDMI2-RX
TB-FMCH-HDMI2-TX
Jumper
Setting
Jumper
Setting
JP6: SCL0
1-2 short: Normal
-
-
JP7: SDA0
1-2 short: Normal
-
-
JP8: DDC0_5V
1-2 short: Normal
JP7: DDC0_5V
1-2 short: Normal
JP9: DDC0_HPD
1-2 short: Normal
JP8: DDC0_HPD
1-2 short: Normal
JP10: DDC0_SDA
1-2 short: Normal
JP4: DDC0_SDA
1-2 short: Normal
JP11: DDC0_SCL
1-2 short: Normal
JP5: DDC0_SCL
1-2 short: Normal
JP12: DDC0_GND
1-2 short: Normal
JP6: DDC0_GND
1-2 short: Normal
JP3: SCL1
1-2 short: Normal
-
-
JP4: SDA1
1-2 short: Normal
-
-
JP13: DDC1_5V
1-2 short: Normal
JP12: DDC1_5V
1-2 short: Normal
JP14: DDC1_HPD
1-2 short: Normal
JP13: DDC1_HPD
1-2 short: Normal
JP15: DDC1_SDA
1-2 short: Normal
JP9: DDC1_SDA
1-2 short: Normal
JP16: DDC1_SCL
1-2 short: Normal
JP10: DDC1_SCL
1-2 short: Normal
JP17: DDC1_GND
1-2 short: Normal
JP11: DDC1_GND
1-2 short: Normal
SG
HDMI
DDC_SCL
DDC_SDA
DDC_5V
DDC_GND
HOTPLUG_DET
DDC_SCL
DDC_SCA
DDC_5V
DDC_GND
DDC_HPD
RX
DDC
EEPROM
DEC
DET
DET
DDC_GND
MONITOR
HDMI
DDC_SCL
DDC_SDA
DDC_5V
DDC_GND
HOTPLUG_DET
DDC_SCL
DDC_SCA
DDC_5V
DDC_GND
DDC_HPD
TX
ENC
VCC_5V
T_SHILD
DDC
TB-FMCH-HDMI2-RX TB-FMCH-HDMI2-TX
Figure 6-1 DDC Connection Structure (Normal)
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6.2. DDC Connection (Through)
Table 6-2 shows DDC connection jumper setting (Through) and Figure 6-2 shows DDC connection
structure (Through).
Table 6-2 DDC Jumper Setting (Through)
TB-FMCH-HDMI2-RX
TB-FMCH-HDMI2-TX
Jumper
Setting
Jumper
Setting
JP6: SCL0
Open - -
JP7: SDA0
Open - -
JP8: DDC0_5V
1-2 short: Normal
JP7: DDC0_5V
1-2 short: Normal
JP9: DDC0_HPD
1-2 short: Normal
JP8: DDC0_HPD
1-2 short: Normal
JP10: DDC0_SDA
2-3 short: Through
JP4: DDC0_SDA
2-3 short: Through
JP11: DDC0_SCL
2-3 short: Through
JP5: DDC0_SCL
2-3 short: Through
JP12: DDC0_GND
2-3 short: Through
JP6: DDC0_GND
2-3 short: Through
JP3: SCL1
Open - -
JP4: SDA1
Open - -
JP13: DDC1_5V
1-2 short: Normal
JP12: DDC1_5V
1-2 short: Normal
JP14: DDC1_HPD
1-2 short: Normal
JP13: DDC1_HPD
1-2 short: Normal
JP15: DDC1_SDA
2-3 short: Through
JP9: DDC1_SDA
2-3 short: Through
JP16: DDC1_SCL
2-3 short: Through
JP10: DDC1_SCL
2-3 short: Through
JP17: DDC1_GND
2-3 short: Through
JP11: DDC1_GND
2-3 short: Through
SG
HDMI
DDC_SCL
DDC_SDA
DDC_5V
DDC_GND
HOTPLUG_DET
DDC_SCL
DDC_SCA
DDC_5V
DDC_GND
DDC_HPD
RX
DDC
EEPROM
DEC
DET
DET
DDC_GND
MONITOR
HDMI
DDC_SCL
DDC_SDA
DDC_5V
DDC_GND
HOTPLUG_DET
DDC_SCL
DDC_SCA
DDC_5V
DDC_GND
DDC_HPD
TX
ENC
VCC_5V
T_SHILD
DDC_SCL
DDC_SDA
DDC
+5V
GND
HPD
DDC_SCL
DDC_SDA
+5V
GND
HPD
DDC Cable
TB-FMCH-HDMI2-RX TB-FMCH-HDMI2-TX
Figure 6-2 DDC Connection Structure (Through)
*To select DDC connection (Through), connect RX board-J4 and TX board -J1 or RX board-J2
and TX board -J3 using an attached cable.
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7. Default Switch Setting
Figure 7-1 shows default TB-FMCH-HDMI2-RX switch settings (portions enclosed by dotted lines).
JP1
JP7、JP12、JP10、JP8
JP6、JP11、JP9
JP4、JP3、JP16、JP14
JP17、JP15、JP13
Figure 7-1 TB-FMCH-HDMI2-RX Default Switch Settings (component side)
Table 7-1 TB-FMCH-HDMI2-RX Default Settings (JP pin)
No.
Silk No.
Initial Setting
Function
1
JP6
1-2 short
SCL0 (1-2: HDMI / 2-3: FPGA)
2
JP7
1-2 short
SDA0 (1-2: HDMI / 2-3: FPGA)
3
JP8
1-2 short
DDC0_5V (1-2: Normal / 2-3: Through)
4
JP9
1-2 short
DDC0_HPD (1-2: Normal / 2-3: Through)
5
JP10
1-2 short
DDC0_SDA (1-2: Normal / 2-3: Through)
6
JP11
1-2 short
DDC0_SCL (1-2: Normal / 2-3: Through)
7
JP12
1-2 short
DDC0_GND (1-2: Normal / 2-3: Through)
8
JP3
1-2 short
SCL1 (1-2: HDMI / 2-3: FPGA)
9
JP4
1-2 short
SDA1 (1-2: HDMI / 2-3: FPGA)
10
JP13
1-2 short
DDC1_5V (1-2: Normal / 2-3: Through)
11
JP14
1-2 short
DDC1_HPD (1-2: Normal / 2-3: Through)
12
JP15
1-2 short
DDC1_SDA (1-2: Normal / 2-3: Through)
13
JP16
1-2 short
DDC1_SCL (1-2: Normal / 2-3: Through)
14
JP17
1-2 short
DDC1_GND (1-2: Normal / 2-3: Through)
15
JP1
1-2 short
12VIN_SEL (1-2: FMC connector / 2-3: External power source)
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Table 7-2 TB-FMCH-HDMI2-RX Default Setting (DSW/RSW)
No.
Silk No.
Default Setting 1 S1-1
OFF 2 S1-2
OFF 3 S1-3
OFF 4 S1-4
OFF 5 S1-5
OFF 6 S1-6
OFF 7 S1-7
OFF 8 S1-8
OFF 9 S2
0
For the setting at the time of use, refer to Table 4-7 Switches
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Figure 7-2 shows TB-FMCH-HDMI2-TX default switch settings (portions enclosed by dotted lines).
JP3
JP8、JP5、JP4、JP6
JP7
JP12
JP13、JP10、JP9、JP11
Figure 7-2 TB-FMCH-HDMI2-TX Default Settings (component side)
Table 7-3 TB-FMCH2-TX Default Settings (JP Pin)
No.
Silk No.
Initial Setting
Function
1
JP7
1-2 short
DDC0_5V (1-2: Normal / 2-3: Through)
2
JP8
1-2 short
DDC0_HPD (1-2: Normal / 2-3: Through)
3
JP4
1-2 short
DDC0_SDA (1-2: Normal / 2-3: Through)
4
JP5
1-2 short
DDC0_SCL (1-2: Normal / 2-3: Through)
5
JP6
1-2 short
DDC0_GND (1-2: Normal / 2-3: Through)
6
JP12
1-2 short
DDC1_5V (1-2: Normal / 2-3: Through)
7
JP13
1-2 short
DDC1_HPD (1-2: Normal / 2-3: Through)
8
JP9
1-2 short
DDC1_SDA (1-2: Normal / 2-3: Through)
9
JP10
1-2 short
DDC1_SCL (1-2: Normal / 2-3: Through)
10
JP11
1-2 short
DDC1_GND (1-2: Normal / 2-3: Through)
11
JP3
1-2 short
12VIN_SEL (1-2: FMC connector / 2-3: External power source)
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Table 7-4 TB-FMCH-HDMI2-TX Default Switch Settings (DSW/RSW)
No.
Silk No.
Default Setting
1
S1-1
OFF 2 S1-2
OFF 3 S1-3
OFF 4 S1-4
OFF 5 S1-5
OFF 6 S1-6
OFF 7 S1-7
OFF 8 S1-8
OFF 9 S2
0
For the setting at the time of use, refer to Table 5-7 Switch Function.
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8. Usage Example
Figure 8-1 shows a usage example.
Be careful about the jumper setting of the TB-6S-LX150T-IMG2 main board.
If the image is not output, push the S3 of the TB-FMCH-HDMI2-RX or TB-FMCH-HDMI2-TX for only
a short period of time.
RX
TB-FMCH-HDMI2-RX connects to CN4.
TB-FMCH-HDMI2-RX
TB-FMCH-HDMI2-TX
*TB-FMCH-HDMI2-RX are initial setting.
TB-FMCH-HDMI2-TX connects to CN3.
*TB-FMCH-HDMI2-TX are initial setting.
TB-6S-LX150T-IMG2
JP6, JP7 : 5-6 Short
JP1 : 1-2 Short
JP4, JP5 : 5-6 Short
JP2 : 1-2 Short
Figure 8-1 Usage Example
Table 8-1 Setting Example
No.
Silk No.
Setting
Function
1
JP1
1-2
Bank3 voltage setting (2.5V / 3.3V)
2
JP6
JP7
5-6
FMC-LPC2VADJ voltage setting (2.5V / 3.3V / none)
(Two jumpers must be always the same)
3
JP2
1-2
Bank0 voltage setting (2.5V / 3.3V)
4
JP4
JP5
5-6
FMC-LPC1 VADJ voltage setting (2.5V / 3.3V /none)
(Two jumpers must be always the same)
Note: The bold characters are the setting in the usage example.
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PLD Solution Dept. PLD Division
URL: http://solutions.inrevium.com/
E-mail: psd-support@teldevice.co.jp
HEAD Quarter: Yokohama East Square, 1-4 Kinko-cho, Kanagawa-ku, Yokohama City,
Kanagawa, Japan 221-0056
TEL: +81-45-443-4016 FAX: +81-45-443-4058
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