INOVC IA63484-PLC68I Datasheet

IA63484 Data Sheet

Advanced CRT Controller

FEATURES

• High-speed graphics

- Drawing rate: 200 ns/pixel max (color drawing)

- Commands: 38 commands including 23 graphic drawing commands:

Dot, Line, Rectangle, Poly-line, Polygon, Circle, Ellipse, Paint, Copy, etc.

- Colors: 16 bits/word: 1,2,4,8,16 bits/pixel (5 types) monochrome to 64k colors max

- Pattern RAM: 32 bytes

- Converts logical X-Y coordinate to physical address

- Color operation and conditional drawing

- Drawing area control for hardware clipping and hitting

• Large frame-memory space

- Maximum 2 Mbytes graphic memory and 128 kbytes character memory separate from MPU memory.

- Maximum Resolution: 4096 x 4096 pixels (1 bit/pixel mode)

• CRT display control

- Split Screens: three displays and one window

- Zoom: 1 to 16 times

- Scroll: vertical and horizontal

• Interleaved access mode for flashless display and superimposition

• External synchronization between ARTCs or between ACRTC and external device (TV system

or other controller.

• DMA interface

• Two programmable cursors

• Three Scan modes

- Non-interlaced

- Interlace sync

- Interlace sync and video

• Interrupt request to MPU

• 256 characters/line 32 raster/ line, 4096 rasters/screen

• Maximum clock frequency: 25MHz

• CMOS, single +5V power supply

The IA63484 is a "plug-and-play" drop-in replacement for the original Hitachi© HD63484. This replacement IC has been developed using innovASIC’s MILESTM, or Managed IC Lifetime Extension System, cloning technology. This technology produces replacement ICs far more complex than "emulation" while ensuring they are compatible with the original IC. MILESTM captures the design of a clone so it can be produced even as silicon technology advances. MILESTM also verifies the clone against the original IC so that even the "undocumented features" are duplicated. This data sheet documents all necessary engineering information about the IA63484 including functional and I/O descriptions, electrical characteristics, and applicable timing.

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IA63484 Data Sheet

Advanced CRT Controller

68 Pin Package: ACRTC PLCC PINOUT Pin Arrangement:

dack_n

dtack_n(T)

irq(O,D)

hsync_n

vsync_n

Vcc

exsync_n

Vss

d0(T) d1(T)

d2(T)

d3(T)

d4(T)

d5(T)

d6(T) d7(T)

rs

res_n

dreq_n

done_n(O,D)

27

d9(T)

d8(T)

cs_n

d10(T)

d12(T)

d11(T)

rw_n

O,D: Open Drain

T: Three State

Vcc

cud1_n

cud2_n

19

68

IA63484

Vss

d15(T)

d14(T)

d13(T)

disp1_n

disp2_n

lpstb

ra4

ma_ra18_2

ma_ra19_3

mad3(T)

mad2(T)

mad1(T)

mad0(T)

60

44

mad14(T)

mad15(T)

ma_ra17_1

ma_ra16_0

mad4(T)

chr

mrd

draw_n

as_n

mcyc

Vss

clk_2

Vcc

mad5(T)

mad6(T) mad7(T)

mad8(T)

mad9(T) mad10(T)

mad11(T)

mad12(T)

mad13(T)

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IA63484 Data Sheet

Advanced CRT Controller

BLOCK DIAGRAM

Figure 1: System Block Diagram

Figure 2 illustrates the ACRTC system environment. The following paragraphs will further describe the system block diagram and design in more detail.

MPU

(8/16b)

SYSTEM

MEMORY

DMAC

ADDRESS

DATA

res_n

irq_n

d[15:0]

dtack_n

cs_n

rs

rw_n

dreq_n

dack_n

done_n

CONTROL

clk_2

Vss

Vcc

ACRTC

as_n

mrd

disp2_n

disp1_n

cud2_n

cud1_n

lpstb

exsync_n

vsync_n

hsync_n

ma[19:16]

mad[15:0]

FRAME

L

BUFFER

2MB, MAX

DOT SHIFTER

CRT

VIDEO

SIGNAL

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IA63484 Data Sheet

cs_nIChip Select: enables transfers between the host and the ACRTC.

clk_2

I/O

ARTC clock: is the baasic operating clock, twice the frequency of the dot clock.

-*

Higer-order

address

bits/character

screen

rastar

address:MA16/R0-

MA19/RA3

are

Higer-order

character

screen

rastar

address

bit:isthe

high

bitofthe

character

screen

MPU

Advanced CRT Controller

I/O SIGNAL DESCRIPTION:

The diagram below describes the I/O characteristics for each signal on the IC. The signal names correspond to the signal names on the pinout diagrams provided.

I/O Characteristics:

Signal Name I/O Group Description

res_n I ACRTC reset:

d[15,0] rw_n I Read/write strobe: controls the direction of host/ACRTC transformers.

I/O

Databus (three state): are the bidirectional data bus to the host mpu or dmac. D0-D are used in 8-bit data bus mode.

rs

dtack_n

irq_n dreq_n I DMA request: recieves DMA acknowledge timing from the host DMAC. dack I/O DMA acknoledge:

done_n

mad[15,0] as_n O Address strobe: output demultiplexes the address/data bus.

MA16/R0

MA19/RA

RA

chr

mcyc mrd O Frame buffer memory read: output controls the frame buffer data bus direction.

draw_n

disp1, disp2

cud1, cud2 vsync_n O CRT vertical sync pulse: outputs the crt vertical synchronization pulse. hsync_n CRT horizontal sync pulse: outputs the crt horizontal synchronization pulse.

exsync_n lpstb I Lightpen strobe: is the lightpen input

3

4

I

O

I

O

I/O

Interface

DMAC

Interface

CRT

Interface

Register Select: selectsthe ACRTC register to be accessed. It isusually connected to

the least significant bit of the host address bus.

Data transfer acknowledge (three state): output provides asynchronous bus cycle

timing. It is compatible with the HD68000 mpu dtack output.

Interrupt request (open drain): output generates interrupt service requests to the

host MPU.

DMA done: terminates DMA transfer. It is compatible with the HD68450 DMAC DONE signal.

Multiplexed frame buffer address/data bus: are the multiplexed frame buffer address/data bus.

the upper bits of the graphics screen ddress multiplexed with th lower bits of the character screen raster address.

raster address (up to 32 rasters.) Graphic or character screen access: output indicates whether a graphic or character

screen is being accessed. Frame buffer memory acess timing signal: is the frame buffer access timing output, 1/2 the frequency of clk_2.

Draw/refresh signal: output differentiates between drawing and CRT displayrefresh cycles. Display enable: programmable display enable outputs can enable, disable, and blanck logical screens. Coursor Display: outputs provides cursor timing programmed by ACRTC parameters such as cursor definition, cursor mode, cursor address, etc.

External sync:allows synchronization between multiple ACRTSs and other videro signal generators.

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IA63484 Data Sheet

Advanced CRT Controller

Figure 2: ACRTC Block Diagram

res_n

dreq_n

DMA

dack_n

done_n

irq_n

Control

Unit

Interrupt

Control

Unit

16

d[15:0]

cs_n

rs_n

rw_n

dtack_n

MPU

Interface

ACRTC System Description:

Register Address

Data

Drawing

Processor

Display

Processor

Timing

Processor

23

25

V

cc

SS

20

16

20

15

2

draw_adrs[19:0]

draw_data[15:0]

draw_en

write

disp_adrs[19:0]

raster_adrs[4:0]

chr_int

ccud

lpstb

gcud[1:0]

hsync

vsync

exsync

disp[1:0]

m_cyc

as

clk2

CRT

Interface

draw_n mrd

16

4

2

mad[15:0]

ma19_16_ra[3:0]

ra4

chr

lpstb

cud1_n, cud2_n

hsync_n vsync_n exsync_n

disp1_n, disp2_n

mcyc as_n clk_2

Some CRT controllers provide a single bus interface to the frame buffer that must be shared with the host MPU. However, refreshing large frame buffers, and accessing the frame buffer for drawing operations can quickly saturate the shared bus.

The ACRTC uses separate host MPU and frame buffer interfaces. This allows the ACRTC full access to the frame buffer for display refresh and drawing operations and minimizes the use of the MPU system bus by the ACRTC. A related benefit is that a large frame buffer (2 MB for each ACRTC) can be used, even if the host MPU has a smaller address space or segment size restriction.

The ACRTC can use an external Direct Memory Access Controller (DMAC) to increase system throughput when many commands, parameters and data must be transferred to the ACRTC. Advanced DMAC features such as the HD68450 “chaining” modes can be used to develop powerful graphics system architectures.

More cost-sensitive or less performance-sensitive applications might not require a DMAC. In these cases, the interface to the ACRTC can be handled under MPU software control.

While both ACRTC bus interfaces (host MPU and frame buffer) are 16 bits wide, the ACRTC also offers an 8 bit MPU mode for easy connection to popular 8 bit busses.

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IA63484 Data Sheet

Advanced CRT Controller

FUNCTIONAL REQUIREMENTS:

Drawing Processor:

The Drawing Processor performs drawing operations on the frame buffer memory upon interpreting commands and command parameters issued by the host bus (MPU or DMAC). The drawing processor then executes ACRTC drawing algorithms and converts lo gical X-Y addresses to physical frame buffer addresses.

The drawing processor uses three operation control units; the Drawing Algorithm Control unit, the Drawing Address Generation unit and the Logical Operation unit.

The Drawing Algorithm Control Unit int erprets graphic commands and parameters and executes the appropriate micro-programmed drawing algorithm. This control unit calculates coordinates using logical pixel X-Y addressing.

The Drawing Address Generation Unit converts logical X-Y addresses from the Drawing Algorithm Control unit to a bit address in the frame buffer. The frame buffer is organized as sequential 16 bit words. The bit address consists of 20 bits and bits 0-4 specifying the logical pixel bit address within the physical frame buffer word.

Logical Operation Unit, using the address calculated in the drawing algorithm control and drawing address generation units, performs logical operations between the existing read data in the frame buffer and the drawing pattern in the pattern RAM, and rewrites the results into the frame buffer. A detailed description of the Drawing Processor is contained in its module specification.

Display Processor:

The display processor manages frame buffer refresh addressing based on the user specified display screen organization. It combines and displays as many as 4 independent screen segments (3 horizontal split screens and 1 window) using an internal high-speed address calculation unit. It controls display refresh outputs in graphic (physical frame buffer address) or character (physical refresh memory address and row address) modes.

Display Functions:

The ACRTC allows the frame buffer to be divided into four separate logical screens:

• Upper

• Base

• Lower

• Window

In the simplest case, only the base screen parameters must be defined. Other screens may be selectively enabled, disabled, and blanked under software control.

The background screens (upper, base, and lower) split the screen into three horizontal partitions whose positions are fully programmable. The window screen is unique, since the ACRTC usually gives it higher priority than the background screens. A typical application might be to use the base screen for the bulk of the user interaction, while using the upper screen for pull-down menus and the lower screen for status line indicators. The exception is in the ACRTC superimpose mode, in which the window has the same priority as the background screens. In this mode, the window and

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IA63484 Data Sheet

Advanced CRT Controller

background screens are superimposed on the display. Figure 3 is an example of the screen combinations.

Figure 3: Screen Combination Examples

Screen Number 0 1 2 3

Upper

Base

Lower

Screen Name Screen Group Upper Screen Base Screen Lower Screen Window Screen

Window

Upper Upper

Base

Background Screen

Base

Window

Lower

Window

Lower

Display Control:

The ACRTC can have two types of external frame memory: 2 Mbyte frame buffer and 128 kbyte refresh memory. The chr signal controls which memory is accessed.

Each screen has its own memory width, vertical display width, and character/graphic attribution set by the control registers. Horizontal display control registers are set in units of memory cycles. Vertical display control registers are set in units of rasters. Figure 4 illustrates the relation between the frame memory and the display screens, while Figure 5 illustrates the timing.

Note that display width of registers marked with an (*) in Figure 4 is:

Display width = Register value + 1 memory cycle.

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IA63484 Data Sheet

Advanced CRT Controller

Figure 4: Frame Memory and Display Screens

Frame Memory Image

Refresh Memory

(Character)

$0000

MW0

$FFFF

$00000

Frame Buffer

(Graphic)

SA0

SA2

SA1

File Name: MOS

MW2

Left : Layout Right : Symbol

MW1

File Name: MOS

MW3

SA3

Left : Layout Right : Symbol

$FFFFF

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IA63484 Data Sheet

Advanced CRT Controller

Figure 5: Display Screen Specification

HC*

hsync_n

HWS* HWW*

HDS*HSW HDW*

Display Screen Period

(Upper)

(Base) (Base)

(Lower)

(Window)

vsync_n

VDS SP0 SP1 SP2

VC

VSWVWS VWW

Timing Processor:

The Timing Processor generates the CRT synchronization signals and signals used internally by the ACRTC. The details for this block are contained in the module specification for the Display Processor.

CRT Interface:

The CRT Interface manages the communication between the frame buffer, the light pen and the CRT. The frame buffer interface manages the frame buffer bus and selects display drawing or refreshes address outputs. The light pen interface uses a 20-bit address register and a strobe input pin (lpstb).

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IA63484 Data Sheet

Advanced CRT Controller

Frame Buffer Interface:

The ACRTC allows for two types of independent frame memories. The first type is up to a 2 Mbyte frame buffer and the second is a 128 Kbytes refresh memory. The chr output pin can access either the Graphic or Character screen.

The width of the frame memory is defined by setting-up the memory width register (mwr) and independently, the horizontal display width is defined by the horizontal display register (hdr). This allows for the frame buffer area to be bigger than the display area; reference Figure 6.

Figure 6: Frame Memory and Display Screen Area

Memory Width

Start Address

Vertical

Display Screen Area

Display Width

The ACRTC has two ways to access the frame memory (or buffer); (1) Display Memory Access (three types) and (2) Graphic Address Increment mode.

Display Memory Access Modes:

In Single Access Mode, a display or drawing cycle is defined as two cycles of clk_2. During the first cycle, the frame buffer display or drawing address is output. During the second clk_2 cycle, the frame buffer data is read (display cycles and/or drawing cycles) or written (drawing cycles).

Display and drawing cycles contend for access to the frame buffer. The ACRTC allows the priority to be defined as display priority or drawing priority. If display has priority, drawing cycles are only allowed to occur during the horizontal or vertical fly back periods (a ‘flash less’ display is obtained). If drawing has priority, drawing may occur during display (display may flash).

text

Horizontal Display Width

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INOVC IA63484-PLC68I Datasheet

Specifications and Main Features

Frequently Asked Questions

User Manual