Infineon Technologies XC161 User Manual

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User’s Manual, V2.2, Jan. 2004

XC161

16-Bit Single-Chip Microcontroller with C166SV2 Core

Volume 2 (of 2): Peripheral Units

Microcontrollers

Never stop thinking.

Edition 2004-01 Published by Infineon Technologies AG,

St.-Martin-Strasse 53, 81669 München, Germany

Attention please!

The information herein is given to describe certain components and shall not be considered as a guarantee of characteristics.

Terms of delivery and rights to technical change reserved. We hereby disclaim any and all warranties, including but not limited to warranties of non-infringement, regarding

circuits, descriptions and charts stated herein.

Information

For further information on technology, delivery terms and conditions and prices please contact your nearest Infineon Technologies Office (www.infineon.com).

Warnings

Due to technical requirements components may contain dangerous substances. For information on the types in question please contact your nearest Infineon Technologies Office.

Infineon Technologies Components may only be used in life-support devices or systems with the express written approval of Infineon Technologies, if a failure of such components can reasonably be expected to cause the failure of that life-support device or system, or to affect the safety or effectiveness of that device or system. Life support devices or systems are intended to be implanted in the human body, or to support and/or maintain and sustain and/or protect human life. If they fail, it is reasonable to assume that the health of the user or other persons may be endangered.

User’s Manual, V2.2, Jan. 2004

XC161

16-Bit Single-Chip Microcontroller with C166SV2 Core

Volume 2 (of 2): Peripheral Units

Microcontrollers

Never stop thinking.

XC161 Volume 2 (of 2): Peripheral Units

Revision History: V2.2, 2004-01

Previous Version: V2.2, 2003-09 (Pre-release)

V2.1, 2003-06 V2.0, 2003-03 V1.1, 2002-02 (Draft Manual) V1.0, 2001-04 (Draft Manual)

Page Subjects (major changes since version V2.1)

14-1ff Timer block description introduced 14-7 Phrasing improved 14-26 Figure corrected 14-27 Prescaler table reworked 14-29 Timer register description added 14-35 Phrasing improved 14-50 Prescaler table reworked

14-53 Timer register description added 17-1ff Register names adapted

1) In order to create the current version V2.2 of this manual, the layout of several graphics and text structures has been adapted to company documentation rules. The contents have not been changed otherwise, except for the Pre-release note on page 1-2 or obvious typographical errors.

Controller Area Network (CAN): License of Robert Bosch GmbH

We Listen to Your Comments

Any information within this document that you feel is wrong, unclear or missing at all? Your feedback will help us to continuously improve the quality of this document. Please send your proposal (including a reference to this document) to:

mcdocu.comments@infineon.com

Template: mc_tmplt_a5.fm / 3 / 2003-09-01

XC161 Derivatives

Peripheral Units (Vol. 2 of 2)

Table of Contents Page

This User’s Manual consists of two Volumes, “System Units” and “Peripheral Units”. For your convenience this table of contents (and also the keyword index) lists both volumes, so can immediately find the reference to the desired section in the corresponding document ([1] or [2]).

1 Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1-1 [1]

1.1 Members of the 16-bit Microcontroller Family . . . . . . . . . . . . . . . . . . . 1-3 [1]

1.2 Summary of Basic Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1-5 [1]

1.3 Abbreviations . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1-9 [1]

1.4 Naming Conventions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1-10 [1]

2 Architectural Overview . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-1 [1]

2.1 Basic CPU Concepts and Optimizations . . . . . . . . . . . . . . . . . . . . . . . 2-2 [1]

2.1.1 High Instruction Bandwidth/Fast Execution . . . . . . . . . . . . . . . . . . . 2-4 [1]

2.1.2 Powerful Execution Units . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-5 [1]

2.1.3 High Performance Branch-, Call-, and Loop-Processing . . . . . . . . . 2-6 [1]

2.1.4 Consistent and Optimized Instruction Formats . . . . . . . . . . . . . . . . 2-7 [1]

2.1.5 Programmable Multiple Priority Interrupt System . . . . . . . . . . . . . . 2-8 [1]

2.1.6 Interfaces to System Resources . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-9 [1]

2.2 On-Chip System Resources . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-10 [1]

2.3 On-Chip Peripheral Blocks . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-14 [1]

2.4 Clock Generation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-29 [1]

2.5 Power Management Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-29 [1]

2.6 On-Chip Debug Support (OCDS) . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-31 [1]

2.7 Protected Bits . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-32 [1]

3 Memory Organization . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-1 [1]

3.1 Address Mapping . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-3 [1]

3.2 Special Function Register Areas . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-4 [1]

3.3 Data Memory Areas . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-8 [1]

3.4 Program Memory Areas . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-10 [1]

3.5 System Stack . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-12 [1]

3.6 IO Areas . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-13 [1]

3.7 External Memory Space . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-14 [1]

3.8 Crossing Memory Boundaries . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-15 [1]

3.9 The On-Chip Program Flash Module . . . . . . . . . . . . . . . . . . . . . . . . . 3-16 [1]

3.9.1 Flash Operating Modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-18 [1]

3.9.2 Command Sequences . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-19 [1]

3.9.3 Error Correction and Data Integrity . . . . . . . . . . . . . . . . . . . . . . . . 3-25 [1]

3.9.4 Protection and Security Features . . . . . . . . . . . . . . . . . . . . . . . . . 3-27 [1]

3.9.5 Flash Status Information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-32 [1]

3.9.6 Operation Control and Error Handling . . . . . . . . . . . . . . . . . . . . . . 3-35 [1]

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3.10 Program Memory Control . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-37 [1]

3.10.1 Address Map . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-38 [1]

3.10.2 Flash Memory Access . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-39 [1]

3.10.3 IMB Control Functions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-41 [1]

4 Central Processing Unit (CPU) . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4-1 [1]

4.1 Components of the CPU . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4-4 [1]

4.2 Instruction Fetch and Program Flow Control . . . . . . . . . . . . . . . . . . . . 4-5 [1]

4.2.1 Branch Detection and Branch Prediction Rules . . . . . . . . . . . . . . . . 4-7 [1]

4.2.2 Correctly Predicted Instruction Flow . . . . . . . . . . . . . . . . . . . . . . . . 4-7 [1]

4.2.3 Incorrectly Predicted Instruction Flow . . . . . . . . . . . . . . . . . . . . . . . 4-9 [1]

4.3 Instruction Processing Pipeline . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4-11 [1]

4.3.1 Pipeline Conflicts Using General Purpose Registers . . . . . . . . . . . 4-13 [1]

4.3.2 Pipeline Conflicts Using Indirect Addressing Modes . . . . . . . . . . . 4-15 [1]

4.3.3 Pipeline Conflicts Due to Memory Bandwidth . . . . . . . . . . . . . . . . 4-17 [1]

4.3.4 Pipeline Conflicts Caused by CPU-SFR Updates . . . . . . . . . . . . . 4-20 [1]

4.4 CPU Configuration Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4-26 [1]

4.5 Use of General Purpose Registers . . . . . . . . . . . . . . . . . . . . . . . . . . 4-29 [1]

4.5.1 GPR Addressing Modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4-31 [1]

4.5.2 Context Switching . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4-33 [1]

4.6 Code Addressing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4-37 [1]

4.7 Data Addressing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4-39 [1]

4.7.1 Short Addressing Modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4-39 [1]

4.7.2 Long Addressing Modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4-41 [1]

4.7.3 Indirect Addressing Modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4-45 [1]

4.7.4 DSP Addressing Modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4-47 [1]

4.7.5 The System Stack . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4-53 [1]

4.8 Standard Data Processing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4-57 [1]

4.8.1 16-bit Adder/Subtracter, Barrel Shifter, and 16-bit Logic Unit . . . . 4-61 [1]

4.8.2 Bit Manipulation Unit . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4-61 [1]

4.8.3 Multiply and Divide Unit . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4-63 [1]

4.9 DSP Data Processing (MAC Unit) . . . . . . . . . . . . . . . . . . . . . . . . . . . 4-65 [1]

4.9.1 Representation of Numbers and Rounding . . . . . . . . . . . . . . . . . . 4-66 [1]

4.9.2 The 16-bit by 16-bit Signed/Unsigned Multiplier and Scaler . . . . . 4-67 [1]

4.9.3 Concatenation Unit . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4-67 [1]

4.9.4 One-bit Scaler . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4-67 [1]

4.9.5 The 40-bit Adder/Subtracter . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4-67 [1]

4.9.6 The Data Limiter . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4-68 [1]

4.9.7 The Accumulator Shifter . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4-68 [1]

4.9.8 The 40-bit Signed Accumulator Register . . . . . . . . . . . . . . . . . . . . 4-69 [1]

4.9.9 The MAC Unit Status Word MSW . . . . . . . . . . . . . . . . . . . . . . . . . 4-70 [1]

4.9.10 The Repeat Counter MRW . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4-72 [1]

4.10 Constant Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4-74 [1]

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5 Interrupt and Trap Functions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5-1 [1]

5.1 Interrupt System Structure . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5-2 [1]

5.2 Interrupt Arbitration and Control . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5-4 [1]

5.3 Interrupt Vector Table . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5-10 [1]

5.4 Operation of the Peripheral Event Controller Channels . . . . . . . . . . 5-18 [1]

5.4.1 The PEC Source and Destination Pointers . . . . . . . . . . . . . . . . . . 5-22 [1]

5.4.2 PEC Transfer Control . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5-24 [1]

5.4.3 Channel Link Mode for Data Chaining . . . . . . . . . . . . . . . . . . . . . . 5-26 [1]

5.4.4 PEC Interrupt Control . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5-27 [1]

5.5 Prioritization of Interrupt and PEC Service Requests . . . . . . . . . . . . 5-29 [1]

5.6 Context Switching and Saving Status . . . . . . . . . . . . . . . . . . . . . . . . 5-31 [1]

5.7 Interrupt Node Sharing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5-34 [1]

5.8 External Interrupts . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5-35 [1]

5.9 OCDS Requests . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5-40 [1]

5.10 Service Request Latency . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5-41 [1]

5.11 Trap Functions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5-43 [1]

6 General System Control Functions . . . . . . . . . . . . . . . . . . . . . . . . . 6-1 [1]

6.1 System Reset . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6-2 [1]

6.1.1 Reset Sources and Phases . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6-3 [1]

6.1.2 Status After Reset . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6-6 [1]

6.1.3 Application-Specific Initialization Routine . . . . . . . . . . . . . . . . . . . 6-11 [1]

6.1.4 System Startup Configuration . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6-14 [1]

6.1.5 Hardware Configuration in External Start Mode . . . . . . . . . . . . . . 6-18 [1]

6.1.6 Default Configuration in Single-Chip Mode . . . . . . . . . . . . . . . . . . 6-23 [1]

6.1.7 Reset Behavior Control . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6-24 [1]

6.2 Clock Generation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6-26 [1]

6.2.1 Oscillators . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6-27 [1]

6.2.2 Clock Generation and Frequency Control . . . . . . . . . . . . . . . . . . . 6-30 [1]

6.2.3 Clock Distribution . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6-37 [1]

6.2.4 Oscillator Watchdog . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6-38 [1]

6.2.5 Interrupt Generation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6-38 [1]

6.2.6 Generation of an External Clock Signal . . . . . . . . . . . . . . . . . . . . 6-39 [1]

6.3 Central System Control Functions . . . . . . . . . . . . . . . . . . . . . . . . . . . 6-43 [1]

6.3.1 Status Indication . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6-45 [1]

6.3.2 Reset Source Indication . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6-46 [1]

6.3.3 Peripheral Shutdown Handshake . . . . . . . . . . . . . . . . . . . . . . . . . 6-47 [1]

6.3.4 Flexible Peripheral Management . . . . . . . . . . . . . . . . . . . . . . . . . . 6-47 [1]

6.3.5 Debug System Control . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6-49 [1]

6.3.6 Register Security Mechanism . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6-51 [1]

6.4 Watchdog Timer (WDT) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6-55 [1]

6.5 Identification Control Block . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6-60 [1]

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7 Parallel Ports . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7-1 [1]

7.1 Input Threshold Control . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7-2 [1]

7.2 Output Driver Control . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7-3 [1]

7.3 Alternate Port Functions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7-8 [1]

7.4 PORT0 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7-9 [1]

7.5 PORT1 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7-13 [1]

7.6 Port 2 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7-24 [1]

7.7 Port 3 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7-29 [1]

7.8 Port 4 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7-41 [1]

7.9 Port 5 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7-51 [1]

7.10 Port 6 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7-54 [1]

7.11 Port 7 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7-65 [1]

7.12 Port 9 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7-72 [1]

7.13 Port 20 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7-82 [1]

8 Dedicated Pins . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8-1 [1]

9 The External Bus Controller EBC . . . . . . . . . . . . . . . . . . . . . . . . . . 9-1 [1]

9.1 External Bus Signals . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9-3 [1]

9.2 Timing Principles . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9-4 [1]

9.2.1 Basic Bus Cycle Protocols . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9-4 [1]

9.2.1.1 Demultiplexed Bus . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9-5 [1]

9.2.1.2 Multiplexed Bus . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9-6 [1]

9.2.2 Bus Cycle Phases . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9-7 [1]

9.2.2.1 A Phase - CS

9.2.2.2 B Phase - Address Setup/ALE Phase . . . . . . . . . . . . . . . . . . . . . 9-7 [1]

9.2.2.3 C Phase - Delay Phase . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9-7 [1]

9.2.2.4 D Phase - Write Data Setup/MUX Tristate Phase . . . . . . . . . . . . 9-7 [1]

9.2.2.5 E Phase - RD/WR Command Phase . . . . . . . . . . . . . . . . . . . . . . 9-7 [1]

9.2.2.6 F Phase - Address/Write Data Hold Phase . . . . . . . . . . . . . . . . . 9-8 [1]

9.2.3 Bus Cycle Examples: Fastest Access Cycles . . . . . . . . . . . . . . . . . 9-8 [1]

9.3 Functional Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9-10 [1]

9.3.1 Configuration Register Overview . . . . . . . . . . . . . . . . . . . . . . . . . . 9-10 [1]

9.3.2 The EBC Mode Register 0 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9-12 [1]

9.3.3 The EBC Mode Register 1 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9-14 [1]

9.3.4 The Timing Configuration Registers TCONCSx . . . . . . . . . . . . . . 9-15 [1]

9.3.5 The Function Configuration Registers FCONCSx . . . . . . . . . . . . . 9-16 [1]

9.3.6 The Address Window Selection Registers ADDRSELx . . . . . . . . . 9-18 [1]

9.3.6.1 Definition of Address Areas . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9-18 [1]

9.3.6.2 Address Window Arbitration . . . . . . . . . . . . . . . . . . . . . . . . . . . 9-20 [1]

9.3.7 Ready Controlled Bus Cycles . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9-21 [1]

9.3.7.1 General . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9-21 [1]

9.3.7.2 The Synchronous/Asynchronous READY . . . . . . . . . . . . . . . . . 9-22 [1]

Change Phase . . . . . . . . . . . . . . . . . . . . . . . . . . . 9-7 [1]

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9.3.7.3 Combining the READY Function with Predefined Wait States . 9-22 [1]

9.3.8 Access Control to TwinCAN . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9-23 [1]

9.3.9 External Bus Arbitration . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9-24 [1]

9.3.9.1 Initialization of Arbitration . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9-24 [1]

9.3.9.2 Arbitration Master Scheme . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9-24 [1]

9.3.9.3 Arbitration Slave Scheme . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9-26 [1]

9.3.9.4 Bus Lock Function . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9-27 [1]

9.3.9.5 Direct Master Slave Connection . . . . . . . . . . . . . . . . . . . . . . . . 9-27 [1]

9.3.10 Shutdown Control . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9-28 [1]

9.4 LXBus Access Control and Signal Generation . . . . . . . . . . . . . . . . . 9-29 [1]

9.5 EBC Register Table . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9-29 [1]

10 The Bootstrap Loader . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10-1 [1]

10.1 Entering the Bootstrap Loader . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10-2 [1]

10.2 Loading the Startup Code . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10-4 [1]

10.3 Exiting Bootstrap Loader Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10-4 [1]

10.4 Choosing the Baudrate for the BSL . . . . . . . . . . . . . . . . . . . . . . . . . 10-5 [1]

11 Debug System . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11-1 [1]

11.1 Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11-1 [1]

11.2 Debug Interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11-2 [1]

11.3 OCDS Module . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11-3 [1]

11.3.1 Debug Events . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11-5 [1]

11.3.2 Debug Actions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11-6 [1]

11.4 Cerberus . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11-7 [1]

11.4.1 Functional Overview . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11-7 [1]

11.5 Emulation Device . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11-9 [1]

12 Instruction Set Summary . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12-1 [1]

13 Device Specification . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13-1 [1]

14 The General Purpose Timer Units . . . . . . . . . . . . . . . . . . . . . . . . . 14-1 [2]

14.1 Timer Block GPT1 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14-2 [2]

14.1.1 GPT1 Core Timer T3 Control . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14-4 [2]

14.1.2 GPT1 Core Timer T3 Operating Modes . . . . . . . . . . . . . . . . . . . . . 14-8 [2]

14.1.3 GPT1 Auxiliary Timers T2/T4 Control . . . . . . . . . . . . . . . . . . . . . 14-15 [2]

14.1.4 GPT1 Auxiliary Timers T2/T4 Operating Modes . . . . . . . . . . . . . 14-18 [2]

14.1.5 GPT1 Clock Signal Control . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14-27 [2]

14.1.6 GPT1 Timer Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14-29 [2]

14.1.7 Interrupt Control for GPT1 Timers . . . . . . . . . . . . . . . . . . . . . . . . 14-30 [2]

14.2 Timer Block GPT2 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14-31 [2]

14.2.1 GPT2 Core Timer T6 Control . . . . . . . . . . . . . . . . . . . . . . . . . . . 14-33 [2]

14.2.2 GPT2 Core Timer T6 Operating Modes . . . . . . . . . . . . . . . . . . . . 14-36 [2]

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14.2.3 GPT2 Auxiliary Timer T5 Control . . . . . . . . . . . . . . . . . . . . . . . . 14-39 [2]

14.2.4 GPT2 Auxiliary Timer T5 Operating Modes . . . . . . . . . . . . . . . . . 14-41 [2]

14.2.5 GPT2 Register CAPREL Operating Modes . . . . . . . . . . . . . . . . . 14-45 [2]

14.2.6 GPT2 Clock Signal Control . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14-50 [2]

14.2.7 GPT2 Timer Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14-53 [2]

14.2.8 Interrupt Control for GPT2 Timers and CAPREL . . . . . . . . . . . . . 14-54 [2]

14.3 Interfaces of the GPT Module . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14-55 [2]

15 Real Time Clock . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15-1 [2]

15.1 Defining the RTC Time Base . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15-2 [2]

15.2 RTC Run Control . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15-5 [2]

15.3 RTC Operating Modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15-7 [2]

15.3.1 48-bit Timer Operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15-10 [2]

15.3.2 System Clock Operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15-10 [2]

15.3.3 Cyclic Interrupt Generation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15-11 [2]

15.4 RTC Interrupt Generation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15-12 [2]

16 The Analog/Digital Converter . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16-1 [2]

16.1 Mode Selection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16-3 [2]

16.1.1 Compatibility Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16-3 [2]

16.1.2 Enhanced Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16-5 [2]

16.2 ADC Operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16-8 [2]

16.2.1 Fixed Channel Conversion Modes . . . . . . . . . . . . . . . . . . . . . . . . 16-11 [2]

16.2.2 Auto Scan Conversion Modes . . . . . . . . . . . . . . . . . . . . . . . . . . . 16-12 [2]

16.2.3 Wait for Read Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16-13 [2]

16.2.4 Channel Injection Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16-14 [2]

16.3 Automatic Calibration . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16-17 [2]

16.4 Conversion Timing Control . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16-18 [2]

16.5 A/D Converter Interrupt Control . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16-21 [2]

16.6 Interfaces of the ADC Module . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16-22 [2]

17 Capture/Compare Units . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17-1 [2]

17.1 The CAPCOM Timers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17-4 [2]

17.2 CAPCOM Timer Interrupts . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17-9 [2]

17.3 Capture/Compare Channels . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17-10 [2]

17.4 Capture Mode Operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17-13 [2]

17.5 Compare Mode Operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17-14 [2]

17.5.1 Compare Mode 0 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17-15 [2]

17.5.2 Compare Mode 1 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17-15 [2]

17.5.3 Compare Mode 2 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17-18 [2]

17.5.4 Compare Mode 3 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17-18 [2]

17.5.5 Double-Register Compare Mode . . . . . . . . . . . . . . . . . . . . . . . . 17-22 [2]

17.6 Compare Output Signal Generation . . . . . . . . . . . . . . . . . . . . . . . . 17-25 [2]

17.7 Single Event Operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17-27 [2]

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17.8 Staggered and Non-Staggered Operation . . . . . . . . . . . . . . . . . . . . 17-29 [2]

17.9 CAPCOM Interrupts . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17-34 [2]

17.10 External Input Signal Requirements . . . . . . . . . . . . . . . . . . . . . . . . 17-36 [2]

17.11 Interfaces of the CAPCOM Units . . . . . . . . . . . . . . . . . . . . . . . . . . . 17-37 [2]

18 Asynchronous/Synchronous Serial Interface (ASC) . . . . . . . . . . 18-1 [2]

18.1 Operational Overview . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18-3 [2]

18.2 Asynchronous Operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18-5 [2]

18.2.1 Asynchronous Data Frames . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18-6 [2]

18.2.2 Asynchronous Transmission . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18-9 [2]

18.2.3 Transmit FIFO Operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18-9 [2]

18.2.4 Asynchronous Reception . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18-12 [2]

18.2.5 Receive FIFO Operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18-12 [2]

18.2.6 FIFO Transparent Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18-15 [2]

18.2.7 IrDA Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18-16 [2]

18.2.8 RxD/TxD Data Path Selection in Asynchronous Modes . . . . . . . 18-17 [2]

18.3 Synchronous Operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18-19 [2]

18.3.1 Synchronous Transmission . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18-20 [2]

18.3.2 Synchronous Reception . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18-20 [2]

18.3.3 Synchronous Timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18-20 [2]

18.4 Baudrate Generation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18-22 [2]

18.4.1 Baudrate in Asynchronous Mode . . . . . . . . . . . . . . . . . . . . . . . . . 18-22 [2]

18.4.2 Baudrate in Synchronous Mode . . . . . . . . . . . . . . . . . . . . . . . . . 18-26 [2]

18.5 Autobaud Detection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18-27 [2]

18.5.1 General Operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18-27 [2]

18.5.2 Serial Frames for Autobaud Detection . . . . . . . . . . . . . . . . . . . . . 18-28 [2]

18.5.3 Baudrate Selection and Calculation . . . . . . . . . . . . . . . . . . . . . . . 18-29 [2]

18.5.4 Overwriting Registers on Successful Autobaud Detection . . . . . 18-33 [2]

18.6 Hardware Error Detection Capabilities . . . . . . . . . . . . . . . . . . . . . . 18-34 [2]

18.7 Interrupts . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18-35 [2]

18.8 Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18-39 [2]

18.9 Interfaces of the ASC Modules . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18-56 [2]

19 High-Speed Synchronous Serial Interface (SSC) . . . . . . . . . . . . 19-1 [2]

19.1 Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19-1 [2]

19.2 Operational Overview . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19-1 [2]

19.2.1 Operating Mode Selection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19-3 [2]

19.2.2 Full-Duplex Operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19-8 [2]

19.2.3 Half-Duplex Operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19-11 [2]

19.2.4 Continuous Transfers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19-12 [2]

19.2.5 Baudrate Generation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19-12 [2]

19.2.6 Error Detection Mechanisms . . . . . . . . . . . . . . . . . . . . . . . . . . . 19-14 [2]

19.2.7 SSC Register Summary . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19-16 [2]

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19.2.8 Port Configuration Requirements . . . . . . . . . . . . . . . . . . . . . . . . 19-17 [2]

19.3 Interfaces of the SSC Modules . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19-18 [2]

20 IIC-Bus Module . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20-1 [2]

20.1 Overview . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20-2 [2]

20.2 Register Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20-5 [2]

20.3 IIC-Bus Module Operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20-12 [2]

20.3.1 Operation in Single-Master Mode . . . . . . . . . . . . . . . . . . . . . . . . 20-12 [2]

20.3.2 Operation in Multimaster Mode . . . . . . . . . . . . . . . . . . . . . . . . . . 20-12 [2]

20.3.3 Operation in Slave Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20-13 [2]

20.3.4 Transmit/Receive Buffer . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20-14 [2]

20.3.5 Baud Rate Generation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20-15 [2]

20.3.6 Notes for Programming the IIC-Bus Module . . . . . . . . . . . . . . . . 20-16 [2]

20.4 Interrupt Request Operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20-17 [2]

20.5 Port Connection and Configuration . . . . . . . . . . . . . . . . . . . . . . . . . 20-19 [2]

20.6 Interfaces of the IIC-Bus Module . . . . . . . . . . . . . . . . . . . . . . . . . . . 20-21 [2]

20.7 IIC-Bus Overview . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20-22 [2]

21 TwinCAN Module . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21-1 [2]

21.1 Kernel Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21-1 [2]

21.1.1 Overview . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21-1 [2]

21.1.2 TwinCAN Control Shell . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21-4 [2]

21.1.2.1 Initialization Processing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21-4 [2]

21.1.2.2 Interrupt Request Compressor . . . . . . . . . . . . . . . . . . . . . . . . . 21-5 [2]

21.1.2.3 Global Control and Status Logic . . . . . . . . . . . . . . . . . . . . . . . . 21-6 [2]

21.1.3 CAN Node Control Logic . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21-7 [2]

21.1.3.1 Overview . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21-7 [2]

21.1.3.2 Timing Control Unit . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21-9 [2]

21.1.3.3 Bitstream Processor . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21-11 [2]

21.1.3.4 Error Handling Logic . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21-11 [2]

21.1.3.5 Node Interrupt Processing . . . . . . . . . . . . . . . . . . . . . . . . . . . 21-12 [2]

21.1.3.6 Message Interrupt Processing . . . . . . . . . . . . . . . . . . . . . . . . 21-13 [2]

21.1.3.7 Interrupt Indication . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21-13 [2]

21.1.4 Message Handling Unit . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21-15 [2]

21.1.4.1 Arbitration and Acceptance Mask Register . . . . . . . . . . . . . . . 21-16 [2]

21.1.4.2 Handling of Remote and Data Frames . . . . . . . . . . . . . . . . . . 21-17 [2]

21.1.4.3 Handling of Transmit Message Objects . . . . . . . . . . . . . . . . . . 21-18 [2]

21.1.4.4 Handling of Receive Message Objects . . . . . . . . . . . . . . . . . . 21-21 [2]

21.1.4.5 Single Data Transfer Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . 21-23 [2]

21.1.5 CAN Message Object Buffer (FIFO) . . . . . . . . . . . . . . . . . . . . . . 21-24 [2]

21.1.5.1 Buffer Access by the CAN Controller . . . . . . . . . . . . . . . . . . . 21-26 [2]

21.1.5.2 Buffer Access by the CPU . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21-27 [2]

21.1.6 Gateway Message Handling . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21-28 [2]

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21.1.6.1 Normal Gateway Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21-29 [2]

21.1.6.2 Normal Gateway with FIFO Buffering . . . . . . . . . . . . . . . . . . . 21-33 [2]

21.1.6.3 Shared Gateway Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21-36 [2]

21.1.7 Programming the TwinCAN Module . . . . . . . . . . . . . . . . . . . . . . 21-40 [2]

21.1.7.1 Configuration of CAN Node A/B . . . . . . . . . . . . . . . . . . . . . . . 21-40 [2]

21.1.7.2 Initialization of Message Objects . . . . . . . . . . . . . . . . . . . . . . . 21-40 [2]

21.1.7.3 Controlling a Message Transfer . . . . . . . . . . . . . . . . . . . . . . . 21-41 [2]

21.1.8 Loop-Back Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21-44 [2]

21.1.9 Single Transmission Try Functionality . . . . . . . . . . . . . . . . . . . . 21-45 [2]

21.1.10 Module Clock Requirements . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21-46 [2]

21.2 TwinCAN Register Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21-47 [2]

21.2.1 Register Map . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21-47 [2]

21.2.2 CAN Node A/B Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21-49 [2]

21.2.3 CAN Message Object Registers . . . . . . . . . . . . . . . . . . . . . . . . . 21-64 [2]

21.2.4 Global CAN Control/Status Registers . . . . . . . . . . . . . . . . . . . . . 21-80 [2]

21.3 XC161 Module Implementation Details . . . . . . . . . . . . . . . . . . . . . . 21-82 [2]

21.3.1 Interfaces of the TwinCAN Module . . . . . . . . . . . . . . . . . . . . . . . 21-82 [2]

21.3.2 TwinCAN Module Related External Registers . . . . . . . . . . . . . . . 21-83 [2]

21.3.2.1 System Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21-84 [2]

21.3.2.2 Port Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21-85 [2]

21.3.2.3 Interrupt Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21-90 [2]

21.3.3 Register Table . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21-91 [2]

22 Serial Data Link Module SDLM . . . . . . . . . . . . . . . . . . . . . . . . . . . 22-1 [2]

22.1 Overview . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22-1 [2]

22.2 SDLM Kernel Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22-2 [2]

22.2.1 J1850 Concept . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22-2 [2]

22.2.1.1 Frame Format Basics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22-3 [2]

22.2.1.2 J1850 Bits and Symbols . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22-5 [2]

22.2.1.3 Frame Arbitration . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22-6 [2]

22.2.2 Block Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22-6 [2]

22.2.2.1 4x Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22-8 [2]

22.2.2.2 Break Operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22-8 [2]

22.2.3 Interrupt Handling . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22-9 [2]

22.2.3.1 Message Operating Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22-10 [2]

22.2.3.2 Receive Operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22-10 [2]

22.2.3.3 Transmit Operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22-11 [2]

22.2.4 In-Frame Response (IFR) Operation . . . . . . . . . . . . . . . . . . . . . . 22-12 [2]

22.2.5 Block Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22-13 [2]

22.2.6 Bus Access in FIFO Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22-15 [2]

22.2.7 Flowcharts . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22-16 [2]

22.2.7.1 Overview . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22-16 [2]

22.2.7.2 Transmission Control . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22-17 [2]

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Table of Contents Page

22.2.7.3 Read Operations . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22-20 [2]

22.2.8 IFR Handling . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22-22 [2]

22.2.8.1 IFR Types 1, 2 via IFRVAL . . . . . . . . . . . . . . . . . . . . . . . . . . . 22-22 [2]

22.3 SDLM Register Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22-23 [2]

22.3.1 Global Control and Timing Registers . . . . . . . . . . . . . . . . . . . . . . 22-24 [2]

22.4 Control and Status Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22-29 [2]

22.4.1 Transmission Related Registers . . . . . . . . . . . . . . . . . . . . . . . . . 22-39 [2]

22.4.2 Reception Related Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22-43 [2]

22.5 SDLM Module Register Table . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22-50 [2]

22.6 XC161 Module Implementation Details . . . . . . . . . . . . . . . . . . . . . . 22-51 [2]

22.6.1 Interfaces of the SDLM Module . . . . . . . . . . . . . . . . . . . . . . . . . . 22-51 [2]

22.6.2 SDLM Module Related External Registers . . . . . . . . . . . . . . . . . 22-53 [2]

22.6.2.1 System Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22-54 [2]

22.6.2.2 Port Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22-55 [2]

22.6.2.3 Interrupt Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22-60 [2]

23 Register Set . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23-1 [2]

23.1 PD+BUS Peripherals . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23-1 [2]

23.2 LXBUS Peripherals . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23-16 [2]

Keyword Index . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . i-1 [1+2]

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The General Purpose Timer Units

14 The General Purpose Timer Units

The General Purpose Timer Unit blocks GPT1 and GPT2 have very flexible multifunctional timer structures which may be used for timing, event counting, pulse width measurement, pulse generation, frequency multiplication, and other purposes. They incorporate five 16-bit timers that are grouped into the two timer blocks GPT1 and GPT2. Each timer in each block may operate independently in a number of different modes such as gated timer or counter mode, or may be concatenated with another timer of the same block. Each block has alternate input/output functions and specific interrupts associated with it.

Block GPT1 contains three timers/counters: The core timer T3 and the two auxiliary timers T2 and T4. The maximum resolution is optionally be configured as reload or capture registers for the core timer. These registers are listed in Section 14.1.6.

•

/4 maximum resolution

GPT

• 3 independent timers/counters

• Timers/counters can be concatenated

• 4 operating modes:

– Timer Mode – Gated Timer Mode – Counter Mode – Incremental Interface Mode

• Reload and Capture functionality

• Separate interrupt lines

/4. The auxiliary timers of GPT1 may

GPT

Block GPT2 contains two timers/counters: The core timer T6 and the auxiliary timer T5. The maximum resolution is

/2. An additional Capture/Reload register (CAPREL)

GPT

supports capture and reload operation with extended functionality. These registers are listed in Section 14.2.7. The core timer T6 may be concatenated with timers of the CAPCOM units (T0, T1, T7, and T8).

The following list summarizes the features which are supported:

•

/2 maximum resolution

GPT

• 2 independent timers/counters

• Timers/counters can be concatenated

• 3 operating modes:

– Timer Mode – Gated Timer Mode – Counter Mode

• Extended capture/reload functions via 16-bit capture/reload register CAPREL

• Separate interrupt lines

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The General Purpose Timer Units

14.1 Timer Block GPT1

From a programmer’s point of view, the GPT1 block is composed of a set of SFRs as summarized below. Those portions of port and direction registers which are used for alternate functions by the GPT1 block are shaded.

Data Registers Control Registers Port Registers

T2 T2CON T2IC

T3 T3CON T3IC

T4 T4CON T4IC

SYSCON3

Tx GPT1 Timer x Register TxCON GPT1 Timer x Control Register TxIC GPT1 Timer x Interrupt Ctrl. Reg. SYSCON3 System Ctrl. Reg. 3 (Per. M gmt.)

Interrupt Control

ODP3

DP3

ALTSEL0P3

P5DIDIS

ODP3 Port 3 Open Drain Control Register DP3 Port 3 Direction Control Register P3 Port 3 Data Register ALTSEL0P3 Port 3 Alternate Output Select Reg. P5 Port 5 Data Register P5DIDIS Port 5 Digital Input Disable Reg.

mc_gpt0100_registers.vsd

Figure 14-1 SFRs Associated with Timer Block GPT1

All three timers of block GPT1 (T2, T3, T4) can run in one of 4 basic modes: Timer Mode, Gated Timer Mode, Counter Mode, or Incremental Interface Mode. All timers can count up or down. Each timer of GPT1 is controlled by a separate control register TxCON.

Each timer has an input pin TxIN (alternate pin function) associated with it, which serves as the gate control in gated timer mode, or as the count input in counter mode. The count direction (up/down) may be programmed via software or may be dynamically altered by a signal at the External Up/Down control input TxEUD (alternate pin function). An overflow/underflow of core timer T3 is indicated by the Output Toggle Latch T3OTL, whose state may be output on the associated pin T3OUT (alternate pin function). The auxiliary timers T2 and T4 may additionally be concatenated with the core timer T3 (through T3OTL) or may be used as capture or reload registers for the core timer T3.

The current contents of each timer can be read or modified by the CPU by accessing the corresponding timer count registers T2, T3, or T4, located in the non-bitaddressable SFR space (see Section 14.1.6). When any of the timer registers is written to by the CPU in the state immediately preceding a timer increment, decrement, reload, or capture operation, the CPU write operation has priority in order to guarantee correct results.

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The General Purpose Timer Units

The interrupts of GPT1 are controlled through the Interrupt Control Registers TxIC. These registers are not part of the GPT1 block. The input and output lines of GPT1 are connected to pins of ports P3 and P5. The control registers for the port functions are located in the respective port modules.

Note: The timing requirements for external input signals can be found in Section 14.1.5,

Section 14.3 summarizes the module interface signals, including pins.

T3CON.BPS1

GPT

T2I N

T2EUD

2n: 1f

Mode

Control

Basic clock

U/D

Reload

Capture

Aux. Timer T2

Interrupt Request (T2IRQ)

T3I N

T3EUD

T4I N

T4EUD

Mode

Control

Mode

Control

U/D

Capture

Reload

U/D

Toggle Latch

Core Timer T3 T3O TL

Aux. Timer T4

Interrupt Request (T3IRQ)

T3O UT

Interrupt Request (T4IRQ)

mc_gpt0101_bldiax1.vsd

Figure 14-2 GPT1 Block Diagram (n = 2 … 5)

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The General Purpose Timer Units

14.1.1 GPT1 Core Timer T3 Control

The current contents of the core timer T3 are reflected by its count register T3. This register can also be written to by the CPU, for example, to set the initial start value.

The core timer T3 is configured and controlled via its bitaddressable control register T3CON.

GPT12E_T3CON Timer 3 Control Register SFR (FF42

1514131211109876543210

DIR

rh rwh rwh rw rwh rw rw rw rw rw rw

T3 ED GE

BPS1

OTLT3OET3UDET3UD

Field Bits Typ Description

/A1H) Reset Value: 0000

T3R T3M T3I

T3RDIR 15 rh Timer T3 Rotation Direction Flag

0 Timer T3 counts up 1 Timer T3 counts down

T3CHDIR 14 rwh Timer T3 Count Direction Change Flag

This bit is set each time the count direction of timer T3 changes. T3CHDIR must be cleared by SW. 0 No change of count direction was detected 1 A change of count direction was detected

T3EDGE 13 rwh Timer T3 Edge Detection Flag

The bit is set each time a count edge is detected. T3EDGE must be cleared by SW. 0 No count edge was detected 1 A count edge was detected

BPS1 [12:11] rw GPT1 Block Prescaler Control

Selects the basic clock for block GPT1 (see also Section 14.1.5) 00 01 10 11

GPT

/8 /4 /32 /16

T3OTL 10 rwh Timer T3 Overflow Toggle Latch

Toggles on each overflow/underflow of T3. Can be set or reset by software (see separate description)

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Field Bits Typ Description T3OE 9rwOverflow/Underflow Output Enable

0 Alternate Output Function Disabled 1 State of T3 toggle latch is output on pin T3OUT

T3UDE 8rwTimer T3 External Up/Down Enable

0 Input T3EUD is disconnected 1 Direction influenced by input T3EUD

T3UD 7rwTimer T3 Up/Down Control

T3R 6rwTimer T3 Run Bit

0 Timer T3 stops 1Timer T3 runs

T3M [5:3] rw Timer T3 Mode Control (Basic Operating Mode)

000 Timer Mode 001 Counter Mode 010 Gated Timer Mode with gate active low 011 Gated Timer Mode with gate active high 100 Reserved. Do not use this combination. 101 Reserved. Do not use this combination. 110 Incremental Interface Mode

(Rotation Detection Mode)

111 Incremental Interface Mode

(Edge Detection Mode)

T3I [2:0] rw Timer T3 Input Parameter Selection

Depends on the operating mode, see respective sections for encoding:

Table 14-7 for Timer Mode and Gated Timer Mode Table 14-2 for Counter Mode Table 14-3 for Incremental Interface Mode

1) See Table 14-1 for encoding of bits T3UD and T3EUD.

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The General Purpose Timer Units

Timer T3 Run Control

The core timer T3 can be started or stopped by software through bit T3R (Timer T3 Run Bit). This bit is relevant in all operating modes of T3. Setting bit T3R will start the timer, clearing bit T3R stops the timer.

In gated timer mode, the timer will only run if T3R = 1 and the gate is active (high or low, as programmed).

Note: When bit T2RC or T4RC in timer control register T2CON or T4CON is set, bit T3R

will also control (start and stop) the auxiliary timer(s) T2 and/or T4.

Count Direction Control

The count direction of the GPT1 timers (core timer and auxiliary timers) can be controlled either by software or by the external input pin TxEUD (Timer Tx External Up/Down Control Input). These options are selected by bits TxUD and TxUDE in the respective control register TxCON. When the up/down control is provided by software (bit TxUDE = 0), the count direction can be altered by setting or clearing bit TxUD. When bit TxUDE = 1, pin TxEUD is selected to be the controlling source of the count direction. However, bit TxUD can still be used to reverse the actual count direction, as shown in

Table 14-1. The count direction can be changed regardless of whether or not the timer

is running.

Note: When pin TxEUD is used as external count direction control input, it must be

configured as input (its corresponding direction control bit must be cleared).

Table 14-1 GPT1 Timer Count Direction Control Pin TxEUD Bit TxUDE Bit TxUD Count Direction Bit TxRDIR

X 00Count Up0 X 0 1 Count Down 1 0 10Count Up0 1 1 0 Count Down 1 0 1 1 Count Down 1 1 11Count Up0

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The General Purpose Timer Units

Timer 3 Output Toggle Latch

The overflow/underflow signal of timer T3 is connected to a block named ‘Toggle Latch’, shown in the timer mode diagrams. Figure 14-3 illustrates the details of this block. An overflow or underflow of T3 will clock two latches: The first latch represents bit T3OTL in control register T3CON. The second latch is an internal latch toggled by T3OTL’s output. Both latch outputs are connected to the input control blocks of the auxiliary timers T2 and T4. The output level of the shadow latch will match the output level of T3OTL, but is delayed by one clock cycle. When the T3OTL value changes, this will result in a temporarily different output level from T3OTL and the shadow latch, which can trigger the selected count event in T2 and/or T4.

When software writes to T3OTL, both latches are set or cleared simultaneously. In this case, both signals to the auxiliary timers carry the same level and no edge will be detected. Bit T3OE (overflow/underflow output enable) in register T3CON enables the state of T3OTL to be monitored via an external pin T3OUT. When T3OTL is linked to an external port pin (must be configured as output), T3OUT can be used to control external HW. If T3OE = 1, pin T3OUT outputs the state of T3OTL. If T3OE = 0, pin T3OUT outputs a high level (as long as the T3OUT alternate function is selected for the port pin).

The trigger signals can serve as an input for the counter function or as a trigger source for the reload function of the auxiliary timers T2 and T4.

As can be seen from Figure 14-3, when latch T3OTL is modified by software to determine the state of the output line, also the internal shadow latch is set or cleared accordingly. Therefore, no trigger condition is detected by T2/T4 in this case.

Core Timer

Overflow/ Underflow

Set/Clear (SW )

TxOTL

Toggle Latch Logic

Shadow

Latch

TxOE

MUX

To Port Logic

To Aux. Timer Input Logic

mc_gpt0106_otl.vsd

TxOUT

Figure 14-3 Block Diagram of the Toggle Latch Logic of Core Timer T3

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14.1.2 GPT1 Core Timer T3 Operating Modes

Timer 3 in Timer Mode

Timer mode for the core timer T3 is selected by setting bitfield T3M in register T3CON to 000 programmable prescalers controlled by bitfields BPS1 and T3I in register T3CON. Please see Section 14.1.5 for details on the input clock options.

T3EUD

. In timer mode, T3 is clocked with the module’s input clock f

GPT

Prescaler Core Timer T3 Toggle Latch

BPS1 T3I

T3UD

T3R

Count

MUX

Up/Down

divided by two

GPT

T3IRQ

T3OUT

to T2/T4

T3UDE

MCB05391

Figure 14-4 Block Diagram of Core Timer T3 in Timer Mode

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The General Purpose Timer Units

Gated Timer Mode

Gated timer mode for the core timer T3 is selected by setting bitfield T3M in register T3CON to 010

or 011B. Bit T3M.0 (T3CON.3) selects the active level of the gate input.

The same options for the input frequency are available in gated timer mode as in timer mode (see Section 14.1.5). However, the input clock to the timer in this mode is gated by the external input pin T3IN (Timer T3 External Input). To enable this operation, the associated pin T3IN must be configured as input, that is, the corresponding direction control bit must contain 0.

T3IRQ

GPT

T3IN

Prescaler

BPS1 T3I

Gate

Ctrl.

T3R

Count

Core Timer T3 Toggle Latch

T3OUT

to T2/T4

T3UD

MUX

Up/Down

MCB05392

T3EUD

T3UDE

Figure 14-5 Block Diagram of Core Timer T3 in Gated Timer Mode

If T3M = 010 stops the timer. If T3M = 011

, the timer is enabled when T3IN shows a low level. A high level at this line

, line T3IN must have a high level in order to enable the

timer. Additionally, the timer can be turned on or off by software using bit T3R. The timer will only run if T3R is 1 and the gate is active. It will stop if either T3R is 0 or the gate is inactive.

Note: A transition of the gate signal at pin T3IN does not cause an interrupt request.

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Counter Mode

Counter Mode for the core timer T3 is selected by setting bitfield T3M in register T3CON to 001

. In counter mode, timer T3 is clocked by a transition at the external input pin

T3IN. The event causing an increment or decrement of the timer can be a positive, a negative, or both a positive and a negative transition at this line. Bitfield T3I in control register T3CON selects the triggering transition (see Table 14-2).

T3IRQ

Edge

T3IN

Select

T3I

T3UD

T3EUD

T3R

Count

MUX

Core Timer T3 Toggle Latch

Up/Down

T3OUT

to T2/T4

T3UDE

MCB05393

Figure 14-6 Block Diagram of Core Timer T3 in Counter Mode

Table 14-2 GPT1 Core Timer T3 (Counter Mode) Input Edge Selection T3I Triggering Edge for Counter Increment/Decrement

0 0 0 None. Counter T3 is disabled 0 0 1 Positive transition (rising edge) on T3IN 0 1 0 Negative transition (falling edge) on T3IN 0 1 1 Any transition (rising or falling edge) on T3IN 1 X X Reserved. Do not use this combination

For counter mode operation, pin T3IN must be configured as input (the respective direction control bit DPx.y must be 0). The maximum input frequency allowed in counter mode depends on the selected prescaler value. To ensure that a transition of the count input signal applied to T3IN is recognized correctly, its level must be held high or low for a minimum number of module clock cycles before it changes. This information can be found in Section 14.1.5.

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The General Purpose Timer Units

Incremental Interface Mode

Incremental interface mode for the core timer T3 is selected by setting bitfield T3M in register T3CON to 110

or 111B. In incremental interface mode, the two inputs

associated with core timer T3 (T3IN, T3EUD) are used to interface to an incremental encoder. T3 is clocked by each transition on one or both of the external input pins to provide 2-fold or 4-fold resolution of the encoder input.

T3IN

Edge

Select

T3I

T3R

Count

EDGE

Core

Timer T3

RDIR

Toggle

Latch

T3OUT

to T2/T4

T3IRQ

T3UD

T3EUD

Phase Detect

T3UDE

MUX

Change

Detect

T3CH

DIR

T3M

MCB05394

Figure 14-7 Block Diagram of Core Timer T3 in Incremental Interface Mode

Bitfield T3I in control register T3CON selects the triggering transitions (see Table 14-3). The sequence of the transitions of the two input signals is evaluated and generates count pulses as well as the direction signal. So T3 is modified automatically according to the speed and the direction of the incremental encoder and, therefore, its contents always represent the encoder’s current position.

The interrupt request (T3IRQ) generation mode can be selected: In Rotation Detection Mode (T3M = 110 T3 changes. In Edge Detection Mode (T3M = 111

), an interrupt request is generated each time the count direction of

), an interrupt request is generated

each time a count edge for T3 is detected. Count direction, changes in the count direction, and count requests are monitored by status bits T3RDIR, T3CHDIR, and T3EDGE in register T3CON.

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Table 14-3 Core Timer T3 (Incremental Interface Mode) Input Edge Selection T3I Triggering Edge for Counter Increment/Decrement

0 0 0 None. Counter T3 stops. 0 0 1 Any transition (rising or falling edge) on T3IN. 0 1 0 Any transition (rising or falling edge) on T3EUD. 0 1 1 Any transition (rising or falling edge) on any T3 input (T3IN or T3EUD). 1 X X Reserved. Do not use this combination.

The incremental encoder can be connected directly to the XC161 without external interface logic. In a standard system, however, comparators will be employed to convert the encoder’s differential outputs (such as A, A

) to digital signals (such as A). This greatly

increases noise immunity.

Note: The third encoder output T0, which indicates the mechanical zero position, may

be connected to an external interrupt input and trigger a reset of timer T3 (for example via PEC transfer from ZEROS).

Signal

Encoder Controller

A A

B B

T0 T0

Conditioning

T3Input

Interrupt

MCS04372

Figure 14-8 Connection of the Encoder to the XC161

For incremental interface operation, the following conditions must be met:

• Bitfield T3M must be 110

or 111B.

• Both pins T3IN and T3EUD must be configured as input, i.e. the respective direction control bits must be 0.

• Bit T3UDE must be 1 to enable automatic external direction control.

The maximum count frequency allowed in incremental interface mode depends on the selected prescaler value. To ensure that a transition of any input signal is recognized correctly, its level must be held high or low for a minimum number of module clock cycles before it changes. This information can be found in Section 14.1.5.

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As in incremental interface mode two input signals with a 90° phase shift are evaluated, their maximum input frequency can be half the maximum count frequency.

In incremental interface mode, the count direction is automatically derived from the sequence in which the input signals change, which corresponds to the rotation direction of the connected sensor. Table 14-4 summarizes the possible combinations.

Table 14-4 GPT1 Core Timer T3 (Incremental Interface Mode) Count Direction Level on Respective

other Input

Rising Falling Rising Falling

T3IN Input T3EUD Input

High Down Up Up Down Low Up Down Down Up

Figure 14-9 and Figure 14-10 give examples of T3’s operation, visualizing count signal

generation and direction control. They also show how input jitter is compensated, which might occur if the sensor rests near to one of its switching points.

Forward Jitter Backward Jitter Forward

T3IN

T3EUD

Contents of T3

Note: This example shows the timer behaviour assuming that T3 counts upon any

transition on input, i.e. T3I = '011

Up Down Up

MCT04373

Figure 14-9 Evaluation of Incremental Encoder Signals, 2 Count Inputs

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Forward Jitter Backward Jitter Forward

T3IN

T3EUD

Contents of T3

Note: This example shows the timer behaviour assuming that T3 counts upon any

transition on input T3IN, i.e. T3I = '001

Up Down Up

The General Purpose Timer Units

MCT04374

Figure 14-10 Evaluation of Incremental Encoder Signals, 1 Count Input

Note: Timer T3 operating in incremental interface mode automatically provides

information on the sensor’s current position. Dynamic information (speed, acceleration, deceleration) may be obtained by measuring the incoming signal periods. This is facilitated by an additional special capture mode for timer T5 (see

Section 14.2.5).

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14.1.3 GPT1 Auxiliary Timers T2/T4 Control

Auxiliary timers T2 and T4 have exactly the same functionality. They can be configured for timer mode, gated timer mode, counter mode, or incremental interface mode with the same options for the timer frequencies and the count signal as the core timer T3. In addition to these 4 counting modes, the auxiliary timers can be concatenated with the core timer, or they may be used as reload or capture registers in conjunction with the core timer. The start/stop function of the auxiliary timers can be remotely controlled by the T3 run control bit. Several timers may thus be controlled synchronously.

The current contents of an auxiliary timer are reflected by its count register T2 or T4, respectively. These registers can also be written to by the CPU, for example, to set the initial start value.

The individual configurations for timers T2 and T4 are determined by their bitaddressable control registers T2CON and T4CON, which are organized identically. Note that functions which are present in all 3 timers of block GPT1 are controlled in the same bit positions and in the same manner in each of the specific control registers.

Note: The auxiliary timers have no output toggle latch and no alternate output function.

GPT12E_T2CON Timer 2 Control Register SFR (FF40

1514131211109876543210

DIR

rh rwh rwh rw - - rw rw rw rw rw rw

T2 ED GE

DIS

T2RCT2

UDET2UD

/A0H) Reset Value: 0000

T2R T2M T2I

GPT12E_T4CON Timer 4 Control Register SFR (FF44

1514131211109876543210

DIR

rh rwh rwh rw - - rw rw rw rw rw rw

T4 ED GE

DIS

T4RCT4

UDET4UD

/A2H) Reset Value: 0000

T4R T4M T4I

Field Bits Typ Description

TxRDIR 15 rh Timer Tx Rotation Direction

0 Timer x counts up 1 Timer x counts down

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Field Bits Typ Description TxCHDIR 14 rwh Timer Tx Count Direction Change

This bit is set each time the count direction of timer Tx changes. TxCHDIR must be cleared by SW. 0 No change in count direction was detected 1 A change in count direction was detected

TxEDGE 13 rwh Timer Tx Edge Detection

The bit is set each time a count edge is detected. TxEDGE must be cleared by SW. 0 No count edge was detected 1 A count edge was detected

TxIRDIS 12 rw Timer Tx Interrupt Request Disable

0 Interrupt generation for TxCHDIR and

TxEDGE interrupts in Incremental Interface Mode is enabled

1 Interrupt generation for TxCHDIR and

TxEDGE interrupts in Incremental Interface Mode is disabled

TxRC 9rwTimer Tx Remote Control

0 Timer Tx is controlled by its own run bit TxR 1 Timer Tx is controlled by the run bit T3R of core

timer 3, not by bit TxR

TxUDE 8rwTimer Tx External Up/Down Enable

0 Input TxEUD is disconnected 1 Direction influenced by input TxEUD

TxUD 7rwTimer Tx Up/Down Control

TxR 6rwTimer Tx Run Bit

0Timer Tx stops 1Timer Tx runs

Note: This bit only controls timer Tx if bit TxRC = 0.

TxM [5:3] rw Timer Tx Mode Control (Basic Operating Mode)

000 Timer Mode 001 Counter Mode 010 Gated Timer Mode with gate active low 011 Gated Timer Mode with gate active high 100 Reload Mode 101 Capture Mode 110 Incremental Interface Mode (Rotation Detect.) 111 Incremental Interface Mode (Edge Detection)

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Field Bits Typ Description TxI [2:0] rw Timer Tx Input Parameter Selection

Depends on the operating mode, see respective sections for encoding:

Table 14-7 for Timer Mode and Gated Timer Mode Table 14-2 for Counter Mode Table 14-3 for Incremental Interface Mode

1) See Table 14-1 for encoding of bits TxUD and TxEUD.

Timer T2/T4 Run Control

Each of the auxiliary timers T2 and T4 can be started or stopped by software in two different ways:

• Through the associated timer run bit (T2R or T4R). In this case it is required that the respective control bit TxRC = 0.

• Through the core timer’s run bit (T3R). In this case the respective remote control bit must be set (TxRC = 1).

The selected run bit is relevant in all operating modes of T2/T4. Setting the bit will start the timer, clearing the bit stops the timer.

In gated timer mode, the timer will only run if the selected run bit is set and the gate is active (high or low, as programmed).

Note: If remote control is selected T3R will start/stop timer T3 and the selected auxiliary

timer(s) synchronously.

Count Direction Control

The count direction of the GPT1 timers (core timer and auxiliary timers) is controlled in the same way, either by software or by the external input pin TxEUD. Please refer to the description in Table 14-1.

Note: When pin TxEUD is used as external count direction control input, it must be

configured as input (its corresponding direction control bit must be cleared).

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14.1.4 GPT1 Auxiliary Timers T2/T4 Operating Modes

The operation of the auxiliary timers in the basic operating modes is almost identical with the core timer’s operation, with very few exceptions. Additionally, some combined operating modes can be selected.

Timers T2 and T4 in Timer Mode

Timer mode for an auxiliary timer Tx is selected by setting its bitfield TxM in register TxCON to 000

GPT

Prescaler

BPS1 TxI

TxR

T3R

MUX

Count

Auxiliary

Timer Tx

TxIRQ

TxRC

TxUD

MUX

Up/Down

x = 2, 4

MCB05395

TxEUD

TxUDE

Figure 14-11 Block Diagram of an Auxiliary Timer in Timer Mode

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Timers T2 and T4 in Gated Timer Mode

Gated timer mode for an auxiliary timer Tx is selected by setting bitfield TxM in register TxCON to 010

or 011B. Bit TxM.0 (TxCON.3) selects the active level of the gate input.

Note: A transition of the gate signal at line TxIN does not cause an interrupt request.

MUX

TxRC

Count

MUX

Up/Down

Auxiliary

Timer Tx

TxIRQ

GPT

TxIN

TxEUD

Prescaler

BPS1 TxI

TxUD

Gate

Ctrl.

TxM

TxR

T3R

TxUDE

x = 2, 4

MCB05396

Figure 14-12 Block Diagram of an Auxiliary Timer in Gated Timer Mode

Note: There is no output toggle latch for T2 and T4.

Start/stop of an auxiliary timer can be controlled locally or remotely.

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Timers T2 and T4 in Counter Mode

Counter mode for an auxiliary timer Tx is selected by setting bitfield TxM in register TxCON to 001

. In counter mode, an auxiliary timer can be clocked either by a transition

at its external input line TxIN, or by a transition of timer T3’s toggle latch T3OTL. The event causing an increment or decrement of a timer can be a positive, a negative, or both a positive and a negative transition at either the respective input pin or at the toggle latch. Bitfield TxI in control register TxCON selects the triggering transition (see Table 14-5).

TxR

T3R

Edge

Select

TxI

MUX

Count

Auxiliary

Timer Tx

TxIRQ

TxIN

T3 Toggle Latch

MUX

TxI.2

TxRC

TxUD

MUX

Up/Down

x = 2, 4

MCB05397

TxEUD

TxUDE

Figure 14-13 Block Diagram of an Auxiliary Timer in Counter Mode

Table 14-5 GPT1 Auxiliary Timer (Counter Mode) Input Edge Selection T2I/T4I Triggering Edge for Counter Increment/Decrement

X 0 0 None. Counter Tx is disabled 0 0 1 Positive transition (rising edge) on TxIN 0 1 0 Negative transition (falling edge) on TxIN 0 1 1 Any transition (rising or falling edge) on TxIN 1 0 1 Positive transition (rising edge) of T3 toggle latch T3OTL 1 1 0 Negative transition (falling edge) of T3 toggle latch T3OTL 1 1 1 Any transition (rising or falling edge) of T3 toggle latch T3OTL

Note: Only state transitions of T3OTL which are caused by the overflows/underflows of

T3 will trigger the counter function of T2/T4. Modifications of T3OTL via software will NOT trigger the counter function of T2/T4.

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For counter operation, pin TxIN must be configured as input (the respective direction control bit DPx.y must be 0). The maximum input frequency allowed in counter mode depends on the selected prescaler value. To ensure that a transition of the count input signal applied to TxIN is recognized correctly, its level must be held high or low for a minimum number of module clock cycles before it changes. This information can be found in Section 14.1.5.

Timers T2 and T4 in Incremental Interface Mode

Incremental interface mode for an auxiliary timer Tx is selected by setting bitfield TxM in the respective register TxCON to 110

or 111B. In incremental interface mode, the two

inputs associated with an auxiliary timer Tx (TxIN, TxEUD) are used to interface to an incremental encoder. Tx is clocked by each transition on one or both of the external input pins to provide 2-fold or 4-fold resolution of the encoder input.

TxIN

Edge

Select

Count

Auxiliary

Timer Tx

Overflow

Underflow

MUX

TxRC

TxUDE

Edge

MUX

RDIR

Change

Detect

TxCH

DIR

TxM

TxIRDIS

TxIRQ

MCB05398

TxEUD

TxI

TxUD

Phase Detect

TxR

T3R

Figure 14-14 Block Diagram of an Auxiliary Timer in Incremental Interface Mode

The operation of the auxiliary timers T2 and T4 in incremental interface mode and the interrupt generation are the same as described for the core timer T3. The descriptions, figures and tables apply accordingly.

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Timer Concatenation

Using the toggle bit T3OTL as a clock source for an auxiliary timer in counter mode concatenates the core timer T3 with the respective auxiliary timer. This concatenation forms either a 32-bit or a 33-bit timer/counter, depending on which transition of T3OTL is selected to clock the auxiliary timer.

• 32-bit Timer/Counter: If both a positive and a negative transition of T3OTL are used to clock the auxiliary timer, this timer is clocked on every overflow/underflow of the core timer T3. Thus, the two timers form a 32-bit timer.

• 33-bit Timer/Counter: If either a positive or a negative transition of T3OTL is selected to clock the auxiliary timer, this timer is clocked on every second overflow/underflow of the core timer T3. This configuration forms a 33-bit timer (16-bit core timer + T3OTL + 16-bit auxiliary timer). As long as bit T3OTL is not modified by software, it represents the state of the internal toggle latch, and can be regarded as part of the 33-bit timer.

The count directions of the two concatenated timers are not required to be the same. This offers a wide variety of different configurations.

T3, which represents the low-order part of the concatenated timer, can operate in timer mode, gated timer mode or counter mode in this case.

T3IRQ

GPT

T3IN

TxIN

Operating

Mode

Control

BPS1 TxI

MUX

TxI.2

T3R

Edge

Select

TxI

Count

TxR

T3R

Core Timer T3

Up/Down

MUX

TxRC

Count

Toggle Latch T3OUT

Auxiliary

Timer Tx

Up/Down

x = 2, 4

TxIRQ

MCA05399

Figure 14-15 Concatenation of Core Timer T3 and an Auxiliary Timer

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Auxiliary Timer in Reload Mode

Reload Mode for an auxiliary timer Tx is selected by setting bitfield TxM in the respective register TxCON to 100

. In reload mode, the core timer T3 is reloaded with the contents

of an auxiliary timer register, triggered by one of two different signals. The trigger signal is selected the same way as the clock source for counter mode (see Table 14-5), i.e. a transition of the auxiliary timer’s input TxIN or the toggle latch T3OTL may trigger the reload.

Note: When programmed for reload mode, the respective auxiliary timer (T2 or T4) stops

independently of its run flag T2R or T4R. The timer input pin TxIN must be configured as input if it shall trigger a reload operation.

T3IRQ

GPT

T3IN

Operating

Mode

Control

Count

Core Timer T3

Toggle Latch T3OUT

Up/Down

Reload

TxIRQ

Auxiliary

Timer Tx

x = 2, 4

MCA05400

TxIN

BPS1 TxI

MUX

TxI.2

T3R

Edge

Select

TxI

Figure 14-16 GPT1 Auxiliary Timer in Reload Mode

Upon a trigger signal, T3 is loaded with the contents of the respective timer register (T2 or T4) and the respective interrupt request flag (T2IR or T4IR) is set.

Note: When a T3OTL transition is selected for the trigger signal, the interrupt request

flag T3IR will also be set upon a trigger, indicating T3’s overflow or underflow. Modifications of T3OTL via software will NOT trigger the counter function of T2/T4.

To ensure that a transition of the reload input signal applied to TxIN is recognized correctly, its level must be held high or low for a minimum number of module clock cycles, detailed in Section 14.1.5.

The reload mode triggered by the T3 toggle latch can be used in a number of different configurations. The following functions can be performed, depending on the selected active transition:

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• If both a positive and a negative transition of T3OTL are selected to trigger a reload, the core timer will be reloaded with the contents of the auxiliary timer each time it overflows or underflows. This is the standard reload mode (reload on overflow/underflow).

• If either a positive or a negative transition of T3OTL is selected to trigger a reload, the core timer will be reloaded with the contents of the auxiliary timer on every second overflow or underflow.

• Using this “single-transition” mode for both auxiliary timers allows to perform very flexible Pulse Width Modulation (PWM). One of the auxiliary timers is programmed to reload the core timer on a positive transition of T3OTL, the other is programmed for a reload on a negative transition of T3OTL. With this combination the core timer is alternately reloaded from the two auxiliary timers.

Figure 14-17 shows an example for the generation of a PWM signal using the “single-

transition” reload mechanism. T2 defines the high time of the PWM signal (reloaded on positive transitions) and T4 defines the low time of the PWM signal (reloaded on negative transitions). The PWM signal can be output on pin T3OUT if T3OE = 1. With this method, the high and low time of the PWM signal can be varied in a wide range.

Note: The output toggle latch T3OTL is accessible via software and may be changed, if

required, to modify the PWM signal. However, this will NOT trigger the reloading of T3.

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Auxiliary

Timer T2

T2IN

GPT

T3IN

MUX

T2I.2

Operating

Mode

Control

BPS1 T3I

Edge

Select

T2I

T3R

Reload

Count

Core Timer T3

Up/Down

The General Purpose Timer Units

T2IRQ

T3IRQ

Toggle Latch T3OUT

T4IN

MUX

T4I.2

Edge

Select

T4I

Reload

T4IRQ

Auxiliary

Timer T4

MCA05401

Figure 14-17 GPT1 Timer Reload Configuration for PWM Generation

Note: Although possible, selecting the same reload trigger event for both auxiliary timers

should be avoided. In such a case, both reload registers would try to load the core timer at the same time. If this combination is selected, T2 is disregarded and the contents of T4 is reloaded.

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Auxiliary Timer in Capture Mode

Capture mode for an auxiliary timer Tx is selected by setting bitfield TxM in the respective register TxCON to 101

. In capture mode, the contents of the core timer T3 are latched

into an auxiliary timer register in response to a signal transition at the respective auxiliary timer’s external input pin TxIN. The capture trigger signal can be a positive, a negative, or both a positive and a negative transition.

The two least significant bits of bitfield TxI select the active transition (see Table 14-5). Bit 2 of TxI is irrelevant for capture mode and must be cleared (TxI.2 = 0).

Note: When programmed for capture mode, the respective auxiliary timer (T2 or T4)

stops independently of its run flag T2R or T4R.

T3IRQ

GPT

T3IN

Operating

Mode

Control

BPS1 T3I

T3R

Count

Core Timer T3

Up/Down

Toggle Latch T3OUT

to Ty

Edge

TxIN

Select

TxI

Capture

Auxiliary

Timer Tx

TxIRQ

x = 2, 4 y = 4, 2

MCA05402

Figure 14-18 GPT1 Auxiliary Timer in Capture Mode

Upon a trigger (selected transition) at the corresponding input pin TxIN the contents of the core timer are loaded into the auxiliary timer register and the associated interrupt request flag TxIR will be set.

For capture mode operation, the respective timer input pin TxIN must be configured as input. To ensure that a transition of the capture input signal applied to TxIN is recognized correctly, its level must be held high or low for a minimum number of module clock cycles, detailed in Section 14.1.5.

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14.1.5 GPT1 Clock Signal Control

All actions within the timer block GPT1 are triggered by transitions of its basic clock. This basic clock is derived from the system clock by a basic block prescaler, controlled by bitfield BPS1 in register T3CON (see Figure 14-2). The count clock can be generated in two different ways:

• Internal count clock, derived from GPT1’s basic clock via a programmable prescaler, is used for (gated) timer mode.

• External count clock, derived from the timer’s input pin(s), is used for counter mode.

For both ways, the basic clock determines the maximum count frequency and the timer’s resolution:

Table 14-6 Basic Clock Selection for Block GPT1 Block Prescaler

Prescaling Factor for GPT1: F(BPS1)

BPS1 = 01

F(BPS1) = 4

BPS1 = 00

F(BPS1) = 8

BPS1 = 11

F(BPS1) = 16

BPS1 = 10

F(BPS1) = 32

Maximum External

/8 f

GPT

/16 f

GPT

/32 f

GPT

/64

Count Frequency Input Signal

× t

GPT

8 × t

GPT

16 × t

GPT

32 × t

GPT

Stable Time

1) Please note the non-linear encoding of bitfield BPS1.

2) Default after reset.

Internal Count Clock Generation

In timer mode and gated timer mode, the count clock for each GPT1 timer is derived from the GPT1 basic clock by a programmable prescaler, controlled by bitfield TxI in the respective timer’s control register TxCON.

The count frequency

for a timer Tx and its resolution rTx are scaled linearly with lower

clock frequencies, as can be seen from the following formula:

<Txl>

MHz[]

(14.1)

------------ ------------------------ ---------= r F BPS1()2

GPT

<Txl>

µs[]

F BPS1()2

------------ ------------------------ ---------=

GPT

The effective count frequency depends on the common module clock prescaler factor

<TxI>

F(BPS1) as well as on the individual input prescaler factor 2

. Table 14-7 summarizes

the resulting overall divider factors for a GPT1 timer that result from these cascaded prescalers.

Table 14-8 lists a timer’s parameters (such as count frequency, resolution, and period)

resulting from the selected overall prescaler factor and the applied system frequency. Note that some numbers may be rounded.

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Table 14-7 GPT1 Overall Prescaler Factors for Internal Count Clock Individual

Prescaler for Tx

TxI = 000 TxI = 001 TxI = 010 TxI = 011 TxI = 100 TxI = 101 TxI = 110 TxI = 111

1) Please note the non-linear encoding of bitfield BPS1.

BPS1 = 01

481632 8163264 16 32 64 128 32 64 128 256 64 128 256 512 128 256 512 1024 256 512 1024 2048 512 1024 2048 4096

Common Prescaler for Module Clock

BPS1 = 00

BPS1 = 11

BPS1 = 10

Table 14-8 GPT1 Timer Parameters

System Clock = 10 MHz

Frequency Resolution Period Frequency Resolution Period

Overall Divider

System Clock = 40 MHz

Factor

2.5 MHz 400 ns 26.21 ms

1.25 MHz 800 ns 52.43 ms

625.0 kHz 1.6

312.5 kHz 3.2

156.25 kHz 6.4

78.125 kHz 12.8

39.06 kHz 25.6

19.53 kHz 51.2

9.77 kHz 102.4

4.88 kHz 204.8

2.44 kHz 409.6

µs 104.9 ms 16 2.5 MHz 400 ns 26.21 ms µs 209.7 ms 32 1.25 MHz 800 ns 52.43 ms µs 419.4 ms 64 625.0 kHz 1.6 µs 104.9 ms

µs 838.9 ms 128 312.5 kHz 3.2 µs 209.7 ms µs 1.678 s 256 156.25 kHz 6.4 µs 419.4 ms µs 3.355 s 512 78.125 kHz 12.8 µs 838.9 ms

µs 6.711 s 1024 39.06 kHz 25.6 µs 1.678 s µs13.42 s2048 19.53 kHz 51.2 µs 3.355 s µs26.84 s4096 9.77 kHz 102.4 µs 6.711 s

4 10.0 MHz 100 ns 6.55 ms 8 5.0 MHz 200 ns 13.11 ms

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External Count Clock Input

The external input signals of the GPT1 block are sampled with the GPT1 basic clock (see

Figure 14-2). To ensure that a signal is recognized correctly, its current level (high or

low) must be held active for at least one complete sampling period, before changing. A signal transition is recognized if two subsequent samples of the input signal represent different levels. Therefore, a minimum of two basic clock periods are required for the sampling of an external input signal. Thus, the maximum frequency of an input signal must not be higher than half the basic clock.

Table 14-9 summarizes the resulting requirements for external GPT1 input signals.

Table 14-9 GPT1 External Input Signal Limits

System Clock = 10 MHz

Max. Input Frequency

Min. Level Hold Time

1.25 MHz 400 ns

Input Frequ. Factor

/8 01

GPT

GPT1 Divider BPS1

Input Phase Duration

4 × t

GPT

System Clock = 40 MHz

Max. Input Frequency

Min. Level Hold Time

5.0 MHz 100 ns

625.0 kHz 800 ns

312.5 kHz 1.6

156.25 kHz 3.2

µs f µs f

GPT

/16 00 /32 11 /64 10

8 × t 16 × t 32 × t

GPT

2.5 MHz 200 ns

1.25 MHz 400 ns

625.0 kHz 800 ns

These limitations are valid for all external input signals to GPT1, including the external count signals in counter mode and incremental interface mode, the gate input signals in gated timer mode, and the external direction signals.

14.1.6 GPT1 Timer Registers

GPT12E_Tx Timer x Count Register SFR (FE4x

1514131211109876543210

Txvalue

/2yH) Reset Value: 0000

rwh

Table 14-10 GPT1 Timer Register Locations Timer Register Physical Address 8-Bit Address

T3 FE42 T2 FE40 T4 FE44

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14.1.7 Interrupt Control for GPT1 Timers

When a timer overflows from FFFFH to 0000H (when counting up), or when it underflows from 0000 T4IR) in register TxIC will be set. This will cause an interrupt to the respective timer interrupt vector (T2INT, T3INT or T4INT) or trigger a PEC service, if the respective interrupt enable bit (T2IE, T3IE or T4IE in register TxIC) is set. There is an interrupt control register for each of the three timers.

GPT12E_T2IC Timer 2 Intr. Ctrl. Reg. SFR (FF60

1514131211109876543210

-------GPXT2IRT2IE ILVL GLVL

- - - - - - - rw rwh rw rw rw

GPT12E_T3IC Timer 3 Intr. Ctrl. Reg. SFR (FF62

to FFFFH (when counting down), its interrupt request flag (T2IR, T3IR or

/B0H) Reset Value: - - 00

/B1H) Reset Value: - - 00

1514131211109876543210

-------GPXT3IRT3IE ILVL GLVL

- - - - - - - rw rwh rw rw rw

GPT12E_T4IC Timer 4 Intr. Ctrl. Reg. SFR (FF64

1514131211109876543210

-------GPXT4IRT4IE ILVL GLVL

- - - - - - - rw rwh rw rw rw

/B2H) Reset Value: - - 00

Note: Please refer to the general Interrupt Control Register description for an

explanation of the control fields.

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14.2 Timer Block GPT2

From a programmer’s point of view, the GPT2 block is represented by a set of SFRs as summarized below. Those portions of port and direction registers which are used for alternate functions by the GPT2 block are shaded.

Data Registers Control Registers Port Registers

T5 T5CON T5IC

T6 T6CON T6IC

CAPREL CRIC

SYSCON3

Tx GPT2 Timer x Register CAPREL GPT2 Capture/Reload Register TxCON GPT2 Timer x Control Register TxIC GPT2 Timer x Interrupt Ctrl. Reg. SYSCON3 System Ctrl. Reg. 3 (Per. M gmt.)

Interrupt Control

ODP3

DP3

ALTSEL0P3

P5DIDIS

mc_gpt0102_registers.vsd

Figure 14-19 SFRs Associated with Timer Block GPT2

Both timers of block GPT2 (T5, T6) can run in one of 3 basic modes: Timer Mode, Gated Timer Mode, or Counter Mode. All timers can count up or down. Each timer of GPT2 is controlled by a separate control register TxCON.

Each timer has an input pin TxIN (alternate pin function) associated with it, which serves as the gate control in gated timer mode, or as the count input in counter mode. The count direction (up/down) may be programmed via software. An overflow/underflow of core timer T6 is indicated by the Output Toggle Latch T6OTL, whose state may be output on the associated pin T6OUT (alternate pin function). The auxiliary timer T5 may additionally be concatenated with the core timer T6 (through T6OTL).

The Capture/Reload register CAPREL can be used to capture the contents of timer T5, or to reload timer T6. A special mode facilitates the use of register CAPREL for both functions at the same time. This mode allows frequency multiplication. The capture function is triggered by the input pin CAPIN, or by GPT1 timer’s T3 input lines T3IN and T3EUD. The reload function is triggered by an overflow or underflow of timer T6. Overflows/underflows of timer T6 may also clock the timers of the CAPCOM units.

The current contents of each timer can be read or modified by the CPU by accessing the corresponding timer count registers T5 or T6, located in the non-bitaddressable SFR

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space (see Section 14.2.7). When any of the timer registers is written to by the CPU in the state immediately preceding a timer increment, decrement, reload, or capture operation, the CPU write operation has priority in order to guarantee correct results.

The interrupts of GPT2 are controlled through the Interrupt Control Registers TxIC. These registers are not part of the GPT2 block. The input and output lines of GPT2 are connected to pins of Ports P3 and P5. The control registers for the port functions are located in the respective port modules.

Note: The timing requirements for external input signals can be found in Section 14.2.6,

Section 14.3 summarizes the module interface signals, including pins.

T6CON.BPS2

GPT

T5I N

2n: 1f

Mode

Control

Basic clock

GPT2 Ti mer T5

U/D

Cl ear

Interrupt Request (T5IR)

CAPIN

T3I N/

T3EUD

T6I N

CAPREL

Mode

Control

Mode

Control

Capture

GPT2 CAPREL

Rel oa d

Clear

GPT2 Ti mer T6

U/D

Toggle F F

T6O TL

Interrupt Request (CRIR)

Interrupt Request (T6IR)

T6O UT

T6O UF

mc _gpt0103_bldiax 1.vsd

Figure 14-20 GPT2 Block Diagram

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14.2.1 GPT2 Core Timer T6 Control

The current contents of the core timer T6 are reflected by its count register T6. This register can also be written to by the CPU, for example, to set the initial start value.

The core timer T6 is configured and controlled via its bitaddressable control register T6CON.

GPT12E_T6CON Timer 6 Control Register SFR (FF48

1514131211109876543210

T6SRT6

CLR

rw rw - rw rwh rw - rw rw rw rw

- BPS2

OTLT6OE

Field Bits Typ Description T6SR 15 rw Timer 6 Reload Mode Enable

0 Reload from register CAPREL Disabled 1 Reload from register CAPREL Enabled

/A4H) Reset Value: 0000

T6R T6M T6I

T6CLR 14 rw Timer T6 Clear Enable Bit

0 Timer T6 is not cleared on a capture event 1 Timer T6 is cleared on a capture event

BPS2 [12:11] rw GPT2 Block Prescaler Control

Selects the basic clock for block GPT2 (see also Section 14.2.6) 00 01 10 11

GPT

/4 /2 /16 /8

T6OTL 10 rwh Timer T6 Overflow Toggle Latch

Toggles on each overflow/underflow of T6. Can be set or reset by software (see separate description)

T6OE 9rwOverflow/Underflow Output Enable

0 Alternate Output Function Disabled 1 State of T6 toggle latch is output on pin T6OUT

T6UD 7rwTimer T6 Up/Down Control

0 Timer T6 counts up 1 Timer T6 counts down

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Field Bits Typ Description T6R 6rwTimer T6 Run Bit

0 Timer T6 stops 1Timer T6 runs

T6M [5:3] rw Timer T6 Mode Control (Basic Operating Mode)

T6I [2:0] rw Timer T6 Input Parameter Selection

Depends on the operating mode, see respective sections for encoding:

Table 14-15 for Timer Mode and Gated Timer Mode Table 14-11 for Counter Mode

Timer T6 Run Control

The core timer T6 can be started or stopped by software through bit T6R (timer T6 run bit). This bit is relevant in all operating modes of T6. Setting bit T6R will start the timer, clearing bit T6R stops the timer.

In gated timer mode, the timer will only run if T6R = 1 and the gate is active (high or low, as programmed).

Note: When bit T5RC in timer control register T5CON is set, bit T6R will also control

(start and stop) the Auxiliary Timer T5.

Count Direction Control

The count direction of the GPT2 timers (core timer and auxiliary timer) can be controlled by software. The count direction can be altered by setting or clearing bit TxUD. The count direction can be changed regardless of whether or not the timer is running.

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Timer 6 Output Toggle Latch

The overflow/underflow signal of timer T6 is connected to a block named ‘Toggle Latch’, shown in the timer mode diagrams. Figure 14-21 illustrates the details of this block. An overflow or underflow of T6 will clock two latches: The first latch represents bit T6OTL in control register T6CON. The second latch is an internal latch toggled by T6OTL’s output. Both latch outputs are connected to the input control block of the auxiliary timer T5. The output level of the shadow latch will match the output level of T6OTL, but is delayed by one clock cycle. When the T6OTL value changes, this will result in a temporarily different output level from T6OTL and the shadow latch, which can trigger the selected count event in T5.

When software writes to T6OTL, both latches are set or cleared simultaneously. In this case, both signals to the auxiliary timers carry the same level and no edge will be detected. Bit T6OE (overflow/underflow output enable) in register T6CON enables the state of T6OTL to be monitored via an external pin T6OUT. When T6OTL is linked to an external port pin (must be configured as output), T6OUT can be used to control external HW. If T6OE = 1, pin T6OUT outputs the state of T6OTL. If T6OE = 0, pin T6OUT outputs a high level (while it selects the timer output signal).

As can be seen from Figure 14-21, when latch T6OTL is modified by software to determine the state of the output line, also the internal shadow latch is set or cleared accordingly. Therefore, no trigger condition is detected by T5 in this case.

TxOE

MUX

To Port Logic

To Aux. Timer Input Logic

mc_gpt0106_otl.vsd

TxOUT

Core Timer

Overflow/ Underflow

Set/Clear (SW )

TxOTL

Toggle Latch Logic

Shadow

Latch

Figure 14-21 Block Diagram of the Toggle Latch Logic of Core Timer T6

Note: T6 is also used to clock the timers in the CAPCOM units. For this purpose, there

is a direct internal connection between the T6 overflow/underflow line and the CAPCOM timers (signal T6OUF).

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14.2.2 GPT2 Core Timer T6 Operating Modes

Timer 6 in Timer Mode

Timer mode for the core timer T6 is selected by setting bitfield T6M in register T6CON to 000 programmable prescalers controlled by bitfields BPS2 and T6I in register T6CON. Please see Section 14.2.6 for details on the input clock options.

. In this mode, T6 is clocked with the module’s input clock f

GPT

Prescaler Core Timer T6 Toggle Latch

BPS2 T6I

Count

T6R

divided by two

GPT

T6IRQ

T6OUT

to T5/

CAPREL

T6OUF

T6UD

Up/Down

Figure 14-22 Block Diagram of Core Timer T6 in Timer Mode

MCB05403

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Gated Timer Mode

Gated timer mode for the core timer T6 is selected by setting bitfield T6M in register T6CON to 010

or 011B. Bit T6M.0 (T6CON.3) selects the active level of the gate input.

The same options for the input frequency are available in gated timer mode as in timer mode (see Section 14.2.6). However, the input clock to the timer in this mode is gated by the external input pin T6IN (Timer T6 External Input). To enable this operation, the associated pin T6IN must be configured as input (the corresponding direction control bit must contain 0).

T6IRQ

GPT

T6IN

Prescaler

BPS2 T6I

Gate

Ctrl.

T6R

Count

Core Timer T6 Toggle Latch

Clear

T6OUT

to T5,

CAPREL

T6OUF

T6UD

Up/Down

MCB05404

Figure 14-23 Block Diagram of Core Timer T6 in Gated Timer Mode

If T6M = 010 stops the timer. If T6M = 011

, the timer is enabled when T6IN shows a low level. A high level at this line

, line T6IN must have a high level in order to enable the

timer. Additionally, the timer can be turned on or off by software using bit T6R. The timer will only run if T6R is 1 and the gate is active. It will stop if either T6R is 0 or the gate is inactive.

Note: A transition of the gate signal at pin T6IN does not cause an interrupt request.

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Counter Mode

Counter mode for the core timer T6 is selected by setting bitfield T6M in register T6CON to 001

. In counter mode, timer T6 is clocked by a transition at the external input pin

T6IN. The event causing an increment or decrement of the timer can be a positive, a negative, or both a positive and a negative transition at this line. Bitfield T6I in control register T6CON selects the triggering transition (see Table 14-11).

T6IRQ

Edge

T6IN

Select

T6I

T6R

Count

T6UD

Core Timer T6 Toggle Latch

Clear

Up/Down

T6OUT

to T5,

CAPREL

T6OUF

MCB05405

Figure 14-24 Block Diagram of Core Timer T6 in Counter Mode

Table 14-11 GPT2 Core Timer T6 (Counter Mode) Input Edge Selection T6I Triggering Edge for Counter Increment/Decrement

0 0 0 None. Counter T6 is disabled 0 0 1 Positive transition (rising edge) on T6IN 0 1 0 Negative transition (falling edge) on T6IN 0 1 1 Any transition (rising or falling edge) on T6IN 1 X X Reserved. Do not use this combination

For counter mode operation, pin T6IN must be configured as input (the respective direction control bit DPx.y must be 0). The maximum input frequency allowed in counter mode depends on the selected prescaler value. To ensure that a transition of the count input signal applied to T6IN is recognized correctly, its level must be held high or low for a minimum number of module clock cycles before it changes. This information can be found in Section 14.2.6.

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14.2.3 GPT2 Auxiliary Timer T5 Control

Auxiliary timer T5 can be configured for timer mode, gated timer mode, or counter mode with the same options for the timer frequencies and the count signal as the core timer T6. In addition to these 3 counting modes, the auxiliary timer can be concatenated with the core timer. The contents of T5 may be captured to register CAPREL upon an external or an internal trigger. The start/stop function of the auxiliary timers can be remotely controlled by the T6 run control bit. Several timers may thus be controlled synchronously.

The current contents of the auxiliary timer are reflected by its count register T5. This register can also be written to by the CPU, for example, to set the initial start value.

The individual configurations for timer T5 are determined by its bitaddressable control register T5CON. Some bits in this register also control the function of the CAPREL register. Note that functions which are present in all timers of block GPT2 are controlled in the same bit positions and in the same manner in each of the specific control registers.

Note: The auxiliary timer has no output toggle latch and no alternate output function.

GPT12E_T5CON Timer 5 Control Register SFR (FF46

/A3H) Reset Value: 0000

1514131211109876543210

T5SCT5

CLR

rw rw rw rw rw rw - rw rw rw rw

CT3

T5R T5M T5I

Field Bits Typ Description T5SC 15 rw Timer 5 Capture Mode Enable

0 Capture into register CAPREL Disabled 1 Capture into register CAPREL Enabled

T5CLR 14 rw Timer T5 Clear Enable Bit

0 Timer T5 is not cleared on a capture event 1 Timer T5 is cleared on a capture event

CI [13:12] rw Register CAPREL Capture Trigger Selection

(depending on bit CT3) 00 Capture disabled 01 Positive transition (rising edge) on CAPIN or

any transition on T3IN

10 Negative transition (falling edge) on CAPIN or

any transition on T3EUD

11 Any transition (rising or falling edge) on CAPIN

or any transition on T3IN or T3EUD

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Field Bits Typ Description T5CC 11 rw Timer T5 Capture Correction

0 T5 is just captured without any correction 1 T5 is decremented by 1 before being captured

CT3 10 rw Timer T3 Capture Trigger Enable

0 Capture trigger from input line CAPIN 1 Capture trigger from T3 input lines T3IN and/or

T3EUD

T5RC 9rwTimer T5 Remote Control

0 Timer T5 is controlled by its own run bit T5R 1 Timer T5 is controlled by the run bit T6R of

core timer 6, not by bit T5R

T5UD 7rwTimer T5 Up/Down Control

0 Timer T5 counts up 1 Timer T5 counts down

T5R 6rwTimer T5 Run Bit

0 Timer T5 stops 1Timer T5 runs

Note: This bit only controls timer T5 if bit T5RC = 0.

T5M [5:3] rw Timer T5 Mode Control (Basic Operating Mode)

000 Timer Mode 001 Counter Mode 010 Gated Timer Mode with gate active low 011 Gated Timer Mode with gate active high 1XX Reserved. Do not use this combination

T5I [2:0] rw Timer T5 Input Parameter Selection

Depends on the operating mode, see respective sections for encoding:

Table 14-15 for Timer Mode and Gated Timer Mode Table 14-11 for Counter Mode

Timer T5 Run Control

The auxiliary timer T5 can be started or stopped by software in two different ways:

• Through the associated timer run bit (T5R). In this case it is required that the respective control bit T5RC = 0.

• Through the core timer’s run bit (T6R). In this case the respective remote control bit must be set (T5RC = 1).

The selected run bit is relevant in all operating modes of T5. Setting the bit will start the timer, clearing the bit stops the timer.

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In gated timer mode, the timer will only run if the selected run bit is set and the gate is active (high or low, as programmed).

Note: If remote control is selected T6R will start/stop timer T6 and the auxiliary timer T5

synchronously.

14.2.4 GPT2 Auxiliary Timer T5 Operating Modes

The operation of the auxiliary timer in the basic operating modes is almost identical with the core timer’s operation, with very few exceptions. Additionally, some combined operating modes can be selected.

Timer T5 in Timer Mode

Timer Mode for the auxiliary timer T5 is selected by setting its bitfield T5M in register T5CON to 000

GPT

Prescaler

Count

Auxiliary

Timer T5

T5IRQ

BPS2 T5I

T5R

T6R

MUX

T5RC

T5UD

Clear

Up/Down

MCB05406

Figure 14-25 Block Diagram of Auxiliary Timer T5 in Timer Mode

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Timer T5 in Gated Timer Mode

Gated timer mode for the auxiliary timer T5 is selected by setting bitfield T5M in register T5CON to 010

or 011B. Bit T5M.0 (T5CON.3) selects the active level of the gate input.

Note: A transition of the gate signal at line T5IN does not cause an interrupt request.

MUX

T5RC

Count

Auxiliary

Timer T5

Clear

T5IRQ

GPT

T5IN

Prescaler

BPS2 T5I

Gate

Ctrl.

T5R

T6R

T5UD

Up/Down

MCB05407

Figure 14-26 Block Diagram of Auxiliary Timer T5 in Gated Timer Mode

Note: There is no output toggle latch for T5.

Start/stop of the auxiliary timer can be controlled locally or remotely.

Timer T5 in Counter Mode

Counter mode for auxiliary timer T5 is selected by setting bitfield T5M in register T5CON to 001

. In counter mode, the auxiliary timer can be clocked either by a transition at its

external input line T5IN, or by a transition of timer T6’s toggle latch T6OTL. The event causing an increment or decrement of a timer can be a positive, a negative, or both a positive and a negative transition at either the respective input pin or at the toggle latch. Bitfield T5I in control register T5CON selects the triggering transition (see Table 14-12).

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T5R

T6R

Edge

Select

T5I

MUX

T5RC

T5IN

T6 Toggle Latch

MUX

T5I.2

The General Purpose Timer Units

Count

T5UD

Auxiliary

Timer T5

Clear

Up/Down

T5IRQ

MCB05408

Figure 14-27 Block Diagram of Auxiliary Timer T5 in Counter Mode

Table 14-12 GPT2 Auxiliary Timer (Counter Mode) Input Edge Selection T5I Triggering Edge for Counter Increment/Decrement

X 0 0 None. Counter T5 is disabled 0 0 1 Positive transition (rising edge) on T5IN 0 1 0 Negative transition (falling edge) on T5IN 0 1 1 Any transition (rising or falling edge) on T5IN 1 0 1 Positive transition (rising edge) of T6 toggle latch T6OTL 1 1 0 Negative transition (falling edge) of T6 toggle latch T6OTL 1 1 1 Any transition (rising or falling edge) of T6 toggle latch T6OTL

Note: Only state transitions of T6OTL which are caused by the overflows/underflows of

T6 will trigger the counter function of T5. Modifications of T6OTL via software will NOT trigger the counter function of T5.

For counter operation, pin T5IN must be configured as input (the respective direction control bit DPx.y must be 0). The maximum input frequency allowed in counter mode depends on the selected prescaler value. To ensure that a transition of the count input signal applied to T5IN is recognized correctly, its level must be held high or low for a minimum number of module clock cycles before it changes. This information can be found in Section 14.2.6.

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Timer Concatenation

Using the toggle bit T6OTL as a clock source for the auxiliary timer in counter mode concatenates the core timer T6 with the auxiliary timer T5. This concatenation forms either a 32-bit or a 33-bit timer/counter, depending on which transition of T6OTL is selected to clock the auxiliary timer.

• 32-bit Timer/Counter: If both a positive and a negative transition of T6OTL are used to clock the auxiliary timer, this timer is clocked on every overflow/underflow of the core timer T6. Thus, the two timers form a 32-bit timer.

• 33-bit Timer/Counter: If either a positive or a negative transition of T6OTL is selected to clock the auxiliary timer, this timer is clocked on every second overflow/underflow of the core timer T6. This configuration forms a 33-bit timer (16-bit core timer + T6OTL + 16-bit auxiliary timer). As long as bit T6OTL is not modified by software, it represents the state of the internal toggle latch, and can be regarded as part of the 33-bit timer.

The count directions of the two concatenated timers are not required to be the same. This offers a wide variety of different configurations.

T6, which represents the low-order part of the concatenated timer, can operate in timer mode, gated timer mode or counter mode in this case.

T6IRQ

GPT

T6IN

T5IN

Operating

Mode

Control

BPS2 T6I

MUX

T5I.2

T6R

Edge

Select

T5I

Count

T5R

T6R

Core Timer T6

Clear

MUX

T5RC

Up/Down

Count

Toggle Latch T6OUT

Auxiliary

Timer T5

Clear Up/Down

T5IRQ

MCA05409

Figure 14-28 Concatenation of Core Timer T6 and Auxiliary Timer T5

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14.2.5 GPT2 Register CAPREL Operating Modes

In addition to the capture function, the capture trigger signal can also be used to clear the contents of timers T5 and T6 individually.

The functions of register CAPREL are controlled via several bit(field)s in the timer control registers T5CON and T6CON.

GPT2 Capture/Reload Register CAPREL in Capture Mode

Capture mode for register CAPREL is selected by setting bit T5SC in control register T5CON (set bitfield CI in register T5CON to a non-zero value to select a trigger signal). In capture mode, the contents of the auxiliary timer T5 are latched into register CAPREL in response to a signal transition at the selected external input pin(s). Bit CT3 selects the external input line CAPIN or the input lines T3IN and/or T3EUD of GPT1 timer T3 as the source for a capture trigger. Either a positive, a negative, or both a positive and a negative transition at line CAPIN can be selected to trigger the capture function, or transitions on input T3IN or input T3EUD or both inputs, T3IN and T3EUD. The active edge is controlled by bitfield CI in register T5CON. Table 14-13 summarizes these options.

Table 14-13 CAPREL Register Input Edge Selection CT3 CI Triggering Signal/Edge for Capture Mode

X 0 0 None. Capture Mode is disabled. 0 0 1 Positive transition (rising edge) on CAPIN. 0 1 0 Negative transition (falling edge) on CAPIN. 0 1 1 Any transition (rising or falling edge) on CAPIN. 1 0 1 Any transition (rising or falling edge) on T3IN. 1 1 0 Any transition (rising or falling edge) on T3EUD. 1 1 1 Any transition (rising or falling edge) on T3IN or T3EUD.

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Count Clock

Clear

Edge

CAPIN

T3IN

T3EUD

Select

Signal Select

MUX

CT3

T5CLR

Capture

T5SC

The General Purpose Timer Units

Auxiliary

Timer T5

Up/Down

Capture Correction

CAPREL

T5CC

T5IRQ

CRIRQ

Clear T6

T6CLR

MCA05410

Figure 14-29 GPT2 Register CAPREL in Capture Mode

When a selected trigger is detected, the contents of the auxiliary timer T5 are latched into register CAPREL and the interrupt request line CRIRQ is activated. The same event can optionally clear timer T5 and/or timer T6. This option is enabled by bit T5CLR in register T5CON and bit T6CLR in register T6CON, respectively. If TxCLR = 0 the contents of timer Tx is not affected by a capture. If TxCLR = 1 timer Tx is cleared after the current timer T5 value has been latched into register CAPREL.

Note: Bit T5SC only controls whether or not a capture is performed. If T5SC is cleared

the external input pin(s) can still be used to clear timer T5 and/or T6, or as external interrupt input(s). This interrupt is controlled by the CAPREL interrupt control register CRIC.

When capture triggers T3IN or T3EUD are enabled (CT3 = 1), register CAPREL captures the contents of T5 upon transitions of the selected input(s). These values can be used to measure T3’s input signals. This is useful, for example, when T3 operates in

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XC161 Derivatives

Peripheral Units (Vol. 2 of 2)

The General Purpose Timer Units

incremental interface mode, in order to derive dynamic information (speed, acceleration) from the input signals.

For capture mode operation, the selected pins CAPIN, T3IN, or T3EUD must be configured as input. To ensure that a transition of a trigger input signal applied to one of these inputs is recognized correctly, its level must be held high or low for a minimum number of module clock cycles, detailed in Section 14.2.6.

GPT2 Capture/Reload Register CAPREL in Reload Mode

Reload mode for register CAPREL is selected by setting bit T6SR in control register T6CON. In reload mode, the core timer T6 is reloaded with the contents of register CAPREL, triggered by an overflow or underflow of T6. This will not activate the interrupt request line CRIRQ associated with the CAPREL register. However, interrupt request line T6IRQ will be activated, indicating the overflow/underflow of T6.

CAPREL

Reload

Count Clock

Core Timer T6

Up/Down

Figure 14-30 GPT2 Register CAPREL in Reload Mode

T6SR

T6IRQ

Toggle Latch T6OUT

T6OUF

to T5

MCA05411

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Peripheral Units (Vol. 2 of 2)

The General Purpose Timer Units

GPT2 Capture/Reload Register CAPREL in Capture-And-Reload Mode

Since the reload function and the capture function of register CAPREL can be enabled individually by bits T5SC and T6SR, the two functions can be enabled simultaneously by setting both bits. This feature can be used to generate an output frequency that is a multiple of the input frequency.

Count Clock

CAPIN

T3IN

T3EUD

Edge

Select

Edge

Select

Clear

T5CLR

MUX

CT3

T5SC

Capture

Auxiliary

Timer T5

Up/Down

CAPREL

Capture Correction

T5IRQ

T5CC

Count Clock

T6CLR

Reload

Clear

Core Timer T6

T6SR

Toggle Latch T6OUT

Up/Down

CRIRQ

T6IRQ

T6OUF

to T5

MCA05412

Figure 14-31 GPT2 Register CAPREL in Capture-And-Reload Mode

This combined mode can be used to detect consecutive external events which may occur aperiodically, but where a finer resolution, that means, more ‘ticks’ within the time between two external events is required.

For this purpose, the time between the external events is measured using timer T5 and the CAPREL register. Timer T5 runs in timer mode counting up with a frequency of e.g.

/32. The external events are applied to pin CAPIN. When an external event occurs,

GPT

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The General Purpose Timer Units

the contents of timer T5 are latched into register CAPREL and timer T5 is cleared (T5CLR = 1). Thus, register CAPREL always contains the correct time between two events, measured in timer T5 increments. Timer T6, which runs in timer mode counting down with a frequency of e.g.

/4, uses the value in register CAPREL to perform a

GPT

reload on underflow. This means, the value in register CAPREL represents the time between two underflows of timer T6, now measured in timer T6 increments. Since (in this example) timer T6 runs 8 times faster than timer T5, it will underflow 8 times within the time between two external events. Thus, the underflow signal of timer T6 generates 8 ‘ticks’. Upon each underflow, the interrupt request line T6IRQ will be activated and bit T6OTL will be toggled. The state of T6OTL may be output on pin T6OUT. This signal has 8 times more transitions than the signal which is applied to pin CAPIN.

Note: The underflow signal of Timer T6 can furthermore be used to clock one or more of

the timers of the CAPCOM units, which gives the user the possibility to set compare events based on a finer resolution than that of the external events. This connection is accomplished via signal T6OUF.

Capture Correction

A certain deviation of the output frequency is generated by the fact that timer T5 will count actual time units (e.g. T5 running at 1 MHz will count up to the value 64

/100D for

a 10 kHz input signal), while T6OTL will only toggle upon an underflow of T6 (i.e. the transition from 0000 from 64

, so the underflow would occur after 101 timing ticks of T6. The actual output

to FFFFH). In the above mentioned example, T6 would count down

frequency then is 79.2 kHz, instead of the expected 80 kHz. This deviation can be compensated for by activating the Capture Correction (T5CC = 1).

If capture correction is active, the contents of T5 are decremented by 1 before being captured. The described deviation is eliminated (in the example, T5 would count up to the value 64

/99D, T6 would count exactly 100 ticks, and the output frequency is 80 kHz).

/100D, but the CAPREL register will capture the decremented value

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The General Purpose Timer Units

14.2.6 GPT2 Clock Signal Control

All actions within the timer block GPT2 are triggered by transitions of its basic clock. This basic clock is derived from the system clock by a basic block prescaler, controlled by bitfield BPS2 in register T6CON (see Figure 14-20). The count clock can be generated in two different ways:

• Internal count clock, derived from GPT2’s basic clock via a programmable prescaler, is used for (gated) timer mode.

• External count clock, derived from the timer’s input pin(s), is used for counter mode.

For both ways, the basic clock determines the maximum count frequency and the timer’s resolution:

Table 14-14 Basic Clock Selection for Block GPT2 Block Prescaler

Prescaling Factor for GPT2: F(BPS2)

BPS2 = 01

F(BPS2) = 2

BPS2 = 00

F(BPS2) = 4

BPS2 = 11

F(BPS2) = 8

BPS2 = 10

F(BPS2) = 16

Maximum External

/4 f

GPT

/8 f

GPT

/16 f

GPT

/32

Count Frequency Input Signal

× t

GPT

4 × t

GPT

8 × t

GPT

16 × t

GPT

Stable Time

1) Please note the non-linear encoding of bitfield BPS2.

2) Default after reset.

Internal Count Clock Generation

In timer mode and gated timer mode, the count clock for each GPT2 timer is derived from the GPT2 basic clock by a programmable prescaler, controlled by bitfield TxI in the respective timer’s control register TxCON.

The count frequency

for a timer Tx and its resolution rTx are scaled linearly with lower

clock frequencies, as can be seen from the following formula:

------------ ------------------------ ---------= r

GPT

F BPS2()2

µs[]

<Txl>

F BPS2()2

------------ ------------------------ ---------=

GPT

<Txl>

MHz[]

(14.2)

The effective count frequency depends on the common module clock prescaler factor

<TxI>

F(BPS2) as well as on the individual input prescaler factor 2

. Table 14-15

summarizes the resulting overall divider factors for a GPT2 timer that result from these cascaded prescalers.

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The General Purpose Timer Units

Table 14-15 GPT2 Overall Prescaler Factors for Internal Count Clock Individual

Prescaler for Tx

TxI = 000 TxI = 001 TxI = 010 TxI = 011 TxI = 100 TxI = 101 TxI = 110 TxI = 111

1) Please note the non-linear encoding of bitfield BPS2.

BPS2 = 01

24816 481632 8163264 16 32 64 128 32 64 128 256 64 128 256 512 128 256 512 1024 256 512 1024 2048

Common Prescaler for Module Clock

BPS2 = 00

BPS2 = 11

BPS2 = 10

Table 14-16 lists a timer’s parameters (such as count frequency, resolution, and period)

resulting from the selected overall prescaler factor and the applied system frequency. Note that some numbers may be rounded.

Table 14-16 GPT2 Timer Parameters

System Clock = 10 MHz

Frequency Resolution Period Frequency Resolution Period

Overall Divider

System Clock = 40 MHz

Factor

5.0 MHz 200 ns 13.11 ms

2.5 MHz 400 ns 26.21 ms

1.25 MHz 800 ns 52.43 ms

625.0 kHz 1.6

312.5 kHz 3.2

156.25 kHz 6.4

78.125 kHz 12.8

39.06 kHz 25.6

19.53 kHz 51.2

9.77 kHz 102.4

4.88 kHz 204.8

µs 104.9 ms 16 2.5 MHz 400 ns 26.21 ms µs 209.7 ms 32 1.25 MHz 800 ns 52.43 ms µs 419.4 ms 64 625.0 kHz 1.6 µs 104.9 ms

µs 838.9 ms 128 312.5 kHz 3.2 µs 209.7 ms µs 1.678 s 256 156.25 kHz 6.4 µs 419.4 ms µs 3.355 s 512 78.125 kHz 12.8 µs 838.9 ms

µs 6.711 s 1024 39.06 kHz 25.6 µs 1.678 s µs13.42 s2048 19.53 kHz 51.2 µs 3.355 s

2 20.0 MHz 50 ns 3.28 ms 4 10.0 MHz 100 ns 6.55 ms 8 5.0 MHz 200 ns 13.11 ms

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The General Purpose Timer Units

External Count Clock Input

The external input signals of the GPT2 block are sampled with the GPT2 basic clock (see

Figure 14-20). To ensure that a signal is recognized correctly, its current level (high or

Table 14-17 summarizes the resulting requirements for external GPT2 input signals.

Table 14-17 GPT2 External Input Signal Limits

System Clock = 10 MHz

Max. Input Frequency

Min. Level Hold Time

2.5 MHz 200 ns

Input Frequ. Factor

/4 01

GPT

GPT2 Divider BPS1

Input Phase Duration

2 × t

GPT

System Clock = 40 MHz

Max. Input Frequency

Min. Level Hold Time

10.0 MHz 50 ns

1.25 MHz 400 ns

625.0 kHz 800 ns

312.5 kHz 1.6

µs f

/8 00

GPT

/16 11

GPT

/32 10

GPT

4 × t 8 × t 16 × t

GPT

5.0 MHz 100 ns

2.5 MHz 200 ns

1.25 MHz 400 ns

These limitations are valid for all external input signals to GPT2, including the external count signals in counter mode and the gate input signals in gated timer mode.

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The General Purpose Timer Units

14.2.7 GPT2 Timer Registers

GPT12E_Tx Timer x Count Register SFR (FE4x

1514131211109876543210

Txvalue

Table 14-18 GPT1 Timer Register Locations Timer Register Physical Address 8-Bit Address

T5 FE46 T6 FE48

/2yH) Reset Value: 0000

rwh

GPT12E_CAPREL Capture/Reload Register SFR (FE4A

1514131211109876543210

Capture/Reloadvalue

rwh

/25H) Reset Value: 0000

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Peripheral Units (Vol. 2 of 2)

The General Purpose Timer Units

14.2.8 Interrupt Control for GPT2 Timers and CAPREL

When a timer overflows from FFFFH to 0000H (when counting up), or when it underflows from 0000 register TxIC will be set. Whenever a transition according to the selection in bit field CI is detected at pin CAPIN, interrupt request flag CRIR in register CRIC is set. Setting any request flag will cause an interrupt to the respective timer or CAPREL interrupt vector (T5INT, T6INT or CRINT) or trigger a PEC service, if the respective interrupt enable bit (T5IE or T6IE in register TxIC, CRIE in register CRIC) is set. There is an interrupt control register for each of the two timers and for the CAPREL register.

GPT12E_T5IC Timer 5 Intr. Ctrl. Reg. SFR (FF66

1514131211109876543210

-------GPXT5IRT5IE ILVL GLVL

- - - - - - - rw rwh rw rw rw

to FFFFH (when counting down), its interrupt request flag (T5IR or T6IR) in

/B3H) Reset Value: - - 00

GPT12E_T6IC Timer 6 Intr. Ctrl. Reg. SFR (FF68

1514131211109876543210

-------GPXT6IRT6IE ILVL GLVL

- - - - - - - rw rwh rw rw rw

/B4H) Reset Value: - - 00

GPT12E_CRIC CAPREL Intr. Ctrl. Reg. SFR (FF6A

1514131211109876543210

-------GPXCRIRCRIE ILVL GLVL

- - - - - - - rw rwh rw rw rw

/B5H) Reset Value: - - 00

Note: Please refer to the general Interrupt Control Register description for an

explanation of the control fields.

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Peripheral Units (Vol. 2 of 2)

The General Purpose Timer Units

14.3 Interfaces of the GPT Module

Besides the described intra-module connections, the timer unit blocks GPT1 and GPT2 are connected to their environment in two basic ways (see Figure 14-32):

• Internal connections interface the timers with on-chip resources such as clock generation unit, interrupt controller, or other timers.

• External connections interface the timers with external resources via port pins.

System

Control

Unit

Interrupt

Control

Unit

GPT

GPTDIS

T2IRQ

T3IRQ

T4IRQ

T5IRQ

T6IRQ

CRIRQ

General

Purpose

Timer

Units

T2EUD

T4EUD

T2IN

T3IN

T4IN

T3EUD

T3OUT

T5IN

T6IN

P5.15

P5.14

P3.7

P3.6

P3.5

P3.4

P3.3

P5.13

P5.12

Port Logic for P3 and P5

CAPCOM

Units

T6OUF

CAPIN

T6OUT

P3.2

P3.1

mc_gpt0104_modinterfacex1.vsd

Figure 14-32 GPT Module Interfaces

Port pins to be used for timer input signals must be switched to input, the respective direction control bits must be cleared (DPx.y = 0).

Port pins to be used for timer output signals must be switched to output, the respective direction control bits must be set (DPx.y = 1). The alternate timer output signal must be selected for these pins via the respective alternate select registers (see Chapter 7).

Interrupt nodes to be used for timer interrupt requests must be enabled and programmed to a specific interrupt level.

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Real Time Clock

15 Real Time Clock

The Real Time Clock (RTC) module of the XC161 basically consists of a chain of prescalers and timers. Its count clock is derived from the auxiliary oscillator or from the prescaled main oscillator. The RTC serves various purposes:

• 48-bit timer for long term measurements

• System clock to determine the current time and date (the RTC’s structure supports the direct representation of time and date)

• Cyclic time based interrupt (can be generated by any timer of the chain)

A number of programming options as well as interrupt request signals adjust the operation of the RTC to the application’s requirements. The RTC can continue its operation while the XC161 is in a power-saving mode, such that real time date and time information is provided.

Control Registers Data Registers Counter Registers Interrupt Control

RTC_CON RTC_T14REL RTC_T14 RTC_ISNC

SYSCON0

SYSCON3

RTC_CON Real Time Clock Control Register SYSCON0 General System Control Register SYSCON3 Power Management Control Reg. RTC_ISNC Interrupt Subnode Control Register RTC_IC RTC Interrupt Control Register

RTC_RELH

RTC_RELL

RTC_RTCH

RTC_RTCL

RTC_T14 Timer T14 Count Register RTC_T14REL Timer T14 Reload Register RTC_RTCH/L RTC Count Registers, High/Low RTC_RELH/L RTC Reload Reg., High/Low

RTC_IC

mca04463_xc.vsd

EEE

Figure 15-1 SFRs Associated with the RTC Module

The RTC module consists of a chain of 3 divider blocks:

• a selectable 8:1 divider (on - off)

• the reloadable 16-bit timer T14

• the 32-bit RTC timer block (accessible via RTC_RTCH and RTC_RTCL), made of: – the reloadable 10-bit timer CNT0 – the reloadable 6-bit timer CNT1 – the reloadable 6-bit timer CNT2 – the reloadable 10-bit timer CNT3

All timers count upwards. Each of the five timers can generate an interrupt request. All requests are combined to a common node request.

Note: The RTC registers are not affected by a system reset in order to maintain the

correct system time even when intermediate resets are executed.

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Real Time Clock

15.1 Defining the RTC Time Base

The timer chain of the RTC is clocked with the count clock signal f from the auxiliary oscillator or from the prescaled main oscillator (see Figure 15-2 and

Figure 15-3). Optionally prescaled by a factor of 8, this is the basic RTC clock.

Depending on the operating mode, timer T14 may provide the count increments used by the application and thus determine the input frequency of the RTC timer, that is, the RTC time base (see also Table 15-3).

The RTC is also supplied with the system clock

of the XC161. This clock signal is

SYS

used to control the RTC’s logic blocks and its bus interface. To synchronize properly to the count clock, the system clock must run at least four times faster than the count clock, this means

Aux.

OSC

SYS

≥ 4 × f

OSCa

CNT

REFCLK RUN

RTCa

RTCm

MUX

RTC

8:1

which is derived

RTC

MUX

CNT

RTC Count Clock

PRE

Main OSC

OSCm

32:1

Clock

Generation

Unit

SYS

Async Mode

Sync Mode

MUX

RTCCM SYSCON0.14

RTC Module Clock

MCB05413

Figure 15-2 RTC Clock Supply Block Diagram

For an example, Table 15-1 lists the interrupt period range and the T14 reload values (for a time base of 1 s and 1 ms):

Table 15-1 RTC Time Base Examples Oscillator

Frequency

32.768 kHz 30.52

T14 Intr. Period Reload Value A Reload Value B

Min. Max. T14REL Base T14REL Base

µs 16.0 s 8000

/F000H1.000 s FFDFH/

FFFC

1.007 ms/

0.977 ms

Note: Select one value from the reload value pairs, depending if the 8:1 prescaler is

disabled/enabled.

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Real Time Clock

Asynchronous Operation

When the system clock frequency becomes lower than 4

× f

proper synchronization

CNT

is not possible and count events may be missed. When the XC161 enters e.g. sleep mode the system clock stops completely and the RTC would stop counting.

In these cases the RTC can be switched to Asynchronous Mode (by setting bit RTCCM in register SYSCON0). In this mode the count registers are directly controlled by the count clock independent of the system clock (hence the name). Asynchronous operation ensures correct time-keeping even during sleep mode or powerdown mode.

However, as no synchronization between the count registers and the bus interface can be maintained in asynchronous mode, the RTC registers cannot be written. Read accesses may interfere with count events and, therefore, must be verified (e.g. by reading the same value with three consecutive read accesses).

Note: The access restrictions in asynchronous mode are only meaningful if the system

clock is not switched off, of course.

Switching Clocking Modes

The clocking mode of the RTC (synchronous or asynchronous) is selected via bit RTCCM in register SYSCON0. After reset, the RTC operates in Synchronous Mode (RTCCM = 0) with the 8:1 prescaler enabled.

The selected clocking mode also affects the access to RTC registers. Bit ACCPOS in register RTC_CON indicates if full register access is possible (ACCPOS = 1, default after reset) or not (ACCPOS = 0). This also indicates the current clocking mode.

Attention: Software should poll bit ACCPOS to determine the proper transition to

the intended clocking mode.

After switching to Asynchronous Mode (RTCCM = 1), bit ACCPOS = 0 indicates proper operation in Asynchronous Mode. In this case the system clock can be stopped or reduced.

After switching to Synchronous Mode, (RTCCM = 0), bit ACCPOS = 1 indicates proper operation in Synchronous Mode. In this case the RTC registers can again be accessed properly (read and write).

Note: The RTC might lose a counting event (edge of

) when switching from

CNT

synchronous mode to asynchronous mode while the 8:1 prescaler is disabled. For these applications it is, therefore, recommended to set up the RTC with the 8:1 prescaler enabled.

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Peripheral Units (Vol. 2 of 2)

Real Time Clock

Increased RTC Accuracy through Software Correction

The accuracy of the XC161’s RTC is determined by the oscillator frequency and by the respective prescaling factor (excluding or including T14 and the 8:1 prescaler). The accuracy limit generated by the prescaler is due to the quantization of a binary counter (where the average is zero), while the accuracy limit generated by the oscillator frequency is due to the difference between the ideal and real frequencies (and therefore accumulates over time). This effect is predictable and can be compensated. The total accuracy of the RTC can be further increased via software for specific applications that demand a high time accuracy.

The key to the improved accuracy is knowledge of the exact oscillator frequency. The relation of this frequency to the expected ideal frequency is a measure of the RTC’s deviation. The number of cycles, N, after which this deviation causes an error of can be easily computed. So, the only action is to correct the count by

±1 after each series

±1 cycle

of N cycles. The correction may be made cyclically, for instance, within an interrupt service routine, or by evaluating a formula when the RTC registers are read (for this the respective “last” RTC value must be available somewhere).

Note: For the majority of applications, however, the standard accuracy provided by the

RTC’s structure will be more than sufficient.

Adjusting the current RTC value would require reading and then writing the complete 48-bit value. This can only be accomplished by three successive accesses each. To avoid the hassle of reading/writing multi-word values, the RTC incorporates a correction option to simply add or suppress one count pulse.

This is done by setting bit T14INC or T14DEC, respectively, in register RTC_CON. This will add an extra count pulse (T14INC) upon the next count event, or suppress the next count event (T14DEC). The respective bit remains set until its associated action has been performed and is automatically cleared by hardware after this event.

Note: Setting both bits, T14INC and T14DEC, at the same time will have no effect on the

count values.

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Real Time Clock

15.2 RTC Run Control

If the RTC shall operate bit RUN in register RTC_CON must be set (default after reset). Bit RUN can be cleared, for example, to exclude certain operation phases from time keeping. The RTC can be completely disabled by setting the corresponding bit RTCDIS in register SYSCON3.

Note: A valid count clock is required for proper RTC operation, of course.

A reset for the RTC is triggered via software by setting bit RTCRST in register SYSCON0. In this case all RTC registers are set to their initial values and bit RTCRST is cleared automatically. A normal system reset does not affect the RTC registers and its operation (RTC_IC will be reset, however). The initialization software must ensure the proper RTC operating mode.

The RTC control register RTC_CON selects the basic operation of the RTC module.

RTC_CON Control Register ESFR (F110

/88H) Reset Value: 8003

1514131211109876543210

ACC POS

rh----------rwrwh rwh rw rw

----------

REF CLK

T14 INC

T14

DEC

PRE RUN

Field Bits Type Description ACCPOS 15 rh RTC Register Access Possible

0 No write access is possible, only

asynchronous reads

1 Registers can be read and written

REFCLK 4rwReference Clock Source

0 The RTC count clock is derived from the

auxiliary oscillator (

OSCa

)

1 The RTC count clock is derived from the main

oscillator (

OSCm

/32)

T14INC 3rwhIncrement Timer T14 Value

Setting this bit to 1 adds one count pulse upon the next count event, thus incrementing T14. This bit is cleared by hardware after incrementation.

T14DEC 2rwhDecrement Timer T14 Value

Setting this bit to 1 suppresses the next count event, thus decrementing T14. This bit is cleared by hardware after decrementation.

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Peripheral Units (Vol. 2 of 2)

Real Time Clock

Field Bits Type Description PRE 1rwRTC Input Source Prescaler Enable

0 Prescaler disabled, T14 clocked with 1 Prescaler enabled, T14 clocked with f

RUN 0rwRTC Run Bit

0 RTC stopped 1RTC runs

RTC

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Real Time Clock

15.3 RTC Operating Modes

The RTC can be configured for several operating modes according to the purpose it is meant to serve. These operating modes are configured by selecting appropriate reload values and interrupt signals.

PRE

1 MUX 0

Interrupt Sub Node

CNT

INT0

10 Bits 6 Bits 6 Bits 10 Bits

CNT

INT1

REL-Register

CNT

INT2

CNT

INT3

RTCINT

RTC

RUN

T14REL

CNT

T14

T14-Register CNT-Register

10 Bits 6 Bits 6 Bits 10 Bits

mcb04805_xc.vsd

Figure 15-3 RTC Block Diagram

RTC Register Access

The actual value of the RTC is indicated by the three registers T14, RTCL, and RTCH. As these registers are concatenated to build the RTC counter chain, internal overflows occur while the RTC is running. When reading or writing the RTC value, such internal overflows must be taken into account to avoid reading/writing corrupted values.

Care must be taken, when reading the timer(s), as this requires up to three read accesses to the different registers with an inherent time delay between the accesses. An overflow from T14 to RTCL and/or from RTCL to RTCH might occur between the accesses, which needs to be taken into account appropriately.

For example, reading/writing 0000

to RTCH and then accessing RTCL could produce

a corrupted value as RTCL may overflow before it can be accessed. In this case, RTCH would be 0001

. The same precautions must be taken for T14 and T14REL.

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Real Time Clock

Timer T14 and its reload register are accessed via dedicated locations. The four RTC counters CNT3 … CNT0 are accessed via the two 16-bit RTC timer registers, RTCH and RTCL. The associated four reload values REL3 … REL0 are accessed via the two 16-bit RTC reload registers, RELH and RELL.

Table 15-2 Register Locations for Timer T14 Register Name Long/Short

Address

RTC_T14 F0D2

/69

Reset Value

0000

Notes

16-bit timer, can be used as prescaler for the RTC block

RTC_T14REL F0D0

/68

0000

Timer T14 reload register

RTC_RTCH RTC Timer High Register ESFR (F0D6

1514131211109876543210

/6BH) Reset Value: 0000

CNT3 CNT2

rwh rwh

RTC_RTCL RTC Timer Low Register ESFR (F0D4

1514131211109876543210

CNT1 CNT0

rwh rwh

/6AH) Reset Value: 0000

Field Bits Type Description CNTx

(x = 3 … 0)

[15:6] [5:0] [15:10] [9:0]

rwh RTC Timer Count Section CNTx

An overflow of this bitfield triggers a count pulse to the next count section CNTx+1 (except for CNT3) followed by a reload of CNTx from bitfield RELx. In addition, an interrupt request is triggered.

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Peripheral Units (Vol. 2 of 2)

Real Time Clock

RTC_RELH RTC Reload High Register ESFR (F0CE

1514131211109876543210

REL3 REL2

rw rw

/67H) Reset Value: 0000

RTC_RELL RTC Reload Low Register ESFR (F0CC

1514131211109876543210

REL1 REL0

rw rw

/66H) Reset Value: 0000

Field Bits Type Description RELx

(x = 3 … 0)

[15:6] [5:0] [15:10]

rw RTC Reload Value RELx

This bitfield is copied to bitfield CNTx upon an overflow of count section CNTx.

[9:0]

Note: The registers of the RTC receive their reset values only upon a specific RTC reset.

This reset is not triggered upon a system reset, but via software.

User’s Manual 15-9 V2.2, 2004-01 RTC_X8, V2.1

XC161 Derivatives

Peripheral Units (Vol. 2 of 2)

Real Time Clock

15.3.1 48-bit Timer Operation

The concatenation of timers T14 and COUNT0 … COUNT3 can be regarded as a 48-bit timer which is clocked with the RTC input frequency, optionally divided by the prescaler. The reload registers T14REL, RELL, and RELH must be cleared to produce a true binary 48-bit timer. However, any other reload value may be used. Reload values other than zero must be used carefully, due to the individual sections of the RTC timer with their own individual overflows and reload values.

The maximum usable timespan is 2

(≈ 1014) T14 input clocks (assuming no prescaler),

which would equal more than 200 years at an oscillator frequency of 32 kHz.

15.3.2 System Clock Operation

A real time system clock can be maintained that keeps on running also during power saving modes (optionally) and indicates the current time and date. This is possible

because the RTC module is not affected by a system reset The resolution for this clock information is determined by the input clock of timer T14. By

selecting appropriate reload values each cascaded timer can represent directly a part of the current time and/or date. Due to its width, T14 can adjust the RTC to the intended range of operation (time or date). The maximum usable timespan is achieved when T14REL is loaded with 0000

and so T14 divides by 216.

System Clock Example

The RTC count clock is

(8:1 prescaler off). By selecting appropriate reload values

OSCa

the RTC timers directly indicate the current time (see Figure 15-4 and Table 15-3).

3E8

REL3

CNT3

Hours

REL2

CNT2

Minutes

REL1

CNT1

Seconds

018

REL0

CNT0

1/1000

Seconds

FFDF

T14REL

T14

Prescaler

CNT

32.768 kHz

MCA05414

Figure 15-4 RTC Configuration Example

Note: This setup can generate an interrupt request every millisecond, every second,

every minute, every hour, or every day.

1) After a power on reset, however, the RTC registers are undefined.

User’s Manual 15-10 V2.2, 2004-01 RTC_X8, V2.1

XC161 Derivatives

Peripheral Units (Vol. 2 of 2)

Each timer in the chain divides the clock by (2

<timer_width>

- <reload_value>) : 1, as the

Real Time Clock

timers count up. Table 15-3 shows the reload values which must be chosen for a specific scenario (i.e. operating mode of the RTC).

Table 15-3 Reload Value Scenarios

REL3 REL2 REL1 REL0 T14REL Formula 210 - 24 26 - 60 26 - 60 210 - 1000 216 - 33 Rel. Value 3E8

018

FFDF

Function h m s 1/1000 s Prescaler

Time of Day

Intr. Period day hour minute second millisec.

(Figure 15-4)

Formula 210 - 7 26 - 24 26 - 60 210 - 60 216 - 32768 Rel. Value 3F9

3C4

8000

Function day h m s Prescaler

Day of the

1) T14 errors in the first example (ms) can be compensated either by choosing an adapted value for REL0, or by using software correction.

Intr. Period week day hour minute second

Week

15.3.3 Cyclic Interrupt Generation

The RTC module can generate an interrupt request whenever one of the timers overflows and is reloaded. This interrupt request may be used, for example, to provide a system time tick independent of the CPU frequency without loading the general purpose timers, or to wake up regularly from sleep mode. The interrupt cycle time can be adjusted by choosing appropriate reload values and by enabling the appropriate interrupt request.

In this mode, the other operating modes can be combined. For example, a reload value of T14REL = F9C0 up the system regularly. Still the subsequent timers can be configured to represent the time or build a binary counter, however with a different time base.

(216 - 1600) generates a T14 interrupt request every 50 ms to wake-

User’s Manual 15-11 V2.2, 2004-01 RTC_X8, V2.1

XC161 Derivatives

Peripheral Units (Vol. 2 of 2)

Real Time Clock

15.4 RTC Interrupt Generation

The overflow signals of each timer of the RTC timer chain can generate an interrupt request. The RTC’s interrupt subnode control register ISNC combines these requests to activate the common RTC interrupt request line RTC_IRQ.

Each timer overflow sets its associated request flag in register ISNC. Individual enable bits for each request flag determine whether this request also activates the common interrupt line. The enabled requests are ORed together on this line (see Figure 15-5).

The interrupt handler can determine the source of an interrupt request via the specific request flags and must clear them after appropriate processing (not cleared by hardware). The common node request bit is automatically cleared when the interrupt handler is vectored to.

Note: If only one source is enabled, no additional software check is required, of course.

Both the individual request and the common interrupt node must be enabled.

CNT3 Overflow

CNT2 Overflow

CNT1 Overflow

CNT0 Overflow

T14 Overflow

Set

SW Clear

Set

SW Clear

Set

SW Clear

Set

SW Clear

Set

SW Clear

CNT3

CNT2

CNT1

CNT0

T14

CNT3

CNT2

CNT1

CNT0

T14

Interrupt Request RTC_IRQ

MCB05415

Figure 15-5 Interrupt Block Diagram

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XC161 Derivatives

Peripheral Units (Vol. 2 of 2)

Real Time Clock

RTC_ISNC Interrupt Subnode Ctrl. Reg. ESFR (F10C

1514131211109876543210

------

CNT

3IR

rwh rw rwh rw rwh rw rwh rw rwh rw

3IE

/86H) Reset Value: 0000

CNT

2IR

2IE

CNT

1IR

CNT

1IE

CNT

0IR

CNT

0IE

T14 IRT14

Field Bits Type Description CNTxIR

(x = 3 … 0)

9, 7, 5, 3rwh Section CNTx Interrupt Request Flag

0 No request pending 1 This source has raised an interrupt request

CNTxIE (x = 3 … 0)

8, 6, 4, 2rw Section CNTx Interrupt Enable Control Bit

0 Interrupt request is disabled 1 Interrupt request is enabled

T14IR 1rwhT14 Overflow Interrupt Request Flag

0 No request pending 1 This source has raised an interrupt request

T14IE 0rwT14 Overflow Interrupt Enable Control Bit

0 Interrupt request is disabled 1 Interrupt request is enabled

Note: The interrupt request flags in register ISNC must be cleared by software. They are

not cleared automatically when the service routine is entered.

RTC_IC RTC Interrupt Ctrl. Reg. ESFR (F1A0

1514131211109876543210

-------GPX

-------rw

/D0H) Reset Value: 0000

RTCIRRTC

rwh rw rw rw

ILVL GLVL

Note: Please refer to the general Interrupt Control Register description for an

explanation of the control fields. Register RTC_IC is not part of the RTC module and is reset with any system reset.

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XC161 Derivatives

Peripheral Units (Vol. 2 of 2)

The Analog/Digital Converter

16 The Analog/Digital Converter

The XC161 provides an Analog/Digital Converter with 8-bit or 10-bit resolution and a sample & hold circuit on-chip. An input multiplexer selects between up to 12 analog input channels (alternate functions of Port 5) either via software (fixed channel modes) or automatically (auto scan modes).

To fulfill most requirements of embedded control applications the ADC supports the following conversion modes:

• Fixed Channel Single Conversion

produces just one result from the selected channel

• Fixed Channel Continuous Conversion

repeatedly converts the selected channel

• Auto Scan Single Conversion

produces one result from each of a selected group of channels

• Auto Scan Continuous Conversion

repeatedly converts the selected group of channels

• Wait for ADDAT Read Mode

start a conversion automatically when the previous result was read

• Channel Injection Mode

start a conversion when a hardware trigger occurs, can insert the conversion of a specific channel into a group conversion (auto scan)

A set of SFRs and port pins provide access to control functions and results of the ADC. The enhanced-mode registers provide more detailed control functions for the ADC.

Data Registers Control Registers System Registers

ADC_DAT ADC_CON ADC_CIC

ADC_DAT2

Compatibility Mode: ADC_CON ADC Control Register ADC_CON1 ADC Control Register 1 Enhanced Mode: ADC_CTR0 ADC Control Register 0 ADC_CTR2 ADC Control Register 2 ADC_CTR2IN ADC Control Injection Register

ADC_CON1

ADC_CTR0

ADC_CTR2

ADC_CTR2IN

Interrupt Control

ADC_EIC

ADC_DAT ADC Result Register ADC_DAT2 ADC Injection Result Register ADC_CIC ADC End-of-Conversion Intr. Reg. ADC_EIC ADC Conversion-Error Intr. Reg. P5 Port 5 Analog Input Port

(AN15...AN12, AN7...AN0)

P5DIDIS Port 5 Digital Input Disable Reg.

P5DIDIS

SYSCON3

mc_adc0100_registers.vsd

Figure 16-1 SFRs and Port Pins Associated with the A/D Converter

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XC161 Derivatives

Peripheral Units (Vol. 2 of 2)

The external analog reference voltages V

AREF

and V

The Analog/Digital Converter

are fixed. The separate supply

AGND

for the ADC reduces the interference with other digital signals. The reference voltages must be stable during the reset calibration phase and during an entire conversion, to achieve a maximum of accuracy.

The sample time as well as the conversion time is programmable, so the ADC can be adjusted to the internal resistances of the analog sources and/or the analog reference voltage supply (you may also want to refer to application note AP2428).

CTR0

CON CTR2

CON1 CTR2IN

MUX

Injection Requests

Conversion Control

ADC_CIRQ ADC_EIRQ

AN0

AN7

AN12

AN15

MUX

Sample

Hold

8/10-bit

Capacitive Network

Conversion

DAT

DAT2

MCB05416

Figure 16-2 Analog/Digital Converter Block Diagram

The ADC is implemented as a capacitive network using successive approximation conversion. A conversion consists of 3 phases.

• During the sample phase, the capacitive network is connected to the selected analog

input and is charged or discharged to the voltage of the analog signal.

• During the actual conversion phase, the network is disconnected from the analog

input and is repeatedly charged or discharged via

during the steps of

AREF

successive approximation.

• After the (optional) post-calibration phase (to adjust the network to changing

conditions such as temperature) the result is written to the result register and an interrupt request is generated.

There are two sets of control, data, and status registers, one set for compatibility mode and one set for enhanced mode. Only one of these register sets may be active at a given time. As most of the bits and bitfields of the registers of the two sets control the same functionality or control the functionality in a very similar way, the following description is organized according to the functionality, not according to the two register sets.

User’s Manual 16-2 V2.2, 2004-01 ADC_X1, V2.1

XC161 Derivatives

Peripheral Units (Vol. 2 of 2)

The Analog/Digital Converter

16.1 Mode Selection

The analog input channels AN15 … AN12, AN7 … AN0 are alternate functions of Port 5 which is an input-only port. The Port 5 lines may either be used as analog or digital inputs. For pins that shall be used as analog inputs it is recommended to disable the digital input stage via register P5DIDIS. This avoids undesired cross currents and switching noise while the (analog) input signal level is between

and VIH.

The functions of the A/D converter are controlled by two sets of bit-addressable control registers. In compatibility mode, registers ADC_CON and ADC_CON1 are used, in enhanced mode, registers ADC_CTR0, ADC_CTR2, and ADC_CTR2IN are used. Their bitfields specify the analog channel to be acted upon, the conversion mode, and also reflect the status of the converter.

16.1.1 Compatibility Mode

In compatibility mode (MD = 0), registers ADC_CON and ADC_CON1 select the basic functions. The register layout is compatible with previous versions of the ADC module, while providing limited options.

ADC_CON ADC Control Register SFR (FFA0

1514131211109876543210

ADCTC ADSTC

rw rw rwh rw rw rwh rwh - rw rw

CRQ

CIN

AD WRAD

BSY

/D0H) Reset Value: 0000

- ADM ADCH

Field Bits Type Function ADCTC [15:14] rw ADC Conversion Time Control (Defines the ADC

basic conversion clock

00 01 10 11

f f f

BC BC BC BC

= f = f = f = f

ADC ADC ADC ADC

/4 /2 /16 /8

)

ADSTC [13:12] rw ADC Sample Time Control (Defines the ADC

sample time in a certain range) 00 01 10 11

t t t t

BC BC BC BC

× 8 × 16 × 32 × 64

ADCRQ 11 rwh ADC Channel Injection Request Flag ADCIN 10 rw ADC Channel Injection Enable

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Peripheral Units (Vol. 2 of 2)

The Analog/Digital Converter

Field Bits Type Function ADWR 9rwADC Wait for Read Control ADBSY 8rhADC Busy Flag

0 ADC is idle 1 A conversion is active

ADST 7rwhADC Start Bit

0 Stop a running conversion 1 Start conversion(s)

ADM [5:4] rw ADC Mode Selection

00 Fixed Channel Single Conversion 01 Fixed Channel Continuous Conversion 10 Auto Scan Single Conversion 11 Auto Scan Continuous Conversion

ADCH [3:0] rw ADC Analog Channel Input Selection

Selects the (first) ADC channel which is to be converted.

ADC_CON1 ADC Control Register 1 SFR (FFA6

1514131211109876543210

SAM

PLE

CAL RES ADCTC ADSTC

rh rh rw rw rw

ICST

/D3H) Reset Value: 0000

Field Bits Type Description ICST 15 rw Improved Conversion and Sample Timing

Selects the active timing control bitfields 0 Standard conversion and sample time control,

2-bit fields in ADC_CON (default after reset)

1 Improved conversion and sample time control,

6-bit fields in ADC_CON1

SAMPLE 14 rh Sample Phase Status Flag

0 A/D Converter is not in sampling 1 A/D Converter is currently in the sample phase

CAL 13 rh Reset Calibration Phase Status Flag

0 A/D Converter is not in calibration phase 1 A/D Converter is in calibration phase

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Peripheral Units (Vol. 2 of 2)

The Analog/Digital Converter

Field Bits Type Description RES 12 rw Conversion Resolution Control

0 10-bit resolution (default after reset) 1 8-bit resolution

ADCTC [11:6] rw ADC Conversion Time Control

Defines the ADC basic conversion clock:

= f

/ (<ADCTC> + 1)

ADC

ADSTC [5:0] rw ADC Sample Time Control

Defines the ADC sample time:

= tBC × 4 × (<ADSTC> + 1)

Note: The limit values for fBC (see data sheet) must not be exceeded when selecting

ADCTC and

ADC

16.1.2 Enhanced Mode

In enhanced mode (MD = 1), registers ADC_CTR0, ADC_CTR2, and ADC_CTR2IN select the basic functions. The register layout differs from the compatibility-mode layout, but this mode provides more options.

Conversion timing is selected via registers ADC_CTR2(IN), where ADC_CTR2 controls standard conversions and ADC_CTR2IN controls injected conversions.

ADC_CTR0 ADC Control Register 0 SFR (FFBE

1514131211109876543210

SAM

PLE

rw rh rw rwh rw rw rh rwh rw rw rw

ADCTS

CRQADCINADWRADBSYADST

/DFH) Reset Value: 1000

ADM

CAL OFF

ADCH

Field Bits Type Description MD 15 rw Mode Control

0 Compatibility Mode 1 Enhanced Mode

Note: Any modification of control bit MD is forbidden

while a conversion is currently running. User software must take care.

SAMPLE 14 rh Sample Phase Status Flag

0 A/D Converter is not in sample phase 1 A/D Converter in sample phase

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Peripheral Units (Vol. 2 of 2)

The Analog/Digital Converter

Field Bits Type Description ADCTS [13:12] rw Channel Injection Trigger Input Select

00 Channel injection trigger input disabled 01 Trigger input CAPCOM selected 10 Reserved 11 Reserved

Note: Reset value of bitfield ADCTS is 01

compatibility purposes.

ADCRQ 11 rwh Channel Injection Request Flag ADCIN 10 rw Channel Injection Enable Control ADWR 9rwWait for Read Control ADBSY 8rhBusy Flag

0 ADC is idle 1 A conversion is active

ADST 7rwhADC Start/Stop Control

0 Stop a running conversion 1 Start conversion(s)

for

ADM [6:5] rw Mode Selection Control

00 Fixed Channel Single Conversion 01 Fixed Channel Continuous Conversion 10 Auto Scan Single Conversion 11 Auto Scan Continuous Conversion

CALOFF 4rwCalibration Disable Control

0 Calibration cycles are executed 1 Calibration is disabled (off)

Note: This control bit is active in both compatibility

and enhanced mode.

ADCH [3:0] rw Analog Input Channel Selection

Selects the (first) ADC channel which is to be converted

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Peripheral Units (Vol. 2 of 2)

The Analog/Digital Converter

ADC_CTR2 ADC Control Register 2 ESFR (F09C

1514131211109876543210

- RES ADCTC ADSTC

-rw rw rw

/4EH) Reset Value: 0000

ADC_CTR2IN Injection Control Register 2 ESFR (F09E

1514131211109876543210

- RES ADCTC ADSTC

rrw rw rw

/4FH) Reset Value: 0000

Field Bits Type Description

RES [13:12] rw Converter Resolution Control

00 10-bit resolution (default after reset) 01 8-bit resolution 1x Reserved

ADCTC [11:6] rw ADC Conversion Time Control

Defines the ADC basic conversion clock:

= f

/ (<ADCTC> + 1)

ADC

ADSTC [5:0] rw ADC Sample Time Control

Defines the ADC sample time:

= tBC × 4 × (<ADSTC> + 1)

Note: The limit values for fBC (see data sheet) must not be exceeded when selecting

ADCTC and

ADC

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XC161 Derivatives

Peripheral Units (Vol. 2 of 2)

The Analog/Digital Converter

16.2 ADC Operation

Channel Selection, ADCH

Bitfield ADCH controls the input channel multiplexer logic. In the Single Channel Modes, it specifies the analog input channel which is to be converted. In the Auto Scan Modes, it specifies the highest channel number to be converted in the auto scan round.

ADCH may be changed while a conversion is in progress. The new value will go into effect after the current conversion is finished in the fixed channel modes, or after the current conversion round is finished in the auto scan modes.

ADC Flags, ADBSY, SAMPLE

The ADC Busy Status Flag is set when the ADC is started (by setting ADST) and remains set as long as the ADC performs conversions or calibration cycles.

ADBSY is cleared when the ADC is idle, meaning there are no conversion or calibration operations in progress.

Bit SAMPLE is set during the sample phase.

ADC Start/Stop Control, ADST

Bit ADST is used to start or to stop the ADC. A single conversion or a conversion sequence is started by setting bit ADST.

The busy flag ADBSY will be set and the converter then selects and samples the input channel, which is specified by the channel selection field ADCH. The sampled level will then be held internally during the conversion. When the conversion of this channel is complete, the result together with the number of the converted channel is transferred into the result register and the interrupt request is generated. The conversion result is placed into bitfield ADRES.

ADST remains set until cleared either by hardware or by software. Hardware clears the bit dependent on the conversion mode:

• In Fixed Channel Single Conversion mode, ADST is cleared after the conversion of

the specified channel is finished.

• In Auto Scan Single Conversion mode, ADST is cleared after the conversion of

channel 0 is finished.

Note: In the continuous conversion modes, ADST is never cleared by hardware.

Stopping the ADC via software is performed by clearing bit ADST. The reaction of the ADC depends on the conversion mode:

• In Fixed Channel Single Conversion mode, the ADC finishes the conversion and then

stops. There is no difference to the operation if ADST was not cleared by software.

• In Fixed Channel Continuous Conversion mode, the ADC finishes the current

conversion and then stops. This is the usual way to terminate this conversion mode.

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Peripheral Units (Vol. 2 of 2)

The Analog/Digital Converter

• In Auto Scan Single Conversion mode, the ADC continues the auto scan round until

the conversion of channel 0 is finished, then it stops. There is no difference to the operation if ADST was not cleared by software.

• In Auto Scan Continuous Conversion mode, the ADC continues the auto scan round

until the conversion of channel 0 is finished, then it stops. This is the usual way to terminate this conversion mode.

A restart of the ADC can be performed by clearing and then setting bit ADST. This sequence will abort the current conversion and restart the ADC with the new parameters given in the control registers.

Conversion Mode Selection, ADM

Bitfield ADM selects the conversion mode of the A/D converter, as listed in Table 16-1.

Table 16-1 A/D Converter Conversion Mode ADM Description

00 Fixed Channel Single Conversion 01 Fixed Channel Continuous Conversion 10 Auto Scan Single Conversion 11 Auto Scan Continuous Conversion

While a conversion is in progress, the mode selection field ADM and the channel selection field ADCH may be changed. ADM will be evaluated after the current conversion. ADCH will be evaluated after the current conversion (fixed channel modes) or after the current conversion sequence (auto scan modes).

Conversion Resolution Control, RES

The ADC can produce either a 10-bit result (RES = 0) or an 8-bit result (RES = 1). Depending on the application’s needs a higher conversion speed (an 8-bit conversion requires less conversion time) or a higher resolution can be chosen.

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Peripheral Units (Vol. 2 of 2)

The Analog/Digital Converter

Conversion Result

The result of a conversion is stored in the result register ADC_DAT, or in register ADC_DAT2 for an injected conversion.

The position of the result depends on the basic operating mode (compatibility or enhanced) and on the selected resolution (8-bit or 10-bit).

Note: Bitfield CHNR of register ADC_DAT is loaded by the ADC to indicate, which

channel the result refers to. Bitfield CHNR of register ADC_DAT2 is loaded by the CPU to select the analog channel, which is to be injected.

ADC_DAT ADC Result Register SFR (FEA0

1514131211109876543210

CHNR ADRES

rwh rwh

/50H) Reset Value: 0000

ADC_DAT2 ADC Chan. Inj. Result Reg. ESFR (F0A0

1514131211109876543210

CHNR ADRES

/50H) Reset Value: 0000

rwh

Field Bits Type Function CHNR [15:12] rw[h] Channel Number (identifies the converted analog

channel)

ADRES [11:0] rwh A/D Conversion Result

The digital result of the most recent conversion. In compatibility mode, the result is placed as follows: 8-bit: ADRES[9:2] 10-bit: ADRES[9:0] In enhanced mode, the result is placed as follows: 8-bit: ADRES[11:4] 10-bit: ADRES[11:2]

Note: Unused bits of ADRES are always set to 0.

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Peripheral Units (Vol. 2 of 2)

The Analog/Digital Converter

16.2.1 Fixed Channel Conversion Modes

These modes are selected by programming the mode selection bitfield ADM to 00 (single conversion) or to 01B (continuous conversion). After starting the converter through bit ADST the busy flag ADBSY will be set and the channel specified in bitfield ADCH will be converted. After the conversion is complete, the interrupt request flag ADCIR will be set.

In Single Conversion Mode the converter will automatically stop and reset bits ADBSY and ADST.

In Continuous Conversion Mode the converter will automatically start a new conversion of the channel specified in ADCH. ADCIR will be set after each completed conversion.

When bit ADST is reset by software, while a conversion is in progress, the converter will complete the current conversion and then stop and reset bit ADBSY.

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Peripheral Units (Vol. 2 of 2)

The Analog/Digital Converter

16.2.2 Auto Scan Conversion Modes

These modes are selected by programming the mode selection field ADM to 10B (single conversion) or to 11 a sequence of analog channels, beginning with the channel specified in bitfield ADCH and ending with channel 0, without requiring software to change the channel number. After starting the converter through bit ADST, the busy flag ADBSY will be set and the channel specified in bitfield ADCH will be converted. After the conversion is complete, the interrupt request flag ADCIR will be set and the converter will automatically start a new conversion of the next lower channel. ADCIR will be set after each completed conversion. After conversion of channel 0 the current sequence is complete.

In Single Conversion Mode the converter will automatically stop and reset bits ADBSY and ADST.

In Continuous Conversion Mode the converter will automatically start a new sequence beginning with the conversion of the channel specified in ADCH.

When bit ADST is reset by software, while a conversion is in progress, the converter will complete the current sequence (including conversion of channel 0) and then stop and reset bit ADBSY.

(continuous conversion). Auto Scan modes automatically convert

Conversion

of Channel..

Write ADC_DAT

ADC_DAT Full

Generate Interrupt

Request

Read of ADC_DAT;

Result of Channel:

# 3

# x

# x # 3

# 3

# 2

# 1 # 0

# 2

# 2 # 1

# 1

# 3 # 2

# 0 # 3

ADC_DAT Full;

Channnel 0 Result Lost

MC_ADC0001_AUTOSCAN

# 3

Overrun Error

Interrupt Request

Figure 16-3 Auto Scan Conversion Mode Example

Note: Auto Scan sequences that begin with channel numbers above 7 will generate (up

to) 4 invalid results from channels 11 … 8 which are not connected to input pins. Starting an Auto Scan sequence with ADCH = E

will generate the following

15 results: 14, 13, 12, x, x, x, x, 7, 6, 5, 4, 3, 2, 1, 0. Starting a sequence with ADCH = B

… 8H generates 4 … 1 invalid results at the

beginning of the sequence and therefore makes no sense in an application.

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Peripheral Units (Vol. 2 of 2)

The Analog/Digital Converter

16.2.3 Wait for Read Mode

If in default mode of the ADC a previous conversion result has not been read out of the result register by the time a new conversion is complete, the previous result is lost because it is overwritten by the new value, and the A/D overrun error interrupt request flag ADEIR will be set.

In order to avoid error interrupts and the loss of conversion results especially when using continuous conversion modes, the ADC can be switched to “Wait for Read Mode” by setting bit ADWR.

If the result value has not been read by the time the current conversion is complete, the new result is stored in a temporary buffer and the next conversion is suspended (ADST and ADBSY will remain set in the meantime, but no end-of-conversion interrupt will be generated). After reading the previous value the temporary buffer is copied into ADC_DAT (generating an ADCIR interrupt) and the suspended conversion is started. This mechanism applies to both single and continuous conversion modes.

Note: While in standard mode continuous conversions are executed at a fixed rate

(determined by the conversion time), in “Wait for Read Mode” there may be delays due to suspended conversions. However, this only affects the conversions, if the CPU (or PEC) cannot keep track with the conversion rate.

Conversion

of Channel..

Write ADC_DAT

ADC_DAT Full

Temp-Latch Full

Generate Interrupt

Request

Read of ADC_DAT;

Result of Channel:

# 3

# x

# 2 # 1 wait

# 2# 3

Figure 16-4 Wait for Read Mode Example

Hold Result in

Temp-Latch

# 3# 0

# 1 # 0 # 3

# 2# 3 # 1

# 0

MC_ADC0002_WAITREAD

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Peripheral Units (Vol. 2 of 2)

The Analog/Digital Converter

16.2.4 Channel Injection Mode

Channel Injection Mode allows the conversion of a specific analog channel (also while the ADC is running in a continuous or auto scan mode) without changing the current operating mode. After the conversion of this specific channel the ADC continues with the original operating mode.

Channel Injection mode is enabled by setting bit ADCIN and requires the Wait for Read Mode (ADWR = 1). The channel to be converted in this mode is specified in bitfield CHNR of register ADC_DAT2.

Note: Bitfield CHNR in ADC_DAT2 is not modified by the A/D converter, but only the

ADRES bitfield. Since the channel number for an injected conversion is not buffered, bitfield CHNR of ADC_DAT2 must never be modified during the sample phase of an injected conversion, otherwise the input multiplexer will switch to the new channel. It is recommended to only change the channel number with no injected conversion running.

Conversion

of Channel..

Write ADC_DAT;

ADC_DAT Full

Read ADC_DAT

Injected

Conversion

of Channel # y

ADC_DAT2 Full

Read ADC_DAT2

# x+1

# x

# x+1

# x-1

# x

Channel Injection Request

# x-2

# x-1

Figure 16-5 Channel Injection Example

# x-2

# y

Write ADC_DAT2

Int. Request

ADEINT

# x-3

# x-4

# x-3 # x-4

# x-3

MC_ADC0003_INJECT

# ...

# x-4

User’s Manual 16-14 V2.2, 2004-01 ADC_X1, V2.1

XC161 Derivatives

Peripheral Units (Vol. 2 of 2)

The Analog/Digital Converter

A channel injection can be triggered in two ways:

• setting of the Channel Injection Request bit ADCRQ via software

• a compare or a capture event of Capture/Compare register CC31 of the CAPCOM2

unit, which also sets bit ADCRQ.

The second method triggers a channel injection at a specific time, on the occurrence of a predefined count value of the CAPCOM timers or on a capture event of register CC31. This can be either the positive, the negative, or both the positive and the negative edge of an external signal. In addition, this option allows recording the time of occurrence of this signal.

Note: The channel injection request bit ADCRQ will be set on any interrupt request of

CAPCOM2 channel CC31, regardless whether the channel injection mode is enabled or not. It is recommended to always clear bit ADCRQ before enabling the channel injection mode.

After the completion of the current conversion (if any is in progress) the converter will start (inject) the conversion of the specified channel. When the conversion of this channel is complete, the result will be placed into the alternate result register ADC_DAT2, and a Channel Injection Complete Interrupt request will be generated, which uses the interrupt request flag ADEIR (for this reason the Wait for Read Mode is required).

Note: The result of an injected conversion is directly written to ADC_DAT2. If the

previous result has not been read in the meantime, it is overwritten. Standard conversions are suspended if the temporary buffer is full.

User’s Manual 16-15 V2.2, 2004-01 ADC_X1, V2.1

XC161 Derivatives

Peripheral Units (Vol. 2 of 2)

The Analog/Digital Converter

Arbitration of Conversions

Conversion requests that are activated while the ADC is idle immediately trigger the respective conversion. If a conversion is requested while another conversion is currently in progress the operation of the A/D converter depends on the kind of the involved conversions (standard or injected).

Note: A conversion request is activated if the respective control bit (ADST or ADCRQ)

is toggled from 0 to 1, i.e. the bit must have been zero before being set.

Table 16-2 summarizes the ADC operation in the possible situations.

Table 16-2 Conversion Arbitration Conversion

in Progress

Standard Injected

Standard Abort running conversion,

and start requested new conversion.

New Requested Conversion

Complete running conversion, start requested conversion after that.

Injected Complete running conversion,

start requested conversion after that.

Complete running conversion, start requested conversion after that. Bit ADCRQ will be 0 for the second conversion, however.

1) If an injected conversion is pending when a standard conversion is re-started, the injected conversion is executed before the newly started standard conversion.

User’s Manual 16-16 V2.2, 2004-01 ADC_X1, V2.1

XC161 Derivatives

Peripheral Units (Vol. 2 of 2)

The Analog/Digital Converter

16.3 Automatic Calibration

The ADC of the XC161 features automatic self-calibration. This calibration corrects gain errors, which are mainly due to process variation, and offset errors, which are mainly due to temperature changes.

Two types of calibration are supported:

• Reset calibration performs a thorough basic calibration of the ADC after a reset. In

particular this is required after a power-on reset.

• Post-calibration performs one small calibration step after each conversion.

Reset Calibration

After a reset, a thorough power-up calibration is performed automatically to correct gain and offset errors of the A/D converter. To achieve best calibration results, the reference voltages as well as the supply voltages must be stable during the power-up calibration. During the calibration sequence a series of calibration cycles is executed, where the step width for adjustments is reduced gradually. The total number of executed calibration cycles depends on the actual properties of the respective ADC module. The maximum duration of the power-up calibration is 11,696 cycles of the basic clock

Status flag CAL is set as long as this power-up calibration takes place.

Post-Calibration

After each conversion a small calibration step can be executed. For 8-bit and 10-bit conversions post-calibration is not mandatory in order not to exceed the total unadjusted error (TUE) specified in the data sheet. Post-calibration can be disabled by setting bit CALOFF in register ADC_CTR0. When disabled, the post-calibration cycles are skipped which reduces the total conversion time.

Note: Calibration may be disabled only after the reset calibration is complete.

User’s Manual 16-17 V2.2, 2004-01 ADC_X1, V2.1

XC161 Derivatives

Peripheral Units (Vol. 2 of 2)

The Analog/Digital Converter

16.4 Conversion Timing Control

When a conversion is started, first the capacitances of the converter are loaded via the respective analog input pin to the current analog input voltage. The time to load the capacitances is referred to as sample time. Next the sampled voltage is converted to a digital value in successive steps, which correspond to the resolution of the ADC. During these phases (except for the sample time) the internal capacitances are repeatedly charged and discharged via pins

The current that has to be drawn from the sources for sampling and changing charges depends on the time that each respective step takes, because the capacitors must reach their final voltage level within the given time, at least with a certain approximation. The maximum current, however, that a source can deliver, depends on its internal resistance.

The time that the two different actions during conversion take (sampling, and converting) can be programmed within a certain range in the XC161 relative to the CPU clock. The absolute time that is consumed by the different conversion steps therefore is independent from the general speed of the controller. This allows adjusting the A/D converter of the XC161 to the properties of the system:

AREF

and V

AGND

Fast Conversion can be achieved by programming the respective times to their absolute possible minimum. This is preferable for scanning high frequency signals. The internal resistance of analog source and analog supply must be sufficiently low, however.

High Internal Resistance can be achieved by programming the respective times to a higher value, or the possible maximum. This is preferable when using analog sources and supply with a high internal resistance in order to keep the current as low as possible. The conversion rate in this case may be considerably lower, however.

Control Bitfields

For the timing control of the conversion and the sample phase two mechanisms are provided:

• Standard timing control uses two 2-bit fields in register ADC_CON to select

prescaler values for the general conversion timing and the duration of the sample phase. This provides compact control, while limiting the prescaler factors to a few steps.

• Improved timing control uses two 6-bit fields in register ADC_CON1 (compatibility

mode) or register ADC_CTR2/ADC_CTR2IN (enhanced mode). This provides a wide range of prescaler factors, so the ADC can be better adjusted to the internal and external system circumstances.

Improved timing control is selected by setting bit ICST in register ADC_CON1 in compatibility mode, or by selecting enhanced mode.

User’s Manual 16-18 V2.2, 2004-01 ADC_X1, V2.1

Infineon Technologies XC161 User Manual

Specifications and Main Features

Frequently Asked Questions

User Manual

Table of Contents Page

14 The General Purpose Timer Units

14.1 Timer Block GPT1

14.1.1 GPT1 Core Timer T3 Control

14.1.2 GPT1 Core Timer T3 Operating Modes

14.1.3 GPT1 Auxiliary Timers T2/T4 Control

14.1.4 GPT1 Auxiliary Timers T2/T4 Operating Modes

14.1.5 GPT1 Clock Signal Control

14.1.6 GPT1 Timer Registers

14.1.7 Interrupt Control for GPT1 Timers

14.2 Timer Block GPT2

14.2.1 GPT2 Core Timer T6 Control

14.2.2 GPT2 Core Timer T6 Operating Modes

14.2.3 GPT2 Auxiliary Timer T5 Control

14.2.4 GPT2 Auxiliary Timer T5 Operating Modes

14.2.5 GPT2 Register CAPREL Operating Modes

14.2.6 GPT2 Clock Signal Control

14.2.7 GPT2 Timer Registers

14.2.8 Interrupt Control for GPT2 Timers and CAPREL

14.3 Interfaces of the GPT Module

15 Real Time Clock

15.1 Defining the RTC Time Base

15.2 RTC Run Control

15.3 RTC Operating Modes

15.3.1 48-bit Timer Operation

15.3.2 System Clock Operation

15.3.3 Cyclic Interrupt Generation

15.4 RTC Interrupt Generation

16 The Analog/Digital Converter

16.1 Mode Selection

16.1.1 Compatibility Mode

16.1.2 Enhanced Mode

16.2 ADC Operation

16.2.1 Fixed Channel Conversion Modes

16.2.2 Auto Scan Conversion Modes

16.2.3 Wait for Read Mode

16.2.4 Channel Injection Mode

16.3 Automatic Calibration

16.4 Conversion Timing Control