AADesign Guide for ICE2PCSxxApp
Never stop thinking.
Power Management & Supply
Design Guide for Boost Type CCM PFC with
ICE2PCSxx
Application note, Ver 1.0, May 2008
Edition 2008-08-01
Published by Infineon Technologies Asia Pacific,
168 Kallang Way,
349253 Singapore, Singapore
© Infineon Technologies AP 2005.
All Rights Reserved.
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Revision History: 2008-08 V1.0
Previous Version: none
Page Subjects (major changes since last revision)
Design Guide for Boost Type CCM PFC with ICE2PCSxx
License to Infineon Technologies Asia Pacific Pte Ltd AN-PS0029
Liu Jianwei
Luo Junyang
Jeoh Meng Kiat
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ICE2PCSxx
Table of Contents Page
Application Note 4 2008-08-01
1 Introduction ...................................................................................................................................5
2 Boost PFC design with ICE2PCXX ..............................................................................................7
2.1 Target specification .........................................................................................................................7
2.2 Bridge rectifier .................................................................................................................................7
2.3 Power MOSFET and Gate Drive Circuit .........................................................................................7
2.4 Boost Diode.....................................................................................................................................8
2.5 Boost inductor .................................................................................................................................9
2.6 AC line current filter.......................................................................................................................11
2.7 Boost Output Bulk Capacitance ....................................................................................................12
2.8 Current Sense Resistor.................................................................................................................12
2.9 Output voltage sensing divider......................................................................................................13
2.10 Frequency setting (only for ICE2PCS01)......................................................................................13
2.11 AC Brown-out Shutdown (only for ICE2PCS02)...........................................................................14
2.12 IC supply .......................................................................................................................................15
2.13 PCB layout guide ..........................................................................................................................16
3 Voltage loop and current loop compensation..........................................................................17
3.1 How to achieve PFC function without sinusoidal reference sensing ............................................18
3.2 Current Loop Regulation and Transfer Function...........................................................................19
3.3 Voltage Loop Compensation.........................................................................................................22
3.4 Design Example ............................................................................................................................28
3.5 Vcomp and M1, M2 value at full load condition ............................................................................29
Application Note 5 2008-08-01
Abstract
ICE2PCS01/02 are the 2
nd
generation of Continuous Conduction Mode (CCM) PFC controllers, which
employ
BiCMOS technology. Its control scheme does not need the direct sine-wave sensing reference
signal from the AC mains compared to the conventional PFC solution. Average current control is
implemented to achieve the unity power factor. In this application note, the design process for the boost PFC
with ICE2PCXX is presented and the design details for a 300W output power PFC with the universal input
voltage range of 85~265VAC are included.
1 Introduction
The Pin layout of ICE2PCS01 and ICE2PCS02 is shown in Figure 1.
1
6
7
8
4
3
2
5
GATEGND
ICOMP
ISENSE
VCC
VSENSE
FREQ
VCOMP
1
6
7
8
4
3
2
5
GATEGND
ICOMP
ISENSE
VCC
VSENSE
VINS
VCOMP
ICE2PCS01 ICE2PCS02
Figure 1 Pin Layout of ICE2PCS01 and ICE2PCS02
From the layout, it can be seen that most of Pins in ICE2PCS02 are the same as ICE2PCS01 except Pin 4.
In ICE2PCS01, Pin 4 is to set the switching frequency. However, for ICE2PCS02, Pin 4 is for AC brown out
detection and the switching frequency is fixed by internal oscillator at 65kHz. The typical application circuits
of ICE2PCS01 and ICE2PCS02 are shown in Figure 2 and Figure 3 respectively.
Application Note 6 2008-08-01
Figure 2 Typical application circuit of ICE2PCS01
Figure 3 Typical application circuit of ICE2PCS02
L1
T1
R1
R2
C
OUT
R
SENSE
EMI Filte
r
R3
GATE
GND VSENSE
ISENSE
C1
C2
R4
C3
VCOMP
VINS
ICOMP
VCC
Auxiliary Supply
ICE2PCS02
Rectifie
r
VIN=85V ...265V AC
V
OUT
=400VDC
C4
R6
R5
D
2
D
1
L1
T1
R1
R2
C
OUT
R
SENSE
EMI Filte
r
R3
GATE
GND VSENSE
ISENSE
C1 C2
R4
C3
VCOMP
FREQ
ICOMP
VCC
Auxiliary Supply
ICE2PCS01
Rectifie
r
VIN=85V ...265V AC
R
FREQ
V
OUT
=400VDC
D1
Application Note 7 2008-08-01
2 Boost PFC design with ICE2PCXX
2.1 Target specification
The fundamental electrical data of the circuit are the input voltage range Vin, the output power Pout, the
output voltage Vout, the operating switching frequency f
SW
and the value of the high frequency ripple of the
AC line current I
ripple
. Table 1 shows the relevant values for the system calculated in this Application Note.
The efficiency at rated output power Pout is estimated to 91 % over the complete input voltage range.
Input voltage 85VAC~265VAC
Input frequency 50Hz
Output voltage and current 390VDC, 0.76A
Output power 300W
Efficiency >90% at full load
Switching Frequency 65kHz
Maximum Ambient temperature around PFC 70ºC
Table 1 Design parameter for the proposed design
2.2 Bridge rectifier
In order to obtain 300W output power at 85 V minimum AC input voltage, the maximum input RMS current is
A
V
P
I
in
out
RMSin
92.3
%9085
300
min_
_
=
⋅
=
⋅
=
η
(1)
and the sinusoidal peak value of AC current is
AII
RMSinpkin
54.592.322
__
=⋅=⋅= (2)
For these values a bridge rectifier with an average current capability of 6A or higher is a good choice. Please
note here, that due to a power dissipation of approximately
WAVIVP
RMSinFBR
84.792.3122
_
=⋅⋅=⋅⋅= (3)
the rectifier bridge should be connected to an appropriate heatsink. Assuming a maximum junction
temperature T
Jmax
of 125°C, a maximum ambient temperature T
Amax
of 70°C, the thermal junction-to-case
R
thJC
of approximate 2.5 K/W and the thermal case to heatsink R
thCHS
of approximate 1K/W, the heatsink
must have a maximum thermal resistance of
WKRR
P
TT
R
thCHSthJC
BR
AJ
BRthHS
/52.315.2
84.7
70125
maxmax
_
=−−
−
=−−
−
=
(4)
2.3 Power MOSFET and Gate Drive Circuit
Due to the switch mode operation, the loss is only valid during the on-time of the MOSFET. The duty cycle of
the transistor in boost converters operating in CCM at minimum AC input RMS voltage is
782.0
390
85
11
min_
=−=−=
out
in
on
V
V
D
(5)
Application Note 8 2008-08-01
Since rms-values have the same effect on a system as DC-values, it is possible to calculate a characteristic
duty cycle for the rms-value. Therefore, the on-state loss of the MOSFET in CCM-mode at a junctiontemperature of 125°C is
)125(
2
_ CdsononRMSincond
RDIP ⋅⋅= (6)
the MOSFET switching loss can be estimated as
SWoffonSW
fEEP ⋅+= )( (7)
where, E
on
and E
off
are the switch-on and switch-off energy loss which can be found in MOSFET datasheet,
f
SW
is the switching frequency.
For 300W design, if SPP20N60C3 is used, the conduction loss is
WP
cond
05.542.0782.092.3
2
=⋅⋅=
assuming the switching current is about 6A and gate drive resistance Rg=3.6Ω, then the switching loss is
WkHzmWsmWsP
SW
43.165*)015.0007.0(
=
+=
the total loss is
WPPP
SWcondtotalMOS
48.6_=+= (8)
the required heatsink for the MOSFET is
WKRR
P
TT
R
thCHSMOSthJC
totalMOS
AJ
MOSthHS
/89.616.0
48.6
70125
_
_
maxmax
_
=−−
−
=−−
−
= (9)
thCHS
R is the Rth of the insulation pad between MOSFET and heatsink.
Gate drive resistance is used to drive MOSFET as fast as possible but also keep dv/dt within EMI
specification. In this 300W example, 3.6Ω gate resistor is chosen for SPP20N60C3 MOSFET.
Beside gate drive resistance, one 10kΩ resistor is also commonly connected between MOSFET gate and
source to discharge gate capacitor.
2.4 Boost Diode
The boost diode D1 has big influence on the system’s performance due to the reverse recovery behaviour.
So the Ultra-fast diode with very low t
rr
and Qrr is necessary to reduce the switching loss. The new diode
technology of silicon carbide (SiC) Schottky shows its outstanding performance with almost no reverse
recovery behaviour. The switching loss due to the boost diode can be ignored with SiC Schottky diode. Only
conduction loss is calculated as below.
WAVDIVP
onRMSinFdiode
71.1)782.01(92.32)1(
_
=−⋅
⋅=−⋅⋅= (10)
To decide the current rating of a SiC diode, there is a rule of thumb - the SiC diode can handle output power
Pout of 100 W to120 W in a CCM-PFC-system per one rated ampere. For example, the SDT04S60 from
Infineon Technologies is rated at a forward current IF = 4 A, so it is capable for a system of Pout = 4*100 W
= 400 W system in minimum. Therefore, this diode should be suitable for the proposed design.
The required heatsink for boost diode is
WKRR
P
TT
R
thCHSdiodethJC
diode
AJ
diodethHS
/06.2711.4
71.1
70125
_
maxmax
_
=−−
−
=−−
−
=
(11)
Application Note 9 2008-08-01
The SiC boost diodes often have a poor surge current handling capability. Therefore a so called bypass
diode is necessary such as the diode D3 as Figure 4. For the proposed system, 1N5408 is suitable.
L1
T1
R1
R2
C
OUT
R
SENSE
Rectifier
D1
D3
Figure 4 inrush current bypass diode
2.5 Boost inductor
The peak current that the inductor must carry is the peak line current at the lowest input voltage plus the high
frequency ripple current. The high frequency ripple current peak to peak, I
HF
, can be related to maximum
input power and minmum input voltage as equation below.
min_
max_
2
in
in
HF
V
P
kI ⋅⋅=
(12)
Where, k must be kept reasonably small, and is usually optimized in the range of 15% to 25% for cost
effective design based on the current magnetic component status. If k is too high, the larger AC input filter is
required to filter out this ripple noise. If k is too low, the value of the inductance is too large and leads to big
size of the magnetic core.
For example, we choose k = 22%, then,
A
V
P
I
in
in
HF
2.12%22
min_
max_
=⋅⋅=
The peak current passing through inductor is
A
I
II
HF
peakinpkL
14.6
2
2.1
54.5
2
__
=+=+=
(13)
The boost choke inductance must be
SWHF
out
boost
fI
VDD
L
⋅
⋅−⋅
≥
)1(
(14)
D=0.5 will generate the maximum value for the above equation.
mH
kH
z
A
V
L
boost
25.1
652.1
390)5.01(5.0
=
⋅
⋅−⋅
≥
The magnetic core of the boost choke can be either magnetic powder or ferrite material.
(1) sendust powder toroid core
The required effective magnetic volume of the core, V
e
, is
Application Note 10 2008-08-01
3322
max
_
0
6.1166.11)
8.0
14.6
(25.16257.1125)( cmme
T
A
mHe
B
I
LV
pkL
boostre
=−=⋅−⋅=≥
µµ
(15)
where,
r
µ
is the relative permeability of the material. It should be noted that
r
µ
changes with different
DC magnetizing force H, and so does the inductance. As an example, Figure 5 illustrates the relationship
between the Percent Permeability and the DC Magnetizing Force H.
0
µ
in (15) is the magnetic field constant which is equal to 1.257e-6; B
max
is the maximum magnetic flux
density for the selected magnetic material (for sendust, B
max
is up to 0.8T.)
Figure 5 Percent Permeability and DC Magnetizing Force H (from Changsung)
Select a core with similar Ve value from the magnetic core datasheet. For example, the core type
CS468125 from Chang Sung Corporation is selected. The parameters of CS468125 are V
e
=15.584cm3,
A
e
=1.34cm2, C=11.63cm,
r
µ
=125. The turn number of the boost choke winding is
83
0
_
=
⋅
=
er
boost
boosttoroid
A
CL
N
µµ
(16)
where, C is the magnetic path length and Ae is the effective magnetic cross section area.
To check the actual
r
µ
at low line, maximum power, the DC Magnetizing Force H is calculated
)(50_Oe
C
NI
H
pkin
==
Application Note 11 2008-08-01
Then
r
µ
= 125 * 50% = 62.5 according to Figure 5. The actual inductance can be re-calculated as
mH
C
AN
L
er
boost
625.0
0
2
==
µµ
. Hence, the corresponding ripple current will be higher than the
previously assumed value.
The copper loss of the winding wire can be calculated on I
in_RMS
.
boostLRMSinboostL
RIP
_
2
__
⋅= (17)
Select the proper wire type to fullfil the loss and thermal requirement for the choke.
(2) ferrite core
To make sure the ferrite core will not go into saturation, the turn number of the boost choke winding with
ferrite core is
minmax
_
_
AB
LI
N
boostpkL
boostferrite
⋅
⋅
≥
(18)
where, B
max
is up to 0.3T according to ferrite material specification; A
min
is the minimum magnetic cross
section area.
The winding wire copper loss calculation is the same as in the above section of sendust powder toroid
core.
2.6 AC line current filter
As decribed in section 2.5, there is high frequency ripple current peak to peak IHF passing through boost
choke. This ripple will also go into AC line power network. The current filter is necessary to reduce the
amplitude of high frequency current component. The filtering circuit consists of a capacitor and an inductor
as shown in Figure 6.
Current Filter
Rectifier
VIN=85V ...265VAC
L
filterCfilter
I
HF
I
HF_spec
Figure 6 AC line current filter
The required L
filter
is
filterSW
specHF
HF
filter
Cf
I
I
L
2
_
)2(
1
π
+
≥
(19)
normally there is one EMI X2 capacitor which can act as C
filter
. In this example, if we define I
HF_spec
as 0.2A
peak to peak and asumming X2 capacitance 0.47µF, then
H
FkHz
A
A
L
filter
µ
µπ
89
47.0)652(
1
2.0
2.1
2
=
⋅⋅
+
≥
Application Note 12 2008-08-01
The leakage inductance of EMI common mode choke can be used for current filter. If the leakage inductance
is large enough, no need to add the additional differential mode inductor for filtering. Otherwise, a current
filter choke is necessary. The calculation method for the current filter choke is the same as for boost choke.
2.7 Boost Output Bulk Capacitance
The bulk capacitance has to fullfil two requirements, output double line frequency ripple and holdup time.
(1) output double line frequency ripple limit.
The inherent PFC always presents 2*f
L
ripple. The amplitude of ripple voltage is dependant on output
current and bulk capacitance as below.
pprippleoutL
out
out
Vf
I
C
__
*2 ⋅⋅
≥
π
(20)
where, I
out
is the PFC output current, V
out_ripple_pp
is the output voltage ripple (peak to peak), and fL is the
AC line frequency.
Please note that ICE2PCXX has enhance dynamic block which is active when Vout exceed ±5% of
regulated level. The enchanc dynamic block should be designed to work only during load or line change.
During steady state with constant load, the enhance dynamic block should not be triggered, otherwise
THD will be deteriorated. That means the target V
out_ripple_pp
must be lower than 10% of V
out
. For this
example, Vout=390VDC, then V
out_ripple_pp
must be lower than 39V. if we define V
out_ripple_pp
=12V, then
F
Vf
I
C
pprippleoutL
out
out
µ
π
220
2
__
=
⋅⋅⋅
≥
(21)
(2) holdup time requirement
After the PFC stage, there is commonly a PWM stage to provide isolated DC output for end user. Some
applications, especially computing, have the holdup time requirement. It means that PWM stage should
be able to provide the isolated output even if AC input voltage become zero for a short holdup time. The
common specification for this holdup time is 20ms. If minimum input voltage for PWM stage is defined as
250VDC, then the bulk capacitance will be
F
msW
VV
tP
C
outout
holdupout
out
µ
134
250390
203002
2
222
min_
2
=
−
⋅⋅
=
−
⋅⋅
≥
(22)
the final C
out
capacitance should be higher value calculated from the above two requirements.
2.8 Current Sense Resistor
The current sense resistance is calculated based on the IC soft over current control threshold and peak
current carried by boost choke.
When the Isense signal reaches the soft over control threshold, IC will reduce the internal control voltage and
accordingly the duty cycle is reduced in the following cycles. Finally the boost choke current is limited.
According to IC datasheet, soft over current control threshold is -0.68V maximum. So the current sense
resistor should be
Ω==≤ 11.0
14.6
68.068.0
_
A
V
I
V
R
pkL
sense
(23)
Application Note 13 2008-08-01
According to Figure 2 and Figure 3, the transistor current as well as the diode current flows through R
sense
.
That means, when AC is powered up, a large negative voltage drop at R
sense
will be observed when large
inrush current in the range of about 150 A to 200 A flows through the resistor. It is therefore necessary to
limit the current into Pin 2 (ISENSE) to 1 mA, which is realized with resistor R3. A value of R3 = 220Ω is
sufficient for this resistor.
2.9 Output voltage sensing divider
The output voltage is set with the voltage divider represented by R1 and R2 in Figure 2 and Figure 3. First,
choose the value of the lower resistor R
2
. Then the value of the upper resistor R1 is
21
R
V
VV
R
ref
refout
⋅
−
= (24)
where, Vref is IC internal reference voltage for voltage sensing, 3V typical.
If R
2
=6kΩ,
Ω=Ω⋅
−
= kkR 77410
3
3390
1
It is recommended to take resistor values with a tolerance of 1% for R
1
and R2. Due to the voltage stress of
R1, it is recommended to split this value into few resistors in series.
2.10 Frequency setting (only for ICE2PCS01)
The frequency of the ICE2PCS01 is adjustable in the range of 50 kHz up to 250 kHz. The external resistor
R
FREQ
according to Figure 7 programs a current which controls the oscillator.
Figure 7 Resistor-frequency characteristic
Application Note 14 2008-08-01
2.11 AC Brown-out Shutdown (only for ICE2PCS02)
Brown-out occurs when the input voltage VAC falls below the minimum input voltage of the design (i.e. 85V
for universal input voltage range) and the VCC has not entered into the VCCUVLO level yet. For a system
without input brown out protection (IBOP), the boost converter will increasingly draw a higher current from
the mains at a given output power which may exceed the maximum design values of the input current and
lead to over heat of MOSFET and boost diode. ICE2PCS02 provides a new IBOP feature whereby it senses
directly the input voltage for Input Brown-Out condition via an external resistor/capacitor/diode network as
shown in Figure 8. This network provides a filtered value of VIN which turns the IC on when the voltage at
Pin 4 (VINS) is more than 1.5V. The IC enters into the standby mode and gate is off when VINS goes below
0.7V. The hysteresis prevents the system to oscillate between normal and standby mode.
Figure 8 Block diagram of voltage loop
Because of the high input impedence of comparator of C4 and C5, R5 can be high ohmic resistance to
reduce the loss. From the datasheet, the bias current on VINS Pin is 1µA maximum. In order to have the
design consistence, the current passing through R5 and R6 has to be much higher than this bias current, for
example 6µA. Then R6 is:
Ω== k
uA
V
R 117
6
7.0
6
(25)
R6 is selected 120KΩ. R5 is selcted by
6
_
5
5.1
5.12
R
V
VV
R
onAC
⋅
−⋅
= (26)
where, V
AC_on
is the minimum AC input voltage (RMS) to start PFC, for example 70VAC.
Ω=Ω⋅
−⋅
= Mk
V
VV
R 8.7120
5.1
5.1702
5
Due to the voltage stress of R
5
, it is recommended to split this value into few resistors in series.
C
4
is used to modulate the ripple at the VINS pin. The timing diagram of VINS pin when IC enters brown-out
shutdown is shown in Figure 9.
Application Note 15 2008-08-01
Figure 9 Timing diagram of VINS Pin when IC enters brown-out shutdown
If the bottom level of the ripple voltage touches 0.7V, PFC is in standby mode and gate is off. The ripple
voltage defines PFC brown out off threshold of AC input voltage (RMS), V
AC_off
. C4 can be obtained from the
following equation. Assuming
offACAVEINS
V
RR
R
V
_
65
6
_
⋅
+
=
, where, V
AC_off
is the maximum AC input voltage
(RMS) to switch off PFC, for example 65VAC.
VeV
RR
R
CR
t
offAC
edisch
7.0)7.02(
46
arg
_
65
6
=⋅−⋅
+
⋅
−
(27)
assuming t
discharge
is equal to half cycle time of line frequency, ie.
L
edisch
ft2
1
arg
= , then
nF
V
VV
kM
k
kHzC
V
VV
RR
R
RfC
offAC
L
140
7.0
7.065
1208.7
120
2
ln120502
7.0
7.02
ln2
1
4
1
_
65
6
64
=
−
Ω+Ω
Ω
⋅
Ω⋅⋅=
−
+
⋅
=
−
−
(28)
2.12 IC supply
The IC supply voltage operating range is 11~26V.
There are two stages during IC turned on. First Vcc capacitor is charged from 0V to 7V, the IC internal
regulator block starts to reset voltage at all external pins. The reset process will take about 10us. And then
when Vcc voltage is charged to Vcc_on threshold, IC starts the soft start with gate switching. In the case of
Vcc decoupling capacitance is too low such as 0.1uF, Vcc voltage may be charged up too fast and the time
interval from Vcc=7V to Vcc_on is less than the reset time. Then the IC will not go through a proper soft start
as the voltages at IC pins are not yet properly reset. To avoid such a problem, the delay circuitry is needed.
Application Note 16 2008-08-01
Power on
control
IC Vcc
Cvcc
10k
10k
C
delay
0.47uF0.1uF
Q1
Q2
AUX supply
input
R1
R2
Figure 10 Vcc supply circuitry
Figure 10 is a typical circuitry to supply PFC controller. Q2 is NPN transistor and controlled by external
“Power on” signal. When “Power on” signal is “high”, Q2 is turned on provides base current for Q1. Q1 is
turned on accordingly to supply auxiliary power to IC Vcc. The reset delay time is adjustable by changing the
RC time constant of R1, R2 and C
delay
. The recommended values are shown in Figure 10 as 10kΩ, 10kΩ and
0.47uF respectively.
The same reset process also happens during IC power down when Vcc is discharged from Vcc_off to 7V.
The reset time for power down is around 200us. Because IC is in power down mode with very low current
consumption, typically 300uA only, the required Vcc capacitance for power down reset can be calculated as:
nF
VV
sA
VV
tI
C
resetoffcc
resetdownpower
VCC
2.38
74.10
200650
min__
max__
=
−
⋅
=
−
⋅
≥
µµ
(29)
So the common Vcc decoupling capacitance 0.1uF is enough for reset delay requirement.
2.13 PCB layout guide
In order to avoid crosstalk on the board between power and signal path, and to keep the IC GND pin as
“clean” from noise as possible, the PCB layout for GND must be taken care of properly. Below are some
suggestions for GND connection and Figure 11 below illustrates as a good example.
(1) Star connection rule for main power stage GND: the PCB tracks of MOSFET source, output load
GND, IC auxiliary supply GND and shunt resistor are separated and connected together at bulk
capacitor negative Pin.
(2) Star connection rule for small signal IC GND: the IC external components which need to be
connected to the small signal GND bus highlighted in red color. Such GND bus is connected to IC
GND Pin.
(3) Connection between main power stage GND and small signal IC GND: in Figure 11, a single PCB
track in pink color directly connect IC GND pin to power stage star connection point - bulk capacitor
negative. This is to ensure that the voltage between IC Isense Pin and IC GND Pin does not observe
the switching rectangular noise current. The dark green and blue tracks denote for flowing paths of
high frequency rectangular switching current.
(4) Vcc decoupling capacitor Cvcc: the decoupling capacitor need to be placed close to IC Vcc and
GND Pins as much as possible. The GND track of Cvcc (green color in Figure 11) should be
connected at the point on the single PCB track connecting between IC GND Pin and power GND
point so that the large gate charging current will not pass through the small signal GND bus.
(5) Vsense capacitor Cvsense: to reduce noise in Vsense Pin, small capacitor up to 0.1uF can be added
between Vsense Pin and small signal GND bus.
Application Note 17 2008-08-01
L1
T1
R1
R2
C
OUT
R
SENSE
EMI Filter
R3
GATE
GND
VSENSE
ISENSE
C2
R4
C3
VCOMP
FREQ
ICOMP
VCC
Auxiliary Supply
ICEXPCS01
Rectifier
VIN=85V ...265V AC
R
FREQ
V
OUT
=400VDC
C1
Cvsense
Cvcc
Figure 11 Good PCB layout illustration
3 Voltage loop and current loop compensation
This section provides a model and a tool for evaluating and improving the control loop characteristics of
ICE2PCS02-based PFC pre-regulators in boost topology. The goal is not only to ensure a narrow bandwidth
in order to achieve a high Power Factor, but also to have enough phase margin so as to make sure the
system is stable over a large range of operating conditions. The design example is demonstrated as well.
Traditional diode rectifiers used in front of the electronic equipment draw pulsed current from the utility line,
which deteriorates the line voltage, produce radiated and conducted electromagnetic interference, leads to
poor utilization of the capacity of the power sources. In compliance with IEC 61000-3-2 harmonic regulation,
active power factor correction (PFC) circuit is getting more and more attention in recent years. For low power
up to 200W, discontinuous conduction mode (DCM) PFC is popular due to its lower cost. Furthermore, there
is only one control loop, i.e. voltage loop, in its transferring control blocks. The design is easy and simple for
DCM operation. However, due to its inherent high current ripple, DCM is seldom to be used for high power
applications. In high power applications, continuous conduction mode (CCM) PFC is more attractive.
V, I
OUT
I
I
L
I
IN
DCM operation CCM operation
Figure 12 DCM and CCM PFC principle
Application Note 18 2008-08-01
3.1 How to achieve PFC function without sinusoidal reference sensing
3.1.1 Boost converter modeling
Figure 13 shows the inductor current waveform for boost converter operating in continuous conduction mode.
di
L
i
L
T
SW
t
on
t
off
I
0
Figure 13 inductor current waveform of boost converter operating in CCM mode
assuming Vin is boost converter input DC voltage, Vout is the boost converter output voltage, L is the boost
choke inductance, ton is the on time duration in one switching cycle, toff is the off time duration in one
switching cycle, doff is the off time duty cycle and Tsw is the time duration in one switching cycle.
During “on” interval,
L
V
dt
di
in
L
=
(30)
During “off” interval,
L
VV
dt
di
outin
L
−
=
(31)
And then the boost inductor current variation after one switching cycle is:
SW
offoutin
off
outin
on
in
L
T
L
dVV
t
L
VV
t
L
V
di ⋅
⋅−
=⋅
−
+⋅= (32)
The instant boost inductor current after n switching cycle is:
SW
noffnoutnin
nLnL
T
L
dVV
ii ⋅
⋅
−
+=
−
___
1__
(33)
3.1.2 PFC IC control principle with boost topology
PFC IC control block is inserted in boost converter as shown in Figure 14.
Application Note 19 2008-08-01
Vin
Boost converter
i
L
IC PWM modulation
doff=K*i
L
doff
SW
noffnoutnin
nLnL
T
L
dVV
ii ⋅
⋅
−
+=
−
___
1__
Figure 14 PFC current loop principle
IC senses boost inductor average current, and calculate the off duty cycle to be proportional to inductor
current, and then send such off duty cycle back to boost converter. The negative feedback loop can be seen
from Figure 14. A small disturb increasing on i
L
will result in a little bit increasing on off duty cycle. The
increasing off duty cycle will lead to decreasing of i
L
after processing by boost converter. In the stead state,
Loutoffoutin
iKVdVV ⋅⋅=⋅=
(34)
Where, K is the modulation gain defined by IC. It can be seen that boost inductor current shape follows AC
input voltage and it is how PFC function to be achieved.
In the following sections, detail mathematical analysis of current loop and voltage loop will be described and
the transfer function for each block is given in order to design IC external compensation network
components.
3.2 Current Loop Regulation and Transfer Function
The detail block diagram of current loop for ICE2PCS02 is shown in the Figure 15. The boost converter
stage K
boost
is elaborated in S-plane.
Boost Converter Power Stage
Kboost(s)
PWM
Comparator
Kc(S)
i
L
Current Averaging
Kave(S)
M2
Vicomp
M1
D
off
Vin
Vout
+
-
X 1/sL
Figure 15 Block diagram of current loop
3.2.1 Current Averaging Circuit
IC sense the boost inductor current via shunt resistor Rsense as shown in Figure 2. The sensing signal is
sent to Isense Pin. As the voltage in Isense Pin is negative signal together with switching ripple, IC need to
do signal averaging and convert the polarity to positive for following PWM modulation blocks. The output of
averaging block is Vicomp voltage at Icomp Pin. the block diagram of current averaging block is shown in
Figure 16.
Application Note 20 2008-08-01
Figure 16 current averaging block diagram
The transfer function of averaging circuit block can be derived as below.
21
1
1
1
1
)(
OTA
icomp
sense
L
icomp
AVE
gM
CK
s
M
RK
i
V
sK
⋅+
==
(35)
where, K
1
is a ratio between R501 and R7 which is equal to 4, C
icomp
is the capacitor at Icomp Pin, g
OTA2
is
the trans-conductance of the error amplifier of OTA2 for current averaging, typical 1.0mS as shown in
Datasheet, M1 is the variable controlled by voltage loop.
The function of the averaging circuit is to filter out the switching current ripple. So the corner frequency of the
averaging circuit f
AVE
must be lower than the switching frequency fSW. Then,
AVE
OTA
icomp
fK
Mg
C
π
2
1
12
⋅
≥
(36)
3.2.2 PWM comparator block
The averaged Vicomp signal is sent to PWM comparator block and compared with internal triangular ramp
signal to derive duty cycle. The timing diagram of this block is shown in Figure 17.
Application Note 21 2008-08-01
C1
PWM
Comparator
Vramp=M2*Kfq
Tosc
Vicomp
From protection logic
To PWM logic and
gate driver block
Ramp
Gate drive
Vicomp
Oscillator
Figure 17 The block diagram and timing sequence of PWM comparator block
The operating principle is explained as following. Gate output is in “low” state in the beginning of the each
cycle. Gate output is turned to “high” at the intersection of the triangular ramp signal and Vicomp signal. Gate
output is turned to “low” by oscillator synchronous signal. Based on the operating principle, the transfer
function of K
C
(s) is:
2
1
)(
MKV
d
sK
FQicomp
off
C
==
(37)
Where, K
FQ
is a design constant which is equal to 9.183, M2 is the variable controlled by voltage loop.
3.2.3 Boost converter stage
The transfer function of boost converter stage K
Boost
(s) can be obtain via State-Space Averaging method.
Combining equation (30) and (31) by state –space averaging,
L
dVV
d
L
VV
d
L
V
dt
di
offoutin
off
outin
on
in
L
−
=
−
+=
(38)
Make Laplace transformation for equation (38) with assuming Vin and Vout are constant for current loop
analysis,
sL
sdVVsi
offoutinL
1
))(()(
−= (39)
The equation (39) has been described in current loop block diagram in Figure 15. Although Vin is not
physically sensed by circuit, the input sinusoidal signal is presented in transfer functions only if
boost topology is applied.
3.2.4 Open loop transfer function gain for current loop
The open loop gain of current regulation loop is:
)1(
)()()(
21
1
21
1
OTA
icomp
FQ
outsense
out
CAVEC
gM
CK
ss
LMMK
VRK
sL
V
sKsKsG
⋅+
==
(40)
Application Note 22 2008-08-01
The selected C
icomp
must also meet the requirement that the cross over frequency of the current loop fC is
much lower than the switching frequency f
SW
.
3.2.5 Steady state solution of I
L
Solving the current loop in Figure 15,
sL
sisKsKVV
sL
sdVVsi
LAVECoutinoffoutinL
1
))()()((
1
))(()( −=−=
)(1
)()(
1
)(
sG
sL
V
sL
sKsKV
sL
V
si
C
in
AVECout
in
L
+
=
+
=
(41)
For AC line frequency which is much lower than f
C
, then 1)( >>sG
c
21
1
1
21
1
)()(1
)(
OTA
icomp
outsense
inFQ
C
in
C
in
L
gM
CK
s
VRK
VMMK
sG
sL
V
sG
sL
V
si
⋅+
=≈
+
=
(42)
For AC line frequency which is also much lower than f
AVE
,
1
21
1
<<⋅
OTA
icomp
gM
CK
s
, then the steady state I
L
can
be derived as
outsense
inFQ
L
VRK
VMMK
I
1
21
= (43)
from the above steady state solution of I
L
, it can be seen that the choke current IL is always following
input voltage V
in
. This is how PFC function is achieved.
3.3 Voltage Loop Compensation
The control loop block diagram for ICE2PCS02 based CCM PFC is shown in Figure 18 and Figure 19. There
are four blocks in the loop. IC PWM Modulator G
2
(s) has been discussed in above Section 3. the rest of them
are Error Amplifier G
1
(s), nonlinear block G
NON
(s), boost converter output stage G3(s) and Feedback Sensing
G
4
(s).
Error Amplifier
G1(s)
Vref
+
Vcomp
PWM Modulator
G2(s)
i
L
Vsense
Vout
Boost converter
output Stage
G3(s)
Feedback
G4(s)
-
Vin
5V
400V
0V
Vcomp_DC
Nonlinear block
G
NON
(s)
M1M2
Figure 18 Large signal modeling of voltage loop
Application Note 23 2008-08-01
Output Stage G3(s)
PWM modulation G2(s)
Voltage loop
Error Amplifier
G1(s)
+
Output Stage
Feedback
-
Vsense∆
Vcomp∆
AVEout
inrms
V
V
_
out
I∆
out
sC
1
out
V
∆
Non-
linear
G
NON
(s)
rmsLI_
∆
)(21MM∆
21
_
MM
I
rmsL
+
-
AVEout
rmsL
V
I
_
_
Figure 19 Small signal modeling of voltage loop
3.3.1 Boost converter output stage G
3
(s)
Boost converter output stage is described as influencing of variation on i
L
to bulk output voltage Vout. The
transfer function of power stage, G
3
(s), is separated to two stages as:
rmsL
out
out
out
rmsL
out
I
I
I
V
I
V
sG
__
3
)(
∆
∆
⋅
∆
∆
=
∆
∆
= (44)
where V
out
is the DC output voltage, I
out
the DC output current and I
L_rms
is the boost inductor current.
3.3.1.1 ∆V
out
/ ∆I
out
Under the above assumption, the power stage can be modeled as illustrated in Figure 20: a controlled
current source (with a shunt resistor Re) that drives the output bulk capacitor C
out
and the load resistance
Rout (= Vout / Iout). The zero due to the ESR associated with C
out
is far beyond the crossover frequency thus
it is neglected.
Re Rout
Iout
VoutCout
Figure 20 Power stage modeling
A few algebraic manipulations would show that the shunt resistor Re always equals the DC load resistance
Rout, thus it changes depending on the power delivered by the system. There are two kinds of load in the
application. Two cases will give a different result in case of resistive load or constant power load. For purely
resistive load, the AC load resistance equals Ro. In case of constant power load like additional isolated PWM
DC/DC converter, the AC load resistance is equal to -Ro (if the DC bus decreases, the current demanded of
the PFC increases. hence the negative sign is shown.). As a result, the parallel combination with Re tends to
infinity and the two resistances cancel. The current source drives only the output capacitor. The result is
summarized as below:
Application Note 24 2008-08-01
⋅+
=
∆
∆
out
outout
out
out
out
sC
CR
s
R
I
V
1
)
2
1(2
(45)
In this application note, the calculation is only carried out for constant power load situation
3.3.1.2 ∆I
out
/ ∆I
L_rms
The current source Iout can be characterized with the following considerations as shown in Figure 21. The
low frequency component of the boost diode current is found by averaging the discharge portion of the
inductor current over a given switching cycle. The low frequency current, averaged over a mains half-cycle
yields the DC output current Iout:
i
L
i
diode
I
OUT
I
L_PK
Figure 21 The simplification and characterization for I
out
/ I
L_rms
AVEout
rmsLinrms
AVEout
rmsLinrms
PKLonout
V
IV
dSin
V
IV
dSinIDI
_
_
0
2
_
_
0
_
)(
2
)1(
1
==−=
∫∫
ππ
αα
π
αα
π
(46)
So,
AVEout
inrms
rmsL
out
V
V
I
I
__
=
∆
∆
(47)
where, Don is the switch duty cycle; α is the instantaneous phase angle of the mains voltage, Vinrms is the
input RMS voltage value, I
L_PK
is choke current sinewave peak value and V
out_AVE
is the averaging bulk DC
output voltage.
In case of constant power load, the transfer function of G
3
(s) is:
outAVEout
inrms
rmsL
out
out
out
rmsL
out
sCV
V
I
I
I
V
I
V
sG1)(
___
3
⋅=
∆
∆
⋅
∆
∆
=
∆
∆
=
(48)
3.3.2 Small signal transfer function of ∆V
out
/∆(M1M2) for voltage loop analysis
There is a internal feedback from Vout to G2(s). this inner loop has to be solved to obtain the transfer
function of ∆V
out
/∆(M1M2). Rewrite the equation (43) at input voltage RMS point:
outsense
inrmsFQ
rmsL
VRK
VMMK
I
1
21
_
= (49)
Resistive Load
Constant Power Load
Application Note 25 2008-08-01
making a perturbation on I
L_rms
, (M1M2), V
out
, then
out
AVEout
rmsLrmsL
rmsL
V
V
I
MM
MM
I
I ∆−∆=∆
_
_
21
21
_
_
)( (50)
replacing ∆I
L_rms
by ∆V
out/G3
(s) according to voltage loop block diagram,
out
AVEout
rmsLrmsL
out
V
V
I
MM
MM
I
sG
V
∆−∆=
∆
_
_
21
21
_
3
)(
)(
(51)
then the transfer function of dV
out
/dV
comp
is
11
)(
)(
2
21
3
_1
21
_
_
2
_
21
_
21
23
+
=
+
=
∆
∆
=
s
VMMK
CVRK
MM
V
s
VI
CV
MM
V
MM
V
sG
inrmsFQ
outAVEoutsense
AVEout
inrmsrmsL
outAVEout
AVEout
out
(52)
With
2
21
3
_1
23
2
1
inrmsFQ
outAVEoutsense
VMMK
CVRK
f
π
= ,
23
21
_
21
23
2
1
)(
)(
f
s
MM
V
MM
V
sG
AVEout
out
π
+
=
∆
∆
=
(53)
3.3.3 Nonlinear block G
NON
(s)
The Vcomp voltage is sent to nonlinear gain block. The output of nonlinear is two internal variables, M1 and
M2. The two variables are used to define boost choke current amplitude I
L
as in equation (43). The
characteristic of nonlinear gain block is shown in Table 2 and Figure 22. The small signal gain between
∆(M1*M2) and ∆Vcomp can be derived as well at different operating point.
Vcomp M1 M2 M1*M2
0.00 4.686E-02 4.964E-04 2.326E-05
0.25 4.685E-02 7.072E-04 3.313E-05
0.50 4.665E-02 1.199E-03 5.595E-05
0.75 4.685E-02 3.292E-03 1.542E-04
1.00 4.823E-02 3.224E-02 1.555E-03
1.25 8.153E-02 1.075E-01 8.766E-03
1.50 1.261E-01 1.921E-01 2.423E-02
1.75 1.901E-01 2.796E-01 5.316E-02
2.00 2.747E-01 3.686E-01 1.013E-01
2.25 3.768E-01 4.590E-01 1.729E-01
2.50 4.884E-01 5.523E-01 2.697E-01
2.75 5.992E-01 6.539E-01 3.918E-01
3.00 6.992E-01 7.794E-01 5.449E-01
3.25 7.816E-01 9.669E-01 7.557E-01
3.50 8.443E-01 1.287E+00 1.087E+00
3.75 8.888E-01 1.802E+00 1.601E+00
4.00 9.184E-01 2.442E+00 2.243E+00
4.25 9.339E-01 2.911E+00 2.719E+00
Application Note 26 2008-08-01
4.50 9.350E-01 2.911E+00 2.722E+00
4.75 9.351E-01 2.911E+00 2.722E+00
5.00 9.351E-01 2.911E+00 2.722E+00
Table 2 nonlinear block characteristic data
0.0
0.5
1.0
1.5
2.0
2.5
3.0
3.5
012345
Vcomp
M1
M2
M1* M2
Figure 22 The characteristics of nonlinear block
3.3.4 Error Amplifier compensation G
1
(s)
The circuit of error amplifier compensation circuit is shown in Figure 23. The sensing voltage Vsense is
compared to internal reference voltage 3V typical. The difference between Vsense and internal reference is
sent to transconductance error amplifier and converted to a current source to charge or discharge the RC
components in Vcomp Pin.
Figure 23 Error Amplifier compensation G
1
(s)
The transfer function is:
Application Note 27 2008-08-01
1
32
324
32
24
1
1
1
)1()(
1
)(
OTA
sense
OTA
OTA
comp
sense
comp
g
CC
CCR
ssCC
CsR
V
I
I
V
V
V
sG ⋅
+
++
+
=
∆
∆
⋅
∆
∆
=
∆
∆
=
(54)
where, g
OTA1
is the trans-conductance of OTA1, 42uS typically for ICE2PCS02.
With
24
21CR
f
CZ
π
=
and
32
324
2
1
CC
CCR
f
CP
+
=
π
,
)
2
1()(
)
2
1(
)(
32
1
1
CP
CZ
OTA
f
s
sCC
f
s
g
sG
π
π
++
+
=
(55)
The pole and zero are to regulate the overall voltage loop with the cross-over frequency below 100Hz and
create the phase margin for the loop stability.
3.3.5 Feedback G
4
(s)
The Feedback block is a simple voltage divider to monitor the bulk capacitor output voltage. The circuit is
shown in Figure 24.
21
2
4
)(
RR
R
V
V
sG
out
sense
+
=
∆
∆
=
(56)
Figure 24 bulk voltage sensing divider
3.3.6 Overall Open Loop Transfer Function G
V
(s)
With combining all of the blocks above, the overall open loop gain for voltage loop is equal to:
)()()()()(
4231
sGsGsGsGsG
NONV
=
(57)
Due to PF requirement, inherent PFC dynamic voltage loop compensation is always implemented with low
bandwidth in order not to make the response for 2*f
L
ripple. For example, for 50Hz AC line input, PFC
voltage loop bandwidth is normally set below 20Hz. The compensation circuit R4, C2 and C3 are used to
optimize the loop gain and phase margin.
3.3.7 Enhance dynamic response
R1
R2
Vout
Vsense
Application Note 28 2008-08-01
As mentioned in Section 4.6, the inherent low bandwidth of voltage loop in PFC application will lead to slow
response in case of sudden load step and result in large output overshoot or drop. Enhance dynamic
response feature is integrated in ICE2PCS02 to have a fast response in the case of load step. The voltage
loop with including enhance dynamic response block is shown in Figure 25.
Error Amplifier
G1(s)
Vref
+
Vcomp
PWM Modulator
G2(s)
i
L
Vsense
Vout
Boost converter
output Stage
G3(s)
Feedback
G4(s)
-
Vin
5V
400V
0V
Vcomp_DC
Nonlinear block
G
NON
(s)
M1M2
+
+/-
Enhance dynamic
Figure 25 voltage loop block diagram including enhance dynamic response
When Vsense voltage variation is within -5% to +5% of nominal value, there is no function of enhance
dynamic response block. However, when Vsense variation is out of such +/-5% range, enhance block will
add offset voltage on top of Vcomp voltage to influence the current amplitude.
The timing diagram of enhance dynamic response operation is shown in Figure 26 with sudden load jump
situation. It can be seen that during enhance dynamic operation, the high current of boost choke is delivered
for fast response. Within half sinusoidal period, when Vsense operating around the boundary of -5%
threshold, the first part of boost choke current follows high amplitude profile due to enhance mode offset and
the rest of boost choke current come back to low amplitude profile without enhance mode offset. When
Vsense voltage is pulled back within +/-5% range, enhance dynamic offset disappear and boost choke
current waveform will stay as perfect sinusoidal shape.
enhance
Vin
Iin
Pin
Pin_ave
Ichg
Ichg_ave
Vout Vout_ave nominal
0
0
0
- 5%
Normal Normal
Vcomp
Figure 26 timing diagram for enhance dynamic operation
3.4 Design Example
Assuming a 300W application with universal input AC voltage 85~265VAC,
constant power load
efficiency=90%
Application Note 29 2008-08-01
Vout=400VDC
Cout=220uF/450V
f
SW
=125kHz
Rsense=0.1ohm
Boost choke inductance L=1.2mH (please note that the inductance may change at different choke current)
Vsense divider: R1=390kohm*2=780kohm, R2=6kohm
3.5 Vcomp and M1, M2 value at full load condition
(1) 85VAC:
RMS AC input current under full load:
A
V
P
I
inrms
out
rmsL
92.3
859.0
300
85_
85__
=
⋅
=
⋅
=
η
(58)
From equation (43), With
34.4=
FQ
K and
4
1
=
K
from the ICE2PCS02 Datasheet,
70.1
8534.4
4001.0492.3
85_
185__
85
21
=
⋅
⋅⋅⋅
==
inrmsFQ
outsensermsL
VAC
VK
VRKI
MM
(59)
From table 2 and Figure 22, it can be obtained
Vcomp M1 M2 M1*M2
3.75 8.888E-01 1.802E+00 1.601E+00
4.00 9.184E-01 2.442E+00 2.243E+00
With Linear approximation:
VV
VV
MMMM
MMMM
VV
comp
compcomp
VcompVcomp
Vcomp
VAC
compcomp
79.3)75.34(
601.1243.2
601.170.1
75.3
)(
85_
1_2_
1_
21
2_
21
1_
21
85
21
1_85_
=−⋅
−
−
+=
−⋅
−
−
+=
(60)
894.0)75.379.3(
75.34
889.0918.0
889.0
)(
85
1
1_85_
1_2_
1_12_1
1_1
85
1
=−⋅
−
−
+=
−⋅
−
−
+=
VAC
compcomp
compcomp
VAC
M
VV
VV
MM
MM
(61)
91.1)75.379.3(
75.34
802.1442.2
802.1
)(
85
2
1_85_
1_2_
1_22_2
1_2
85
2
=−⋅
−
−
+=
−⋅
−
−
+=
VAC
compcomp
compcomp
VAC
M
VV
VV
MM
MM
(62)
The small signal gain of nonlinear block is
568.2
75.34
601.1243.2
)(
1_2_
1_
21
2_
21
85
=
−
−
=
−
−
=
compcomp
VcompVcomp
VAC
NON
VV
MMMM
sG
(63)
The inherent pole of f
23
is
Application Note 30 2008-08-01
Hz
VMMK
CVRK
f
inrms
VAC
FQ
outAVEoutsense
VAC
54.1
)(
2
1
2
85_
85
21
3
_1
85
23
=
⋅⋅
=
π
(64)
(2) 265VAC
RMS AC input current under full load:
A
V
P
I
inrms
out
rmsL
257.1
2659.0
300
265_
265__
=
⋅
=
⋅
=
η
(65)
From equation (43),
175.0
26534.4
4001.04257.1
265_
1265__
265
21
=
⋅
⋅⋅⋅
==
inrmsFQ
outsensermsL
VAC
VK
VRKI
MM
(66)
From table 2 and Figure 22, it can be obtained
Vcomp M1 M2 M1*M2
2.25 3.768E-01 4.590E-01 1.729E-01
2.50 4.884E-01 5.523E-01 2.697E-01
With Linear approximation:
VV
VV
MMMM
MMMM
VV
comp
compcomp
VcompVcomp
Vcomp
VAC
compcomp
255.2)25.25.2(
1729.02697.0
1729.0175.0
25.2
)(
265_
1_2_
1_
21
2_
21
1_
21
265
21
1_265_
=−⋅
−
−
+=
−⋅
−
−
+=
(67)
386.0)25.2266.2(
25.25.2
3768.04884.0
3768.0
)(
265
1
1_265_
1_2_
1_12_1
1_1
265
1
=−⋅
−
−
+=
−⋅
−
−
+=
VAC
compcomp
compcomp
VAC
M
VV
VV
MM
MM
(68)
461.0)25.2255.2(
25.25.2
459.05523.0
459.0
)(
265
2
1_265_
1_2_
1_22_2
1_2
265
2
=−⋅
−
−
+=
−⋅
−
−
+=
VAC
compcomp
compcomp
VAC
M
VV
VV
MM
MM
(69)
The small signal gain of nonlinear block is
3872.0
25.25.2
1729.02697.0
)(
1_2_
1_
21
2_
21
265
=
−
−
=
−
−
=
compcomp
VcompVcomp
VAC
NON
VV
MMMM
sG
(70)
The inherent pole of f
23
is
Hz
VMMK
CVRK
f
inrms
VAC
FQ
outAVEoutsense
VAC
54.1
)(
2
1
2
265_
265
21
3
_1
265
23
=
⋅⋅
=
π
(71)
Application Note 31 2008-08-01
3.5.1 Current Averaging Circuit
With g
OTA2
=1.0mS from Datasheet, M1@85VAC, and assuming f
AVE
=13kHz which is 10 times less than
switching frequency 125kHz, then
nF
E
E
fK
Mg
C
AVE
VAC
OTA
icomp
3
32424
895.030.1
2
1
85
12
=
⋅⋅
⋅−
=
⋅
≥
ππ
(72)
Select C
icomp
=3.3nF
3.5.2 Current Loop Regulation
Insert M1 and M2 value in equation (40). The amplitude and phase angle of G
C
(s) is shown in Figure 27 to
verify the stability of current loop and the requirement of f
C
less than switching frequency.
10
0
10
1
10
2
10
3
10
4
10
5
10
6
10
7
-150
-100
-50
0
50
100
f(HZ)
Gain(db)
85VAC full load
265VAC full load
Application Note 32 2008-08-01
10
0
10
1
10
2
10
3
10
4
10
5
10
6
10
7
-180
-170
-160
-150
-140
-130
-120
-110
-100
-90
f(HZ)
Phase Angle
85VAC full load
265VAC full load
Figure 27 The bode plot and phase angle for current loop
The cross over frequency and phase margin are 3kHz and 75º for 85VAC, and 10kHz and 25º for 265VAC.
Application Note 33 2008-08-01
3.5.3 Voltage Loop Regulation
From the above sections, it can be obtained:
)
2
1()(
)
2
1(
)(
32
1
1
CP
CZ
OTA
sense
comp
f
s
sCC
f
s
g
V
V
sG
π
π
++
+
=
∆
∆
=
(73)
comp
NON
V
MM
sG
∆
∆
=)()(
21
(74)
23
21
_
21
23
2
1
)(
)(
f
s
MM
V
MM
V
sG
AVEout
out
π
+
=
∆
∆
=
(75)
0077.0.
2.806
2.6
)(
21
2
4
==
+
=
∆
∆
=
RR
R
V
V
sG
out
sense
(76)
The open loop gain for voltage loop is to times all above factors together as:
)()()()()(
4231
sGsGsGsGsG
NONV
=
G
1
(s) is used to provide enough phase margin and also limit the bandwidth below 20HZ. R4, C2 and C3 can
be chosen as required. f
CZ
normally select to be compensate the pole in G23(s). fCP normally select to be
40~70Hz in order to fast put down the gain amplitude and reject the high frequency interference. In this
example f
23
is around 1.54Hz at 85VAC/ 265VAC and full load. So the initial target is: fCZ is chosen to be
close to 1.5Hz, and f
CP
is chosen to be 50Hz.
C2 and C3 is calculated to obtain Gv(s) cross over frequency around 10Hz. The gain amplitude of
G
NON*G23*G4
in 85VAC and full load is shown in Figure 28. It can be seen that at f=10Hz, the gain is about -
4.52dB. So G1 should provide the gain +4.52dB at f=10Hz. Considering that C2>>C3 due to fcz<fcp and
10Hz>>1Hz=f
CZ
, then
F
Hz
Hz
Hz
C
dB
HzC
Hz
Hz
g
HzG
OTA
µ
π
π
69.3
10210
1
10
1039
52.4
102
1
10
)10(
20
52.4
6
2
2
1
1
=
⋅⋅
⋅⋅
=
+=
⋅⋅
=
−
(77)
3.97uF is not common for ceramic type capacitor. So select C
2
=1uF, then fCZ is recalculated as:
Application Note 34 2008-08-01
Hz
HzF
Hz
f
dB
HzC
f
Hz
g
HzG
CZ
CZ
OTA
30.4
1
1039
102101
10
52.4
102
)
10
(1
)10(
2
6
20
52.4
2
2
1
1
=
−
⋅
⋅⋅⋅
=
+=
⋅⋅
+
=
−
πµ
π
(78)
according to
Hz
CR
f
CZ
30.4
2
1
24
==
π
then
Ω=
⋅⋅
= k
CHz
R 37
30.42
1
2
4
π
(79)
select R4=33kΩ, and
Hz
CR
CC
CCR
f
CP
50
2
1
2
1
34
32
324
=≈
+
=
π
π
nF
RHz
C 5.96
502
1
4
3
=
⋅⋅
=
π
(80)
select C3=100nF
The gain amplitude and phase angle of overall voltage loop G
V
(s) at 85VAC and 265VAC in full load
condition is shown in Figure 28 and Figure 29. At 85VAC, the cross over frequency f
V
is around 9.5Hz and
the phase margin is about 63º. At 265VAC, the cross over frequency f
V
is around 14Hz and the phase
margin is about 62º.
Application Note 35 2008-08-01
10
-1
10
0
10
1
10
2
10
3
10
4
-120
-100
-80
-60
-40
-20
0
20
40
60
f(HZ)
Gain(db)
Gv=G1*Gnon*G23*G4
Gnon*G23*G4
10
-1
10
0
10
1
10
2
10
3
10
4
-180
-170
-160
-150
-140
-130
-120
-110
-100
-90
f(HZ)
Phase Angle
Gv
Figure 28 the bode plot and phase angle for voltage loop at 85VAC and full load
Application Note 36 2008-08-01
10
-1
10
0
10
1
10
2
10
3
10
4
-120
-100
-80
-60
-40
-20
0
20
40
60
f(HZ)
Gain(db)
10
-1
10
0
10
1
10
2
10
3
10
4
-180
-170
-160
-150
-140
-130
-120
-110
-100
-90
f(HZ)
Phase A ngle
Figure 29 The bode plot and phase angle for voltage loop at 265VAC and full load
Application Note 37 2008-08-01
References
[1] Infineon Technologies: ICE2PCS01 - Standalone Power Factor Correction Controller in Continuous
Conduction Mode; Preliminary datasheet; Infineon Technologies; Munich; Germany; Sept. 2007.
[2] Infineon Technologies: ICE2PCS02 - Standalone Power Factor Correction (PFC) Controller in
Continuous Conduction Mode (CCM) at Fixed Frequency, Preliminary datasheet; Infineon Technologies;
Munich; Germany; Sept. 2007.
[3] Luo Junyang, Liu Jianwei, Jeoh Meng Kiat, 300W CCM PFC Evaluation Board with ICE2PCS02,
CoolMOS™ and SiC Diode thinQ!™, Application note, Infineon Technologies, Munich, Germany, Feb. 2007.
[4] Luo Junyang, Liu Jianwei, Jeoh Meng Kiat, ICE2PCSxx, New generation of BiCMOS technology,
Application note, Infineon Technologies, Munich, Germany, Feb, 2007
[5] Luo Junyang, Liu Jianwei, Jeoh Meng Kiat, ICE1PCS01 Based Boost Type CCM PFC Design Guide
- Control Loop Modeling, Application note, Infineon Technologies, Munich, Germany, May, 2007.
[6] Luo Junyang, Liu Jianwei, Jeoh Meng Kiat, ICE1PCS01/02 Boost Type CCM PFC Design with
ICE1PCS01. Application note, Infineon Technologies, Munich, Germany, Apr. 2007.
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