INFINEON XC878CLM User Manual

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8-Bit

XC878CLM

8-Bit Single-Chip Microcontroller

Data Sheet

V1.2 2009-11

Microcontrollers

Edition 2009-11

Published by Infineon Technologies AG 81726 Munich, Germany

Legal Disclaimer

The information given in this document shall in no event be regarded as a guarantee of conditions or characteristics. With respect to any examples or hints given herein, any typical values stated herein and/or any information regarding the application of the device, Infineon Technologies hereby disclaims any and all warranties and liabilities of any kind, including without limitation, warranties of non-infringement of intellectual property rights of any third party.

Information

For further information on technology, delivery terms and conditions and prices, please contact the nearest Infineon Technologies Office (www.infineon.com).

Warnings

Due to technical requirements, components may contain dangerous substances. For information on the types in question, please contact the nearest Infineon Technologies Office.

Infineon Technologies components may be used in life-support devices or systems only with the express written approval of Infineon Technologies, if a failure of such components can reasonably be expected to cause the failure of that life-support device or system or to affect the safety or effectiveness of that device or system. Life support devices or systems are intended to be implanted in the human body or to support and/or maintain and sustain and/or protect human life. If they fail, it is reasonable to assume that the health of the user or other persons may be endangered.

8-Bit

XC878CLM

8-Bit Single-Chip Microcontroller

Data Sheet

V1.2 2009-11

Microcontrollers

XC878CLM

XC878 Revision History: 2009-11 V1.2

Previous Version: V1.1

Page Subjects (major changes since last revision)

Changes from V1.1 2009-08 to V1.2 2009-10

3 Table 1 and Table 2 has been updated to include the variants for the

Automotive profile.

57 Table 21 has been added to show the Flash data retention and

endurance for Automotive profile.

106 Table 37 has been updated to show the Chip Identification number for the

new Automotive variants.

We Listen to Your Comments

Any information within this document that you feel is wrong, unclear or missing at all? Your feedback will help us to continuously improve the quality of this document. Please send your proposal (including a reference to this document) to:

mcdocu.comments@infineon.com

Data Sheet V1.2, 2009-11

XC878CLM

Data Sheet V1.2, 2009-11

XC878CLM

Table of Contents

1 Summary of Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1

2 General Device Information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5

2.1 Block Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5

2.2 Logic Symbol . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6

2.3 Pin Configuration . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7

2.4 Pin Definitions and Functions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8

3 Functional Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19

3.1 Processor Architecture . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19

3.2 Memory Organization . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20

3.2.1 Memory Protection Strategy . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22

3.2.1.1 Flash Memory Protection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22

3.2.2 Special Function Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24

3.2.2.1 Address Extension by Mapping . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24

3.2.2.2 Address Extension by Paging . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26

3.2.3 Bit Protection Scheme . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 30

3.2.3.1 Password Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 31

3.2.4 XC878 Register Overview . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 32

3.2.4.1 CPU Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 32

3.2.4.2 MDU Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 33

3.2.4.3 CORDIC Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 34

3.2.4.4 System Control Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 35

3.2.4.5 WDT Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 38

3.2.4.6 Port Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 38

3.2.4.7 ADC Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 41

3.2.4.8 Timer 2 Compare/Capture Unit Registers . . . . . . . . . . . . . . . . . . . . . 45

3.2.4.9 Timer 21 Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 47

3.2.4.10 CCU6 Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 48

3.2.4.11 UART1 Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 52

3.2.4.12 SSC Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 52

3.2.4.13 MultiCAN Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 53

3.2.4.14 OCDS Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 53

3.2.4.15 Flash Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 55

3.3 Flash Memory . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 56

3.3.1 Flash Bank Pagination . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 58

3.4 Interrupt System . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 59

3.4.1 Interrupt Source . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 59

3.4.2 Interrupt Source and Vector . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 65

3.4.3 Interrupt Priority . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 67

3.5 Parallel Ports . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 68

3.6 Power Supply System with Embedded Voltage Regulator . . . . . . . . . . . . 70

Data Sheet I-1 V1.2, 2009-11

XC878CLM

Table of Contents

3.7 Reset Control . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 71

3.7.1 Module Reset Behavior . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 71

3.7.2 Booting Scheme . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 72

3.8 Clock Generation Unit . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 73

3.8.1 Recommended External Oscillator Circuits . . . . . . . . . . . . . . . . . . . . . . 75

3.8.2 Clock Management . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 77

3.9 Power Saving Modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 80

3.10 Watchdog Timer . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 81

3.11 Multiplication/Division Unit . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 84

3.12 CORDIC Coprocessor . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 85

3.13 UART and UART1 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 86

3.13.1 Baud-Rate Generator . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 86

3.13.2 Baud Rate Generation using Timer 1 . . . . . . . . . . . . . . . . . . . . . . . . . . 89

3.14 Normal Divider Mode (8-bit Auto-reload Timer) . . . . . . . . . . . . . . . . . . . . . 89

3.15 LIN Protocol . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 90

3.15.1 LIN Header Transmission . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 90

3.16 High-Speed Synchronous Serial Interface . . . . . . . . . . . . . . . . . . . . . . . . . 92

3.17 Timer 0 and Timer 1 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 94

3.18 Timer 2 and Timer 21 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 95

3.19 Timer 2 Capture/Compare Unit . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 96

3.20 Capture/Compare Unit 6 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 97

3.21 Controller Area Network (MultiCAN) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 99

3.22 Analog-to-Digital Converter . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 101

3.22.1 ADC Clocking Scheme . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 101

3.22.2 ADC Conversion Sequence . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 102

3.23 On-Chip Debug Support . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 104

3.23.1 JTAG ID Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 105

3.24 Chip Identification Number . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 106

4 Electrical Parameters . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 108

4.1 General Parameters . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 108

4.1.1 Parameter Interpretation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 108

4.1.2 Absolute Maximum Rating . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 109

4.1.3 Operating Conditions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 110

4.2 DC Parameters . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 111

4.2.1 Input/Output Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 111

4.2.2 Supply Threshold Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . 114

4.2.3 ADC Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 115

4.2.3.1 ADC Conversion Timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 118

4.2.4 Power Supply Current . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 119

4.3 AC Parameters . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 123

4.3.1 Testing Waveforms . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 123

4.3.2 Output Rise/Fall Times . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 124

Data Sheet I-2 V1.2, 2009-11

XC878CLM

Table of Contents

4.3.3 Power-on Reset and PLL Timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 125

4.3.4 On-Chip Oscillator Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . 126

4.3.5 External Data Memory Characteristics . . . . . . . . . . . . . . . . . . . . . . . . 127

4.3.6 External Clock Drive XTAL1 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 129

4.3.7 JTAG Timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 130

4.3.8 SSC Master Mode Timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 132

5 Package and Quality Declaration . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 133

5.1 Package Parameters . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 133

5.2 Package Outline . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 134

5.3 Quality Declaration . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 135

Data Sheet I-3 V1.2, 2009-11

XC878CLM

Table of Contents

Data Sheet I-4 V1.2, 2009-11

XC878CLM8-Bit Single-Chip Microcontroller

1 Summary of Features

The XC878 has the following features:

• High-performance XC800 Core – compatible with standard 8051 processor – two clocks per machine cycle architecture (for memory access without wait state) – two data pointers

• On-chip memory – 8 Kbytes of Boot ROM – 256 bytes of RAM – 3 Kbytes of XRAM – 64/52 Kbytes of Flash;

(includes memory protection strategy)

• I/O port supply at 3.3 V or 5.0 V and core logic supply at 2.5 V (generated by embedded voltage regulator)

(more features on next page)

52K/64K x 8

Boot ROM

8K x 8

XRAM 3K x 8

RAM

256 x 8

Flash

Timer 0

16-bit

On-Chip Debug Support

XC800 Core

Timer 1

16-bit

Timer 21

16-bit

Watchdog

Timer

UART

Capture/Compare Unit

Compare Unit

Timer 2 Capture/

Compare Unit

UART1

SSC

16-bit

ADC

10-bit

8-channel

8-bit Analog Input

Port 0

Port 1

Port 3

Port 4

Port 5MDU CORDIC Multi CAN

8-bi t D i gital I/O

8-bi t Digi tal I/O

Figure 1 XC878 Functional Units

Data Sheet 1 V1.2, 2009-11

XC878CLM

Summary of Features

Features: (continued)

• Power-on reset generation

• Brownout detection for core logic supply

• On-chip OSC and PLL for clock generation – Loss-of-Clock detection

• Power saving modes – slow-down mode – idle mode – power-down mode with wake-up capability via RXD or EXINT0 – clock gating control to each peripheral

• Programmable 16-bit Watchdog Timer (WDT)

• Five ports – Up to 40 pins as digital I/O – 8 dedicated analog inputs used as A/D converter input

• 8-channel, 10-bit ADC

• Four 16-bit timers – Timer 0 and Timer 1 (T0 and T1) – Timer 2 and Timer 21 (T2 and T21)

• Multiplication/Division Unit for arithmetic operations (MDU)

• CORDIC Coprocessor for computation of trigonometric, hyperbolic and linear functions

• MultiCAN with 2 nodes, 32 message objects

• Two Capture/compare units – Capture/compare unit 6 for PWM signal generation (CCU6) – Timer 2 Capture/compare unit for vaious digital signal generation (T2CCU)

• Two full-duplex serial interfaces (UART and UART1)

• Synchronous serial channel (SSC)

• On-chip debug support – 1 Kbyte of monitor ROM (part of the 8-Kbyte Boot ROM) – 64 bytes of monitor RAM

• PG-LQFP-64 pin package

• Temperature range T – SAF (-40 to 85 °C) – SAX (-40 to 105 °C)

Data Sheet 2 V1.2, 2009-11

XC878CLM

Summary of Features

XC878 Variant Devices

The XC878 product family features devices with different configurations, program memory sizes, power supply voltage, temperature and quality profiles (Automotive or Industrial), to offer cost-effective solutions for different application requirements.

The list of XC878 device configurations are summarized in Table 1. The type of package available is the LQFP-64.

Table 1 Device Configuration

Device Name CAN

Module

LIN BSL Support

MDU Module

XC878 NoNoNo

XC878M No No Yes

XC878CM Yes No Yes

XC878LM No Yes Yes

XC878CLM Yes Yes Yes

From these 5 different combinations of configuration, each are further made available in many sales types, which are grouped according to device type, program memory sizes, power supply voltage, temperature and quality profiles (Automotive or Industrial), as shown in Table 2.

Table 2 Device Profile

Sales Type Device

Type

Program Memory (Kbytes)

Power Supply (V)

Temperature (°C)

Quality Profile

SAF-XC878-13FFI 5V Flash 52 5.0 -40 to 85 Industrial

SAF-XC878M-13FFI 5V Flash 52 5.0 -40 to 85 Industrial

SAF-XC878CM-13FFI 5V Flash 52 5.0 -40 to 85 Industrial

SAF-XC878-16FFI 5V Flash 64 5.0 -40 to 85 Industrial

SAF-XC878M-16FFI 5V Flash 64 5.0 -40 to 85 Industrial

SAF-XC878CM-16FFI 5V Flash 64 5.0 -40 to 85 Industrial

SAF-XC878-13FFI 3V3 Flash 52 3.3 -40 to 85 Industrial

SAF-XC878M-13FFI 3V3 Flash 52 3.3 -40 to 85 Industrial

SAF-XC878CM-13FFI 3V3 Flash 52 3.3 -40 to 85 Industrial

SAF-XC878-16FFI 3V3 Flash 64 3.3 -40 to 85 Industrial

SAF-XC878M-16FFI 3V3 Flash 64 3.3 -40 to 85 Industrial

Data Sheet 3 V1.2, 2009-11

Table 2 Device Profile (cont’d)

XC878CLM

Summary of Features

Sales Type Device

Type

Program Memory (Kbytes)

Power Supply (V)

Temperature (°C)

Quality Profile

SAF-XC878CM-16FFI 3V3 Flash 64 3.3 -40 to 85 Industrial

SAX-XC878-13FFA 5V Flash 52 5.0 -40 to 105 Automotive

SAX-XC878CM-13FFA 5V Flash 52 5.0 -40 to 105 Automotive

SAX-XC878LM-13FFA 5V Flash 52 5.0 -40 to 105 Automotive

SAX-XC878CLM-13FFA 5V Flash 52 5.0 -40 to 105 Automotive

SAX-XC878-16FFA 5V Flash 64 5.0 -40 to 105 Automotive

SAX-XC878CM-16FFA 5V Flash 64 5.0 -40 to 105 Automotive

SAX-XC878LM-16FFA 5V Flash 64 5.0 -40 to 105 Automotive

SAX-XC878CLM-16FFA 5V Flash 64 5.0 -40 to 105 Automotive

As this document refers to all the derivatives, some description may not apply to a specific product. For simplicity, all versions are referred to by the term XC878 throughout this document.

Ordering Information

The ordering code for Infineon Technologies microcontrollers provides an exact reference to the required product. This ordering code identifies:

• The derivative itself, i.e. its function set, the temperature range, and the supply voltage

• The package and the type of delivery

For the available ordering codes for the XC878, please refer to your responsible sales representative or your local distributor.

Data Sheet 4 V1.2, 2009-11

XC878CLM

General Device Information

2 General Device Information

Chapter 2 contains the block diagram, pin configurations, definitions and functions of the

XC878.

2.1 Block Diagram

The block diagram of the XC878 is shown in Figure 2.

TMS MBC

RESET

DDP

SSP

DDC

SSC

XTAL1 XTAL2

XC878

8-Kbyte

Boot ROM

256-byte RAM

64-byte monitor

RAM

3-Kbyte XRAM

52/64-Kbyte

Flash

Clock Generator

4 MHz

On-chip OSC

PLL

Internal Bus

XC800 Core

T0 & T1 UART

UART1CORDIC

SSCMDU

WDT

OCDS

CCU 6

MultiCAN

Timer 2 Capture/

Compare Unit

Timer 21

P0.0 - P0.7

P1.0 - P1.7

P3.0 - P3.7

P4.0 - P4.7

Port 4Port 5

P5.0 - P5.7

AN0 – AN7

ADC Port 0Port 1Port 3

V V

AREF

AGND

1) Includes 1-Kbyte monitor ROM

Figure 2 XC878 Block Diagram

Data Sheet 5 V1.2, 2009-11

2.2 Logic Symbol

The logic symbol of the XC878 is shown in Figure 3.

XC878CLM

General Device Information

AREF

AGND

RESET

MBC

TMS

XTAL1

XTAL2

DDP

XC878

SSP

Port 0 8-Bit

Port 1 8-Bit

Port 3 8-Bit

Port 4 8-Bit

Port 5 8-Bit

AN0 – AN7

Figure 3 XC878 Logic Symbol

DDC

SSC

Data Sheet 6 V1.2, 2009-11

2.3 Pin Configuration

The pin configuration of the XC878 in Figure 4.

P3.0

P3. 2

P3. 3

P3. 4

P3. 5

P4.5

P4.6

P4.7

P3.1

P4.4

48 47 46 45 44 43 42 41 40 39 38 37 36 35 34 33

P3.6

P3.7

P4.3

XC878CLM

General Device Information

P1.3

P1.4

P1.5

P1.2

P1.0

P1.1

AN7

AREF

AGND

AN6

AN5

RESET

SSP

DDP

N.C.

XC878

MBC

P4. 0

P4. 1

P4. 2

P0. 7

P0. 3

P0. 4

123 45 678910111213141516

P5 . 0

P0 . 5

XTA L 2

P0 . 6

XTA L 1

SSCVDDC

DDP

P5 . 1

P1 . 6

P1 . 7

P5 . 2

P5 . 4

P5 . 3

TMS

P5 . 5

Figure 4 XC878 Pin Configuration, PG-LQFP-64 Package (top view)

AN4

AN3

SSP

DDP

AN2

AN1

AN0

P5.7

P5.6

P0.2

P0.0

Data Sheet 7 V1.2, 2009-11

XC878CLM

General Device Information

2.4 Pin Definitions and Functions

The functions and default states of the XC878 external pins are provided in Table 3.

Table 3 Pin Definitions and Functions

Symbol Pin Number

(LQFP-64)

Type Reset

State

Function

P0 I/O Port 0

Port 0 is an 8-bit bidirectional general purpose I/O port. It can be used as alternate functions for the JTAG, CCU6, UART, UART1, T2CCU, Timer Interface.

P0.0 17 Hi-Z TCK_0

T12HR_1

CC61_1

CLKOUT_0 RXDO_1

P0.1 21 Hi-Z TDI_0

T13HR_1

RXD_1 RXDC1_0 COUT61_1

EXF2_1

21, MultiCAN, SSC and External

JTAG Clock Input CCU6 Timer 12 Hardware Run Input Input/Output of Capture/Compare channel 1 Clock Output UART Transmit Data Output

JTAG Serial Data Input CCU6 Timer 13 Hardware Run Input UART Receive Data Input MultiCAN Node 1 Receiver Input Output of Capture/Compare channel 1 Timer 2 External Flag Output

P0.2 18 PU CTRAP_2

TDO_0 TXD_1

CCU6 Trap Input JTAG Serial Data Output UART Transmit Data Output/Clock Output

TXDC1_0

MultiCAN Node 1 Transmitter Output

P0.3 63 Hi-Z SCK_1

COUT63_1

SSC Clock Input/Output Output of Capture/Compare

channel 3 RXDO1_0 A17

Data Sheet 8 V1.2, 2009-11

UART1 Transmit Data Output

Address Line 17 Output

Table 3 Pin Definitions and Functions (cont’d)

XC878CLM

General Device Information

Symbol Pin Number

(LQFP-64)

Type Reset

State

Function

P0.4 64 Hi-Z MTSR_1

CC62_1

TXD1_0

A18

P0.5 1 Hi-Z MRST_1

EXINT0_0 T2EX1_1 RXD1_0 COUT62_1

A19

P0.6 2 PU T2CC4_1

SSC Master Transmit Output/

Slave Receive Input

Input/Output of

Capture/Compare channel 2

UART1 Transmit Data

Output/Clock Output

Address Line 18 Output

SSC Master Receive Input/Slave

Transmit Output

External Interrupt Input 0

Timer 21 External Trigger Input

UART1 Receive Data Input

Output of Capture/Compare

channel 2

Address Line 19 Output

Compare Output Channel 4

External Data Write Control

Output

P0.7 62 PU CLKOUT_1

T2CC5_1 RD

Clock Output

Compare Output Channel 5

External Data Read Control

Output

Data Sheet 9 V1.2, 2009-11

Table 3 Pin Definitions and Functions (cont’d)

XC878CLM

General Device Information

Symbol Pin Number

(LQFP-64)

Type Reset

State

Function

P1 I/O Port 1

Port 1 is an 8-bit bidirectional general purpose I/O port. It can be used as alternate functions for the JTAG, CCU6, UART, Timer 0, Timer 1, T2CCU, Timer 21, MultiCAN, SSC and External Interface.

P1.0 34 PU RXD_0

T2EX_0 RXDC0_0 A8

P1.1 35 PU EXINT3_0

T0_1 TXD_0

TXDC0_0

UART Receive Data Input

Timer 2 External Trigger Input

MultiCAN Node 0 Receiver Input

Address Line 8 Output

External Interrupt Input 3

Timer 0 Input

UART Transmit Data

Output/Clock Output

MultiCAN Node 0 Transmitter

Output

Address Line 9 Output

P1.2 36 PU SCK_0

A10

P1.3 37 PU MTSR_0

SCK_2 TXDC1_3

A11

P1.4 38 PU MRST_0

EXINT0_1 RXDC1_3 MTSR_2

A12

SSC Clock Input/Output

Address Line 10 Output

SSC Master Transmit

Output/Slave Receive Input

SSC Clock Input/Output

MultiCAN Node 1 Transmitter

Output

Address Line 11 Output

SSC Master Receive Input/

Slave Transmit Output

External Interrupt Input 0

MultiCAN Node 1 Receiver Input

SSC Master Transmit

Output/Slave Receive Input

Address Line 12 Output

Data Sheet 10 V1.2, 2009-11

Table 3 Pin Definitions and Functions (cont’d)

XC878CLM

General Device Information

Symbol Pin Number

(LQFP-64)

Type Reset

State

Function

P1.5 39 PU CCPOS0_1

EXINT5_0 T1_1 MRST_2

EXF2_0 RXDO_0

P1.6 10 PU CCPOS1_1

T12HR_0

EXINT6_0 RXDC0_2 T21_1

P1.7 11 PU CCPOS2_1

T13HR_0

T2_1 TXDC0_2

CCU6 Hall Input 0

External Interrupt Input 5

Timer 1 Input

SSC Master Receive Input/

Slave Transmit Output

Timer 2 External Flag Output

UART Transmit Data Output

CCU6 Hall Input 1

CCU6 Timer 12 Hardware Run

Input

External Interrupt Input 6

MultiCAN Node 0 Receiver Input

Timer 21 Input

CCU6 Hall Input 2

CCU6 Timer 13 Hardware Run

Input

Timer 2 Input

MultiCAN Node 0 Transmitter

Output

P1.5 and P1.6 can be used as a software chip select output for the SSC.

Data Sheet 11 V1.2, 2009-11

Table 3 Pin Definitions and Functions (cont’d)

XC878CLM

General Device Information

Symbol Pin Number

(LQFP-64)

Type Reset

State

Function

P3 I/O Port 3

Port 3 is an 8-bit bidirectional general purpose I/O port. It can be used as alternate functions for CCU6, UART1, T2CCU, Timer 21, MultiCAN and External Interface.

P3.0 43 Hi-Z CCPOS1_2

CC60_0

RXDO1_1 T2CC0_1/ EXINT3_2

P3.1 44 Hi-Z CCPOS0_2

CC61_2

COUT60_0

TXD1_1

CCU6 Hall Input 1

Input/Output of

Capture/Compare channel 0

UART1 Transmit Data Output

External Interrupt Input 3/T2CCU

Capture/Compare Channel 0

CCU6 Hall Input 0

Input/Output of

Capture/Compare channel 1

Output of Capture/Compare

channel 0

UART1 Transmit Data

Output/Clock Output

P3.2 49 Hi-Z CCPOS2_2

RXDC1_1 RXD1_1 CC61_0

T2CC1_1/ EXINT4_2

P3.3 50 Hi-Z COUT61_0

TXDC1_1

T2CC2_1/ EXINT5_2 A13

CCU6 Hall Input 2

MultiCAN Node 1 Receiver Input

UART1 Receive Data Input

Input/Output of

Capture/Compare channel 1

External Interrupt Input 4/T2CCU

Capture/Compare Channel 1

Output of Capture/Compare

channel 1

MultiCAN Node 1 Transmitter

Output

External Interrupt Input 5/T2CCU

Capture/Compare Channel 2

Address Line 13 Output

Data Sheet 12 V1.2, 2009-11

Table 3 Pin Definitions and Functions (cont’d)

XC878CLM

General Device Information

Symbol Pin Number

(LQFP-64)

P3.4 51 Hi-Z CC62_0

Type Reset

State

Function

Input/Output of

Capture/Compare channel 2 RXDC0_1 T2EX1_0 T2CC3_1/ EXINT6_3 A14

P3.5 52 Hi-Z COUT62_0

MultiCAN Node 0 Receiver Input

Timer 21 External Trigger Input

External Interrupt Input 6/T2CCU

Capture/Compare Channel 3

Address Line 14 Output

Output of Capture/Compare

channel 2 EXF21_0 TXDC0_1

Timer 21 External Flag Output

MultiCAN Node 0 Transmitter

Output A15

Address Line 15 Output

P3.6 41 PU CTRAP_0 CCU6 Trap Input

P3.7 42 Hi-Z EXINT4_0

COUT63_0

External Interrupt Input 4

Output of Capture/Compare

channel 3 A16

Address Line 16 Output

Data Sheet 13 V1.2, 2009-11

Table 3 Pin Definitions and Functions (cont’d)

XC878CLM

General Device Information

Symbol Pin Number

(LQFP-64)

Type Reset

State

Function

P4 I/O Port 4

Port 4 is an 8-bit bidirectional general purpose I/O port. It can be used as alternate functions for CCU6, Timer 0, Timer 1, T2CCU, Timer 21, MultiCAN and External Interface.

P4.0 59 Hi-Z RXDC0_3

CC60_1

T2CC0_0/ EXINT3_1 D0

P4.1 60 Hi-Z TXDC0_3

COUT60_1

T2CC1_0/ EXINT4_1 D1

MultiCAN Node 0 Receiver Input

Output of Capture/Compare

channel 0

External Interrupt Input 3/T2CCU

Capture/Compare Channel 0

Data Line 0 Input/Output

MultiCAN Node 0 Transmitter

Output

Output of Capture/Compare

channel 0

External Interrupt Input 4/T2CCU

Capture/Compare Channel 1

Data Line 1 Input/Output

P4.2 61 PU EXINT6_1

T21_0 D2

P4.3 40 Hi-Z T2EX_1

EXF21_1 COUT63_2

P4.4 45 Hi-Z CCPOS0_3

T0_0 CC61_4

T2CC2_0/ EXINT5_1 D4

External Interrupt Input 6

Timer 21 Input

Data Line 2 Input/Output

Timer 2 External Trigger Input

Timer 21 External Flag Output

Output of Capture/Compare

channel 3

Data Line 3 Input/Output

CCU6 Hall Input 0

Timer 0 Input

Output of Capture/Compare

channel 1

External Interrupt Input 5/T2CCU

Capture/Compare Channel 2

Data Line 4 Input/Output

Data Sheet 14 V1.2, 2009-11

Table 3 Pin Definitions and Functions (cont’d)

XC878CLM

General Device Information

Symbol Pin Number

(LQFP-64)

Type Reset

State

Function

P4.5 46 Hi-Z CCPOS1_3

T1_0 COUT61_2

T2CC3_0/ EXINT6_2 D5

P4.6 47 Hi-Z CCPOS2_3

T2_0 CC62_2

T2CC4_0 D6

P4.7 48 Hi-Z CTRAP_3

COUT62_2

T2CC5_0 D7

CCU6 Hall Input 1

Timer 1 Input

Output of Capture/Compare

channel 1

External Interrupt Input 6/T2CCU

Capture/Compare Channel 3

Data Line 5 Input/Output

CCU6 Hall Input 2

Timer 2 Input

Output of Capture/Compare

channel 2

Compare Output Channel 4

Data Line 6 Input/Output

CCU6 Trap Input

Output of Capture/Compare

channel 2

Compare Output Channel 5

Data Line 7 Input/Output

Data Sheet 15 V1.2, 2009-11

Table 3 Pin Definitions and Functions (cont’d)

XC878CLM

General Device Information

Symbol Pin Number

(LQFP-64)

Type Reset

State

Function

P5 I/O Port 5

Port 5 is an 8-bit bidirectional general purpose I/O port. It can be used as alternate functions for UART, UART1, T2CCU, JTAG and External Interface.

P5.0 8 PU EXINT1_1A0External Interrupt Input 1

Address Line 0 Output

P5.1 9 PU EXINT2_1A1External Interrupt Input 2

Address Line 1 Output

P5.2 12 PU RXD_2

T2CC2_2/ EXINT5_3 A2

P5.3 13 PU CCPOS0_0

EXINT1_0 T12HR_2

UART Receive Data Input

External Interrupt Input 5/T2CCU

Capture/Compare Channel 2

Address Line 2 Output

CCU6 Hall Input 0

External Interrupt Input 1

CCU6 Timer 12 Hardware Run

Input CC61_3

Input of Capture/Compare

channel 1 TXD_2

UART Transmit Data

Output/Clock Output T2CC5_2 A3

Compare Output Channel 5

Address Line 3 Output

P5.4 14 PU CCPOS1_0

EXINT2_0 T13HR_2

CCU6 Hall Input 1

External Interrupt Input 2

CCU6 Timer 13 Hardware Run

Input CC62_3

Input of Capture/Compare

channel 2 RXDO_2 T2CC4_2 A4

Data Sheet 16 V1.2, 2009-11

UART Transmit Data Output

Compare Output Channel 4

Address Line 4 Output

Table 3 Pin Definitions and Functions (cont’d)

XC878CLM

General Device Information

Symbol Pin Number

(LQFP-64)

Type Reset

State

Function

P5.5 15 PU CCPOS2_0

CTRAP_1 CC60_3

TDO_1 TXD1_2

T2CC0_2/ EXINT3_3 A5

P5.6 19 PU TCK_1

RXDO1_2 T2CC1_2/ EXINT4_3 A6

P5.7 20 PU TDI_1

RXD1_2 T2CC3_2/ EXINT6_4 A7

CCU6 Hall Input 2

CCU6 Trap Input

Input of Capture/Compare

channel 0

JTAG Serial Data Output

UART1 Transmit Data Output/

Clock Output

External Interrupt Input 3/T2CCU

Capture/Compare Channel 0

Address Line 5 Output

JTAG Clock Input

UART1 Transmit Data Output

External Interrupt Input 4/T2CCU

Capture/Compare Channel 1

Address Line 6 Output

JTAG Serial Data Input

UART1 Receive Data Input

External Interrupt Input 6/T2CCU

Capture/Compare Channel 3

Address Line 7 Output

Data Sheet 17 V1.2, 2009-11

Table 3 Pin Definitions and Functions (cont’d)

XC878CLM

General Device Information

Symbol Pin Number

(LQFP-64)

DDP

7, 25, 55 – – I/O Port Supply (3.3 or 5.0 V)

Type Reset

State

Function

Also used by EVR and analog modules. All pins must be connected.

SSP

26, 54 – – I/O Ground

All pins must be connected.

DDC

SSC

AREF

AGND

6 – – Core Supply Monitor (2.5 V)

5 – – Core Supply Ground

32 – – ADC Reference Voltage

31 – – ADC Reference Ground

AN0 22 I Hi-Z Analog Input 0

AN1 23 I Hi-Z Analog Input 1

AN2 24 I Hi-Z Analog Input 2

AN3 27 I Hi-Z Analog Input 3

AN4 28 I Hi-Z Analog Input 4

AN5 29 I Hi-Z Analog Input 5

AN6 30 I Hi-Z Analog Input 6

AN7 33 I Hi-Z Analog Input 7

XTAL1 4 I Hi-Z External Oscillator Input

(Feedback resistor required, normally NC)

XTAL2 3 O Hi-Z External Oscillator Output

(Feedback resistor required, normally NC)

TMS 16 I PD JTAG Test Mode Select

RESET 53 I PU Reset Input

MBC 58 I PU Monitor & BootStrap Loader Control

TM 57 – – Test Mode

(External pull down device required)

NC 56 – – No Connection

Data Sheet 18 V1.2, 2009-11

XC878CLM

Functional Description

3 Functional Description

Chapter 3 provides an overview of the XC878 functional description.

3.1 Processor Architecture

The XC878 is based on a high-performance 8-bit Central Processing Unit (CPU) that is compatible with the standard 8051 processor. While the standard 8051 processor is designed around a 12-clock machine cycle, the XC878 CPU uses a 2-clock machine cycle. This allows fast access to ROM or RAM memories without wait state. The instruction set consists of 45% one-byte, 41% two-byte and 14% three-byte instructions.

The XC878 CPU provides a range of debugging features, including basic stop/start, single-step execution, breakpoint support and read/write access to the data memory, program memory and Special Function Registers (SFRs).

Figure 5 shows the CPU functional blocks.

External Data

Memory

Program Memory

CCLK

Memory Wait

Reset

Legacy External Interrupts (IEN0, IEN1)

External Interrupts

Non-Maskable Interrupt

Core SFRs

16-bit R egisters & Memory Interface

Opcode &

Immediate

Registers

Opcode D ecoder

State Machine &

Power Saving

Interrupt

Controller

Internal Data

Memory

External SFRs

ALU

Multiplier / Divider

Timer 0 / Timer 1

UART

Figure 5 CPU Block Diagram

Data Sheet 19 V1.2, 2009-11

XC878CLM

Functional Description

3.2 Memory Organization

The XC878 CPU operates in the following address spaces:

• 8 Kbytes of Boot ROM program memory

• 256 bytes of internal RAM data memory

• 3 Kbytes of XRAM memory (XRAM can be read/written as program memory or external data memory)

• A 128-byte Special Function Register area

• 64/52 Kbytes of Flash program memory (Flash devices)

Figure 6 and Figure 7 illustrate the memory address spaces of the XC878 with

64Kbytes and 52Kbytes embedded Flash respectively.

Bank F

Bank E

Bank D

Bank C

Bank B

Bank A

Bank 9

Bank 8

Bank 7

Bank 6

Bank 5

Bank 4

Bank 3

Bank 2Bank 0

Bank 1

Reserved

External

Reserved

External

XRAM

3 KByte

Reserved

Boot ROM

8 KByte

Reserved

D-Flash 4 KByte

P-Flash

60 KByte

F' FF FF

F' 0000 E' FFFF E' 0000 D' FFFF D' 0000 C' FFFF C' 0000 B' FFFF B' 0000 A' FFFF A' 0000 9' FFFF 9' 0000 8' FFFF 8' 0000 7' FFFF 7' 0000 6' FFFF 6' 0000 5' FFFF 5' 0000 4' FFFF 4' 0000 3' FFFF 3' 0000 2' FFFF 2' FEC0

2' FE00 2' FC00

2' F000 2' E000

2' C000

2' 0000 1' FFFF

1' 0000 0' FFFF

0' F000

0' 0000

External

XRAM

3 KByte

External

Reserved

Ext ernal

Reserved

External

Reserved

External

Reserved

F' FFFF F' FC0 0

F' F000

2' FE00 2' FC00

2' F000 2' E000

2' C000

2' 0000 1' FFFF

1' 0000 0' FFFF

Memory Ex tension

Stack Pointer

Ext ensi on Stack R AM

(MEXSP)

Indirect

Address

Internal RAM

Direct

Address

Speci al Func ti on

Registers

Internal RAM

0' 0000

Code Space Internal Data Space

Data Space

Memor y Map U ser Mode

Figure 6 Memory Map of XC878 with 64K Flash Memory in user mode

Data Sheet 20 V1.2, 2009-11

XC878CLM

Functional Description

External

Reserved

External

XRAM

2 KByte

D-Flash 4 KByte

Boot ROM

8 KByte

P-Flash

48 KByte /

Reserved

P-Flash

32 KBy te

F’FFFF

1'0000 FFFF

FEC0

FE00

FC0 0

F000

E000

C00 0

8000

0000

F’FFFF

ExternalReserved

External

Reserved

External

XRAM

2 KBy te

1'0000

FFFF

FEC0

FE00 FC0 0

F000

Reserved

C00 0

Reserved /

Ext ernal

Reserved

8000

Memory Extensi on

Extension Stack RAM

Stack Pointer

(MEXSP)

Indirect

Address

Internal RAM

Direct

Addres s

Special Function

Registers

Internal RAM

0000

Code Spac e Internal Data Space

Data Space

Figure 7 Memory Map of XC878 with 52K Flash Memory in user mode

Memory Map User Mode

Data Sheet 21 V1.2, 2009-11

XC878CLM

Functional Description

3.2.1 Memory Protection Strategy

The XC878 memory protection strategy includes:

• Basic protection: The user is able to block any external access via the boot option to any memory

• Read-out protection: The user is able to protect the contents in the Flash

• Flash program and erase protection

These protection strategies are enabled by programming a valid password (16-bit nonone value) via Bootstrap Loader (BSL) mode 6.

3.2.1.1 Flash Memory Protection

As long as a valid password is available, all external access to the device, including the Flash, will be blocked.

For additional security, the Flash hardware protection can be enabled to implement a second layer of read-out protection, as well as to enable program and erase protection.

Flash hardware protection is available only for Flash devices and comes in two modes:

• Mode 0: Only the P-Flash is protected; the D-Flash is unprotected

• Mode 1: Both the P-Flash and D-Flash are protected

The selection of each protection mode and the restrictions imposed are summarized in

Table 4.

Table 4 Flash Protection Modes

Flash Protection

Hardware Protection Mode

Activation Program a valid password via BSL mode 6

Selection Bit 13 of password = 0 Bit 13 of password = 1

P-Flash contents can be read by

Without hardware protection

-01

Read instructions in any program memory

With hardware protection

Bit 13 of password = 1

MSB of password = 0

Read instructions in the P-Flash

MSB of password = 1

Read instructions in the P-Flash or DFlash

External access to PFlash

Data Sheet 22 V1.2, 2009-11

Not possible Not possible Not possible

Table 4 Flash Protection Modes (cont’d)

XC878CLM

Functional Description

Flash Protection

P-Flash program and erase

D-Flash contents can be read by

External access to DFlash

D-Flash program

D-Flash erase

Without hardware

With hardware protection

protection

Possible Possible only on the

condition that MSB - 1 of password is set to 1

Read instructions in any program memory

Possible only on the condition that MSB - 1 of password is set to 1

Read instructions in the P-Flash or DFlash

Not possible Not possible Not possible

Possible Possible Possible, on the

condition that MSB - 1 of password is set to 1

Possible Possible, on these

conditions:

• MISC_CON.DFLASH

Possible, on the condition that MSB - 1

of password is set to 1 EN bit is set to 1 prior to each erase operation; or

• the MSB - 1 of password is set to 1

BSL mode 6, which is used for enabling Flash protection, can also be used for disabling Flash protection. Here, the programmed password must be provided by the user. To disable the flash protection, a password match is required. A password match triggers an automatic erase of the protected P-Flash and D-Flash contents, including the programmed password. With a valid password, the Flash hardware protection is then enabled or disabled upon next reset. For the other protection strategies, no reset is necessary.

Although no protection scheme can be considered infallible, the XC878 memory protection strategy provides a very high level of protection for a general purpose microcontroller.

Note: If ROM read-out protection is enabled, only read instructions in the ROM memory

can target the ROM contents.

Data Sheet 23 V1.2, 2009-11

XC878CLM

Functional Description

3.2.2 Special Function Register

The Special Function Registers (SFRs) occupy direct internal data memory space in the range 80

to FFH. All registers, except the program counter, reside in the SFR area. The

SFRs include pointers and registers that provide an interface between the CPU and the on-chip peripherals. As the 128-SFR range is less than the total number of registers required, address extension mechanisms are required to increase the number of addressable SFRs. The address extension mechanisms include:

• Mapping

•Paging

3.2.2.1 Address Extension by Mapping

Address extension is performed at the system level by mapping. The SFR area is extended into two portions: the standard (non-mapped) SFR area and the mapped SFR area. Each portion supports the same address range 80 addressable SFRs to 256. The extended address range is not directly controlled by the CPU instruction itself, but is derived from bit RMAP in the system control register SYSCON0 at address 8F

. To access SFRs in the mapped area, bit RMAP in SFR

SYSCON0 must be set. Alternatively, the SFRs in the standard area can be accessed by clearing bit RMAP. The SFR area can be selected as shown in Figure 8.

to FFH, bringing the number of

As long as bit RMAP is set, the mapped SFR area can be accessed. This bit is not cleared automatically by hardware. Thus, before standard/mapped registers are accessed, bit RMAP must be cleared/set, respectively, by software.

Data Sheet 24 V1.2, 2009-11

Functional Description

Standard Area (RMAP = 0)

Module 1 SFRs

XC878CLM

SFR Data

(to/from CPU)

SYSCON0.RMAP

Module 2 SFRs

…...

Module n SFRs

Mapped Area (RMAP = 1)

Module (n+1) SFRs

Module (n+2) SFRs

…...

Module m SFRs

Direct

Internal Data

Memory Address

Figure 8 Address Extension by Mapping

Data Sheet 25 V1.2, 2009-11

XC878CLM

Functional Description

SYSCON0 System Control Register 0 Reset Value: 04

76543210

0 IMODE 0 1 0 RMAP

r rwrrrrw

Field Bits Type Description

RMAP 0rwInterrupt Node XINTR0 Enable

0 The access to the standard SFR area is

enabled

1 The access to the mapped SFR area is

enabled

1 2rReserved

Returns 1 if read; should be written with 1.

0 [7:5],

3,1

r Reserved

Returns 0 if read; should be written with 0.

Note: The RMAP bit should be cleared/set by ANL or ORL instructions.The rest bits of

SYSCON0 should not be modified.

3.2.2.2 Address Extension by Paging

Address extension is further performed at the module level by paging. With the address extension by mapping, the XC878 has a 256-SFR address range. However, this is still less than the total number of SFRs needed by the on-chip peripherals. To meet this requirement, some peripherals have a built-in local address extension mechanism for increasing the number of addressable SFRs. The extended address range is not directly controlled by the CPU instruction itself, but is derived from bit field PAGE in the module page register MOD_PAGE. Hence, the bit field PAGE must be programmed before accessing the SFR of the target module. Each module may contain a different number of pages and a different number of SFRs per page, depending on the specific requirement. Besides setting the correct RMAP bit value to select the SFR area, the user must also ensure that a valid PAGE is selected to target the desired SFR. A page inside the extended address range can be selected as shown in Figure 9.

Data Sheet 26 V1.2, 2009-11

SFR Address

(from CPU)

XC878CLM

Functional Description

PAGE 0

SFR Data

(to/from CPU)

MOD_PAGE.PAGE

SFR0

SFR1

…...

SFRx

PAGE 1

SFR0

SFR1

…...

SFRy

…...

PAGE q

SFR0

SFR1

…...

SFRz

Module

Figure 9 Address Extension by Paging

In order to access a register located in a page different from the actual one, the current page must be exited. This is done by reprogramming the bit field PAGE in the page register. Only then can the desired access be performed.

If an interrupt routine is initiated between the page register access and the module register access, and the interrupt needs to access a register located in another page, the current page setting can be saved, the new one programmed and the old page setting restored. This is possible with the storage fields STx (x = 0 - 3) for the save and restore action of the current page setting. By indicating which storage bit field should be used in parallel with the new page value, a single write operation can:

• Save the contents of PAGE in STx before overwriting with the new value (this is done in the beginning of the interrupt routine to save the current page setting and program the new page number); or

Data Sheet 27 V1.2, 2009-11

XC878CLM

Functional Description

• Overwrite the contents of PAGE with the contents of STx, ignoring the value written to the bit positions of PAGE (this is done at the end of the interrupt routine to restore the previous page setting before the interrupt occurred)

ST3

ST2

ST1

ST0

STNR

value update

PAGE

from CPU

Figure 10 Storage Elements for Paging

With this mechanism, a certain number of interrupt routines (or other routines) can perform page changes without reading and storing the previously used page information. The use of only write operations makes the system simpler and faster. Consequently, this mechanism significantly improves the performance of short interrupt routines.

The XC878 supports local address extension for:

• Parallel Ports

• Analog-to-Digital Converter (ADC)

• Capture/Compare Unit 6 (CCU6)

• System Control Registers

Data Sheet 28 V1.2, 2009-11

XC878CLM

Functional Description

The page register has the following definition:

MOD_PAGE Page Register for module MOD Reset Value: 00

76543210

OP STNR 0 PAGE

wwrrw

Field Bits Type Description

PAGE [2:0] rw Page Bits

When written, the value indicates the new page. When read, the value indicates the currently active page.

STNR [5:4] w Storage Number

This number indicates which storage bit field is the target of the operation defined by bit field OP. If OP = 10

the contents of PAGE are saved in STx before being overwritten with the new value. If OP = 11

the contents of PAGE are overwritten by the contents of STx. The value written to the bit positions of PAGE is ignored.

00 ST0 is selected. 01 ST1 is selected. 10 ST2 is selected. 11 ST3 is selected.

Data Sheet 29 V1.2, 2009-11

Field Bits Type Description

OP [7:6] w Operation

0X Manual page mode. The value of STNR is

ignored and PAGE is directly written.

10 New page programming with automatic page

saving. The value written to the bit positions of PAGE is stored. In parallel, the previous contents of PAGE are saved in the storage bit field STx indicated by STNR.

11 Automatic restore page action. The value

written to the bit positions PAGE is ignored and instead, PAGE is overwritten by the contents of the storage bit field STx indicated by STNR.

XC878CLM

Functional Description

0 3rReserved

Returns 0 if read; should be written with 0.

3.2.3 Bit Protection Scheme

The bit protection scheme prevents direct software writing of selected bits (i.e., protected bits) using the PASSWD register. When the bit field MODE is 11 bit field PASS opens access to writing of all protected bits, and writing 10101 field PASS closes access to writing of all protected bits. In both cases, the value of the bit field MODE is not changed even if PASSWD register is written with 98 only be changed when bit field PASS is written with 11000

, for example, writing D0H to

PASSWD register disables the bit protection scheme.

Note that access is opened for maximum 32 CCLKs if the “close access” password is not written. If “open access” password is written again before the end of 32 CCLK cycles, there will be a recount of 32 CCLK cycles. The protected bits include the N- and KDivider bits, NDIV and KDIV; the Watchdog Timer enable bit, WDTEN; and the powerdown and slow-down enable bits, PD and SD.

, writing 10011B to the

to the bit

or A8H. It can

Data Sheet 30 V1.2, 2009-11

XC878CLM

Functional Description

3.2.3.1 Password Register

PASSWD Password Register Reset Value: 07

76543210

PASS

wrhrw

PROTECT

Field Bits Type Description

MODE [1:0] rw Bit Protection Scheme Control Bits

00 Scheme disabled - direct access to the

protected bits is allowed.

11 Scheme enabled - the bit field PASS has to be

written with the passwords to open and close

the access to protected bits. (default) Others:Scheme Enabled. These two bits cannot be written directly. To change the value between 11 must be written with 11000

and 00B, the bit field PASS

; only then, will the

MODE[1:0] be registered.

PROTECT_S 2rhBit Protection Signal Status Bit

This bit shows the status of the protection. 0 Software is able to write to all protected bits. 1 Software is unable to write to any protected

bits.

MODE

PASS [7:3] w Password Bits

The Bit Protection Scheme only recognizes three patterns. 11000B Enables writing of the bit field MODE. 10011 10101

Data Sheet 31 V1.2, 2009-11

Opens access to writing of all protected bits.

Closes access to writing of all protected bits

XC878CLM

Functional Description

3.2.4 XC878 Register Overview

The SFRs of the XC878 are organized into groups according to their functional units. The contents (bits) of the SFRs are summarized in Chapter 3.2.4.1 to Chapter 3.2.4.15.

Note: The addresses of the bitaddressable SFRs appear in bold typeface.

3.2.4.1 CPU Registers

The CPU SFRs can be accessed in both the standard and mapped memory areas (RMAP = 0 or 1).

Table 5 CPU Register Overview

Addr Register Name Bit 7 6 5 4 3 2 1 0

RMAP = 0 or 1

SP Reset: 07

Stack Pointer Register

DPL Reset: 00

Data Pointer Register Low

DPH Reset: 00

Data Pointer Register High

PCON Reset: 00

Power Control Register

TCON Reset: 00

Timer Control Register

TMOD Reset: 00

Timer Mode Register

TL0 Reset: 00

Timer 0 Register Low

TL1 Reset: 00

Timer 1 Register Low

TH0 Reset: 00

Timer 0 Register High

TH1 Reset: 00

Timer 1 Register High

MEX1 Reset: 00

Memory Extension Register 1

MEX2 Reset: 00

Memory Extension Register 2

MEX3 Reset: 00

Memory Extension Register 3

Bit Field

Type rw

Bit Field

Type rw rw rw rw rw rw rw rw

Bit Field

Type rw rw rw rw rw rw rw rw

Bit Field

Type rw r rw rw r rw

Bit Field

Type rwh rw rwh rw rwh rw rwh rw

Bit Field

Type rw rw rw rw rw rw

Bit Field

Type rwh

Bit Field

Type rwh

Bit Field

Type rwh

Bit Field

Type rwh

Bit Field

Type r rw

Bit Field MCM MCB IB

Type rw rw rw

Bit Field MCB1

Type rw r rw rw rw

DPL7 DPL6 DPL5 DPL4 DPL3 DPL2 DPL1 DPL0

DPH7 DPH6 DPH5 DPH4 DPH3 DPH2 DPH1 DPH0

SMOD 0 GF1 GF0 0 IDLE

TF1 TR1 TF0 TR0 IE1 IT1 IE0 IT0

GATE1T1S T1M GATE0T0S T0M

CB NB

0 MXB19MXM MXB

VAL

Data Sheet 32 V1.2, 2009-11

XC878CLM

Functional Description

Table 5 CPU Register Overview (cont’d)

Addr Register Name Bit 7 6 5 4 3 2 1 0

MEXSP Reset: 7F

Memory Extension Stack Pointer Register

SCON Reset: 00

Serial Channel Control Register

SBUF Reset: 00

Serial Data Buffer Register

EO Reset: 00

Extended Operation Register

IEN0 Reset: 00

Interrupt Enable Register 0

IP Reset: 00

Interrupt Priority Register

IPH Reset: 00

Interrupt Priority High Register

PSW Reset: 00

Program Status Word Register

ACC Reset: 00

Accumulator Register

IEN1 Reset: 00

Interrupt Enable Register 1

B Reset: 00

B Register

IP1 Reset: 00

Interrupt Priority 1 Register

IPH1 Reset: 00

Interrupt Priority 1 High Register

Bit Field

Type r rwh

Bit Field

Type rw rw rw rw rw rwh rwh rwh

Bit Field

Type rwh

Bit Field

Type r rw r rw

Bit Field

Type rw r rwrwrwrwrwrw

Bit Field

Type r rwrwrwrwrwrw

Bit Field

Type r rwrwrwrwrwrw

Bit Field

Type rwh rwh rw rw rw rwh rw rh

Bit Field

Type rw rw rw rw rw rw rw rw

Bit Field

Type rw rw rw rw rw rw rw rw

Bit Field

Type rw rw rw rw rw rw rw rw

Bit Field

Type rw rw rw rw rw rw rw rw

Bit Field

Type rw rw rw rw rw rw rw rw

0 MXSP

SM0 SM1 SM2 REN TB8 RB8 TI RI

VAL

0 TRAP_

EA 0 ET2 ES ET1 EX1 ET0 EX0

0 PT2 PS PT1 PX1 PT0 PX0

0 PT2H PSH PT1H PX1H PT0H PX0H

CY AC F0 RS1 RS0 OV F1 P

ACC7 ACC6 ACC5 ACC4 ACC3 ACC2 ACC1 ACC0

ECCIP3ECCIP2ECCIP1ECCIP0EXM EX2 ESSC EADC

B7 B6 B5 B4 B3 B2 B1 B0

PCCIP3PCCIP2PCCIP1PCCIP0PXM PX2 PSSC PADC

PCCIP3HPCCIP2HPCCIP1HPCCIP0HPXMH PX2H PSSCHPADC

0 DPSE

3.2.4.2 MDU Registers

The MDU SFRs can be accessed in the mapped memory area (RMAP = 1).

Table 6 MDU Register Overview

Addr Register Name Bit 7 6 5 4 3 2 1 0

RMAP = 1

MDUSTAT Reset: 00

MDU Status Register

Bit Field

Type r rh rwh rwh

Data Sheet 33 V1.2, 2009-11

0 BSY IERR IRDY

XC878CLM

Functional Description

Table 6 MDU Register Overview (cont’d)

Addr Register Name Bit 7 6 5 4 3 2 1 0

MDUCON Reset: 00

MDU Control Register

MD0 Reset: 00

MDU Operand Register 0

MR0 Reset: 00

MDU Result Register 0

MD1 Reset: 00

MDU Operand Register 1

MR1 Reset: 00

MDU Result Register 1

MD2 Reset: 00

MDU Operand Register 2

MR2 Reset: 00

MDU Result Register 2

MD3 Reset: 00

MDU Operand Register 3

MR3 Reset: 00

MDU Result Register 3

MD4 Reset: 00

MDU Operand Register 4

MR4 Reset: 00

MDU Result Register 4

MD5 Reset: 00

MDU Operand Register 5

MR5 Reset: 00

MDU Result Register 5

Bit Field

Type rw rw rw rwh rw

Bit Field

Type rw

Bit Field

Type rh

Bit Field

Type rw

Bit Field

Type rh

Bit Field

Type rw

Bit Field

Type rh

Bit Field

Type rw

Bit Field

Type rh

Bit Field

Type rw

Bit Field

Type rh

Bit Field

Type rw

Bit Field

Type rh

IE IR RSEL STAR

DATA

OPCODE

3.2.4.3 CORDIC Registers

The CORDIC SFRs can be accessed in the mapped memory area (RMAP = 1).

Table 7 CORDIC Register Overview

Addr Register Name Bit 7 6 5 4 3 2 1 0

RMAP = 1

CD_CORDXL Reset: 00

CORDIC X Data Low Byte

CD_CORDXH Reset: 00

CORDIC X Data High Byte

Data Sheet 34 V1.2, 2009-11

Bit Field

Type rw

Bit Field

Type rw

DATAL

DATAH

XC878CLM

Functional Description

Table 7 CORDIC Register Overview (cont’d)

Addr Register Name Bit 7 6 5 4 3 2 1 0

CD_CORDYL Reset: 00

CORDIC Y Data Low Byte

CD_CORDYH Reset: 00

CORDIC Y Data High Byte

CD_CORDZL Reset: 00

CORDIC Z Data Low Byte

CD_CORDZH Reset: 00

CORDIC Z Data High Byte

CD_STATC Reset: 00

CORDIC Status and Data Control Register

CD_CON Reset: 00

CORDIC Control Register

Bit Field

Type rw

Bit Field

Type rw

Bit Field

Type rw

Bit Field

Type rw

Bit Field

Type rw rw rw rw rw rwh rh rh

Bit Field

Type rw rw rw rw rw rwh

KEEPZKEEPYKEEPXDMAP INT_ENEOC ERRORBSY

MPS X_USIGNST_M

ODE

DATAL

DATAH

DATAL

DATAH

ROTV

MODE ST

3.2.4.4 System Control Registers

The system control SFRs can be accessed in the mapped memory area (RMAP = 0).

Table 8 SCU Register Overview

Addr Register Name Bit 7 6 5 4 3 2 1 0

RMAP = 0 or 1

RMAP = 0

RMAP = 0, PAGE 0

SYSCON0 Reset: 04

System Control Register 0

SCU_PAGE Reset: 00

Page Register

MODPISEL Reset: 00

Peripheral Input Select Register

IRCON0 Reset: 00

Interrupt Request Register 0

IRCON1 Reset: 00

Interrupt Request Register 1

IRCON2 Reset: 00

Interrupt Request Register 2

Bit Field

Type r rw r r r rw

Bit Field

Type w w r rwh

Bit Field

Type r rwrwrwrwrwrwrw

Bit Field

Type r rwh rwh rwh rwh rwh rwh rwh

Bit Field

Type r rwh rwh rwh rwh rwh rwh rwh

Bit Field

Type rrwhrrwh

0 URRISHJTAGT

0 EXINT6EXINT5EXINT

0 CANS

0 IMOD

OP STNR 0 PAGE

DIS

RC2

CANS

RC1

0 CANS

JTAGT

CKS

ADCSR1ADCSR0RIR TIR EIR

RC3

0 1 0 RMAP

EXINT

2IS

1IS

EXINT2EXINT1EXINT

0 CANS

EXINT

0IS

URRIS

RC0

Data Sheet 35 V1.2, 2009-11

XC878CLM

Functional Description

Table 8 SCU Register Overview (cont’d)

Addr Register Name Bit 7 6 5 4 3 2 1 0

RMAP = 0, PAGE 1

EXICON0 Reset: F0

External Interrupt Control Register 0

EXICON1 Reset: 3F

External Interrupt Control Register 1

NMICON Reset: 00

NMI Control Register

NMISR Reset: 00

NMI Status Register

BCON Reset: 20

Baud Rate Control Register

BG Reset: 00

Baud Rate Timer/Reload Register

FDCON Reset: 00

Fractional Divider Control Register

FDSTEP Reset: 00

Fractional Divider Reload Register

FDRES Reset: 00

Fractional Divider Result Register

ID Reset: 49

Identity Register

PMCON0 Reset: 80

Power Mode Control Register 0

PMCON1 Reset: 00

Power Mode Control Register 1

OSC_CON Reset: XX

OSC Control Register

PLL_CON Reset: 18

PLL Control Register

CMCON Reset: 10

Clock Control Register

Bit Field

Type rw rw rw rw

Bit Field

Typer rwrwrw

Bit Field

Type r rw rw r rw rw rw rw

Bit Field

Type r rwh rwh r rwh rwh rwh rwh

Bit Field

Type rw rw rw rw rw

Bit Field

Type rwh

Bit Field

Type rw rw rwh rwh rwh rwh rw rw

Bit Field

Type rw

Bit Field

Type rh

Bit Field

Type r r

Bit Field

Type rh rwh rwh rw rw rwh rw

Bit Field

Type r rwrwrwrwrwrwrw

Bit Field

Type rwh rwh rw r rw rwh rwh rh

Bit Field

Type rw rh rh

Bit Field

Type rw r rw rw

EXINT3 EXINT2 EXINT1 EXINT0

0 EXINT6 EXINT5 EXINT4

0 NMI

ECC

0 FNMI

ECC

BGSEL NDOVENBRDIS BRPRE R

BGS SYNENERRSYNEOFSYNBRK NDOV FDM FDEN

VDDP

WARN

PLLRD

RES

WDT RST

0 CDC_

DIS

PLLBYPPLLPD 0 XPD OSCSSEORD

KDIV 0 FCCF

NMI

VDDP

FNMI

VDDP

PRODID VERID

WKRS WK

CAN_

DIS

0 NMI

OCDS

0 FNMI

OCDS

BR_VALUE

STEP

RESULT

SEL

MDU_

DIS

NDIV PLLR PLL_L

SD PD WS

T2CC

U_DIS

NMI

FLASH

FNMI

FLASH

CCU_

DIS

CLKREL

NMI PLL

FNMI

PLL

SSC_

DIS

RES

NMI

WDT

FNMI

WDT

ADC_

DIS

EXTO

SCR

OCK

Data Sheet 36 V1.2, 2009-11

XC878CLM

Functional Description

Table 8 SCU Register Overview (cont’d)

Addr Register Name Bit 7 6 5 4 3 2 1 0

RMAP = 0, PAGE 3

PASSWD Reset: 07

Password Register

COCON Reset: 00

Clock Output Control Register

MISC_CON Reset: 00

Miscellaneous Control Register

PLL_CON1 Reset: 20

PLL Control Register 1

CR_MISC Reset: 00H or 01

Reset Status Register

XADDRH Reset: F0

On-chip XRAM Address Higher Order

IRCON3 Reset: 00

Interrupt Request Register 3

IRCON4 Reset: 00

Interrupt Request Register 4

MODIEN Reset: 07

Peripheral Interrupt Enable Register

MODPISEL1 Reset: 00

Peripheral Input Select Register 1

MODPISEL2 Reset: 00

Peripheral Input Select Register 2

PMCON2 Reset: 00

Power Mode Control Register 2

MODSUSP Reset: 01

Module Suspend Control Register

MODPISEL3 Reset: 00

Peripheral Input Select Register 3

MODPISEL4 Reset: 00

Peripheral Input Select Register 4

Bit Field

Type w rh rw

Bit Field

Type rw rw r rw

Bit Field

Type rw rw r rwh

Bit Field

Type rw rw

Bit Field

Type rw rw rw rw r rwh

Bit Field

Type rw

Bit Field

Type r rwh rwh r rwh rwh

Bit Field

Type r rwh rwh r rwh rwh

Bit Field

Type r rw rw rw rw rw

Bit Field

Type rw rw rw r

Bit Field

Type r rw rw rw rw rw

Bit Field

Type r rw rw

Bit Field

Type r rwrwrwrwrwrw

Bit Field

Typer rwrwrw

Bit Field

Typer rwrwrw

COUTS TLEN 0 COREL

ADCE

TR0_

MUX

CCCFGMDUC

ADCE

TR1_

MUX

NDIV PDIV

CFG

0 CANS

EXINT6IS UR1RIS T21EX

0 CCTS

0 CIS SIS MIS

0 EXINT5IS EXINT4IS EXINT3IS

PASS PROT

CCUC

0 CM5ENCM4ENRIREN TIREN EIREN

0 T2EXIST21IS T2IS T1IS T0IS

T2CCF

CFG

RC5

RC7

USP

ADDRH

CCU6

SR1

CCU6

SR3

0 UART

T21SUSPT2SUSPT13SUSPT12SUSPWDTS

ECT_S

0 DFLAS

0 HDRS

0 CANS

RC4

RC6

1_DIS

MODE

HEN

CCU6

SR0

CCU6

SR2

T21_D

USP

Data Sheet 37 V1.2, 2009-11

XC878CLM

Functional Description

3.2.4.5 WDT Registers

The WDT SFRs can be accessed in the mapped memory area (RMAP = 1).

Table 9 WDT Register Overview

Addr Register Name Bit 7 6 5 4 3 2 1 0

RMAP = 1

WDTCON Reset: 00

Watchdog Timer Control Register

WDTREL Reset: 00

Watchdog Timer Reload Register

WDTWINB Reset: 00

Watchdog Window-Boundary Count Register

WDTL Reset: 00

Watchdog Timer Register Low

WDTH Reset: 00

Watchdog Timer Register High

Bit Field

Type r rw rh r rw rwh rw

Bit Field

Type rw

Bit Field

Type rw

Bit Field

Type rh

Bit Field

Type rh

0 WINBENWDTP

WDTREL

WDTWINB

0 WDTENWDTRSWDTI

WDT

3.2.4.6 Port Registers

The Port SFRs can be accessed in the standard memory area (RMAP = 0).

Table 10 Port Register Overview

Addr Register Name Bit 7 6 5 4 3 2 1 0

RMAP = 0

RMAP = 0, PAGE 0

PORT_PAGE Reset: 00

Page Register

P0_DATA Reset: 00

P0 Data Register

P0_DIR Reset: 00

P0 Direction Register

P1_DATA Reset: 00

P1 Data Register

P1_DIR Reset: 00

P1 Direction Register

P5_DATA Reset: 00

P5 Data Register

P5_DIR Reset: 00

P5 Direction Register

Bit Field

Type w w r rwh

Bit Field

Type rwhrwhrwhrwhrwhrwhrwhrwh

Bit Field

Type rw rw rw rw rw rw rw rw

Bit Field

Type rwhrwhrwhrwhrwhrwhrwhrwh

Bit Field

Type rw rw rw rw rw rw rw rw

Bit Field

Type rwhrwhrwhrwhrwhrwhrwhrwh

Bit Field

Type rw rw rw rw rw rw rw rw

OP STNR 0 PAGE

P7 P6 P5 P4 P3 P2 P1 P0

Data Sheet 38 V1.2, 2009-11

XC878CLM

Functional Description

Table 10 Port Register Overview (cont’d)

Addr Register Name Bit 7 6 5 4 3 2 1 0

RMAP = 0, PAGE 1

RMAP = 0, PAGE 2

P3_DATA Reset: 00

P3 Data Register

P3_DIR Reset: 00

P3 Direction Register

P4_DATA Reset: 00

P4 Data Register

P4_DIR Reset: 00

P4 Direction Register

P0_PUDSEL Reset: FF

P0 Pull-Up/Pull-Down Select Register

P0_PUDEN Reset: C4

P0 Pull-Up/Pull-Down Enable Register

P1_PUDSEL Reset: FF

P1 Pull-Up/Pull-Down Select Register

P1_PUDEN Reset: FF

P1 Pull-Up/Pull-Down Enable Register

P5_PUDSEL Reset: FF

P5 Pull-Up/Pull-Down Select Register

P5_PUDEN Reset: FF

P5 Pull-Up/Pull-Down Enable Register

P3_PUDSEL Reset: BF

P3 Pull-Up/Pull-Down Select Register

P3_PUDEN Reset: 40

P3 Pull-Up/Pull-Down Enable Register

P4_PUDSEL Reset: FF

P4 Pull-Up/Pull-Down Select Register

P4_PUDEN Reset: 04

P4 Pull-Up/Pull-Down Enable Register

P0_ALTSEL0 Reset: 00

P0 Alternate Select 0 Register

P0_ALTSEL1 Reset: 00

P0 Alternate Select 1 Register

P1_ALTSEL0 Reset: 00

P1 Alternate Select 0 Register

Bit Field

Type rwhrwhrwhrwhrwhrwhrwhrwh

Bit Field

Type rw rw rw rw rw rw rw rw

Bit Field

Type rwhrwhrwhrwhrwhrwhrwhrwh

Bit Field

Type rw rw rw rw rw rw rw rw

Bit Field

Type rw rw rw rw rw rw rw rw

Bit Field

Type rw rw rw rw rw rw rw rw

Bit Field

Type rw rw rw rw rw rw rw rw

Bit Field

Type rw rw rw rw rw rw rw rw

Bit Field

Type rw rw rw rw rw rw rw rw

Bit Field

Type rw rw rw rw rw rw rw rw

Bit Field

Type rw rw rw rw rw rw rw rw

Bit Field

Type rw rw rw rw rw rw rw rw

Bit Field

Type rw rw rw rw rw rw rw rw

Bit Field

Type rw rw rw rw rw rw rw rw

Bit Field

Type rw rw rw rw rw rw rw rw

Bit Field

Type rw rw rw rw rw rw rw rw

Bit Field

Type rw rw rw rw rw rw rw rw

P7 P6 P5 P4 P3 P2 P1 P0

Data Sheet 39 V1.2, 2009-11

XC878CLM

Functional Description

Table 10 Port Register Overview (cont’d)

Addr Register Name Bit 7 6 5 4 3 2 1 0

RMAP = 0, PAGE 3

P1_ALTSEL1 Reset: 00

P1 Alternate Select 1 Register

P5_ALTSEL0 Reset: 00

P5 Alternate Select 0 Register

P5_ALTSEL1 Reset: 00

P5 Alternate Select 1 Register

P3_ALTSEL0 Reset: 00

P3 Alternate Select 0 Register

P3_ALTSEL1 Reset: 00

P3 Alternate Select 1 Register

P4_ALTSEL0 Reset: 00

P4 Alternate Select 0 Register

P4_ALTSEL1 Reset: 00

P4 Alternate Select 1 Register

P0_OD Reset: 00

P0 Open Drain Control Register

P0_DS Reset: FF

P0 Drive Strength Control Register

P1_OD Reset: 00

P1 Open Drain Control Register

P1_DS Reset: FF

P1 Drive Strength Control Register

P5_OD Reset: 00

P5 Open Drain Control Register

P5_DS Reset: FF

P5 Drive Strength Control Register

P3_OD Reset: 00

P3 Open Drain Control Register

P3_DS Reset: FF

P3 Drive Strength Control Register

P4_OD Reset: 00

P4 Open Drain Control Register

P4_DS Reset: FF

P4 Drive Strength Control Register

Bit Field

Type rw rw rw rw rw rw rw rw

Bit Field

Type rw rw rw rw rw rw rw rw

Bit Field

Type rw rw rw rw rw rw rw rw

Bit Field

Type rw rw rw rw rw rw rw rw

Bit Field

Type rw rw rw rw rw rw rw rw

Bit Field

Type rw rw rw rw rw rw rw rw

Bit Field

Type rw rw rw rw rw rw rw rw

Bit Field

Type rw rw rw rw rw rw rw rw

Bit Field

Type rw rw rw rw rw rw rw rw

Bit Field

Type rw rw rw rw rw rw rw rw

Bit Field

Type rw rw rw rw rw rw rw rw

Bit Field

Type rw rw rw rw rw rw rw rw

Bit Field

Type rw rw rw rw rw rw rw rw

Bit Field

Type rw rw rw rw rw rw rw rw

Bit Field

Type rw rw rw rw rw rw rw rw

Bit Field

Type rw rw rw rw rw rw rw rw

Bit Field

Type rw rw rw rw rw rw rw rw

P7 P6 P5 P4 P3 P2 P1 P0

Data Sheet 40 V1.2, 2009-11

XC878CLM

Functional Description

3.2.4.7 ADC Registers

The ADC SFRs can be accessed in the standard memory area (RMAP = 0).

Table 11 ADC Register Overview

AddrRegister Name Bit 76543210

RMAP = 0

RMAP = 0, PAGE 0

RMAP = 0, PAGE 1

ADC_PAGE Reset: 00

Page Register

ADC_GLOBCTR Reset: 30

Global Control Register

ADC_GLOBSTR Reset: 00

Global Status Register

ADC_PRAR Reset: 00

Priority and Arbitration Register

ADC_LCBR Reset: B7

Limit Check Boundary Register

ADC_INPCR0 Reset: 00

Input Class 0 Register

ADC_ETRCR Reset: 00

External Trigger Control Register

ADC_CHCTR0 Reset: 00

Channel Control Register 0

ADC_CHCTR1 Reset: 00

Channel Control Register 1

ADC_CHCTR2 Reset: 00

Channel Control Register 2

ADC_CHCTR3 Reset: 00

Channel Control Register 3

ADC_CHCTR4 Reset: 00

Channel Control Register 4

ADC_CHCTR5 Reset: 00

Channel Control Register 5

ADC_CHCTR6 Reset: 00

Channel Control Register 6

ADC_CHCTR7 Reset: 00

Channel Control Register 7

Bit Field

Type w w r rw

Bit Field

Type rw rw rw r

Bit Field

Type r rh r rh rh

Bit Field

Type rw rw r rw rw rw rw rw

Bit Field

Type rw rw

Bit Field

Type rw

Bit Field

Type rw rw rw rw

Bit Field

Type r rw r rw

Bit Field

Type r rw r rw

Bit Field

Type r rw r rw

Bit Field

Type r rw r rw

Bit Field

Type r rw r rw

Bit Field

Type r rw r rw

Bit Field

Type r rw r rw

Bit Field

Type r rw r rw

OP STNR 0 PAGE

ANON DW CTC 0

0 CHNR 0 SAMPLEBUSY

ASEN1ASEN

BOUND1 BOUND0

SYNEN1SYNE

0 LCC 0 RESRSEL

0 ARBM CSM1 PRIO1 CSM0 PRIO0

STC

ETRSEL1 ETRSEL0

Data Sheet 41 V1.2, 2009-11

XC878CLM

Functional Description

Table 11 ADC Register Overview (cont’d)

AddrRegister Name Bit 76543210

RMAP = 0, PAGE 2

RMAP = 0, PAGE 3

RMAP = 0, PAGE 4

ADC_RESR0L Reset: 00

Result Register 0 Low

ADC_RESR0H Reset: 00

Result Register 0 High

ADC_RESR1L Reset: 00

Result Register 1 Low

ADC_RESR1H Reset: 00

Result Register 1 High

ADC_RESR2L Reset: 00

Result Register 2 Low

ADC_RESR2H Reset: 00

Result Register 2 High

ADC_RESR3L Reset: 00

Result Register 3 Low

ADC_RESR3H Reset: 00

Result Register 3 High

ADC_RESRA0L Reset: 00

Result Register 0, View A Low

ADC_RESRA0H Reset: 00

Result Register 0, View A High

ADC_RESRA1L Reset: 00

Result Register 1, View A Low

ADC_RESRA1H Reset: 00

Result Register 1, View A High

ADC_RESRA2L Reset: 00

Result Register 2, View A Low

ADC_RESRA2H Reset: 00

Result Register 2, View A High

ADC_RESRA3L Reset: 00

Result Register 3, View A Low

ADC_RESRA3H Reset: 00

Result Register 3, View A High

ADC_RCR0 Reset: 00

Result Control Register 0

Bit Field

Type rh r rh rh rh

Bit Field

Type rh

Bit Field

Type rh r rh rh rh

Bit Field

Type rh

Bit Field

Type rh r rh rh rh

Bit Field

Type rh

Bit Field

Type rh r rh rh rh

Bit Field

Type rh

Bit Field

Type rh rh rh rh

Bit Field

Type rh

Bit Field

Type rh rh rh rh

Bit Field

Type rh

Bit Field

Type rh rh rh rh

Bit Field

Type rh

Bit Field

Type rh rh rh rh

Bit Field

Type rh

Bit Field

Type rw rw r rw r rw

RESULT 0 VF DRC CHNR

RESULT

RESULT 0 VF DRC CHNR

RESULT

RESULT 0 VF DRC CHNR

RESULT

RESULT 0 VF DRC CHNR

RESULT

RESULT VF DRC CHNR

RESULT

RESULT VF DRC CHNR

RESULT

RESULT VF DRC CHNR

RESULT

RESULT VF DRC CHNR

RESULT

VFCTRWFR 0 IEN 0 DRCT

Data Sheet 42 V1.2, 2009-11

XC878CLM

Functional Description

Table 11 ADC Register Overview (cont’d)

AddrRegister Name Bit 76543210

RMAP = 0, PAGE 5

RMAP = 0, PAGE 6

ADC_RCR1 Reset: 00

Result Control Register 1

ADC_RCR2 Reset: 00

Result Control Register 2

ADC_RCR3 Reset: 00

Result Control Register 3

ADC_VFCR Reset: 00

Valid Flag Clear Register

ADC_CHINFR Reset: 00

Channel Interrupt Flag Register

ADC_CHINCR Reset: 00

Channel Interrupt Clear Register

ADC_CHINSR Reset: 00

Channel Interrupt Set Register

ADC_CHINPR Reset: 00

Channel Interrupt Node Pointer Register

ADC_EVINFR Reset: 00

Event Interrupt Flag Register

ADC_EVINCR Reset: 00

Event Interrupt Clear Flag Register

ADC_EVINSR Reset: 00

Event Interrupt Set Flag Register

ADC_EVINPR Reset: 00

Event Interrupt Node Pointer Register

ADC_CRCR1 Reset: 00

Conversion Request Control Register 1

ADC_CRPR1 Reset: 00

Conversion Request Pending Register 1

Bit Field

Type rw rw r rw r rw

Bit Field

Type rw rw r rw r rw

Bit Field

Type rw rw r rw r rw

Bit Field

Type r w w w w

Bit Field

Type rh rh rh rh rh rh rh rh

Bit Field

Typewwwwwwww

Bit Field

Typewwwwwwww

Bit Field

Type rw rw rw rw rw rw rw rw

Bit Field

Type rh rh rh rh r rh rh

Bit Field

Typewwww r ww

Bit Field

Typewwww r ww

Bit Field

Type rw rw rw rw r rw rw

Bit Field

Type rwh rwh rwh rwh r

Bit Field

Type rwh rwh rwh rwh r

VFCTRWFR 0 IEN 0 DRCT

0 VFC3 VFC2 VFC1 VFC0

CHINF7CHINF6CHINF5CHINF4CHINF3CHINF2CHINF1CHINF

CHINC7CHINC6CHINC5CHINC4CHINC3CHINC2CHINC1CHINC

CHINS7CHINS6CHINS5CHINS4CHINS3CHINS2CHINS1CHINS

CHINP7CHINP6CHINP5CHINP4CHINP3CHINP2CHINP1CHINP

EVINF7EVINF6EVINF5EVINF

EVINC7EVINC6EVINC5EVINC

EVINS7EVINS6EVINS5EVINS

EVINP7EVINP6EVINP5EVINP

CH7 CH6 CH5 CH4 0

CHP7 CHP6 CHP5 CHP4 0

0 EVINF1EVINF

0 EVINC1EVINC

0 EVINS1EVINS

0 EVINP1EVINP

Data Sheet 43 V1.2, 2009-11

XC878CLM

Functional Description

Table 11 ADC Register Overview (cont’d)

AddrRegister Name Bit 76543210

ADC_CRMR1 Reset: 00

Conversion Request Mode Register 1

ADC_QMR0 Reset: 00

Queue Mode Register 0

ADC_QSR0 Reset: 20

Queue Status Register 0

ADC_Q0R0 Reset: 00

Queue 0 Register 0

ADC_QBUR0 Reset: 00

Queue Backup Register 0

ADC_QINR0 Reset: 00

Queue Input Register 0

Bit Field

Type r w w rw rw rw r rw

Bit Field

Typewwww rrwrrw

Bit Field

Type r r rh rh r rh

Bit Field

Type rh rh rh rh r rh

Bit Field

Type rh rh rh rh r rh

Bit Field

Typewww r w

Rsv LDEV CLRPNDSCAN ENSI ENTR 0 ENGT

CEV TREV FLUSHCLRV 0 ENTR 0 ENGT

Rsv 0 EMPTYEV 0 FILL

EXTR ENSI RF V 0 REQCHNR

EXTR ENSI RF 0 REQCHNR

Data Sheet 44 V1.2, 2009-11

XC878CLM

Functional Description

3.2.4.8 Timer 2 Compare/Capture Unit Registers

The Timer 2 Compare/Capture Unit SFRs can be accessed in the standard memory area (RMAP = 0).

Table 12 T2CCU Register Overview

Addr Register Name Bit 7 6 5 4 3 2 1 0

RMAP = 0

RMAP = 0, PAGE 0

RMAP = 0, PAGE 1

T2_PAGE Reset: 00

Page Register

T2_T2CON Reset: 00

Timer 2 Control Register

T2_T2MOD Reset: 00

Timer 2 Mode Register

T2_RC2L Reset: 00

Timer 2 Reload/Capture Register Low

T2_RC2H Reset: 00

Timer 2 Reload/Capture Register High

T2_T2L Reset: 00

Timer 2 Register Low

T2_T2H Reset: 00

Timer 2 Register High

T2_T2CON1 Reset: 03

Timer 2 Control Register 1

T2CCU_CCEN Reset: 00

T2CCU Capture/Compare Enable Register

T2CCU_CCTBSELReset: 00

T2CCU Capture/Compare Time Base Select Register

T2CCU_CCTRELLReset: 00

T2CCU Capture/Compare Timer Reload Register Low

T2CCU_CCTRELHReset: 00

T2CCU Capture/Compare Timer Reload Register High

T2CCU_CCTL Reset: 00

T2CCU Capture/Compare Timer Register Low

Bit Field

Type w w r rwh

Bit Field

Type rwh rwh r rw rwh rw rw

Bit Field

Type rw rw rw rw rw rw

Bit Field

Type rwh

Bit Field

Type rwh

Bit Field

Type rwh

Bit Field

Type rwh

Bit Field

Type r rw rw

Bit Field

Type rw rw rw rw

Bit Field

Type rwrwhrwrwrwrwrwrw

Bit Field

Type rw

Bit Field

Type rw

Bit Field

Type rwh

OP STNR 0 PAGE

TF2 EXF2 0 EXEN2TR2 C/T2 CP/

T2REGST2RHENEDGE

SEL

CCM3 CCM2 CCM1 CCM0

CASC CCTTOVCCTB5CCTB4CCTB3CCTB2CCTB1CCTB

PREN T2PRE DCEN

RC2

THL2

0 TF2EN EXF2E

CCTREL

CCT

RL2

Data Sheet 45 V1.2, 2009-11

XC878CLM

Functional Description

Table 12 T2CCU Register Overview (cont’d)

Addr Register Name Bit 7 6 5 4 3 2 1 0

RMAP = 0, PAGE 2

RMAP = 0, PAGE 3

T2CCU_CCTH Reset: 00

T2CCU Capture/Compare Timer Register High

T2CCU_CCTCON Reset: 00

T2CCU CaptureCcompare Timer Control Register

T2CCU_COSHDWReset: 00

T2CCU Capture/compare Enable Register

T2CCU_CC0L Reset: 00

T2CCU Capture/Compare Register 0 Low

T2CCU_CC0H Reset: 00

T2CCU Capture/compare Register 0 High

T2CCU_CC1L Reset: 00

T2CCU Capture/compare Register 1 Low

T2CCU_CC1H Reset: 00

T2CCU Capture/compare Register 1 High

T2CCU_CC2L Reset: 00

T2CCU Capture/compare Register 2 Low

T2CCU_CC2H Reset: 00

T2CCU Capture/compare Register 2 High

T2CCU_COCON Reset: 00

T2CCU Compare Control Register

T2CCU_CC3L Reset: 00

T2CCU Capture/compare Register 3 Low

T2CCU_CC3H Reset: 00

T2CCU Capture/compare Register 3 High

T2CCU_CC4L Reset: 00

T2CCU Capture/compare Register 4 Low

T2CCU_CC4H Reset: 00

T2CCU Capture/compare Register 4 High

T2CCU_CC5L Reset: 00

T2CCU Capture/compare Register 5 Low

T2CCU_CC5H Reset: 00

T2CCU Capture/compare Register 5 High

Bit Field

Type rwh

Bit Field

Type rw rwh rw rw rw

Bit Field

Type rwh rwh rwh rwh rwh rwh rwh rwh

Bit Field

Type rwh

Bit Field

Type rwh

Bit Field

Type rwh

Bit Field

Type rwh

Bit Field

Type rwh

Bit Field

Type rwh

Bit Field

Type rw rw rwh rwh rw rw rw

Bit Field

Type rwh

Bit Field

Type rwh

Bit Field

Type rwh

Bit Field

Type rwh

Bit Field

Type rwh

Bit Field

Type rwh

ENSHDWTXOV COOUT5COOUT4COOUT3COOUT2COOUT1COOU

CCM5 CCM4 CM5F CM4F POLB POLA COMOD

CCTPRE CCTOVFCCTO

CCT

TIMSYNCCTS

VEN

CCVALL

CCVALH

CCVALL

CCVALH

CCVALL

CCVALH

CCVALL

CCVALH

CCVALL

CCVALH

CCVALL

CCVALH

Data Sheet 46 V1.2, 2009-11

XC878CLM

Functional Description

Table 12 T2CCU Register Overview (cont’d)

Addr Register Name Bit 7 6 5 4 3 2 1 0

RMAP = 0, PAGE 4

T2CCU_CCTDTCLReset: 00

T2CCU Capture/Compare Timer Dead-Time Control Register Low

T2CCU_CCTDTCHReset: 00

T2CCU Capture/Compare Timer Dead-Time Control Register High

Bit Field

Type rw

Bit Field

Type rwhrh rh rhrwrwrwrw

DTRESDTR2 DTR1 DTR0 DTLEV DTE2 DTE1 DTE0

DTM

3.2.4.9 Timer 21 Registers

The Timer 21 SFRs can be accessed in the mapped memory area (RMAP = 1).

Table 13 T21 Register Overview

Addr Register Name Bit 7 6 5 4 3 2 1 0

RMAP = 1

T21_T2CON Reset: 00

Timer 2 Control Register

T21_T2MOD Reset: 00

Timer 2 Mode Register

T21_RC2L Reset: 00

Timer 2 Reload/Capture Register Low

T21_RC2H Reset: 00

Timer 2 Reload/Capture Register High

T21_T2L Reset: 00

Timer 2 Register Low

T21_T2H Reset: 00

Timer 2 Register High

T21_T2CON1 Reset: 03

Timer 2 Control Register 1

Bit Field

Type rwh rwh r rw rwh rw rw

Bit Field

Type rw rw rw rw rw rw rw rw

Bit Field

Type rwh

Bit Field

Type rwh

Bit Field

Type rwh

Bit Field

Type rwh

Bit Field

Type r rw rw

TF2 EXF2 0 EXEN2TR2 C/T2 CP/

T2REGST2RHENEDGE

SEL

PREN T2PRE DCEN

RC2

THL2

0 TF2EN EXF2E

RL2

Data Sheet 47 V1.2, 2009-11

XC878CLM

Functional Description

3.2.4.10 CCU6 Registers

The CCU6 SFRs can be accessed in the standard memory area (RMAP = 0).

Table 14 CCU6 Register Overview

AddrRegister Name Bit 76543210

RMAP = 0

RMAP = 0, PAGE 0

CCU6_PAGE Reset: 00

Page Register

CCU6_CC63SRL Reset: 00

Capture/Compare Shadow Register for Channel CC63 Low

CCU6_CC63SRH Reset: 00

Capture/Compare Shadow Register for Channel CC63 High

CCU6_TCTR4L Reset: 00

Timer Control Register 4 Low

CCU6_TCTR4H Reset: 00

Timer Control Register 4 High

CCU6_MCMOUTSL Reset: 00

Multi-Channel Mode Output Shadow Register Low

CCU6_MCMOUTSH Reset: 00

Multi-Channel Mode Output Shadow Register High

CCU6_ISRL Reset: 00

Capture/Compare Interrupt Status Reset Register Low

CCU6_ISRH Reset: 00

Capture/Compare Interrupt Status Reset Register High

CCU6_CMPMODIFL Reset: 00

Compare State Modification Register Low

CCU6_CMPMODIFH Reset: 00

Compare State Modification Register High

CCU6_CC60SRL Reset: 00

Capture/Compare Shadow Register for Channel CC60 Low

CCU6_CC60SRH Reset: 00

Capture/Compare Shadow Register for Channel CC60 High

Bit Field

Type w w r rwh

Bit Field

Type rw

Bit Field

Type rw

Bit Field

Type ww r wwww

Bit Field

Type ww r www

Bit Field

Type w r rw

Bit Field

Type w r rw rw

Bit Field

Type wwwwwwww

Bit Field

Type wwww r www

Bit Field

Type r w r www

Bit Field

Type r w r www

Bit Field

Type rwh

Bit Field

Type rwh

OP STNR 0 PAGE

CC63SL

CC63SH

T12

STD

T13

STD

STRMCM0 MCMPS

STRHP0 CURHS EXPHS

RT12PMRT12OMRCC62FRCC62RRCC61FRCC61RRCC60FRCC6

RSTR RIDLE RWHERCHE 0 RTRPFRT13PMRT13

T12

STR

T13

STR

0 MCC6

0 DT

RES

0 T13

0 MCC62SMCC61SMCC6

0 MCC62RMCC61RMCC6

CC60SL

CC60SH

T12

RES

T12RST12R

T13RST13R

Data Sheet 48 V1.2, 2009-11

XC878CLM

Functional Description

Table 14 CCU6 Register Overview (cont’d)

AddrRegister Name Bit 76543210

RMAP = 0, PAGE 1

CCU6_CC61SRL Reset: 00

Capture/Compare Shadow Register for Channel CC61 Low

CCU6_CC61SRH Reset: 00

Capture/Compare Shadow Register for Channel CC61 High

CCU6_CC62SRL Reset: 00

Capture/Compare Shadow Register for Channel CC62 Low

CCU6_CC62SRH Reset: 00

Capture/Compare Shadow Register for Channel CC62 High

CCU6_CC63RL Reset: 00

Capture/Compare Register for Channel CC63 Low

CCU6_CC63RH Reset: 00

Capture/Compare Register for Channel CC63 High

CCU6_T12PRL Reset: 00

Timer T12 Period Register Low

CCU6_T12PRH Reset: 00

Timer T12 Period Register High

CCU6_T13PRL Reset: 00

Timer T13 Period Register Low

CCU6_T13PRH Reset: 00

Timer T13 Period Register High

CCU6_T12DTCL Reset: 00

Dead-Time Control Register for Timer T12 Low

CCU6_T12DTCH Reset: 00

Dead-Time Control Register for Timer T12 High

CCU6_TCTR0L Reset: 00

Timer Control Register 0 Low

CCU6_TCTR0H Reset: 00

Timer Control Register 0 High

CCU6_CC60RL Reset: 00

Capture/Compare Register for Channel CC60 Low

CCU6_CC60RH Reset: 00

Capture/Compare Register for Channel CC60 High

CCU6_CC61RL Reset: 00

Capture/Compare Register for Channel CC61 Low

Bit Field

Type rwh

Bit Field

Type rwh

Bit Field

Type rwh

Bit Field

Type rwh

Bit Field

Type rh

Bit Field

Type rh

Bit Field

Type rwh

Bit Field

Type rwh

Bit Field

Type rwh

Bit Field

Type rwh

Bit Field

Type rw

Bit Field

Type r rhrhrh r rwrwrw

Bit Field

Type rw rh rh rh rw rw

Bit Field

Type r rh rh rw rw

Bit Field

Type rh

Bit Field

Type rh

Bit Field

Type rh

0 DTR2 DTR1 DTR0 0 DTE2 DTE1 DTE0

CTM CDIR STE12T12R T12

0 STE13T13R T13

CC61SL

CC61SH

CC62SL

CC62SH

CC63VL

CC63VH

T12PVL

T12PVH

T13PVL

T13PVH

DTM

T12CLK

PRE

T13CLK

PRE

CC60VL

CC60VH

CC61VL

Data Sheet 49 V1.2, 2009-11

XC878CLM

Functional Description

Table 14 CCU6 Register Overview (cont’d)

AddrRegister Name Bit 76543210

RMAP = 0, PAGE 2

CCU6_CC61RH Reset: 00

Capture/Compare Register for Channel CC61 High

CCU6_CC62RL Reset: 00

Capture/Compare Register for Channel CC62 Low

CCU6_CC62RH Reset: 00

Capture/Compare Register for Channel CC62 High

CCU6_T12MSELL Reset: 00

T12 Capture/Compare Mode Select Register Low

CCU6_T12MSELH Reset: 00

T12 Capture/Compare Mode Select Register High

CCU6_IENL Reset: 00

Capture/Compare Interrupt Enable Register Low

CCU6_IENH Reset: 00

Capture/Compare Interrupt Enable Register High

CCU6_INPL Reset: 40

Capture/Compare Interrupt Node Pointer Register Low

CCU6_INPH Reset: 39

Capture/Compare Interrupt Node Pointer Register High

CCU6_ISSL Reset: 00

Capture/Compare Interrupt Status Set Register Low

CCU6_ISSH Reset: 00

Capture/Compare Interrupt Status Set Register High

CCU6_PSLR Reset: 00

Passive State Level Register

CCU6_MCMCTR Reset: 00

Multi-Channel Mode Control Register

CCU6_TCTR2L Reset: 00

Timer Control Register 2 Low

CCU6_TCTR2H Reset: 00

Timer Control Register 2 High

CCU6_MODCTRL Reset: 00

Modulation Control Register Low

Bit Field

Type rh

Bit Field

Type rh

Bit Field

Type rh

Bit Field

Type rw rw

Bit Field

Type rw rw rw

Bit Field

Type rw rw rw rw rw rw rw rw

Bit Field

Type rw rw rw rw r rw rw rw

Bit Field

Type rw rw rw rw

Bit Field

Type r rw rw rw

Bit Field

Type wwwwwwww

Bit Field

Type wwwwwwww

Bit Field

Type rwh r rwh

Bit Field

Type r rw r rw

Bit Field

Type r rw rw rw rw

Bit Field

Type r rw rw

Bit Field

Type rw r rw

DBYP HSYNC MSEL62

ENT1

STRENIDLEENWHEENCHE

INPCHE INPCC62 INPCC61 INPCC60

ST12PMST12OMSCC62FSCC62RSCC61FSCC61RSCC60FSCC6

SSTR SIDLE SWHE SCHE SWHCSTRPFST13PMST13

PSL63 0 PSL

0 T13TED T13TEC T13

MCM

MSEL61 MSEL60

ENT1

0 INPT13 INPT12 INPERR

0 SWSYN 0 SWSEL

ENCC

62F

0 T13RSEL T12RSEL

0 T12MODEN

CC61VH

CC62VL

CC62VH

ENCC

62R

ENCC

61F

0 EN

ENCC

61R

TRPF

ENCC

60F

ENT1

3PM

SSC

ENCC

60R

ENT1

3CM

T12

SSC

Data Sheet 50 V1.2, 2009-11

XC878CLM

Functional Description

Table 14 CCU6 Register Overview (cont’d)

AddrRegister Name Bit 76543210

RMAP = 0, PAGE 3

CCU6_MODCTRH Reset: 00

Modulation Control Register High

CCU6_TRPCTRL Reset: 00

Trap Control Register Low

CCU6_TRPCTRH Reset: 00

Trap Control Register High

CCU6_MCMOUTL Reset: 00

Multi-Channel Mode Output Register Low

CCU6_MCMOUTH Reset: 00

Multi-Channel Mode Output Register High

CCU6_ISL Reset: 00

Capture/Compare Interrupt Status Register Low

CCU6_ISH Reset: 00

Capture/Compare Interrupt Status Register High

CCU6_PISEL0L Reset: 00

Port Input Select Register 0 Low

CCU6_PISEL0H Reset: 00

Port Input Select Register 0 High

CCU6_PISEL2 Reset: 00

Port Input Select Register 2

CCU6_T12L Reset: 00

Timer T12 Counter Register Low

CCU6_T12H Reset: 00

Timer T12 Counter Register High

CCU6_T13L Reset: 00

Timer T13 Counter Register Low

CCU6_T13H Reset: 00

Timer T13 Counter Register High

CCU6_CMPSTATL Reset: 00

Compare State Register Low

CCU6_CMPSTATH Reset: 00

Compare State Register High

Bit Field

Type rw r rw

Bit Field

Type r rw rw rw

Bit Field

Type rw rw rw

Bit Field

Type r rh rh

Bit Field

Type r rh rh

Bit Field

Type rh rh rh rh rh rh rh rh

Bit Field

Type rh rh rh rh rh rh rh rh

Bit Field

Type rw rw rw rw

Bit Field

Type rw rw rw rw

Bit Field

Type r rw

Bit Field

Type rwh

Bit Field

Type rwh

Bit Field

Type rwh

Bit Field

Type rwh

Bit Field

Type r rhrhrhrhrhrhrh

Bit Field

Type rwh rwh rwh rwh rwh rwh rwh rwh

ECT13O0 T13MODEN

0 TRPM2TRPM1TRPM

TRPPENTRPE

T12PMT12OMICC62FICC62RICC61FICC61RICC60FICC60

STR IDLE WHE CHE TRPS TRPF T13PMT13

T13IM COUT

N13

0 R MCMP

0 CURH EXPH

ISTRP ISCC62 ISCC61 ISCC60

IST12HR ISPOS2 ISPOS1 ISPOS0

0 IST13HR

T12CVL

T12CVH

T13CVL

T13CVH

0 CC63STCC

63PS

POS2CCPOS1CCPOS0

COUT

62PS

CC62PSCOUT

61PS

TRPEN

CC62STCC61STCC60

CC61PSCOUT

60PS

CC60

Data Sheet 51 V1.2, 2009-11

XC878CLM

Functional Description

3.2.4.11 UART1 Registers

The UART1 SFRs can be accessed in the mapped memory area (RMAP = 1).

Table 15 UART1 Register Overview

Addr Register Name Bit 7 6 5 4 3 2 1 0

RMAP = 1

SCON Reset: 00

Serial Channel Control Register

SBUF Reset: 00

Serial Data Buffer Register

BCON Reset: 00

Baud Rate Control Register

BG Reset: 00

Baud Rate Timer/Reload Register

FDCON Reset: 00

Fractional Divider Control Register

FDSTEP Reset: 00

Fractional Divider Reload Register

FDRES Reset: 00

Fractional Divider Result Register

SCON1 Reset: 07

Serial Channel Control Register 1

Bit Field

Type rw rw rw rw rw rwh rwh rwh

Bit Field

Type rwh

Bit Field

Type r rw rw

Bit Field

Type rwh

Bit Field

Type r rwh rw rw

Bit Field

Type rw

Bit Field

Type rh

Bit Field

Type r rw rw rw

SM0 SM1 SM2 REN TB8 RB8 TI RI

VAL

0 BRPRE R

BR_VALUE

0 NDOV FDM FDEN

STEP

RESULT

0 NDOVENTIEN RIEN

3.2.4.12 SSC Registers

The SSC SFRs can be accessed in the standard memory area (RMAP = 0).

Table 16 SSC Register Overview

Addr Register Name Bit 7 6 5 4 3 2 1 0

RMAP = 0

Data Sheet 52 V1.2, 2009-11

SSC_PISEL Reset: 00

Port Input Select Register

SSC_CONL Reset: 00

Control Register Low Programming Mode

SSC_CONL Reset: 00

Control Register Low Operating Mode

SSC_CONH Reset: 00

Control Register High Programming Mode

Bit Field

Type r rw rw rw

Bit Field

Type rw rw rw rw rw

Bit Field

Type r rh

Bit Field

Type rw rw r rw rw rw rw rw

LB PO PH HB BM

EN MS 0 AREN BEN PEN REN TEN

0 CIS SIS MIS

0 BC

XC878CLM

Functional Description

Table 16 SSC Register Overview (cont’d)

Addr Register Name Bit 7 6 5 4 3 2 1 0

SSC_CONH Reset: 00

Control Register High Operating Mode

SSC_TBL Reset: 00

Transmitter Buffer Register Low

SSC_RBL Reset: 00

Receiver Buffer Register Low

SSC_BRL Reset: 00

Baud Rate Timer Reload Register Low

SSC_BRH Reset: 00

Baud Rate Timer Reload Register High

Bit Field

Type rw rw r rh rwh rwh rwh rwh

Bit Field

Type rw

Bit Field

Type rh

Bit Field

Type rw

Bit Field

Type rw

EN MS 0 BSY BE PE RE TE

TB_VALUE

RB_VALUE

BR_VALUE

3.2.4.13 MultiCAN Registers

The MultiCAN SFRs can be accessed in the standard memory area (RMAP = 0).

Table 17 CAN Register Overview

Addr Register Name Bit 7 6 5 4 3 2 1 0

RMAP = 0

ADCON Reset: 00

CAN Address/Data Control Register

ADL Reset: 00

CAN Address Register Low

ADH Reset: 00

CAN Address Register High

DATA0 Reset: 00

CAN Data Register 0

DATA1 Reset: 00

CAN Data Register 1

DATA2 Reset: 00

CAN Data Register 2

DATA3 Reset: 00

CAN Data Register 3

Bit Field

Type rw rw rw rw rw rh rw

Bit Field

Type rwh rwh rwh rwh rwh rwh rwh rwh

Bit Field

Type r rwh rwh rwh rwh

Bit Field

Type rwh

Bit Field

Type rwh

Bit Field

Type rwh

Bit Field

Type rwh

V3 V2 V1 V0 AUAD BSY RWEN

CA9 CA8 CA7 CA6 CA5 CA4 CA3 CA2

0 CA13 CA12 CA11 CA10

3.2.4.14 OCDS Registers

The OCDS SFRs can be accessed in the mapped memory area (RMAP = 1).

Data Sheet 53 V1.2, 2009-11

XC878CLM

Functional Description

Table 18 OCDS Register Overview

Addr Register Name Bit 7 6 5 4 3 2 1 0

RMAP = 1

MMCR2 Reset: 8U

Monitor Mode Control 2 Register

MEXTCR Reset: 0U

Memory Extension Control Register

MMWR1 Reset: 00

Monitor Work Register 1

MMWR2 Reset: 00

Monitor Work Register 2

MMCR Reset: 00

Monitor Mode Control Register

MMSR Reset: 00

Monitor Mode Status Register

MMBPCR Reset: 00

Breakpoints Control Register

MMICR Reset: 00

Monitor Mode Interrupt Control Register

MMDR Reset: 00

Monitor Mode Data Transfer Register Receive

HWBPSR Reset: 00

Hardware Breakpoints Select Register

HWBPDR Reset: 00

Hardware Breakpoints Data Register

Bit Field

Type rw rw rw rwh rw rwh rh rh

Bit Field

Type r rw

Bit Field

Type rw

Bit Field

Type rw

Bit Field

Type w rwh r rw w rwh rh rh

Bit Field

Type rw rwh rwh rwh rwh rwh rwh rwh

Bit Field

Type rw rw rw rw rw

Bit Field

Type rwh rwh rwh rh w rw w rw

Bit Field

Type rh

Bit Field

Type r w rw

Bit Field

Type rw

STMODEEXBC DSUSPMBCONALTDI MMEP MMODEJENA

0 BANKBPx

MMWR1

MMWR2

MEXIT_PMEXIT 0 MSTEPMRAM

S_P

MBCAMMBCIN EXBF SWBF HWB3FHWB2FHWB1FHWB0

SWBC HWB3C HWB2C HWB1

DVECTDRETRCOMRSTMSTSELMMUI

E_P

MMRR

0 BPSEL

HWBPxx

MRAMSTRF RRF

MMUIERRIE_PRRIE

BPSEL

HWB0C

Data Sheet 54 V1.2, 2009-11

XC878CLM

Functional Description

3.2.4.15 Flash Registers

The Flash SFRs can be accessed in the mapped memory area (RMAP = 1).

Table 19 Flash Register Overview

Addr Register Name Bit 7 6 5 4 3 2 1 0

RMAP = 1

FCON Reset: 10

P-Flash Control Register

EECON Reset: 10

D-Flash Control Register

FCS Reset: 80

Flash Control and Status Register

FEAL Reset: 00

Flash Error Address Register, Low Byte

FEAH Reset: 00

Flash Error Address Register, High Byte

FTVAL Reset: 78

Flash Timer Value Register

FCS1 Reset: 00

Flash Control and Status Register 1

Bit Field

Type r rh rwh r rw rw rw rw

Bit Field

Type r rh rwh r rw rw rw rw

Bit Field

Type r rw rwh r rwh rwh rwh rwh

Bit Field

Type rh

Bit Field

Type rh

Bit Field

Type rw rw

Bit Field

Type r rwh

0 FBSY YE 1 NVSTRMAS1 ERASEPROG

0 EEBSYYE 1 NVSTRMAS1 ERASEPROG

1 SBEIE FTEN 0 EEDERREESERRFDERRFSER

ECCEADDR

MODE OFVAL

0 EEAB

ORT

Data Sheet 55 V1.2, 2009-11

XC878CLM

Functional Description

3.3 Flash Memory

The Flash memory provides an embedded user-programmable non-volatile memory, allowing fast and reliable storage of user code and data. It is operated from a single 2.5 V supply from the Embedded Voltage Regulator (EVR) and does not require additional programming or erasing voltage. The pagination of the Flash memory allows each page to be erased independently.

Features

• In-System Programming (ISP) via UART

• In-Application Programming (IAP)

• Error Correction Code (ECC) for dynamic correction of single-bit errors

• Background program and erase operations for CPU load minimization

• Support for aborting erase operation

• Minimum program width

• of 1-byte for D-Flash and 2-bytes for P-Flash

• 1-page minimum erase width

• 1-byte read access

• Flash is delivered in erased state (read all ones)

• Operating supply voltage: 2.5 V ± 7.5 %

• Read access time: 1 ×

CCLK

=38 ns

• Program time for 1 wordline: 1.6 ms

• Page erase time: 20 ms

• Mass erase time: 200 ms

1) Values shown here are typical values. f

frequency range for Flash read access.

2) Values shown here are typical values. range for Flash programming and erasing.

= 144 MHz ± 7.5% (f

sys

= 144 MHz ± 7.5% (f

sys

is used for obtaining the worst case timing.

sysmin

= 24 MHz ± 7.5 %) is the maximum

CCLK

= 24 MHz ± 7.5 %) is the typical frequency

CCLK

Data Sheet 56 V1.2, 2009-11

XC878CLM

Functional Description

Table 20 and Table 21 shows the Flash data retention and endurance targets for

Industrial profile and Automotive profile respectively.

Table 20 Flash Data Retention and Endurance for Industrial Profile

(Operating Conditions apply)

Retention Endurance

1)2)

Program Flash

15 years 1000 cycles up to 60 Kbytes

Data Flash

15 years 1000 cycles 4 Kbytes

10 years 10,000 cycles 4 Kbytes

5 years 30,000 cycles 4 Kbytes

1 year 100,000 cycles 4 Kbytes

1) In Program Flash, one cycle refers to the programming of all pages in the flash bank and a mass erase.

2) In Data Flash, one cycle refers to the programming of all wordlines in a page and a page erase.

Size Remarks

Table 21 Flash Data Retention and Endurance for Automotive Profile

(Operating Conditions apply)

Retention Endurance

1)2)

Size Remarks

Program Flash

15 years 1000 cycles up to 60 Kbytes

Data Flash

15 years 1000 cycles 4 Kbytes

5 years 10,000 cycles 1 Kbytes

2 years 15,000 cycles 512 Bytes

2 years 30,000 cycles 256 Bytes

1 year 100,000 cycles 128 Bytes

1) In Program Flash, one cycle refers to the programming of all pages in the flash bank and a mass erase.

2) In Data Flash, one cycle refers to the programming of all wordlines in a page and a page erase.

Data Sheet 57 V1.2, 2009-11

XC878CLM

Functional Description

3.3.1 Flash Bank Pagination

The XC878 product family offers Flash devices with either 64 Kbytes or 52 Kbytes of embedded Flash memory. Each Flash device consists of a Program Flash (P-Flash) and a single Data Flash (D-Flash) bank. P-Flash has 120 pages of 8 wordlines per page with 64 bytes per wordline. D-Flash has 64 pages of 2 wordlines per page with 32 bytes per wordline. Both types can be used for code and data storage.. The label “Data” neither implies that the D-Flash is mapped to the data memory region, nor that it can only be used for data storage. It is used to distinguish the different page width and wordline of each Flash bank.

The internal structure of each Flash bank represents a page architecture for flexible erase capability. The minimum erase width is always a complete page. The D-Flash bank is divided into smaller size for extended erasing and reprogramming capability; even numbers for each page size are provided to allow greater flexibility and the ability to adapt to a wide range of application requirements.

Data Sheet 58 V1.2, 2009-11

XC878CLM

Functional Description

3.4 Interrupt System

The XC800 Core supports one non-maskable interrupt (NMI) and 14 maskable interrupt requests. In addition to the standard interrupt functions supported by the core, e.g., configurable interrupt priority and interrupt masking, the XC878 interrupt system provides extended interrupt support capabilities such as the mapping of each interrupt vector to several interrupt sources to increase the number of interrupt sources supported, and additional status registers for detecting and determining the interrupt source.

3.4.1 Interrupt Source

Figure 11 to Figure 15 give a general overview of the interrupt sources and nodes, and

their corresponding control and status flags.

WDT Overflow

PLL Los s of Clock

Flash Timer Overflow

VDDP Pre-Warning

Flas h EC C Error

FNMIWDT

NMIISR.0

FNMIPLL

NMIISR.1

FNMIFLASH

NMIISR.2

FNMIVDDP

NMIISR.5

FNMIECC

NMIISR.6

NMIWDT

NMICON.0

NMIPLL

NMICON.1

NMIFLASH

NMICON.2

NMIVDDP

NMICON.5

NMIECC

NMICON.6

>=1

0073

Non

Maskable

Interrupt

Figure 11 Non-Maskable Interrupt Request Sources

Data Sheet 59 V1.2, 2009-11

XC878CLM

Functional Description

Highest

EINT0

Timer 0

Overfl ow

Timer 1

Overflow

UART

Receive

UART

Transmit

EXINT 0

EXICON0.0/1

SCON.0

SCON.1

IT0

TCON.0

TF0

TCON.5

TF1

TCON.7

>=1

IE0

TCON.1

ET0

IEN0.1

ET1

IEN0.3

IEN0.4

EX0

IEN0.0

000B

001B

0023

0003

Lowest

IP.1/

IPH.1

IP.3/

IPH.3

Priority Leve

P o l l i n g

IP.4/

IPH.4

S e q u e n c e

IP.0/

IPH.0

EINT1

IT1

TCON.2

EXIN T1

EXIC ON0.2/ 3

IE1

TCON.3

EX1

IEN0.2

0013

IP.2/

IPH.2

IEN0.7

Bit-addressable

Request flag is cleared by hardware

Figure 12 Interrupt Request Sources (Part 1)

Data Sheet 60 V1.2, 2009-11

XC878CLM

Functional Description

T2EX

EDGES

T2_ T2MOD .5

Timer 2

Overf low

EXEN2

T2_ T2 CON.3

Overf low

Normal Divider

End of

Syn Byte

Syn Byte Error

MultiCAN

Node 0

TF2

T2_T2CON.7

CCT

Overf low

TF2EN

T2_T2CON1.1

EXF2

T2_T2CON.6

T2_T2CON1.0

CCTOVF

T2CCU_CCTCON.3

NDOV

FDCON.2

EOFSYN

FDCON.4

ERRSYN

FDCON.5

EXF2EN

T2CCU_CCTCON.2

CANSRC0

IRCON2.0

>=1

CCTOVEN

NDOVEN

BCON.5

SYNEN

FDCON.6

>=1

ET2

IEN0.5

002B

Highest

Lowest

Priority Level

IP.5/

IPH.5

P o l l i n g

ADC Service

Request 0

ADC Service

Request 1

MultiCAN

Node 1

MultiCAN

Node 2

ADCSRC0

IRCON1.3

ADCSRC1

IRCON1.4

CANSRC1

IRCON1.5

CANSRC2

IRCON1.6

>=1

Bit-

addressable

Request flag is cleared by hardware

Figure 13 Interrupt Request Sources (Part 2)

EADC

IEN1.0

0033

IEN0.7

S e q u e

IP1.0/

IPH1.0

n c e

Data Sheet 61 V1.2, 2009-11

XC878CLM

Functional Description

T21EX

EDGES

T21 _T 2MOD. 5

SSC Error

SSC Transmit

SSC Receive

EINT2

UART1

Timer 21 Overf low

EXEN2

T21_T2CON.3

UART1 Normal

Divider Overflow

EXINT 2

EXICON0.4/5

UART1_SCON.0

UART1_SCON.1

TF2

T21_ T2C ON.7

EXF2

T21_T2CON.6

EIR

IRCON1.0

TIR

IRCON1.1

RIR

IRCON1.2

RIEN

UART1_SCON1.0

TIEN

UART1_SCON1.1

TF2EN

T21_T2CON1.1

EXF2EN

T21_T2CON1.0

NDOV

UART1_FDCON.2

EIREN

MODIEN. 0

TIREN

MODIEN.1

RIREN

MODIEN. 2

EXINT2

IRCON0.2

>=1

NDOVEN

UART1_SCON1.2

>=1

ESSC

IEN1.1

EX2

IEN1.2

003B

0043

Highest

Lowest

Priority Level

IP1.1/

IPH1.1

P o l l i n g

S e q u e n

IP1.2/

IPH1.2

c e

CORDIC

MDU

Result Ready

MDU Error

EOC

CDSTATC.2

IRDY

MDUSTAT.0

IERR

MDUSTAT.1

IEN0.7

Bit-

addressable

Request flag is cleared by hardware

Figure 14 Interrupt Request Sources (Part 3)

Data Sheet 62 V1.2, 2009-11

XC878CLM

Functional Description

Highest

Lowest

Priority Level

T2CC0/

EINT3

T2CC1/

EINT4

T2CC2/

EINT5

T2CC3/

EINT6

EXINT3

EXICON0. 6/7

EXINT4

EXICON1.0/1

EXINT5

EXICON1.2/3

EXINT6

EXICON1.4/5

EXINT3

IRCON0.3

EXINT4

IRCON0.4

EXINT5

IRCON0.5

EXINT6

IRCON0.6

>=1

EXM

IEN1.3

004B

P o l l i n g

IP1.3/

IPH1.3

S e q u e n c e

Compare C hannel 4

Compare C hannel 5

MultiCAN N ode 3

CM4F

T2CC U_COC ON.4

CM5F

T2CC U_COC ON.5

CM4EN

MODIEN.3

CM5EN

MODIEN.4

CANSRC3

IRCON2.4

IEN0.7

Bit-

addressable

Request flag is cleared by hardware

Figure 15 Interrupt Request Sources (Part 4)

Data Sheet 63 V1.2, 2009-11

CCU6 Interrupt node 0

Mult iCAN Node 4

CCU6 Interrupt node 1

Mult iCAN Node 5

CCU6 Interrupt node 2

Mult iCAN Node 6

CCU6S R0

IRCO N3.0

CANS RC4

IRCO N3.1

CCU6S R1

IRCO N3.4

CANSRC5

IRCO N3.5

CCU6S R2

IRCO N4.0

CANS RC6

IRCO N4.1

>=1

ECCIP0

IEN1.4

ECCIP1

IEN1.5

ECCIP2

IEN1.6

0053

005B

0063

XC878CLM

Functional Description

Highest

Lowest

Priority Level

IP1.4/

IPH1.4

IP1.5/

IPH1.5

IP1.6/

IPH1.6

P o l l i n g

S e q u e n c e

CCU6 Interrupt node 3

Mult iCAN Node 7

CCU6S RC3

IRCO N4.4

CANS RC7

IRCO N4.5

>=1

ECCIP3

IEN1.7

Bit-addressable

Request flag is cleared by hardware

Figure 16 Interrupt Request Sources (Part 5)

006B

EA IEN0.7

IP1. 7/

IPH1.7

Data Sheet 64 V1.2, 2009-11

XC878CLM

Functional Description

3.4.2 Interrupt Source and Vector

Each interrupt event source has an associated interrupt vector address for the interrupt node it belongs to. This vector is accessed to service the corresponding interrupt node request. The interrupt service of each interrupt source can be individually enabled or disabled via an enable bit. The assignment of the XC878 interrupt sources to the interrupt vector address and the corresponding interrupt node enable bits are summarized in Table 22.

Table 22 Interrupt Vector Addresses

Interrupt Source

Vector Address

NMI 0073

XINTR0 0003

XINTR1 000B

XINTR2 0013

XINTR3 001B

XINTR4 0023

XINTR5 002B

Assignment for XC878 Enable Bit SFR

Watchdog Timer NMI NMIWDT NMICON

PLL NMI NMIPLL

Flash Timer NMI NMIFLASH

Prewarning NMI NMIVDDP

DDP

Flash ECC NMI NMIECC

External Interrupt 0 EX0 IEN0

Timer 0 ET0

External Interrupt 1 EX1

Timer 1 ET1

UART ES

T2CCU ET2

UART Fractional Divider (Normal Divider Overflow)

MultiCAN Node 0

LIN

Data Sheet 65 V1.2, 2009-11

Table 22 Interrupt Vector Addresses (cont’d)

XC878CLM

Functional Description

Interrupt Source

Vector Address

XINTR6 0033

XINTR7 003B

XINTR8 0043

XINTR9 004B

Assignment for XC878 Enable Bit SFR

MultiCAN Nodes 1 and 2 EADC IEN1

ADC[1:0]

SSC ESSC

External Interrupt 2 EX2

T21

CORDIC

UART1

UART1 Fractional Divider (Normal Divider Overflow)

MDU[1:0]

External Interrupt 3 EXM

External Interrupt 4

External Interrupt 5

External Interrupt 6

XINTR10 0053

XINTR11 005B

XINTR12 0063

XINTR13 006B

T2CCU

MultiCAN Node 3

CCU6 INP0 ECCIP0

MultiCAN Node 4

CCU6 INP1 ECCIP1

MultiCAN Node 5

CCU6 INP2 ECCIP2

MultiCAN Node 6

CCU6 INP3 ECCIP3

MultiCAN Node 7

Data Sheet 66 V1.2, 2009-11

XC878CLM

Functional Description

3.4.3 Interrupt Priority

An interrupt that is currently being serviced can only be interrupted by a higher-priority interrupt, but not by another interrupt of the same or lower priority. Hence, an interrupt of the highest priority cannot be interrupted by any other interrupt request.

If two or more requests of different priority levels are received simultaneously, the request of the highest priority is serviced first. If requests of the same priority are received simultaneously, then an internal polling sequence determines which request is serviced first. Thus, within each priority level, there is a second priority structure determined by the polling sequence shown in Table 23.

Table 23 Priority Structure within Interrupt Level

Source Level

Non-Maskable Interrupt (NMI) (highest)

External Interrupt 0 1

Timer 0 Interrupt 2

External Interrupt 1 3

Timer 1 Interrupt 4

UART Interrupt 5

T2CCU,UART Normal Divider Overflow,

MultiCAN, LIN Interrupt

ADC, MultiCAN Interrupt 7

SSC Interrupt 8

External Interrupt 2, Timer 21, UART1, UART1

Normal Divider Overflow, MDU, CORDIC Interrupt

External Interrupt [6:3], MultiCAN Interrupt 10

CCU6 Interrupt Node Pointer 0, MultiCAN interrupt 11

CCU6 Interrupt Node Pointer 1, MultiCAN Interrupt 12

CCU6 Interrupt Node Pointer 2, MultiCAN Interrupt 13

CCU6 Interrupt Node Pointer 3, MultiCAN Interrupt 14

Data Sheet 67 V1.2, 2009-11

XC878CLM

Functional Description

3.5 Parallel Ports

The XC878 has 40 port pins organized into five parallel ports: Port 0 (P0), Port 1 (P1), Port 3 (P3), Port 4 (P4) and Port 5 (P5). Each pin has a pair of internal pull-up and pulldown devices that can be individually enabled or disabled. These ports are bidirectional and can be used as general purpose input/output (GPIO) or to perform alternate input/output functions for the on-chip peripherals. When configured as an output, the open drain mode can be selected.

Bidirectional Port Features

• Configurable pin direction

• Configurable pull-up/pull-down devices

• Configurable open drain mode

• Configurable drive strength

• Transfer of data through digital inputs and outputs (general purpose I/O)

• Alternate input/output for on-chip peripherals

Data Sheet 68 V1.2, 2009-11

Figure 17 shows the structure of a bidirectional port pin.

Px _ PUD SEL

Pull-up/Pull-down

Internal Bus

Select Register

Px_PUDEN

Pull-up/Pull-down

Enable Register

Px_DS

Drive Str ength

Control Register

Px_O D

Open Drain

Control Register

Pull-up /Pull-do wn

Control Logic

XC878CLM

Functional Description

Alt Dat aO ut 3

Alt Dat aO ut 2

Alt Dat aOut 1

Alt Dat aIn

Px_DI R

Direction Register

Px_AL TSEL 0

Alternate Select Register 0

Px_AL TSEL 1

Alternate Select Register 1

Px_Data

Data Register

Out

OpenDrain/Output

Control Logic

Pull

Device

Output

Dri ver

I nput Dri ver

Schmit t T rigger

Pad

Figure 17 General Structure of Bidirectional Port

Data Sheet 69 V1.2, 2009-11

XC878CLM

Functional Description

3.6 Power Supply System with Embedded Voltage Regulator

The XC878 microcontroller requires two different levels of power supply:

• 3.3 V or 5.0 V for the Embedded Voltage Regulator (EVR) and Ports

• 2.5 V for the core, memory, on-chip oscillator, and peripherals

Figure 18 shows the XC878 power supply system. A power supply of 3.3 V or 5.0 V

must be provided from the external power supply pin. The 2.5 V power supply for the logic is generated by the EVR. The EVR helps to reduce the power consumption of the whole chip and the complexity of the application board design.

The EVR consists of a main voltage regulator and a low power voltage regulator. In active mode, both voltage regulators are enabled. In power-down mode, the main voltage regulator is switched off, while the low power voltage regulator continues to function and provide power supply to the system with low power consumption.

CPU &

Memory

GPIO Ports

(P0-P5)

On-chip

OSC

EVR

DDC

Peripheral

logic

(2.5V)

Figure 18 XC878 Power Supply System

V V

DDP

SSP

ADC

FLASH

PLL

XTAL1&

XTAL2

(3.3V/5.0V)

EVR Features

• Input voltage (

• Output voltage (

): 3.3 V/5.0 V

DDP

): 2.5 V ± 7.5%

DDC

• Low power voltage regulator provided in power-down mode

•

Data Sheet 70 V1.2, 2009-11

prewarning detection

DDP

brownout detection

DDC

XC878CLM

Functional Description

3.7 Reset Control

The XC878 has five types of reset: power-on reset, hardware reset, watchdog timer reset, power-down wake-up reset, and brownout reset.

When the XC878 is first powered up, the status of certain pins (see Table 25) must be defined to ensure proper start operation of the device. At the end of a reset sequence, the sampled values are latched to select the desired boot option, which cannot be modified until the next power-on reset or hardware reset. This guarantees stable conditions during the normal operation of the device.

The second type of reset in XC878 is the hardware reset. This reset function can be used during normal operation or when the chip is in power-down mode. A reset input pin RESET

The Watchdog Timer (WDT) module is also capable of resetting the device if it detects a malfunction in the system.

Another type of reset that needs to be detected is a reset while the device is in power-down mode (wake-up reset). While the contents of the static RAM are undefined after a power-on reset, they are well defined after a wake-up reset from power-down mode.

is provided for the hardware reset.

3.7.1 Module Reset Behavior

Table 24 lists the functions of the XC878 and the various reset types that affect these

functions. The symbol “■” signifies that the particular function is reset to its default state.

Table 24 Effect of Reset on Device Functions

Module/ Function

CPU Core ■■■■■ Peripherals ■■■■■

On-Chip Static RAM

Oscillator, PLL

Port Pins ■■■■■

EVR The voltage

Wake-Up Reset

Not affected, Reliable

■ Not affected ■■■

regulator is switched on

Watchdog Reset

Not affected, Reliable

Not affected Not affected ■■

Hardware Reset

Not affected, Reliable

Power-On Reset

Affected, unreliable

Brownout Reset

Affected, unreliable

FLASH ■■■■■ NMI Disabled Disabled ■■■

Data Sheet 71 V1.2, 2009-11

XC878CLM

Functional Description

3.7.2 Booting Scheme

When the XC878 is reset, it must identify the type of configuration with which to start the different modes once the reset sequence is complete. Thus, boot configuration information that is required for activation of special modes and conditions needs to be applied by the external world through input pins. After power-on reset or hardware reset, the pins MBC, TMS and P0.0 collectively select the different boot options. Table 25 shows the available boot options in the XC878.

Table 25 XC878 Boot Selection

MBC TMS P0.0 Type of Mode PC Start Value

1 0 X User Mode

0 0 X BSL Mode; (LIN Mode3), UART/ MultiCAN

Mode

; on-chip OSC/PLL non-bypassed

4)5)

and Alternate BSL Mode6)); on-chip

0000

OSC/PLL non-bypassed

0 1 0 OCDS Mode; on-chip OSC/PLL non-

0000

bypassed

1 1 0 User (JTAG) Mode7); on-chip OSC/PLL non-

0000

bypassed (normal)

1) In addition to the pins MBC, TMS and P0.0, TM pin also requires an external pull down for all the boot options.

2) BSL mode is automatically entered if no valid password is installed and data at memory address 0000H equals zero.

3) If a device is programmed as LIN, LIN BSL is always used instead of UART/MultiCAN.

4) UART or MultiCAN BSL is decoded by firmware based on the protocol for product variant with MultiCAN. If no MultiCAN and LIN variant, UART BSL is used.

5) In MultiCAN BSL mode, the clock source is switched to XTAL by firmware, bypassing the on-chip oscillator. This avoids any frequency invariance with the on-chip oscillator and allows other frequency clock input, thus ensuring accurate baud rate detection (especially at high bit rates).

6) Alternate BSL Mode is a user defined BSL code programmed in Flash. It is entered if the AltBSLPassword is valid.

7) Normal user mode with standard JTAG (TCK,TDI,TDO) pins for hot-attach purpose.

Note: The boot options are valid only with the default set of UART and JTAG pins.

Data Sheet 72 V1.2, 2009-11

XC878CLM

Functional Description

3.8 Clock Generation Unit

The Clock Generation Unit (CGU) allows great flexibility in the clock generation for the XC878. The power consumption is indirectly proportional to the frequency, whereas the performance of the microcontroller is directly proportional to the frequency. During user program execution, the frequency can be programmed for an optimal ratio between performance and power consumption. Therefore the power consumption can be adapted to the actual application state.

Features

• Phase-Locked Loop (PLL) for multiplying clock source by different factors

•PLL Base Mode

• Prescaler Mode

•PLL Mode

• Power-down mode support

The CGU consists of an oscillator circuit and a PLL. In the XC878, the oscillator can be from either of these two sources: the on-chip oscillator (4 MHz) or the external oscillator (2 MHz to 20 MHz). The term “oscillator” is used to refer to both on-chip oscillator and external oscillator, unless otherwise stated. After the reset, the on-chip oscillator will be used by default.The external oscillator can be selected via software. In addition, the PLL provides a fail-safe logic to perform oscillator run and loss-of-lock detection. This allows emergency routines to be executed for system recovery or to perform system shut down.

Data Sheet 73 V1.2, 2009-11

PLL_LOCK

XC878CLM

Functional Description

Wrapper

PLL

OSC

fosc

OSCSS

Figure 19 CGU Block Diagram

NR:1

PLLPD

lock

detect

PLL

core

NF:1

NDIV

fvco

OD:1

External

oscillator

watchdog

Switching

circuitry

PLLBYPKDIVPDIV

PLL

watchdog

EXTOSCR

SYS

PLLR

Direct Drive (PLL Bypass Operation)

During PLL bypass operation, the system clock has the same frequency as the external clock source.

(3.1)

ff =

OSCSYS

PLL Mode

The CPU clock is derived from the oscillator clock, divided by the NR factor (PDIV), multiplied by the NF factor (NDIV), and divided by the OD factor (KDIV). PLL output must

Data Sheet 74 V1.2, 2009-11

XC878CLM

Functional Description

not be bypassed for this PLL mode. The PLL mode is used during normal system operation.

(3.2)

System Frequency Selection

For the XC878, the value of NF, NR and OD can be selected by bits NDIV, PDIV and KDIV respectively for different oscillator inputs inorder to obtain the required fsys. But the combination of these factors must fulfill the following condition:

xff

OSCSYS

OD x NR

• 100 MHz < f

• 800 KHz < f

<175MHz

VCO

/ (2 * NR) < 8 MHz

OSC

Table 26 provides examples on how the typical system frequency of fsys = 144 MHz

and maximum frequency of 160 MHz (CPU clock = 26.67 MHz)can be obtained for the different oscillator sources.

Table 26 System frequency (

=144MHz)

sys

Oscillator fosc N P K fsys

On-chip 4 MHz 72 2 1 144 MHz

4 MHz 80 2 1 160 MHz

External 8 MHz 72 4 1 144 MHz

6 MHz 72 3 1 144 MHz

4 MHz 72 2 1 144 MHz

3.8.1 Recommended External Oscillator Circuits

The oscillator circuit, a Pierce oscillator, is designed to work with both, an external crystal oscillator or an external stable clock source. It basically consists of an inverting amplifier and a feedback element with XTAL1 as input, and XTAL2 as output.

When using a crystal, a proper external oscillator circuitry must be connected to both pins, XTAL1 and XTAL2. The crystal frequency can be within the range of 2 MHz to

20 MHz. Additionally, it is necessary to have two load capacitances

depending on the crystal type, a series resistor

, to limit the current. A test resistor R

and CX2, and

may be temporarily inserted to measure the oscillation allowance (negative resistance)

of the oscillator circuitry. external feedback resistor

values are typically specified by the crystal vendor. An

is also required in the external oscillator circuitry. The exact

values and related operating range are dependent on the crystal frequency and have to be determined and optimized together with the crystal vendor using the negative

Data Sheet 75 V1.2, 2009-11

XC878CLM

Functional Description

resistance method. Oscillation measurement with the final target system is strongly recommended to verify the input amplitude at XTAL1 and to determine the actual oscillation allowance (margin negative resistance) for the oscillator-crystal system.

When using an external clock signal, the signal must be connected to XTAL1. XTAL2 is left open (unconnected).

The oscillator can also be used in combination with a ceramic resonator. The final circuitry must also be verified by the resonator vendor. Figure 20 shows the recommended external oscillator circuitries for both operating modes, external crystal mode and external input clock mode.

2 - 20

MHz

Fundamental Mode Cryst al

XTAL1

OSC

XC878

Oscillator

XTAL2

External Clock Signal

XTAL1

XC878

Oscillator

XTAL2

OSC

Figure 20 External Oscillator Circuitry

Note: For crystal operation, it is strongly recommended to measure the negative

resistance in the final target system (layout) to determine the optimum parameters for the oscillator operation. Please refer to the minimum and maximum values of the negative resistance specified by the crystal supplier.

Data Sheet 76 V1.2, 2009-11

XC878CLM

Functional Description

3.8.2 Clock Management

The CGU generates all clock signals required within the microcontroller from a single

clock, modules are as follow:

• CPU clock: CCLK, SCLK = 24 MHz

• MultiCAN clock : MCANCLK = 24 or 48 MHz

• MDU clock : MDUCLK = 24 or 48 MHz

• CORDIC clock : CORDICCLK = 24 or 48 MHz

• CCU6 clock : CCU6CLK = 24 or 48 MHz

• T2CCU clock : T2CCUCLK = 24 or 48 MHz

• Peripheral clock: PCLK = 24 MHz

In addition, different clock frequencies can be output to pin CLKOUT (P0.0 or P0.7). The clock output frequency, which is derived from the clock output divider (bit COREL), can further be divided by 2 using toggle latch (bit TLEN is set to 1). The resulting output frequency has a 50% duty cycle. Figure 21 shows the clock distribution of the XC878.

. During normal system operation, the typical frequencies of the different

sys

Data Sheet 77 V1.2, 2009-11

CCCFG

MDUCCFG

CLKREL

CORDIC

CLK

MDU

CLK

CORDIC

MDU

Functional Description

T2CCFG

CCUCCFG

FCCFG

XC878CLM

T2CCU

CLK

CCU6

CLK

MCAN

CLK

T2CCU

CCU6

MultiCAN

Exter nal

OSC

On-chip

OSC

fosc

PLL

fsys

NF,NR,OD

Figure 21 Clock Generation from f

COREL

sys

FCLKOSCS S

TLEN

Toggle

Latch

PCLK

SCLK

CCLK

COUTS

Peripherals

CORE

CLKOUT

Data Sheet 78 V1.2, 2009-11

XC878CLM

Functional Description

For power saving purposes, the clocks may be disabled or slowed down according to

Table 27.

Table 27 System frequency (

=144MHz)

sys

Power Saving Mode Action

Idle Clock to the CPU is disabled.

Slow-down Clocks to the CPU and all the peripherals are divided by a

common programmable factor defined by bit field CMCON.CLKREL.

Power-down Oscillator and PLL are switched off.

Data Sheet 79 V1.2, 2009-11

XC878CLM

Functional Description

3.9 Power Saving Modes

The power saving modes of the XC878 provide flexible power consumption through a combination of techniques, including:

• Stopping the CPU clock

• Stopping the clocks of individual system components

• Reducing clock speed of some peripheral components

• Power-down of the entire system with fast restart capability

After a reset, the active mode (normal operating mode) is selected by default (see

Figure 22) and the system runs in the main system clock frequency. From active mode,

different power saving modes can be selected by software. They are:

• Idle mode

• Slow-down mode

• Power-down mode

any interrupt

& SD=0

set IDLE

bit

IDLE

set IDLE

bit

any interrupt

& SD=1

ACTIVE

set SD

bit

SLOW-DOWN

clear SD

bit

Figure 22 Transition between Power Saving Modes

EXINT0/RXD pin

& SD=0

set PD

bit

POWER- DOWN

set PD

bit

EXINT0/RXD pin

& SD=1

Data Sheet 80 V1.2, 2009-11

XC878CLM

Functional Description

3.10 Watchdog Timer

The Watchdog Timer (WDT) provides a highly reliable and secure way to detect and recover from software or hardware failures. The WDT is reset at a regular interval that is predefined by the user. The CPU must service the WDT within this interval to prevent the WDT from causing an XC878 system reset. Hence, routine service of the WDT confirms that the system is functioning properly. This ensures that an accidental malfunction of the XC878 will be aborted in a user-specified time period.

In debug mode, the WDT is default suspended and stops counting. Therefore, there is no need to refresh the WDT during debugging.

Features

• 16-bit Watchdog Timer

• Programmable reload value for upper 8 bits of timer

• Programmable window boundary

• Selectable input frequency of

PCLK

/2 or f

• Time-out detection with NMI generation and reset prewarning activation (after which

a system reset will be performed)

PCLK

/128

The WDT is a 16-bit timer incremented by a count rate of f

PCLK

/2 or f

/128. This 16-bit

PCLK

timer is realized as two concatenated 8-bit timers. The upper 8 bits of the WDT can be preset to a user-programmable value via a watchdog service access in order to modify the watchdog expire time period. The lower 8 bits are reset on each service access.

Figure 23 shows the block diagram of the WDT unit.

ENW DT

ENW DT_P

PCLK

Logic

1:2

1:128

MUX

WDTIN

WDT

Cont rol

Clear

WDT Low Byte

Overflow/Time-out Control &

Window -boundary cont rol

WDTREL

WDT High Byte

WDTWI NB

FNMIWDT

WDTRST

Figure 23 WDT Block Diagram

Data Sheet 81 V1.2, 2009-11

XC878CLM

Functional Description

If the WDT is not serviced before the timer overflow, a system malfunction is assumed. As a result, the WDT NMI is triggered (assert FNMIWDT) and the reset prewarning is entered. The prewarning period lasts for 30 (assert WDTRST).

The WDT has a “programmable window boundary” which disallows any refresh during the WDT’s count-up. A refresh during this window boundary constitutes an invalid access to the WDT, causing the reset prewarning to be entered but without triggering the WDT NMI. The system will still be reset after the prewarning period is over. The window boundary is from 0000

to the value obtained from the concatenation of WDTWINB and

After being serviced, the WDT continues counting up from the value (<WDTREL> * 2 The time period for an overflow of the WDT is programmable in two ways:

count, after which the system is reset

• The input frequency to the WDT can be selected to be either

PCLK

/2 or f

PCLK

/128

• The reload value WDTREL for the high byte of WDT can be programmed in register

WDTREL

The period, P

, between servicing the WDT and the next overflow can be determined

WDT

by the following formula:

WDT

1WDTIN+ 6×()

------------------------------------------------------------------------------------------------------=

PCLK

WDTREL– 2

×()×

(3.3)

If the Window-Boundary Refresh feature of the WDT is enabled, the period

WDT

between servicing the WDT and the next overflow is shortened if WDTWINB is greater than WDTREL, see Figure 24. This period can be calculated using the same formula by replacing WDTREL with WDTWINB. For this feature to be useful, WDTWINB cannot be smaller than WDTREL.

Data Sheet 82 V1.2, 2009-11

Count

FFFF

WDTWINB

WDTREL

No refresh

allowed

Figure 24 WDT Timing Diagram

XC878CLM

Functional Description

time

Refresh allowed

Table 28 lists the possible watchdog time ranges that can be achieved using a certain

module clock. Some numbers are rounded to 3 significant digits.

Table 28 Watchdog Time Ranges

Reload value In WDTREL

Prescaler for

2 (WDTIN = 0) 128 (WDTIN = 1)

PCLK

24 MHz 24 MHz

21.3 µs1.37 ms

2.75 ms 176 ms

5.46 ms 350 ms

Data Sheet 83 V1.2, 2009-11

XC878CLM

Functional Description

3.11 Multiplication/Division Unit

The Multiplication/Division Unit (MDU) provides fast 16-bit multiplication, 16-bit and 32-bit division as well as shift and normalize features. It has been integrated to support the XC878 Core in real-time control applications, which require fast mathematical computations.

Features

• Fast signed/unsigned 16-bit multiplication

• Fast signed/unsigned 32-bit divide by 16-bit and 16-bit divide by 16-bit operations

• 32-bit unsigned normalize operation

• 32-bit arithmetic/logical shift operations

Table 29 specifies the number of clock cycles used for calculation in various operations.

Table 29 MDU Operation Characteristics

Operation Result Remainder No. of Clock Cycles

used for calculation

Signed 32-bit/16-bit 32-bit 16-bit 33

Signed 16-bit/16bit 16-bit 16-bit 17

Signed 16-bit x 16-bit 32-bit - 16

Unsigned 32-bit/16-bit 32-bit 16-bit 32

Unsigned 16-bit/16-bit 16-bit 16-bit 16

Unsigned 16-bit x 16-bit 32-bit - 16

32-bit normalize - - No. of shifts + 1 (Max. 32)

32-bit shift L/R - - No. of shifts + 1 (Max. 32)

Data Sheet 84 V1.2, 2009-11

XC878CLM

Functional Description

3.12 CORDIC Coprocessor

The CORDIC Coprocessor provides CPU with hardware support for the solving of circular (trigonometric), linear (multiply-add, divide-add) and hyperbolic functions.

Features

• Modes of operation

– Supports all CORDIC operating modes for solving circular (trigonometric), linear

(multiply-add, divide-add) and hyperbolic functions

– Integrated look-up tables (LUTs) for all operating modes

• Circular vectoring mode: Extended support for values of initial X and Y data up to full

range of [-2

• Circular rotation mode: Extended support for values of initial Z data up to full range

of [-2

,(215-1)], representing angles in the range [-π,((215-1)/215)π] for solving

trigonometry

• Implementation-dependent operational frequency of up to 80 MHz

• Gated clock input to support disabling of module

• 16-bit accessible data width

– 24-bit kernel data width plus 2 overflow bits for X and Y each – 20-bit kernel data width plus 1 overflow bit for Z – With KEEP bit to retain the last value in the kernel register for a new calculation

• 16 iterations per calculation: Approximately 41 clock-cycles or less, from set of start

(ST) bit to set of end-of-calculation flag, excluding time taken for write and read access of data bytes.

• Twos complement data processing

– Only exception: X result data with user selectable option for unsigned result

• X and Y data generally accepted as integer or rational number; X and Y must be of

the same data form

• Entries of LUTs are 20-bit signed integers

– Entries of atan and atanh LUTs are integer representations (S19) of angles with

the scaling such that [-2

– Accessible Z result data for circular and hyperbolic functions is integer in data form

of S15

• Emulated LUT for linear function

– Data form is 1 integer bit and 15-bit fractional part (1.15) – Accessible Z result data for linear function is rational number with fixed data form

of S4.11 (signed 4Q16)

• Truncation Error

– The result of a CORDIC calculation may return an approximation due to truncation

of LSBs

– Good accuracy of the CORDIC calculated result data, especially in circular mode

• Interrupt

– On completion of a calculation

,(215-1)] for solving angle and magnitude

,(215-1)] represents the range [-π,((215-1)/215)π]

Data Sheet 85 V1.2, 2009-11

XC878CLM

Functional Description

– Interrupt enabling and corresponding flag

3.13 UART and UART1

The XC878 provides two Universal Asynchronous Receiver/Transmitter (UART and UART1) modules for full-duplex asynchronous reception/transmission. Both are also receive-buffered, i.e., they can commence reception of a second byte before a previously received byte has been read from the receive register. However, if the first byte still has not been read by the time reception of the second byte is complete, one of the bytes will be lost.

Features

• Full-duplex asynchronous modes

– 8-bit or 9-bit data frames, LSB first – Fixed or variable baud rate

• Receive buffered

• Multiprocessor communication

• Interrupt generation on the completion of a data transmission or reception

The UART modules can operate in the four modes shown in Table 30.

Table 30 UART Modes

Operating Mode Baud Rate

Mode 0: 8-bit shift register

PCLK

Mode 1: 8-bit shift UART Variable

Mode 2: 9-bit shift UART

PCLK

/32 or f

PCLK

/64

Mode 3: 9-bit shift UART Variable

1) For UART1 module, the baud rate is fixed at f

PCLK

/64.

There are several ways to generate the baud rate clock for the serial port, depending on the mode in which it is operating. In mode 0, the baud rate for the transfer is fixed at

/2. In mode 2, the baud rate is generated internally based on the UART input clock

PCLK

and can be configured to either

PCLK

/32 or f

/64. For UART1 module, only f

PCLK

/64 is available. The variable baud rate is set by the underflow rate on the dedicated baud-rate generator. For UART module, the variable baud rate alternatively can be set by the overflow rate on Timer 1.

3.13.1 Baud-Rate Generator

Both UART modules have their own dedicated baud-rate generator, which is based on a programmable 8-bit reload value, and includes divider stages (i.e., prescaler and

Data Sheet 86 V1.2, 2009-11

XC878CLM

Functional Description

fractional divider) for generating a wide range of baud rates based on its input clock f see Figure 25.

Fract ional Divider

8-Bit Reload Value

8-Bit Baud Rate Ti mer

NDOV

PCL K

Prescaler

FDM

FDEN

FDSTEP

DIV

0 (overflow)

FDEN&F DM

0 1

Adder

FDRES

DIV

clk

MOD

‘0’

PCLK

Figure 25 Baud-rate Generator Circuitry

The baud rate timer is a count-down timer and is clocked by either the output of the

fractional divider ( output of the prescaler (

) if the fractional divider is enabled (FDCON.FDEN = 1), or the

MOD

) if the fractional divider is disabled (FDEN = 0). For baud rate

DIV

generation, the fractional divider must be configured to fractional divider mode (FDCON.FDM = 0). This allows the baud rate control run bit BCON.R to be used to start or stop the baud rate timer. At each timer underflow, the timer is reloaded with the 8-bit reload value in register BG and one clock pulse is generated for the serial channel.

Enabling the fractional divider in normal divider mode (FDEN = 1 and FDM = 1) stops the baud rate timer and nullifies the effect of bit BCON.R. See Section 3.14.

The baud rate (

• Input clock

• Prescaling factor (2

) value is dependent on the following parameters:

PCLK

BRPRE

) defined by bit field BRPRE in register BCON

• Fractional divider (STEP/256) defined by register FDSTEP

(to be considered only if fractional divider is enabled and operating in fractional divider mode)

• 8-bit reload value (BR_VALUE) for the baud rate timer defined by register BG

Data Sheet 87 V1.2, 2009-11

XC878CLM

Functional Description

The following formulas calculate the final baud rate without and with the fractional divider respectively:

baud rate

-----------------------------------------------------------------------------------

16 2

BRPRE

PCLK

BR_VALUE 1+()××

where 2

BRPRE

BR_VALUE 1+()1>×=

(3.4)

baud rate

-----------------------------------------------------------------------------------

16 2

BRPRE

PCLK

BR_VALUE 1+()××

STEP

-------------- -

×=

256

(3.5)

The maximum baud rate that can be generated is limited to

/32. Hence, for a module

PCLK

clock of 24 MHz, the maximum achievable baud rate is 0.75 MBaud.

Standard LIN protocol can support a maximum baud rate of 20 kHz, the baud rate accuracy is not critical and the fractional divider can be disabled. Only the prescaler is used for auto baud rate calculation. For LIN fast mode, which supports the baud rate of 20 kHz to 57.6 kHz, the higher baud rates require the use of the fractional divider for greater accuracy.

Table 31 lists the various commonly used baud rates with their corresponding parameter

settings and deviation errors. The fractional divider is disabled and a module clock of 24 MHz is used.

Table 31 Typical Baud rates for UART with Fractional Divider disabled

Baud rate Prescaling Factor

(2BRPRE)

19.2 kBaud 1 (BRPRE=000

9600 Baud 1 (BRPRE=000

4800 Baud 2 (BRPRE=001

2400 Baud 4 (BRPRE=010

) 78 (4E

) 156 (9CH)0.17%

Reload Value (BR_VALUE + 1)

)0.17%

Deviation Error

The fractional divider allows baud rates of higher accuracy (lower deviation error) to be generated. Table 32 lists the resulting deviation errors from generating a baud rate of

57.6 kHz, using different module clock frequencies. The fractional divider is enabled (fractional divider mode) and the corresponding parameter settings are shown.

Data Sheet 88 V1.2, 2009-11

Functional Description

Table 32 Deviation Error for UART with Fractional Divider enabled

XC878CLM

PCLK

24 MHz 1 6 (6

12 MHz 1 3 (3

8MHz 1 2 (2

6MHz 1 6 (6

Prescaling Factor (2BRPRE)

Reload Value

STEP Deviation

(BR_VALUE + 1)

) 59 (3BH) +0.03 %

) 236 (ECH) +0.03 %

Error

3.13.2 Baud Rate Generation using Timer 1

In UART modes 1 and 3 of UART module, Timer 1 can be used for generating the variable baud rates. In theory, this timer could be used in any of its modes. But in practice, it should be set into auto-reload mode (Timer 1 mode 2), with its high byte set to the appropriate value for the required baud rate. The baud rate is determined by the Timer 1 overflow rate and the value of SMOD as follows:

Mode 1, 3 baud rate

---------------------------------------------------- -=

32 2 256 TH1–()××

SMOD

PCLK

(3.6)

3.14 Normal Divider Mode (8-bit Auto-reload Timer)

Setting bit FDM in register FDCON to 1 configures the fractional divider to normal divider mode, while at the same time disables baud rate generation (see Figure 25). Once the fractional divider is enabled (FDEN = 1), it functions as an 8-bit auto-reload timer (with no relation to baud rate generation) and counts up from the reload value with each input clock pulse. Bit field RESULT in register FDRES represents the timer value, while bit field STEP in register FDSTEP defines the reload value. At each timer overflow, an overflow flag (FDCON.NDOV) will be set and an interrupt request generated. This gives an output clock f

that is 1/n of the input clock f

MOD

The output frequency in normal divider mode is derived as follows:

×=

MOD

DIV

, where n is defined by 256 - STEP.

DIV

----------------------------- 256 STEP–

(3.7)

Data Sheet 89 V1.2, 2009-11

XC878CLM

Functional Description

3.15 LIN Protocol

The UART module can be used to support the Local Interconnect Network (LIN) protocol for both master and slave operations. The LIN baud rate detection feature, which consists of the hardware logic for Break and Synch Byte detection, provides the capability to detect the baud rate within LIN protocol using Timer 2. This allows the UART to be synchronized to the LIN baud rate for data transmission and reception.

Note: The LIN baud rate detection feature is available for use only with UART. To use

UART1 for LIN communication, software has to be implemented to detect the Break and Synch Byte.

LIN is a holistic communication concept for local interconnected networks in vehicles. The communication is based on the SCI (UART) data format, a single-master/multipleslave concept, a clock synchronization for nodes without stabilized time base. An attractive feature of LIN is self-synchronization of the slave nodes without a crystal or ceramic resonator, which significantly reduces the cost of hardware platform. Hence, the baud rate must be calculated and returned with every message frame.

The structure of a LIN frame is shown in Figure 26. The frame consists of the:

• Header, which comprises a Break (13-bit time low), Synch Byte (55

), and ID field

• Response time

• Data bytes (according to UART protocol)

• Checksum

Frame slot

Frame

Response

Header

Synch

Protected

identifier

space

Da ta 1

Response

Da ta 2 Data N

Checksum

Figure 26 Structure of LIN Frame

3.15.1 LIN Header Transmission

LIN header transmission is only applicable in master mode. In the LIN communication, a master task decides when and which frame is to be transferred on the bus. It also identifies a slave task to provide the data transported by each frame. The information

Data Sheet 90 V1.2, 2009-11

XC878CLM

Functional Description

needed for the handshaking between the master and slave tasks is provided by the master task through the header portion of the frame.

The header consists of a break and synch pattern followed by an identifier. Among these three fields, only the break pattern cannot be transmitted as a normal 8-bit UART data. The break must contain a dominant value of 13 bits or more to ensure proper synchronization of slave nodes.

In the LIN communication, a slave task is required to be synchronized at the beginning of the protected identifier field of frame. For this purpose, every frame starts with a sequence consisting of a break field followed by a synch byte field. This sequence is unique and provides enough information for any slave task to detect the beginning of a new frame and be synchronized at the start of the identifier field.

Upon entering LIN communication, a connection is established and the transfer speed (baud rate) of the serial communication partner (host) is automatically synchronized in the following steps:

STEP 1: Initialize interface for reception and timer for baud rate measurement

STEP 2: Wait for an incoming LIN frame from host

STEP 3: Synchronize the baud rate to the host

STEP 4: Enter for Master Request Frame or for Slave Response Frame

Note: Re-synchronization and setup of baud rate are always done for every Master

Request Header or Slave Response Header LIN frame.

Data Sheet 91 V1.2, 2009-11

INFINEON XC878CLM User Manual

Specifications and Main Features

Frequently Asked Questions

User Manual

1 Summary of Features

2 General Device Information

2.1 Block Diagram

2.2 Logic Symbol

2.3 Pin Configuration

2.4 Pin Definitions and Functions

3 Functional Description

3.1 Processor Architecture

3.2 Memory Organization

3.2.1 Memory Protection Strategy

3.2.1.1 Flash Memory Protection

3.2.2 Special Function Register

3.2.2.1 Address Extension by Mapping

3.2.2.2 Address Extension by Paging

3.2.3 Bit Protection Scheme

3.2.3.1 Password Register

3.2.4 XC878 Register Overview

3.2.4.1 CPU Registers

3.2.4.2 MDU Registers

3.2.4.3 CORDIC Registers

3.2.4.4 System Control Registers

3.2.4.5 WDT Registers

3.2.4.6 Port Registers

3.2.4.7 ADC Registers

3.2.4.8 Timer 2 Compare/Capture Unit Registers

3.2.4.9 Timer 21 Registers

3.2.4.10 CCU6 Registers

3.2.4.11 UART1 Registers

3.2.4.12 SSC Registers

3.2.4.13 MultiCAN Registers

3.2.4.14 OCDS Registers

3.2.4.15 Flash Registers

3.3 Flash Memory

3.3.1 Flash Bank Pagination

3.4 Interrupt System

3.4.1 Interrupt Source

3.4.2 Interrupt Source and Vector

3.4.3 Interrupt Priority

3.5 Parallel Ports

3.6 Power Supply System with Embedded Voltage Regulator

3.7 Reset Control

3.7.1 Module Reset Behavior

3.7.2 Booting Scheme

3.8 Clock Generation Unit

3.8.1 Recommended External Oscillator Circuits

3.8.2 Clock Management

3.9 Power Saving Modes

3.10 Watchdog Timer

3.11 Multiplication/Division Unit

3.12 CORDIC Coprocessor

3.13 UART and UART1

3.13.1 Baud-Rate Generator

3.13.2 Baud Rate Generation using Timer 1

3.14 Normal Divider Mode (8-bit Auto-reload Timer)

3.15 LIN Protocol

3.15.1 LIN Header Transmission