INFINEON XC878CLM User Manual

8-Bit

XC878CLM

8-Bit Single-Chip Microcontroller

Data Sheet

V1.2 2009-11

Microcontrollers

Edition 2009-11

Published by
Infineon Technologies AG
81726 Munich, Germany

© 2009 Infineon Technologies AG

All Rights Reserved.

Legal Disclaimer

The information given in this document shall in no event be regarded as a guarantee of conditions or
characteristics. With respect to any examples or hints given herein, any typical values stated herein and/or any
information regarding the application of the device, Infineon Technologies hereby disclaims any and all warranties
and liabilities of any kind, including without limitation, warranties of non-infringement of intellectual property rights
of any third party.

Information

For further information on technology, delivery terms and conditions and prices, please contact the nearest
Infineon Technologies Office (www.infineon.com).

Warnings

Due to technical requirements, components may contain dangerous substances. For information on the types in
question, please contact the nearest Infineon Technologies Office.

Infineon Technologies components may be used in life-support devices or systems only with the express written
approval of Infineon Technologies, if a failure of such components can reasonably be expected to cause the failure
of that life-support device or system or to affect the safety or effectiveness of that device or system. Life support
devices or systems are intended to be implanted in the human body or to support and/or maintain and sustain
and/or protect human life. If they fail, it is reasonable to assume that the health of the user or other persons may
be endangered.

8-Bit

XC878CLM

8-Bit Single-Chip Microcontroller

Data Sheet

V1.2 2009-11

Microcontrollers

XC878CLM

XC878
Revision History: 2009-11 V1.2

Previous Version: V1.1

Page Subjects (major changes since last revision)

Changes from V1.1 2009-08 to V1.2 2009-10

3 Table 1 and Table 2 has been updated to include the variants for the

Automotive profile.

57 Table 21 has been added to show the Flash data retention and

endurance for Automotive profile.

106 Table 37 has been updated to show the Chip Identification number for the

new Automotive variants.

We Listen to Your Comments

Any information within this document that you feel is wrong, unclear or missing at all?
Your feedback will help us to continuously improve the quality of this document.
Please send your proposal (including a reference to this document) to:

[e-mail]

Data Sheet V1.2, 2009-11

XC878CLM

Data Sheet V1.2, 2009-11

XC878CLM

Table of Contents

Table of Contents

1 Summary of Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1

2 General Device Information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5

2.1 Block Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5

2.2 Logic Symbol . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6

2.3 Pin Configuration . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7

2.4 Pin Definitions and Functions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8

3 Functional Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19

3.1 Processor Architecture . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19

3.2 Memory Organization . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20

3.2.1 Memory Protection Strategy . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22

3.2.1.1 Flash Memory Protection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22

3.2.2 Special Function Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24

3.2.2.1 Address Extension by Mapping . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24

3.2.2.2 Address Extension by Paging . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26

3.2.3 Bit Protection Scheme . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 30

3.2.3.1 Password Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 31

3.2.4 XC878 Register Overview . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 32

3.2.4.1 CPU Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 32

3.2.4.2 MDU Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 33

3.2.4.3 CORDIC Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 34

3.2.4.4 System Control Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 35

3.2.4.5 WDT Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 38

3.2.4.6 Port Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 38

3.2.4.7 ADC Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 41

3.2.4.8 Timer 2 Compare/Capture Unit Registers . . . . . . . . . . . . . . . . . . . . . 45

3.2.4.9 Timer 21 Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 47

3.2.4.10 CCU6 Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 48

3.2.4.11 UART1 Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 52

3.2.4.12 SSC Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 52

3.2.4.13 MultiCAN Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 53

3.2.4.14 OCDS Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 53

3.2.4.15 Flash Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 55

3.3 Flash Memory . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 56

3.3.1 Flash Bank Pagination . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 58

3.4 Interrupt System . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 59

3.4.1 Interrupt Source . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 59

3.4.2 Interrupt Source and Vector . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 65

3.4.3 Interrupt Priority . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 67

3.5 Parallel Ports . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 68

3.6 Power Supply System with Embedded Voltage Regulator . . . . . . . . . . . . 70

Data Sheet I-1 V1.2, 2009-11

XC878CLM

Table of Contents

3.7 Reset Control . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 71

3.7.1 Module Reset Behavior . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 71

3.7.2 Booting Scheme . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 72

3.8 Clock Generation Unit . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 73

3.8.1 Recommended External Oscillator Circuits . . . . . . . . . . . . . . . . . . . . . . 75

3.8.2 Clock Management . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 77

3.9 Power Saving Modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 80

3.10 Watchdog Timer . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 81

3.11 Multiplication/Division Unit . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 84

3.12 CORDIC Coprocessor . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 85

3.13 UART and UART1 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 86

3.13.1 Baud-Rate Generator . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 86

3.13.2 Baud Rate Generation using Timer 1 . . . . . . . . . . . . . . . . . . . . . . . . . . 89

3.14 Normal Divider Mode (8-bit Auto-reload Timer) . . . . . . . . . . . . . . . . . . . . . 89

3.15 LIN Protocol . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 90

3.15.1 LIN Header Transmission . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 90

3.16 High-Speed Synchronous Serial Interface . . . . . . . . . . . . . . . . . . . . . . . . . 92

3.17 Timer 0 and Timer 1 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 94

3.18 Timer 2 and Timer 21 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 95

3.19 Timer 2 Capture/Compare Unit . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 96

3.20 Capture/Compare Unit 6 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 97

3.21 Controller Area Network (MultiCAN) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 99

3.22 Analog-to-Digital Converter . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 101

3.22.1 ADC Clocking Scheme . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 101

3.22.2 ADC Conversion Sequence . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 102

3.23 On-Chip Debug Support . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 104

3.23.1 JTAG ID Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 105

3.24 Chip Identification Number . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 106

4 Electrical Parameters . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 108

4.1 General Parameters . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 108

4.1.1 Parameter Interpretation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 108

4.1.2 Absolute Maximum Rating . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 109

4.1.3 Operating Conditions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 110

4.2 DC Parameters . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 111

4.2.1 Input/Output Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 111

4.2.2 Supply Threshold Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . 114

4.2.3 ADC Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 115

4.2.3.1 ADC Conversion Timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 118

4.2.4 Power Supply Current . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 119

4.3 AC Parameters . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 123

4.3.1 Testing Waveforms . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 123

4.3.2 Output Rise/Fall Times . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 124

Data Sheet I-2 V1.2, 2009-11

XC878CLM

Table of Contents

4.3.3 Power-on Reset and PLL Timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 125

4.3.4 On-Chip Oscillator Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . 126

4.3.5 External Data Memory Characteristics . . . . . . . . . . . . . . . . . . . . . . . . 127

4.3.6 External Clock Drive XTAL1 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 129

4.3.7 JTAG Timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 130

4.3.8 SSC Master Mode Timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 132

5 Package and Quality Declaration . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 133

5.1 Package Parameters . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 133

5.2 Package Outline . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 134

5.3 Quality Declaration . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 135

Data Sheet I-3 V1.2, 2009-11

XC878CLM

Table of Contents

Data Sheet I-4 V1.2, 2009-11

XC878CLM8-Bit Single-Chip Microcontroller

1 Summary of Features

The XC878 has the following features:

• High-performance XC800 Core
– compatible with standard 8051 processor
– two clocks per machine cycle architecture (for memory access without wait state)
– two data pointers

• On-chip memory
– 8 Kbytes of Boot ROM
– 256 bytes of RAM
– 3 Kbytes of XRAM
– 64/52 Kbytes of Flash;

(includes memory protection strategy)

• I/O port supply at 3.3 V or 5.0 V and core logic supply at 2.5 V (generated by
embedded voltage regulator)

(more features on next page)

52K/64K x 8

Boot ROM

8K x 8

XRAM
3K x 8

RAM

256 x 8

Flash

Timer 0

16-bit

On-Chip Debug Support

XC800 Core

Timer 1

16-bit

Timer 21

16-bit

Watchdog

Timer

UART

Capture/Compare Unit

Compare Unit

Timer 2 Capture/

Compare Unit

UART1

SSC

16-bit

16-bit

16-bit

ADC

10-bit

8-channel

8-bit Analog Input

Port 0

Port 1

Port 3

Port 4

Port 5MDU CORDIC Multi CAN

8-bi t D i gital I/O

8-bi t D i gital I/O

.

8-bi t D i gital I/O

8-bi t D i gital I/O

8-bi t Digi tal I/O

Figure 1 XC878 Functional Units

Data Sheet 1 V1.2, 2009-11

XC878CLM

Summary of Features

Features: (continued)

• Power-on reset generation

• Brownout detection for core logic supply

• On-chip OSC and PLL for clock generation
– Loss-of-Clock detection

• Power saving modes
– slow-down mode
– idle mode
– power-down mode with wake-up capability via RXD or EXINT0
– clock gating control to each peripheral

• Programmable 16-bit Watchdog Timer (WDT)

• Five ports
– Up to 40 pins as digital I/O
– 8 dedicated analog inputs used as A/D converter input

• 8-channel, 10-bit ADC

• Four 16-bit timers
– Timer 0 and Timer 1 (T0 and T1)
– Timer 2 and Timer 21 (T2 and T21)

• Multiplication/Division Unit for arithmetic operations (MDU)

• CORDIC Coprocessor for computation of trigonometric, hyperbolic and linear
functions

• MultiCAN with 2 nodes, 32 message objects

• Two Capture/compare units
– Capture/compare unit 6 for PWM signal generation (CCU6)
– Timer 2 Capture/compare unit for vaious digital signal generation (T2CCU)

• Two full-duplex serial interfaces (UART and UART1)

• Synchronous serial channel (SSC)

• On-chip debug support
– 1 Kbyte of monitor ROM (part of the 8-Kbyte Boot ROM)
– 64 bytes of monitor RAM

• PG-LQFP-64 pin package

• Temperature range T
– SAF (-40 to 85 °C)
– SAX (-40 to 105 °C)

:

A

Data Sheet 2 V1.2, 2009-11

XC878CLM

Summary of Features

XC878 Variant Devices

The XC878 product family features devices with different configurations, program
memory sizes, power supply voltage, temperature and quality profiles (Automotive or
Industrial), to offer cost-effective solutions for different application requirements.

The list of XC878 device configurations are summarized in Table 1. The type of package
available is the LQFP-64.

Table 1 Device Configuration

Device Name CAN

Module

LIN BSL
Support

MDU
Module

XC878 NoNoNo

XC878M No No Yes

XC878CM Yes No Yes

XC878LM No Yes Yes

XC878CLM Yes Yes Yes

From these 5 different combinations of configuration, each are further made available in
many sales types, which are grouped according to device type, program memory sizes,
power supply voltage, temperature and quality profiles (Automotive or Industrial), as
shown in Table 2.

Table 2 Device Profile

Sales Type Device

Type

Program
Memory
(Kbytes)

Power
Supply
(V)

Temp­erature
(°C)

Quality
Profile

SAF-XC878-13FFI 5V Flash 52 5.0 -40 to 85 Industrial

SAF-XC878M-13FFI 5V Flash 52 5.0 -40 to 85 Industrial

SAF-XC878CM-13FFI 5V Flash 52 5.0 -40 to 85 Industrial

SAF-XC878-16FFI 5V Flash 64 5.0 -40 to 85 Industrial

SAF-XC878M-16FFI 5V Flash 64 5.0 -40 to 85 Industrial

SAF-XC878CM-16FFI 5V Flash 64 5.0 -40 to 85 Industrial

SAF-XC878-13FFI 3V3 Flash 52 3.3 -40 to 85 Industrial

SAF-XC878M-13FFI 3V3 Flash 52 3.3 -40 to 85 Industrial

SAF-XC878CM-13FFI 3V3 Flash 52 3.3 -40 to 85 Industrial

SAF-XC878-16FFI 3V3 Flash 64 3.3 -40 to 85 Industrial

SAF-XC878M-16FFI 3V3 Flash 64 3.3 -40 to 85 Industrial

Data Sheet 3 V1.2, 2009-11

Table 2 Device Profile (cont’d)

XC878CLM

Summary of Features

Sales Type Device

Type

Program
Memory
(Kbytes)

Power
Supply
(V)

Temp­erature
(°C)

Quality
Profile

SAF-XC878CM-16FFI 3V3 Flash 64 3.3 -40 to 85 Industrial

SAX-XC878-13FFA 5V Flash 52 5.0 -40 to 105 Automotive

SAX-XC878CM-13FFA 5V Flash 52 5.0 -40 to 105 Automotive

SAX-XC878LM-13FFA 5V Flash 52 5.0 -40 to 105 Automotive

SAX-XC878CLM-13FFA 5V Flash 52 5.0 -40 to 105 Automotive

SAX-XC878-16FFA 5V Flash 64 5.0 -40 to 105 Automotive

SAX-XC878CM-16FFA 5V Flash 64 5.0 -40 to 105 Automotive

SAX-XC878LM-16FFA 5V Flash 64 5.0 -40 to 105 Automotive

SAX-XC878CLM-16FFA 5V Flash 64 5.0 -40 to 105 Automotive

As this document refers to all the derivatives, some description may not apply to a
specific product. For simplicity, all versions are referred to by the term XC878 throughout
this document.

Ordering Information

The ordering code for Infineon Technologies microcontrollers provides an exact
reference to the required product. This ordering code identifies:

• The derivative itself, i.e. its function set, the temperature range, and the supply
voltage

• The package and the type of delivery

For the available ordering codes for the XC878, please refer to your responsible sales
representative or your local distributor.

Data Sheet 4 V1.2, 2009-11

XC878CLM

General Device Information

2 General Device Information

Chapter 2 contains the block diagram, pin configurations, definitions and functions of the

XC878.

2.1 Block Diagram

The block diagram of the XC878 is shown in Figure 2.

TMS
MBC

TM

RESET

V

DDP

V

SSP

V

DDC

V

SSC

XTAL1
XTAL2

XC878

8-Kbyte

Boot ROM

1)

256-byte RAM

+

64-byte monitor

RAM

3-Kbyte XRAM

52/64-Kbyte

Flash

Clock Generator

4 MHz

On-chip OSC

PLL

Internal Bus

XC800 Core

T0 & T1 UART

UART1CORDIC

SSCMDU

WDT

OCDS

CCU 6

MultiCAN

Timer 2 Capture/

Compare Unit

Timer 21

P0.0 - P0.7

P1.0 - P1.7

P3.0 - P3.7

P4.0 - P4.7

Port 4Port 5

P5.0 - P5.7

AN0 – AN7

ADC Port 0Port 1Port 3

V
V

AREF

AGND

1) Includes 1-Kbyte monitor ROM

Figure 2 XC878 Block Diagram

Data Sheet 5 V1.2, 2009-11

2.2 Logic Symbol

The logic symbol of the XC878 is shown in Figure 3.

XC878CLM

General Device Information

V

AREF

V

AGND

RESET

MBC

TMS

TM

XTAL1

XTAL2

V

DDP

XC878

V

SSP

Port 0 8-Bit

Port 1 8-Bit

Port 3 8-Bit

Port 4 8-Bit

Port 5 8-Bit

AN0 – AN7

Figure 3 XC878 Logic Symbol

V

DDC

V

SSC

Data Sheet 6 V1.2, 2009-11

2.3 Pin Configuration

The pin configuration of the XC878 in Figure 4.

P3.0

P3. 2

P3. 3

P3. 4

P3. 5

P4.5

P4.6

P4.7

P3.1

P4.4

48 47 46 45 44 43 42 41 40 39 38 37 36 35 34 33

49

50

51

52

P3.6

P3.7

P4.3

XC878CLM

General Device Information

P1.3

P1.4

P1.5

P1.2

P1.0

P1.1

AN7

32

31

30

29

V

AREF

V

AGND

AN6

AN5

RESET

V

SSP

V

DDP

N.C.

53

54

55

56

28

27

26

25

XC878

TM

MBC

P4. 0

P4. 1

P4. 2

P0. 7

P0. 3

P0. 4

57

58

59

60

61

62

63

64

24

23

22

21

20

19

18

17

123 45 678910111213141516

V

P5 . 0

P0 . 5

XTA L 2

P0 . 6

XTA L 1

V

SSCVDDC

DDP

P5 . 1

P1 . 6

P1 . 7

P5 . 2

P5 . 4

P5 . 3

TMS

P5 . 5

Figure 4 XC878 Pin Configuration, PG-LQFP-64 Package (top view)

AN4

AN3

V

SSP

V

DDP

AN2

AN1

AN0

0

P

P5.7

P5.6

P0.2

P0.0

1

.

Data Sheet 7 V1.2, 2009-11

XC878CLM

General Device Information

2.4 Pin Definitions and Functions

The functions and default states of the XC878 external pins are provided in Table 3.

Table 3 Pin Definitions and Functions

Symbol Pin Number

(LQFP-64)

Type Reset

State

Function

P0 I/O Port 0

Port 0 is an 8-bit bidirectional general purpose
I/O port. It can be used as alternate functions
for the JTAG, CCU6, UART, UART1, T2CCU,
Timer
Interface.

P0.0 17 Hi-Z TCK_0

T12HR_1

CC61_1

CLKOUT_0
RXDO_1

P0.1 21 Hi-Z TDI_0

T13HR_1

RXD_1
RXDC1_0
COUT61_1

EXF2_1

21, MultiCAN, SSC and External

JTAG Clock Input
CCU6 Timer 12 Hardware Run
Input
Input/Output of
Capture/Compare channel 1
Clock Output
UART Transmit Data Output

JTAG Serial Data Input
CCU6 Timer 13 Hardware Run
Input
UART Receive Data Input
MultiCAN Node 1 Receiver Input
Output of Capture/Compare
channel 1
Timer 2 External Flag Output

P0.2 18 PU CTRAP_2

TDO_0
TXD_1

CCU6 Trap Input
JTAG Serial Data Output
UART Transmit Data
Output/Clock Output

TXDC1_0

MultiCAN Node 1 Transmitter
Output

P0.3 63 Hi-Z SCK_1

COUT63_1

SSC Clock Input/Output
Output of Capture/Compare

channel 3
RXDO1_0
A17

Data Sheet 8 V1.2, 2009-11

UART1 Transmit Data Output

Address Line 17 Output

Table 3 Pin Definitions and Functions (cont’d)

XC878CLM

General Device Information

Symbol Pin Number

(LQFP-64)

Type Reset

State

Function

P0.4 64 Hi-Z MTSR_1

CC62_1

TXD1_0

A18

P0.5 1 Hi-Z MRST_1

EXINT0_0
T2EX1_1
RXD1_0
COUT62_1

A19

P0.6 2 PU T2CC4_1

WR

SSC Master Transmit Output/

Slave Receive Input

Input/Output of

Capture/Compare channel 2

UART1 Transmit Data

Output/Clock Output

Address Line 18 Output

SSC Master Receive Input/Slave

Transmit Output

External Interrupt Input 0

Timer 21 External Trigger Input

UART1 Receive Data Input

Output of Capture/Compare

channel 2

Address Line 19 Output

Compare Output Channel 4

External Data Write Control

Output

P0.7 62 PU CLKOUT_1

T2CC5_1
RD

Clock Output

Compare Output Channel 5

External Data Read Control

Output

Data Sheet 9 V1.2, 2009-11

Table 3 Pin Definitions and Functions (cont’d)

XC878CLM

General Device Information

Symbol Pin Number

(LQFP-64)

Type Reset

State

Function

P1 I/O Port 1

Port 1 is an 8-bit bidirectional general purpose
I/O port. It can be used as alternate functions
for the JTAG, CCU6, UART, Timer 0, Timer 1,
T2CCU, Timer 21, MultiCAN, SSC and
External Interface.

P1.0 34 PU RXD_0

T2EX_0
RXDC0_0
A8

P1.1 35 PU EXINT3_0

T0_1
TXD_0

TXDC0_0

A9

UART Receive Data Input

Timer 2 External Trigger Input

MultiCAN Node 0 Receiver Input

Address Line 8 Output

External Interrupt Input 3

Timer 0 Input

UART Transmit Data

Output/Clock Output

MultiCAN Node 0 Transmitter

Output

Address Line 9 Output

P1.2 36 PU SCK_0

A10

P1.3 37 PU MTSR_0

SCK_2
TXDC1_3

A11

P1.4 38 PU MRST_0

EXINT0_1
RXDC1_3
MTSR_2

A12

SSC Clock Input/Output

Address Line 10 Output

SSC Master Transmit

Output/Slave Receive Input

SSC Clock Input/Output

MultiCAN Node 1 Transmitter

Output

Address Line 11 Output

SSC Master Receive Input/

Slave Transmit Output

External Interrupt Input 0

MultiCAN Node 1 Receiver Input

SSC Master Transmit

Output/Slave Receive Input

Address Line 12 Output

Data Sheet 10 V1.2, 2009-11

Table 3 Pin Definitions and Functions (cont’d)

XC878CLM

General Device Information

Symbol Pin Number

(LQFP-64)

Type Reset

State

Function

P1.5 39 PU CCPOS0_1

EXINT5_0
T1_1
MRST_2

EXF2_0
RXDO_0

P1.6 10 PU CCPOS1_1

T12HR_0

EXINT6_0
RXDC0_2
T21_1

P1.7 11 PU CCPOS2_1

T13HR_0

T2_1
TXDC0_2

CCU6 Hall Input 0

External Interrupt Input 5

Timer 1 Input

SSC Master Receive Input/

Slave Transmit Output

Timer 2 External Flag Output

UART Transmit Data Output

CCU6 Hall Input 1

CCU6 Timer 12 Hardware Run

Input

External Interrupt Input 6

MultiCAN Node 0 Receiver Input

Timer 21 Input

CCU6 Hall Input 2

CCU6 Timer 13 Hardware Run

Input

Timer 2 Input

MultiCAN Node 0 Transmitter

Output

P1.5 and P1.6 can be used as a software chip
select output for the SSC.

Data Sheet 11 V1.2, 2009-11

Table 3 Pin Definitions and Functions (cont’d)

XC878CLM

General Device Information

Symbol Pin Number

(LQFP-64)

Type Reset

State

Function

P3 I/O Port 3

Port 3 is an 8-bit bidirectional general purpose
I/O port. It can be used as alternate functions
for CCU6, UART1, T2CCU, Timer 21,
MultiCAN and External Interface.

P3.0 43 Hi-Z CCPOS1_2

CC60_0

RXDO1_1
T2CC0_1/
EXINT3_2

P3.1 44 Hi-Z CCPOS0_2

CC61_2

COUT60_0

TXD1_1

CCU6 Hall Input 1

Input/Output of

Capture/Compare channel 0

UART1 Transmit Data Output

External Interrupt Input 3/T2CCU

Capture/Compare Channel 0

CCU6 Hall Input 0

Input/Output of

Capture/Compare channel 1

Output of Capture/Compare

channel 0

UART1 Transmit Data

Output/Clock Output

P3.2 49 Hi-Z CCPOS2_2

RXDC1_1
RXD1_1
CC61_0

T2CC1_1/
EXINT4_2

P3.3 50 Hi-Z COUT61_0

TXDC1_1

T2CC2_1/
EXINT5_2
A13

CCU6 Hall Input 2

MultiCAN Node 1 Receiver Input

UART1 Receive Data Input

Input/Output of

Capture/Compare channel 1

External Interrupt Input 4/T2CCU

Capture/Compare Channel 1

Output of Capture/Compare

channel 1

MultiCAN Node 1 Transmitter

Output

External Interrupt Input 5/T2CCU

Capture/Compare Channel 2

Address Line 13 Output

Data Sheet 12 V1.2, 2009-11

Table 3 Pin Definitions and Functions (cont’d)

XC878CLM

General Device Information

Symbol Pin Number

(LQFP-64)

P3.4 51 Hi-Z CC62_0

Type Reset

State

Function

Input/Output of

Capture/Compare channel 2
RXDC0_1
T2EX1_0
T2CC3_1/
EXINT6_3
A14

P3.5 52 Hi-Z COUT62_0

MultiCAN Node 0 Receiver Input

Timer 21 External Trigger Input

External Interrupt Input 6/T2CCU

Capture/Compare Channel 3

Address Line 14 Output

Output of Capture/Compare

channel 2
EXF21_0
TXDC0_1

Timer 21 External Flag Output

MultiCAN Node 0 Transmitter

Output
A15

Address Line 15 Output

P3.6 41 PU CTRAP_0 CCU6 Trap Input

P3.7 42 Hi-Z EXINT4_0

COUT63_0

External Interrupt Input 4

Output of Capture/Compare

channel 3
A16

Address Line 16 Output

Data Sheet 13 V1.2, 2009-11

Table 3 Pin Definitions and Functions (cont’d)

XC878CLM

General Device Information

Symbol Pin Number

(LQFP-64)

Type Reset

State

Function

P4 I/O Port 4

Port 4 is an 8-bit bidirectional general purpose
I/O port. It can be used as alternate functions
for CCU6, Timer 0, Timer 1, T2CCU, Timer 21,
MultiCAN and External Interface.

P4.0 59 Hi-Z RXDC0_3

CC60_1

T2CC0_0/
EXINT3_1
D0

P4.1 60 Hi-Z TXDC0_3

COUT60_1

T2CC1_0/
EXINT4_1
D1

MultiCAN Node 0 Receiver Input

Output of Capture/Compare

channel 0

External Interrupt Input 3/T2CCU

Capture/Compare Channel 0

Data Line 0 Input/Output

MultiCAN Node 0 Transmitter

Output

Output of Capture/Compare

channel 0

External Interrupt Input 4/T2CCU

Capture/Compare Channel 1

Data Line 1 Input/Output

P4.2 61 PU EXINT6_1

T21_0
D2

P4.3 40 Hi-Z T2EX_1

EXF21_1
COUT63_2

D3

P4.4 45 Hi-Z CCPOS0_3

T0_0
CC61_4

T2CC2_0/
EXINT5_1
D4

External Interrupt Input 6

Timer 21 Input

Data Line 2 Input/Output

Timer 2 External Trigger Input

Timer 21 External Flag Output

Output of Capture/Compare

channel 3

Data Line 3 Input/Output

CCU6 Hall Input 0

Timer 0 Input

Output of Capture/Compare

channel 1

External Interrupt Input 5/T2CCU

Capture/Compare Channel 2

Data Line 4 Input/Output

Data Sheet 14 V1.2, 2009-11

Table 3 Pin Definitions and Functions (cont’d)

XC878CLM

General Device Information

Symbol Pin Number

(LQFP-64)

Type Reset

State

Function

P4.5 46 Hi-Z CCPOS1_3

T1_0
COUT61_2

T2CC3_0/
EXINT6_2
D5

P4.6 47 Hi-Z CCPOS2_3

T2_0
CC62_2

T2CC4_0
D6

P4.7 48 Hi-Z CTRAP_3

COUT62_2

T2CC5_0
D7

CCU6 Hall Input 1

Timer 1 Input

Output of Capture/Compare

channel 1

External Interrupt Input 6/T2CCU

Capture/Compare Channel 3

Data Line 5 Input/Output

CCU6 Hall Input 2

Timer 2 Input

Output of Capture/Compare

channel 2

Compare Output Channel 4

Data Line 6 Input/Output

CCU6 Trap Input

Output of Capture/Compare

channel 2

Compare Output Channel 5

Data Line 7 Input/Output

Data Sheet 15 V1.2, 2009-11

Table 3 Pin Definitions and Functions (cont’d)

XC878CLM

General Device Information

Symbol Pin Number

(LQFP-64)

Type Reset

State

Function

P5 I/O Port 5

Port 5 is an 8-bit bidirectional general purpose
I/O port. It can be used as alternate functions
for UART, UART1, T2CCU, JTAG and External
Interface.

P5.0 8 PU EXINT1_1A0External Interrupt Input 1

Address Line 0 Output

P5.1 9 PU EXINT2_1A1External Interrupt Input 2

Address Line 1 Output

P5.2 12 PU RXD_2

T2CC2_2/
EXINT5_3
A2

P5.3 13 PU CCPOS0_0

EXINT1_0
T12HR_2

UART Receive Data Input

External Interrupt Input 5/T2CCU

Capture/Compare Channel 2

Address Line 2 Output

CCU6 Hall Input 0

External Interrupt Input 1

CCU6 Timer 12 Hardware Run

Input
CC61_3

Input of Capture/Compare

channel 1
TXD_2

UART Transmit Data

Output/Clock Output
T2CC5_2
A3

Compare Output Channel 5

Address Line 3 Output

P5.4 14 PU CCPOS1_0

EXINT2_0
T13HR_2

CCU6 Hall Input 1

External Interrupt Input 2

CCU6 Timer 13 Hardware Run

Input
CC62_3

Input of Capture/Compare

channel 2
RXDO_2
T2CC4_2
A4

Data Sheet 16 V1.2, 2009-11

UART Transmit Data Output

Compare Output Channel 4

Address Line 4 Output

Table 3 Pin Definitions and Functions (cont’d)

XC878CLM

General Device Information

Symbol Pin Number

(LQFP-64)

Type Reset

State

Function

P5.5 15 PU CCPOS2_0

CTRAP_1
CC60_3

TDO_1
TXD1_2

T2CC0_2/
EXINT3_3
A5

P5.6 19 PU TCK_1

RXDO1_2
T2CC1_2/
EXINT4_3
A6

P5.7 20 PU TDI_1

RXD1_2
T2CC3_2/
EXINT6_4
A7

CCU6 Hall Input 2

CCU6 Trap Input

Input of Capture/Compare

channel 0

JTAG Serial Data Output

UART1 Transmit Data Output/

Clock Output

External Interrupt Input 3/T2CCU

Capture/Compare Channel 0

Address Line 5 Output

JTAG Clock Input

UART1 Transmit Data Output

External Interrupt Input 4/T2CCU

Capture/Compare Channel 1

Address Line 6 Output

JTAG Serial Data Input

UART1 Receive Data Input

External Interrupt Input 6/T2CCU

Capture/Compare Channel 3

Address Line 7 Output

Data Sheet 17 V1.2, 2009-11

Table 3 Pin Definitions and Functions (cont’d)

XC878CLM

General Device Information

Symbol Pin Number

(LQFP-64)

V

DDP

7, 25, 55 – – I/O Port Supply (3.3 or 5.0 V)

Type Reset

State

Function

Also used by EVR and analog modules. All
pins must be connected.

V

SSP

26, 54 – – I/O Ground

All pins must be connected.

V

V

V

V

DDC

SSC

AREF

AGND

6 – – Core Supply Monitor (2.5 V)

5 – – Core Supply Ground

32 – – ADC Reference Voltage

31 – – ADC Reference Ground

AN0 22 I Hi-Z Analog Input 0

AN1 23 I Hi-Z Analog Input 1

AN2 24 I Hi-Z Analog Input 2

AN3 27 I Hi-Z Analog Input 3

AN4 28 I Hi-Z Analog Input 4

AN5 29 I Hi-Z Analog Input 5

AN6 30 I Hi-Z Analog Input 6

AN7 33 I Hi-Z Analog Input 7

XTAL1 4 I Hi-Z External Oscillator Input

(Feedback resistor required, normally NC)

XTAL2 3 O Hi-Z External Oscillator Output

(Feedback resistor required, normally NC)

TMS 16 I PD JTAG Test Mode Select

RESET 53 I PU Reset Input

MBC 58 I PU Monitor & BootStrap Loader Control

TM 57 – – Test Mode

(External pull down device required)

NC 56 – – No Connection

Data Sheet 18 V1.2, 2009-11

XC878CLM

Functional Description

3 Functional Description

Chapter 3 provides an overview of the XC878 functional description.

3.1 Processor Architecture

The XC878 is based on a high-performance 8-bit Central Processing Unit (CPU) that is
compatible with the standard 8051 processor. While the standard 8051 processor is
designed around a 12-clock machine cycle, the XC878 CPU uses a 2-clock machine
cycle. This allows fast access to ROM or RAM memories without wait state. The
instruction set consists of 45% one-byte, 41% two-byte and 14% three-byte instructions.

The XC878 CPU provides a range of debugging features, including basic stop/start,
single-step execution, breakpoint support and read/write access to the data memory,
program memory and Special Function Registers (SFRs).

Figure 5 shows the CPU functional blocks.

External Data

Memory

Program Memory

f

CCLK

Memory Wait

Reset

Legacy External Interrupts (IEN0, IEN1)

External Interrupts

Non-Maskable Interrupt

Core SFRs

16-bit R egisters &
Memory Interface

Opcode &

Immediate

Registers

Opcode D ecoder

State Machine &

Power Saving

Interrupt

Controller

Internal Data

Memory

Register Interface

External SFRs

ALU

Multiplier / Divider

Timer 0 / Timer 1

UART

Figure 5 CPU Block Diagram

Data Sheet 19 V1.2, 2009-11

XC878CLM

Functional Description

3.2 Memory Organization

The XC878 CPU operates in the following address spaces:

• 8 Kbytes of Boot ROM program memory

• 256 bytes of internal RAM data memory

• 3 Kbytes of XRAM memory
(XRAM can be read/written as program memory or external data memory)

• A 128-byte Special Function Register area

• 64/52 Kbytes of Flash program memory (Flash devices)

Figure 6 and Figure 7 illustrate the memory address spaces of the XC878 with

64Kbytes and 52Kbytes embedded Flash respectively.

Bank F

Bank E

Bank D

Bank C

Bank B

Bank A

Bank 9

Bank 8

Bank 7

Bank 6

Bank 5

Bank 4

Bank 3

Bank 2Bank 0

Bank 1

Reserved

Reserved

External

Reserved

External

XRAM

3 KByte

Reserved

Boot ROM

8 KByte

Reserved

D-Flash
4 KByte

P-Flash

60 KByte

F' FF FF

F' 0000
E' FFFF
E' 0000
D' FFFF
D' 0000
C' FFFF
C' 0000
B' FFFF
B' 0000
A' FFFF
A' 0000
9' FFFF
9' 0000
8' FFFF
8' 0000
7' FFFF
7' 0000
6' FFFF
6' 0000
5' FFFF
5' 0000
4' FFFF
4' 0000
3' FFFF
3' 0000
2' FFFF
2' FEC0

2' FE00
2' FC00

2' F000
2' E000

2' C000

2' 0000
1' FFFF

1' 0000
0' FFFF

0' F000

0' 0000

H

H

H

H

H

H

H

H

H

H

H

H

H

H

H

H

H

H

H

H

H

H

H

H

H

H

H

H

H

H

H

H

H

H

H

H

H

H

External

XRAM

3 KByte

External

Reserved

Ext ernal

Reserved

External

Reserved

External

Reserved

F' FFFF
F' FC0 0

F' F000

F' 0000
E' FFFF
E' 0000
D' FFFF
D' 0000
C' FFFF
C' 0000
B' FFFF
B' 0000
A' FFFF
A' 0000
9' FFFF
9' 0000
8' FFFF
8' 0000
7' FFFF
7' 0000
6' FFFF
6' 0000
5' FFFF
5' 0000
4' FFFF
4' 0000
3' FFFF
3' 0000
2' FFFF
2' FEC0

2' FE00
2' FC00

2' F000
2' E000

2' C000

2' 0000
1' FFFF

1' 0000
0' FFFF

H

H

H

H

H

H

H

H

H

H

H

H

H

H

H

H

H

H

H

H

H

H

H

H

H

H

H

H

H

H

H

H

H

H

Memory Ex tension

H

Stack Pointer

H

H

H

Ext ensi on Stack R AM

H

(MEXSP)

Indirect

Address

Internal RAM

Direct

Address

Speci al Func ti on

Registers

7F

H

FF

H

80

H

Internal RAM

0' 0000

H

H

00

H

Code Space Internal Data Space

Data Space

Memor y Map U ser Mode

Figure 6 Memory Map of XC878 with 64K Flash Memory in user mode

Data Sheet 20 V1.2, 2009-11

XC878CLM

Functional Description

External

Reserved

External

XRAM

2 KByte

D-Flash
4 KByte

Boot ROM

8 KByte

P-Flash

48 KByte /

Reserved

P-Flash

32 KBy te

F’FFFF

1'0000
FFFF

FEC0

FE00

FC0 0

F000

E000

C00 0

8000

0000

H

F’FFFF

H

ExternalReserved

H

H

H

H

H

H

H

External

Reserved

External

XRAM

2 KBy te

1'0000

FFFF

FEC0

FE00
FC0 0

F000

H

H

H

H

H

H

Reserved

H

C00 0

H

Reserved /

Ext ernal

H

Reserved

8000

H

Memory Extensi on

Extension Stack RAM

Stack Pointer

(MEXSP)

Indirect

Address

Internal RAM

Direct

Addres s

Special Function

Registers

7F

H

FF

H

80

H

Internal RAM

H

0000

H

00

H

Code Spac e Internal Data Space

Data Space

Figure 7 Memory Map of XC878 with 52K Flash Memory in user mode

Memory Map User Mode

Data Sheet 21 V1.2, 2009-11