INFINEON XC167CI-16F User Manual

Data Sheet, V1.2, March 2006

XC167CI-16F

16-Bit Single-Chip Microcontroller
with C166SV2 Core

Microcontrollers

Edition 2006-03

Published by
Infineon Technologies AG
81726 München, Germany

© Infineon Technologies AG 2006.

All Rights Reserved.

Legal Disclaimer

The information given in this document shall in no event be regarded as a guarantee of conditions or
characteristics (“Beschaffenheitsgarantie”). With respect to any examples or hints given herein, any typical values
stated herein and/or any information regarding the application of the device, Infineon Technologies hereby
disclaims any and all warranties and liabilities of any kind, including without limitation warranties of non­infringement of intellectual property rights of any third party.

Information

For further information on technology, delivery terms and conditions and prices please contact your nearest
Infineon Technologies Office (www.infineon.com).

Warnings

Due to technical requirements components may contain dangerous substances. For information on the types in
question please contact your nearest Infineon Technologies Office.

Infineon Technologies Components may only be used in life-support devices or systems with the express written
approval of Infineon Technologies, if a failure of such components can reasonably be expected to cause the failure
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be endangered.

Data Sheet, V1.2, March 2006

XC167CI-16F

16-Bit Single-Chip Microcontroller
with C166SV2 Core

Microcontrollers

XC167-16

Derivatives

XC167
Revision History: V1.2, 2006-03

Previous Version(s):
V1.1, 2003-06
V1.0, 2002-10

Page Subjects (major changes since last revision)

all Layout of graphics and text structures has been adapted to the new

company documentation rules.

73 Minimum oscillator period corrected

77 Output delay/hold time of A23 … A16 moved from

tc

-> tc12, tc21 -> tc

11

82 Parameter tc40 corrected

85 Chapter “Package and Reliability” added.

We Listen to Your Comments

Any information within this document that you feel is wrong, unclear or missing at all?
Your feedback will help us to continuously improve the quality of this document.
Please send your proposal (including a reference to this document) to:

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23

Data Sheet V1.2, 2006-03

XC167-16

Derivatives

Table of Contents

Table of Contents

1 Summary of Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4

2 General Device Information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7

2.1 Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7

2.2 Pin Configuration and Definition . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8

3 Functional Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21

3.1 Memory Subsystem and Organization . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22

3.2 External Bus Controller . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24

3.3 Central Processing Unit (CPU) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26

3.4 Interrupt System . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 28

3.5 On-Chip Debug Support (OCDS) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 33

3.6 Capture/Compare Units (CAPCOM1/2) . . . . . . . . . . . . . . . . . . . . . . . . . . . 34

3.7 The Capture/Compare Unit CAPCOM6 . . . . . . . . . . . . . . . . . . . . . . . . . . . 37

3.8 General Purpose Timer (GPT12E) Unit . . . . . . . . . . . . . . . . . . . . . . . . . . . 38

3.9 Real Time Clock . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 42

3.10 A/D Converter . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 44

3.11 Asynchronous/Synchronous Serial Interfaces (ASC0/ASC1) . . . . . . . . . . 45

3.12 High Speed Synchronous Serial Channels (SSC0/SSC1) . . . . . . . . . . . . 46

3.13 TwinCAN Module . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 47

3.14 IIC Bus Module . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 48

3.15 Watchdog Timer . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 49

3.16 Clock Generation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 50

3.17 Parallel Ports . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 50

3.18 Power Management . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 52

3.19 Instruction Set Summary . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 53

4 Electrical Parameters . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 56

4.1 General Parameters . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 56

4.2 DC Parameters . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 59

4.3 Analog/Digital Converter Parameters . . . . . . . . . . . . . . . . . . . . . . . . . . . . 65

4.4 AC Parameters . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 68

4.4.1 Definition of Internal Timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 68

4.4.2 On-chip Flash Operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 72

4.4.3 External Clock Drive XTAL1 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 73

4.4.4 Testing Waveforms . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 74

4.4.5 External Bus Timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 75

5 Package and Reliability . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 85

5.1 Packaging . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 85

5.2 Flash Memory Parameters . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 86

Data Sheet 3 V1.2, 2006-03

XC16716-Bit Single-Chip Microcontroller with C166SV2 Core

XC166 Family

1 Summary of Features

• High Performance 16-bit CPU with 5-Stage Pipeline
– 25 ns Instruction Cycle Time at 40 MHz CPU Clock (Single-Cycle Execution)
– 1-Cycle Multiplication (16 ×16 bit), Background Division (32 / 16 bit) in 21 Cycles
– 1-Cycle Multiply-and-Accumulate (MAC) Instructions
– Enhanced Boolean Bit Manipulation Facilities
– Zero-Cycle Jump Execution
– Additional Instructions to Support HLL and Operating Systems
– Register-Based Design with Multiple Variable Register Banks
– Fast Context Switching Support with Two Additional Local Register Banks
– 16 Mbytes Total Linear Address Space for Code and Data
– 1024 Bytes On-Chip Special Function Register Area (C166 Family Compatible)

• 16-Priority-Level Interrupt System with 77 Sources, Sample-Rate down to 50 ns

• 8-Channel Interrupt-Driven Single-Cycle Data Transfer Facilities via
Peripheral Event Controller (PEC), 24-Bit Pointers Cover Total Address Space

• Clock Generation via on-chip PLL (factors 1:0.15 … 1:10), or
via Prescaler (factors 1:1 … 60:1)

• On-Chip Memory Modules
– 2 Kbytes On-Chip Dual-Port RAM (DPRAM)
– 4 Kbytes On-Chip Data SRAM (DSRAM)
– 2 Kbytes On-Chip Program/Data SRAM (PSRAM)
– 128 Kbytes On-Chip Program Memory (Flash Memory)

• On-Chip Peripheral Modules
– 16-Channel A/D Converter with Programmable Resolution (10-bit or 8-bit) and

Conversion Time (down to 2.55 µs or 2.15 µs)
– Two 16-Channel General Purpose Capture/Compare Units (32 Input/Output Pins)
– Capture/Compare Unit for flexible PWM Signal Generation (CAPCOM6)

(3/6 Capture/Compare Channels and 1 Compare Channel)
– Multi-Functional General Purpose Timer Unit with 5 Timers
– Two Synchronous/Asynchronous Serial Channels (USARTs)
– Two High-Speed-Synchronous Serial Channels
– On-Chip TwinCAN Interface (Rev. 2.0B active) with 32 Message Objects

(Full CAN/Basic CAN) on Two CAN Nodes, and Gateway Functionality
– IIC Bus Interface (10-bit addressing, 400 kbit/s) with 3 Channels (multiplexed)
– On-Chip Real Time Clock, Driven by Dedicated Oscillator

• Idle, Sleep, and Power Down Modes with Flexible Power Management

• Programmable Watchdog Timer and Oscillator Watchdog

Data Sheet 4 V1.2, 2006-03

Summary of Features

• Up to 12 Mbytes External Address Space for Code and Data
– Programmable External Bus Characteristics for Different Address Ranges
– Multiplexed or Demultiplexed External Address/Data Buses
– Selectable Address Bus Width
– 16-Bit or 8-Bit Data Bus Width
– Five Programmable Chip-Select Signals
– Hold- and Hold-Acknowledge Bus Arbitration Support

• Up to 103 General Purpose I/O Lines,
partly with Selectable Input Thresholds and Hysteresis

• On-Chip Bootstrap Loader

• Supported by a Large Range of Development Tools like C-Compilers,
Macro-Assembler Packages, Emulators, Evaluation Boards, HLL-Debuggers,
Simulators, Logic Analyzer Disassemblers, Programming Boards

• On-Chip Debug Support via JTAG Interface

• 144-Pin TQFP Package, 0.5 mm (19.7 mil) pitch

XC167-16

Derivatives

Ordering Information

The ordering code for Infineon microcontrollers provides an exact reference to the
required product. This ordering code identifies:

• the derivative itself, i.e. its function set, the temperature range, and the supply voltage

• the package and the type of delivery.

For the available ordering codes for the XC167 please refer to the “Product Catalog
Microcontrollers”, which summarizes all available microcontroller variants.

Note: The ordering codes for Mask-ROM versions are defined for each product after

verification of the respective ROM code.

This document describes several derivatives of the XC167 group. Table 1 enumerates
these derivatives and summarizes the differences. As this document refers to all of these
derivatives, some descriptions may not apply to a specific product.

For simplicity all versions are referred to by the term XC167 throughout this document.

Data Sheet 5 V1.2, 2006-03

Table 1 XC167 Derivative Synopsis

Derivative

1)

Temp.
Range

Program
Memory

XC167-16

Derivatives

Summary of Features

On-Chip RAM Interfaces

SAK-XC167CI-16F40F,
SAK-XC167CI-16F20F

-40 °C to
125 °C

128 Kbytes
Flash

2 Kbytes DPRAM,
4 Kbytes DSRAM,
2 Kbytes PSRAM

SAF-XC167CI-16F40F,
SAF-XC167CI-16F20F

-40 °C to
85 °C

128 Kbytes
Flash

2 Kbytes DPRAM,
4 Kbytes DSRAM,
2 Kbytes PSRAM

1) This Data Sheet is valid for devices starting with and including design step AD.

ASC0, ASC1,
SSC0, SSC1,
CAN0, CAN1,
IIC

ASC0, ASC1,
SSC0, SSC1,
CAN0, CAN1,
IIC

Data Sheet 6 V1.2, 2006-03

XC167-16

Derivatives

General Device Information

2 General Device Information

2.1 Introduction

The XC167 derivatives are high-performance members of the Infineon XC166 Family of
full featured single-chip CMOS microcontrollers. These devices extend the functionality
and performance of the C166 Family in terms of instructions (MAC unit), peripherals, and
speed. They combine high CPU performance (up to 40 million instructions per second)
with high peripheral functionality and enhanced IO-capabilities. They also provide clock
generation via PLL and various on-chip memory modules such as program Flash,
program RAM, and data RAM.

Port 20
6 bit

XTAL1

XTAL2

XTAL3

XTAL4

NMI

RSTIN

RSTOUT

EA

READY

ALE

RD

WR/WRL

Port 5
16 bit

V

AREF

V

AGND

XC167

V

DDI/P

V

SSI/P

PORT0
16 bit

PORT1
16 bit

Port 2
8 bit

Port 3
15 bit

Port 4
8 bit

Port 6
8 bit

Port 7
4 bit

Port 9
6 bit

TRST Debug

JTAG

5 bit

2 bit

MCA05554_7

Figure 1 Logic Symbol

Data Sheet 7 V1.2, 2006-03

XC167-16

Derivatives

General Device Information

2.2 Pin Configuration and Definition

The pins of the XC167 are described in detail in Table 2, including all their alternate
functions. Figure 2 summarizes all pins in a condensed way, showing their location on
the 4 sides of the package. E*) and C*) mark pins to be used as alternate external
interrupt inputs, C*) marks pins that can have CAN interface lines assigned to them.

SSI

BRKIN

BRKOUT

RSTIN

XTAL4

XTAL3

SSIVDDI

V

XTAL1

XTAL2

V

P1H.7/A15/CC27IO

P1H.6/A14/CC26IO

P1H.5/A13/CC25IO

P1H.4/A12/CC24IO

P1H.3/A11/SCLK1/E*)

SSPVDDP

P1H.2/A10/CC6POS2/MTSR1

P1H.1/A9/CC6POS1/MRST1

P1H.0/A8/CC6POS0/CC23IO/E*)

V

P1L.7/A7/CTRAP/CC22IO

P1L.6/A6/COUT63

P1L.5/A5/COUT62

P1L.4/A4/CC62

P1L.3/A3/COUT61

P1L.2/A2/CC61

P1L.1/A1/COUT60

P1L.0/A0/CC60

P0H.7/AD15

P0H.6/AD14

P0H.5/AD13

P0H.4/AD12

P0H.3/AD11

P0H.2/AD10

N.C.

N.C.

N.C.

P20.12/RSTOUT

P6.0/CS0/CC0IO
P6.1/CS1/CC1IO
P6.2/CS2/CC2IO
P6.3/CS3/CC3IO
P6.4/CS4/CC4IO

P6.5/HOLD/CC5IO

P6.6/HLDA/CC6IO

P6.7/BREQ/CC7IO

P7.4/CC28IO/C*)
P7.5/CC29IO/C*)
P7.6/CC30IO/C*)
P7.7/CC31IO/C*)

P9.0/SDA0/CC16IO/C*)

P9.1/SCL0/CC17IO/C*)

P9.2/SDA1/CC18IO/C*)

P9.3/SCL1/CC19IO/C*)

P9.4/SDA2/CC20IO

P9.5/SCL2/CC21IO

P5.10/AN10/T6EUD
P5.11/AN11/T5EUD

N.C.

NMI

V

SSP

V

DDP

V

SSP

V

DDP

V

SSP

V

DDP

P5.0/AN0
P5.1/AN1
P5.2/AN2
P5.3/AN3
P5.4/AN4
P5.5/AN5

144

143

142

141

140

139

138

137

136

135

134

133

132

131

130

129

128

127

126

125

124

123

122

121

120

119

118

117

116
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
32
33
34
35

3738394041424344454647484950515253545556575859606162636465666768697071

XC167

115

114

113

112

111

110

109

N.C.

108

N.C.

107

P0H.1/AD9

106

P0H.0/AD8

105

V

104

SSP

V

103

DDP

P0L.7/AD7

102

P0L.6/AD6

101

P0L.5/AD5

100

P0L.4/AD4

99

P0L.3/AD3

98

P0L.2/AD2

97

P0L.1/AD1

96

P0L.0/AD0

95

P20.5/EA

94

P20.4/ALE

93

P20.2/READY

92

P20.1/WR/WRL

91

P20.0/RD

90

V

89

SSP

V

88

DDP

P4.7/A23/C*)

87

P4.6/A22/C*)

86

P4.5/A21/C*)

85

P4.4/A20/C*)

84

P4.3/A19

83

P4.2/A18

82

P4.1/A17

81

P4.0/A16

80

V

79

SSI

V

78

DDI

P3.15/CLKOUT/FOUT

77

P3.13/SCLK0/E*)

76

P3.12/BHE/WRH/E*)

75

TMS

74

TDO

7336

72

SSI

P5.8/AN8

P5.9/AN9

P5.6/AN6

P5.7/AN7

DDI

AREF

AGND

V

V

V

V

P5.12/AN12/T6IN

P5.13/AN13/T5IN

P5.14/AN14/T4EUD

P2.8/CC8IO/EX0IN

P5.15/AN15/T2EUD

P2.9/CC9IO/EX1IN

P2.10/CC10IO/EX2IN

P2.11/CC11IO/EX3IN

P2.12/CC12IO/EX4IN

P2.13/CC13IO/EX5IN

DDP

V

TRST

P3.5/T4IN

P3.6/T3IN

P3.2/CAPIN

P3.3/T3OUT

P2.14/CC14IO/EX6IN

P3.0/T0IN/TxD1/E*)

P3.1/T6OUT/RxD1/E*)

P2.15/CC15IO/EX7IN/T7IN

P3.7/T2IN

P3.4/T3EUD

P3.8/MRST0

P3.9/MTSR0

TDI

TCK

P3.10/TxD0/E*)

P3.11/RxD0/E*)

MCP06458

Figure 2 Pin Configuration (top view)

Data Sheet 8 V1.2, 2006-03

Table 2 Pin Definitions and Functions

XC167-16

Derivatives

General Device Information

Sym­bol

Pin
Num.

Input
Outp.

Function

P20.12 3 IO For details, please refer to the description of P20.

NMI

4 I Non-Maskable Interrupt Input. A high to low transition at this

pin causes the CPU to vector to the NMI trap routine. When
the PWRDN (power down) instruction is executed, the NMI
pin must be low in order to force the XC167 into power down
mode. If NMI

is high, when PWRDN is executed, the part will

continue to run in normal mode.

P6

IO

If not used, pin NMI

Port 6 is an 8-bit bidirectional I/O port. Each pin can be

should be pulled high externally.

programmed for input (output driver in high-impedance
state) or output (configurable as push/pull or open drain
driver). The input threshold of Port 6 is selectable (standard
or special).
The Port 6 pins also serve for alternate functions:

P6.0

P6.1

P6.2

P6.3

P6.4

P6.5

P6.6

7

8

9

10

11

12

13

O
IO
O
IO
O
IO
O
IO
O
IO
I
IO
I/O

CS0

Chip Select 0 Output,
CC0IO CAPCOM1: CC0 Capture Inp./Compare Output
CS1

Chip Select 1 Output,
CC1IO CAPCOM1: CC1 Capture Inp./Compare Output
CS2

Chip Select 2 Output,
CC2IO CAPCOM1: CC2 Capture Inp./Compare Output
CS3

Chip Select 3 Output,
CC3IO CAPCOM1: CC3 Capture Inp./Compare Output
CS4

Chip Select 4 Output,
CC4IO CAPCOM1: CC4 Capture Inp./Compare Output
HOLD

External Master Hold Request Input,
CC5IO CAPCOM1: CC5 Capture Inp./Compare Output
HLDA

Hold Acknowledge Output (master mode) or

Input (slave mode),
CC6IO CAPCOM1: CC6 Capture Inp./Compare Output
BREQ

Bus Request Output,
CC7IO CAPCOM1: CC7 Capture Inp./Compare Output

P6.7

14

IO
O
IO

Data Sheet 9 V1.2, 2006-03

Table 2 Pin Definitions and Functions (cont’d)

XC167-16

Derivatives

General Device Information

Sym­bol

P7

P7.4

P7.5

P7.6

P7.7

Pin
Num.

15

16

17

18

Input
Outp.

IO

I/O
I
I
I/O
O
I
I/O
I
I
I/O
O
I

Function

Port 7 is a 4-bit bidirectional I/O port. Each pin can be
programmed for input (output driver in high-impedance
state) or output (configurable as push/pull or open drain
driver). The input threshold of Port 7 is selectable (standard
or special).
Port 7 pins provide inputs/outputs for CAPCOM2 and serial
interface lines.

1)

CC28IO CAPCOM2: CC28 Capture Inp./Compare Outp.,
CAN2_RxD CAN Node 2 Receive Data Input,
EX7IN Fast External Interrupt 7 Input (alternate pin B)
CC29IO CAPCOM2: CC29 Capture Inp./Compare Outp.,
CAN2_TxD CAN Node 2 Transmit Data Output,
EX6IN Fast External Interrupt 6 Input (alternate pin B)
CC30IO CAPCOM2: CC30 Capture Inp./Compare Outp.,
CAN1_RxD CAN Node 1 Receive Data Input,
EX7IN Fast External Interrupt 7 Input (alternate pin A)
CC31IO CAPCOM2: CC31 Capture Inp./Compare Outp.,
CAN1_TxD CAN Node 1 Transmit Data Output,
EX6IN Fast External Interrupt 6 Input (alternate pin A)

Data Sheet 10 V1.2, 2006-03

Table 2 Pin Definitions and Functions (cont’d)

XC167-16

Derivatives

General Device Information

Sym­bol

P9

P9.0

P9.1

P9.2

P9.3

P9.4

P9.5

Pin
Num.

21

22

23

24

25

26

Input
Outp.

IO

I/O
I
I/O
I/O
O
I/O
I/O
I
I/O
I/O
O
I/O
I/O
I/O
I/O
I/O

Function

Port 9 is a 6-bit bidirectional I/O port. Each pin can be
programmed for input (output driver in high-impedance
state) or output (configurable as push/pull or open drain
driver). The input threshold of Port 9 is selectable (standard
or special).
The following Port 9 pins also serve for alternate functions:
CC16IO CAPCOM2: CC16 Capture Inp./Compare Outp.,
CAN2_RxD CAN Node 2 Receive Data Input,
SDA0 IIC Bus Data Line 0
CC17IO CAPCOM2: CC17 Capture Inp./Compare Outp.,
CAN2_TxD CAN Node 2 Transmit Data Output,
SCL0 IIC Bus Clock Line 0
CC18IO CAPCOM2: CC18 Capture Inp./Compare Outp.,
CAN1_RxD CAN Node 1 Receive Data Input,
SDA1 IIC Bus Data Line 1
CC19IO CAPCOM2: CC19 Capture Inp./Compare Outp.,
CAN1_TxD CAN Node 1 Transmit Data Output,
SCL1 IIC Bus Clock Line 1
CC20IO CAPCOM2: CC20 Capture Inp./Compare Outp.,
SDA2 IIC Bus Data Line 2
CC21IO CAPCOM2: CC21 Capture Inp./Compare Outp.,
SCL2 IIC Bus Clock Line 2

1)

Data Sheet 11 V1.2, 2006-03

Table 2 Pin Definitions and Functions (cont’d)

XC167-16

Derivatives

General Device Information

Sym­bol

P5

P5.0
P5.1
P5.2
P5.3
P5.4
P5.5
P5.10
P5.11
P5.8
P5.9
P5.6
P5.7
P5.12
P5.13
P5.14
P5.15

Pin
Num.

29
30
31
32
33
34
35
36
37
38
39
40
43
44
45
46

Input
Outp.

I

I
I
I
I
I
I
I
I
I
I
I
I
I
I
I
I

Function

Port 5 is a 16-bit input-only port.
The pins of Port 5 also serve as analog input channels for the
A/D converter, or they serve as timer inputs:
AN0
AN1
AN2
AN3
AN4
AN5
AN10, T6EUD GPT1 Timer T4 Ext. Up/Down Ctrl. Inp.
AN11, T5EUD GPT1 Timer T2 Ext. Up/Down Ctrl. Inp
AN8
AN9
AN6
AN7
AN12, T6IN GPT2 Timer T6 Count/Gate Input
AN13, T5IN GPT2 Timer T5 Count/Gate Input
AN14, T4EUD GPT1 Timer T4 Ext. Up/Down Ctrl. Inp.
AN15, T2EUD GPT1 Timer T2 Ext. Up/Down Ctrl. Inp.

Data Sheet 12 V1.2, 2006-03

Table 2 Pin Definitions and Functions (cont’d)

XC167-16

Derivatives

General Device Information

Sym­bol

P2

P2.8

P2.9

P2.10

P2.11

P2.12

P2.13

P2.14

P2.15

Pin
Num.

49

50

51

52

53

54

55

56

Input
Outp.

IO

I/O
I
I/O
I
I/O
I
I/O
I
I/O
I
I/O
I
I/O
I
I/O
I
I

Function

Port 2 is an 8-bit bidirectional I/O port. Each pin can be
programmed for input (output driver in high-impedance
state) or output (configurable as push/pull or open drain
driver). The input threshold of Port 2 is selectable (standard
or special).
The following Port 2 pins also serve for alternate functions:
CC8IO CAPCOM1: CC8 Capture Inp./Compare Output,
EX0IN Fast External Interrupt 0 Input (default pin)
CC9IO CAPCOM1: CC9 Capture Inp./Compare Output,
EX1IN Fast External Interrupt 1 Input (default pin)
CC10IO CAPCOM1: CC10 Capture Inp./Compare Outp.,
EX2IN Fast External Interrupt 2 Input (default pin)
CC11IO CAPCOM1: CC11 Capture Inp./Compare Outp.,
EX3IN Fast External Interrupt 3 Input (default pin)
CC12IO CAPCOM1: CC12 Capture Inp./Compare Outp.,
EX4IN Fast External Interrupt 4 Input (default pin)
CC13IO CAPCOM1: CC13 Capture Inp./Compare Outp.,
EX5IN Fast External Interrupt 5 Input (default pin)
CC14IO CAPCOM1: CC14 Capture Inp./Compare Outp.,
EX6IN Fast External Interrupt 6 Input (default pin)
CC15IO CAPCOM1: CC15 Capture Inp./Compare Outp.,
EX7IN Fast External Interrupt 7 Input (default pin),
T7IN CAPCOM2: Timer T7 Count Input

TRST

57 I Test-System Reset Input. A high-level at this pin activates

the XC167’s debug system.

Note: For normal system operation, pin TRST

should be

held low.

Data Sheet 13 V1.2, 2006-03

Table 2 Pin Definitions and Functions (cont’d)

XC167-16

Derivatives

General Device Information

Sym­bol

P3

P3.0

P3.1

P3.2
P3.3
P3.4
P3.5
P3.6
P3.7
P3.8
P3.9
P3.10

P3.11

P3.12

P3.13

P3.15

Pin
Num.

59

60

61
62
63
64
65
66
67
68
69

70

75

76

77

Input
Outp.

IO

I
O
I
O
I/O
I
I
O
I
I
I
I
I/O
I/O
O
I
I/O
I
O
O
I
I/O
I
O
O

Function

Port 3 is a 15-bit bidirectional I/O port. Each pin can be
programmed for input (output driver in high-impedance
state) or output (configurable as push/pull or open drain
driver). The input threshold of Port 3 is selectable (standard
or special).
The following Port 3 pins also serve for alternate functions:
T0IN CAPCOM1 Timer T0 Count Input,
TxD1 ASC1 Clock/Data Output (Async./Sync),
EX1IN Fast External Interrupt 1 Input (alternate pin B)
T6OUT GPT2 Timer T6 Toggle Latch Output,
RxD1 ASC1 Data Input (Async.) or Inp./Outp. (Sync.),
EX1IN Fast External Interrupt 1 Input (alternate pin A)
CAPIN GPT2 Register CAPREL Capture Input
T3OUT GPT1 Timer T3 Toggle Latch Output
T3EUD GPT1 Timer T3 External Up/Down Control Input
T4IN GPT1 Timer T4 Count/Gate/Reload/Capture Inp
T3IN GPT1 Timer T3 Count/Gate Input
T2IN GPT1 Timer T2 Count/Gate/Reload/Capture Inp
MRST0 SSC0 Master-Receive/Slave-Transmit In/Out.
MTSR0 SSC0 Master-Transmit/Slave-Receive Out/In.
TxD0 ASC0 Clock/Data Output (Async./Sync.),
EX2IN Fast External Interrupt 2 Input (alternate pin B)
RxD0 ASC0 Data Input (Async.) or Inp./Outp. (Sync.),
EX2IN Fast External Interrupt 2 Input (alternate pin A)
BHE
WRH

External Memory High Byte Enable Signal,

External Memory High Byte Write Strobe,
EX3IN Fast External Interrupt 3 Input (alternate pin B)
SCLK0 SSC0 Master Clock Output/Slave Clock Input.,
EX3IN Fast External Interrupt 3 Input (alternate pin A)
CLKOUT Master Clock Output,
FOUT Programmable Frequency Output

TCK 71 I Debug System: JTAG Clock Input

TDI 72 I Debug System: JTAG Data In

TDO 73 O Debug System: JTAG Data Out

TMS 74 I Debug System: JTAG Test Mode Selection

Data Sheet 14 V1.2, 2006-03

Table 2 Pin Definitions and Functions (cont’d)

XC167-16

Derivatives

General Device Information

Sym­bol

P4

P4.0
P4.1
P4.2
P4.3
P4.4

P4.5

P4.6

P4.7

Pin
Num.

80
81
82
83
84

85

86

87

Input
Outp.

IO

O
O
O
O
O
I
I
O
I
I
O
O
I
O
I
O
I

Function

Port 4 is an 8-bit bidirectional I/O port. Each pin can be
programmed for input (output driver in high-impedance
state) or output (configurable as push/pull or open drain
driver). The input threshold of Port 4 is selectable (standard
or special).
Port 4 can be used to output the segment address lines, the
optional chip select lines, and for serial interface lines:

1)

A16 Least Significant Segment Address Line
A17 Segment Address Line
A18 Segment Address Line
A19 Segment Address Line
A20 Segment Address Line,
CAN2_RxD CAN Node 2 Receive Data Input,
EX5IN Fast External Interrupt 5 Input (alternate pin B)
A21 Segment Address Line,
CAN1_RxD CAN Node 1 Receive Data Input,
EX4IN Fast External Interrupt 4 Input (alternate pin B)
A22 Segment Address Line,
CAN1_TxD CAN Node 1 Transmit Data Output,
EX5IN Fast External Interrupt 5 Input (alternate pin A)
A23 Most Significant Segment Address Line,
CAN1_RxD CAN Node 1 Receive Data Input,
CAN2_TxD CAN Node 2 Transmit Data Output,
EX4IN Fast External Interrupt 4 Input (alternate pin A)

Data Sheet 15 V1.2, 2006-03

Table 2 Pin Definitions and Functions (cont’d)

XC167-16

Derivatives

General Device Information

Sym­bol

P20

P20.0

P20.1

P20.2

P20.4

P20.5

P20.12

Pin
Num.

90

91

92

93

94

3

Input
Outp.

IO

O

O

I

O

I

O

Function

Port 20 is a 6-bit bidirectional I/O port. Each pin can be
programmed for input (output driver in high-impedance
state) or output. The input threshold of Port 20 is selectable
(standard or special).
The following Port 20 pins also serve for alternate functions:
RD

External Memory Read Strobe, activated for

every external instruction or data read access.
WR

/WRL External Memory Write Strobe.

In WR

-mode this pin is activated for every
external data write access.
In WRL

-mode this pin is activated for low byte
data write accesses on a 16-bit bus, and for
every data write access on an 8-bit bus.

READY READY Input. When the READY function is

enabled, memory cycle time waitstates can be
forced via this pin during an external access.

ALE Address Latch Enable Output.

Can be used for latching the address into
external memory or an address latch in the
multiplexed bus modes.

EA

External Access Enable pin.
A low-level at this pin during and after Reset
forces the XC167 to latch the configuration from
PORT0 and pin RD

, and to begin instruction

execution out of external memory.
A high-level forces the XC167 to latch the
configuration from pins RD

, ALE, and WR, and
to begin instruction execution out of the internal
program memory. “ROMless” versions must
have this pin tied to ‘0’.

RSTOUT

Internal Reset Indication Output.
Is activated asynchronously with an external
hardware reset. It may also be activated
(selectable) synchronously with an internal
software or watchdog reset.
Is deactivated upon the execution of the EINIT
instruction, optionally at the end of reset, or at
any time (before EINIT) via user software.

Note: Port 20 pins may input configuration values (see EA

Data Sheet 16 V1.2, 2006-03

).

Table 2 Pin Definitions and Functions (cont’d)

XC167-16

Derivatives

General Device Information

Sym­bol

PORT0

P0L.0 ­P0L.7,
P0H.0,
P0H.1,
P0H.2 ­P0H.7

Pin
Num.

95 ­102,
105,
106,
111 ­116

Input

Function

Outp.

IO PORT0 consists of the two 8-bit bidirectional I/O ports P0L

and P0H. Each pin can be programmed for input (output
driver in high-impedance state) or output.
In case of an external bus configuration, PORT0 serves as
the address (A) and address/data (AD) bus in multiplexed
bus modes and as the data (D) bus in demultiplexed bus
modes.

Demultiplexed bus modes:

8-bit data bus: P0H = I/O, P0L = D7 - D0
16-bit data bus: P0H = D15 - D8, P0L = D7 - D0

Multiplexed bus modes:

8-bit data bus: P0H = A15 - A8, P0L = AD7 - AD0
16-bit data bus: P0H = AD15 - AD8, P0L = AD7 - AD0

Note: At the end of an external reset (EA

= 0) PORT0 also

may input configuration values.

Data Sheet 17 V1.2, 2006-03

Table 2 Pin Definitions and Functions (cont’d)

XC167-16

Derivatives

General Device Information

Sym­bol

PORT1

P1L.0
P1L.1
P1L.2
P1L.3
P1L.4
P1L.5
P1L.6
P1L.7

P1H.0

P1H.1

P1H.2

P1H.3

P1H.4
P1H.5
P1H.6
P1H.7

Pin
Num.

117
118
119
120
121
122
123
124

127

128

129

130

131
132
133
134

Input
Outp.

IO

I/O
O
I/O
O
I/O
O
O
I

I/O
I
I
I/O
I
I/O
I
I/O
I/O
I
I/O
I/O
I/O
I/O

Function

PORT1 consists of the two 8-bit bidirectional I/O ports P1L
and P1H. Each pin can be programmed for input (output
driver in high-impedance state) or output.
PORT1 is used as the 16-bit address bus (A) in
demultiplexed bus modes (also after switching from a
demultiplexed to a multiplexed bus mode).
The following PORT1 pins also serve for alt. functions:
CC60 CAPCOM6: Input / Output of Channel 0
COUT60 CAPCOM6: Output of Channel 0
CC61 CAPCOM6: Input / Output of Channel 1
COUT61 CAPCOM6: Output of Channel 1
CC62 CAPCOM6: Input / Output of Channel 2
COUT62 CAPCOM6: Output of Channel 2
COUT63 Output of 10-bit Compare Channel
CTRAP

CAPCOM2: CC22 Capture Inp./Compare Outp.
CTRAP

is an input pin with an internal pull-up
resistor. A low level on this pin switches the
CAPCOM6 compare outputs to the logic level
defined by software (if enabled).

CC22IO CAPCOM2: CC22 Capture Inp./Compare Outp.
CC6POS0

CAPCOM6: Position 0 Input,

EX0IN Fast External Interrupt 0 Input (alternate pin B),
CC23IO CAPCOM2: CC23 Capture Inp./Compare Outp.
CC6POS1

CAPCOM6: Position 1 Input,

MRST1 SSC1 Master-Receive/Slave-Transmit In/Out.
CC6POS2

CAPCOM6: Position 2 Input,

MTSR1 SSC1 Master-Transmit/Slave-Receive Out/Inp.
SCLK1 SSC1 Master Clock Output / Slave Clock Input,
EX0IN Fast External Interrupt 0 Input (alternate pin A)
CC24IO CAPCOM2: CC24 Capture Inp./Compare Outp.
CC25IO CAPCOM2: CC25 Capture Inp./Compare Outp.
CC26IO CAPCOM2: CC26 Capture Inp./Compare Outp.
CC27IO CAPCOM2: CC27 Capture Inp./Compare Outp.

Data Sheet 18 V1.2, 2006-03

Table 2 Pin Definitions and Functions (cont’d)

XC167-16

Derivatives

General Device Information

Sym­bol

XTAL2
XTAL1

XTAL3
XTAL4

RSTIN

Pin
Num.

137
138

Input
Outp.

O
I

Function

XTAL2: Output of the main oscillator amplifier circuit
XTAL1: Input to the main oscillator amplifier and input to

the internal clock generator

To clock the device from an external source, drive XTAL1,
while leaving XTAL2 unconnected. Minimum and maximum
high/low and rise/fall times specified in the AC
Characteristics must be observed.

140
141

I
O

XTAL3: Input to the auxiliary (32-kHz) oscillator amplifier
XTAL4: Output of the auxiliary (32-kHz) oscillator

amplifier circuit

To clock the device from an external source, drive XTAL3,
while leaving XTAL4 unconnected. Minimum and maximum
high/low and rise/fall times specified in the AC
Characteristics must be observed.

142 I Reset Input with Schmitt-Trigger characteristics. A low-level

at this pin while the oscillator is running resets the XC167.
A spike filter suppresses input pulses < 10 ns. Input pulses
> 100 ns safely pass the filter. The minimum duration for a
safe recognition should be 100 ns + 2 CPU clock cycles.

BRK

143 O Debug System: Break Out

OUT

BRKIN

144 I Debug System: Break In

NC 1, 2,

107 ­110

V

V

V

AREF

AGND

DDI

41 – Reference voltage for the A/D converter.

42 – Reference ground for the A/D converter.

48, 78,
135

Note: The reset duration must be sufficient to let the

hardware configuration signals settle.
External circuitry must guarantee low-level at the
RSTIN

pin at least until both power supply voltages

have reached the operating range.

– No connection.

It is recommended not to connect these pins to the PCB.

– Digital Core Supply Voltage (On-Chip Modules):

+2.5 V during normal operation and idle mode.
Please refer to the Operating Conditions.

Data Sheet 19 V1.2, 2006-03

Table 2 Pin Definitions and Functions (cont’d)

XC167-16

Derivatives

General Device Information

Sym­bol

V

DDP

Pin
Num.

6, 20,
28, 58,
88,

Input

Function

Outp.

– Digital Pad Supply Voltage (Pin Output Drivers):

+5 V during normal operation and idle mode.
Please refer to the Operating Conditions.

103,
125

V

V

SSI

SSP

47, 79,
136,
139

5, 19,
27, 89,

– Digital Ground

Connect decoupling capacitors to adjacent
as close as possible to the pins.
All

V

pins must be connected to the ground-line or ground-

–

SS

plane.

104,
126

1) The CAN interface lines are assigned to ports P4, P7, and P9 under software control.

V

DD/VSS

pin pairs

Data Sheet 20 V1.2, 2006-03

XC167-16

Derivatives

Functional Description

3 Functional Description

The architecture of the XC167 combines advantages of RISC, CISC, and DSP
processors with an advanced peripheral subsystem in a very well-balanced way. In
addition, the on-chip memory blocks allow the design of compact systems-on-silicon with
maximum performance (computing, control, communication).

The on-chip memory blocks (program code-memory and SRAM, dual-port RAM, data
SRAM) and the set of generic peripherals are connected to the CPU via separate buses.
Another bus, the LXBus, connects additional on-chip resources as well as external
resources (see Figure 3).

This bus structure enhances the overall system performance by enabling the concurrent
operation of several subsystems of the XC167.

The following block diagram gives an overview of the different on-chip components and
of the advanced, high bandwidth internal bus structure of the XC167.

XTAL

PSRAM DPRAM DSRAM

ProgMem

Flash

128 KBytes

PMU

CPU

DMU

C166SV2-Core

OCDS

Debug Support

Osc / PLL

Clock Generation

ADC

8/10-Bit

Channels

GPT

16

T2
T3
T4

T5
T6

RTC WDT

ASC0

(USAR T)

BRGen

ASC1

(USART)

BRGen

SSC0

(SPI)

BRGen

Interrupt & PEC

SSC1

(SPI)

BRGen

CC1

T0
T1

Interrupt Bus

Peripheral Data Bus

CC2

T7
T8

BRGen

IIC

CC6

EBC

XBUS Control

External Bus

Control

T12
T13

Twin
CAN

A B

P 20

4

66

Port 5

16

PORT1 PORT0Port 2Port 3Port 4Port 6P 7Port 9

81588

16

16

MCB04323_x7.vsd

Figure 3 Block Diagram

Data Sheet 21 V1.2, 2006-03

XC167-16

Derivatives

Functional Description

3.1 Memory Subsystem and Organization

The memory space of the XC167 is configured in a Von Neumann architecture, which
means that all internal and external resources, such as code memory, data memory,
registers and I/O ports, are organized within the same linear address space. This
common memory space includes 16 Mbytes and is arranged as 256 segments of
64 Kbytes each, where each segment consists of four data pages of 16 Kbytes each.
The entire memory space can be accessed bytewise or wordwise. Portions of the
on-chip DPRAM and the register spaces (E/SFR) have additionally been made directly
bitaddressable.

The internal data memory areas and the Special Function Register areas (SFR and
ESFR) are mapped into segment 0, the system segment.

The Program Management Unit (PMU) handles all code fetches and, therefore, controls
accesses to the program memories, such as Flash memory and PSRAM.

The Data Management Unit (DMU) handles all data transfers and, therefore, controls
accesses to the DSRAM and the on-chip peripherals.

Both units (PMU and DMU) are connected via the high-speed system bus to exchange
data. This is required if operands are read from program memory, code or data is written
to the PSRAM, code is fetched from external memory, or data is read from or written to
external resources, including peripherals on the LXBus (such as TwinCAN). The system
bus allows concurrent two-way communication for maximum transfer performance.

128 Kbytes of on-chip Flash memory store code or constant data. The on-chip Flash
memory is organized as four 8-Kbyte sectors, one 32-Kbyte sector, and one 64-Kbyte
sector. Each sector can be separately write protected

1)

, erased and programmed (in
blocks of 128 Bytes). The complete Flash area can be read-protected. A password
sequence temporarily unlocks protected areas. The Flash module combines very fast
64-bit one-cycle read accesses with protected and efficient writing algorithms for
programming and erasing. Thus, program execution out of the internal Flash results in
maximum performance. Dynamic error correction provides extremely high read data
security for all read accesses.
For timing characteristics, please refer to Section 4.4.2.

2 Kbytes of on-chip Program SRAM (PSRAM) are provided to store user code or data.
The PSRAM is accessed via the PMU and is therefore optimized for code fetches.

4 Kbytes of on-chip Data SRAM (DSRAM) are provided as a storage for general user
data. The DSRAM is accessed via the DMU and is therefore optimized for data
accesses.

2 Kbytes of on-chip Dual-Port RAM (DPRAM) are provided as a storage for user
defined variables, for the system stack, and general purpose register banks. A register
bank can consist of up to 16 wordwide (R0 to R15) and/or bytewide (RL0, RH0, …, RL7,

1) Each two 8-Kbyte sectors are combined for write-protection purposes.

Data Sheet 22 V1.2, 2006-03

XC167-16

Derivatives

Functional Description

RH7) so-called General Purpose Registers (GPRs).
The upper 256 bytes of the DPRAM are directly bitaddressable. When used by a GPR,
any location in the DPRAM is bitaddressable.

1024 bytes (2 × 512 bytes) of the address space are reserved for the Special Function
Register areas (SFR space and ESFR space). SFRs are wordwide registers which are
used for controlling and monitoring functions of the different on-chip units. Unused SFR
addresses are reserved for future members of the XC166 Family. Therefore, they should
either not be accessed, or written with zeros, to ensure upward compatibility.

In order to meet the needs of designs where more memory is required than is provided
on chip, up to 12 Mbytes (approximately, see Table 3) of external RAM and/or ROM can
be connected to the microcontroller. The External Bus Interface also provides access to
external peripherals.

Table 3 XC167 Memory Map

1)

Address Area Start Loc. End Loc. Area Size

Flash register space FF’F000

Reserved (Access trap) F8’0000

Reserved for PSRAM E0’0800

Program SRAM E0’0000

Reserved for pr. mem. C2’0000

Program Flash C0’0000

Reserved BF’0000

External memory area 40’0000

External IO area

4)

20’0800

TwinCAN registers 20’0000

External memory area 01’0000

H

H

H

H

H

H

H

H

H

H

H

FF’FFFF

FF’EFFF

F7’FFFF

E0’07FF

DF’FFFF

C1’FFFF

BF’FFFF

BE’FFFF

3F’FFFF

20’07FF

1F’FFFF

4 Kbytes

H

< 0.5 Mbytes Minus Flash

H

< 1.5 Mbytes Minus PSRAM

H

2 Kbytes Maximum

H

< 2 Mbytes Minus Flash

H

128 Kbytes –

H

64 Kbytes –

H

< 8 Mbytes Minus reserved

H

< 2 Mbytes Minus TwinCAN

H

2 Kbytes –

H

< 2 Mbytes Minus segment 0

H

2)

Notes

3)

registers

segment

Data RAMs and SFRs 00’8000

External memory area 00’0000

1) Accesses to the shaded areas generate external bus accesses.

2) The areas marked with “<” are slightly smaller than indicated, see column “Notes”.

3) Not defined register locations return a trap code.

4) Several pipeline optimizations are not active within the external IO area. This is necessary to control external

peripherals properly.

Data Sheet 23 V1.2, 2006-03

H

H

00’FFFF

00’7FFF

32 Kbytes Partly used

H

32 Kbytes –

H

XC167-16

Derivatives

Functional Description

3.2 External Bus Controller

All of the external memory accesses are performed by a particular on-chip External Bus
Controller (EBC). It can be programmed either to Single Chip Mode when no external
memory is required, or to one of four different external memory access modes
are as follows:

• 16 … 24-bit Addresses, 16-bit Data, Demultiplexed

• 16 … 24-bit Addresses, 16-bit Data, Multiplexed

• 16 … 24-bit Addresses, 8-bit Data, Multiplexed

• 16 … 24-bit Addresses, 8-bit Data, Demultiplexed

In the demultiplexed bus modes, addresses are output on PORT1 and data is
input/output on PORT0 or P0L, respectively. In the multiplexed bus modes both
addresses and data use PORT0 for input/output. The high order address (segment) lines
use Port 4. The number of active segment address lines is selectable, restricting the
external address space to 8 Mbytes … 64 Kbytes. This is required when interface lines
are assigned to Port 4.

1)

, which

Up to 5 external CS

signals (4 windows plus default) can be generated in order to save
external glue logic. External modules can directly be connected to the common
address/data bus and their individual select lines.

Access to very slow memories or modules with varying access times is supported via a
particular ‘Ready’ function. The active level of the control input signal is selectable.

A HOLD

/HLDA protocol is available for bus arbitration and allows the sharing of external
resources with other bus masters. The bus arbitration is enabled by software. After
enabling, pins P6.7 … P6.5 (BREQ
EBC. In Master Mode (default after reset) the HLDA
HLDA

is switched to input. This allows the direct connection of the slave controller to

, HLDA, HOLD) are automatically controlled by the

pin is an output. In Slave Mode pin

another master controller without glue logic.

Important timing characteristics of the external bus interface have been made
programmable (via registers TCONCSx/FCONCSx) to allow the user the adaption of a
wide range of different types of memories and external peripherals.

In addition, up to 4 independent address windows may be defined (via registers
ADDRSELx) which control the access to different resources with different bus
characteristics. These address windows are arranged hierarchically where window 4
overrides window 3, and window 2 overrides window 1. All accesses to locations not
covered by these 4 address windows are controlled by TCONCS0/FCONCS0. The
currently active window can generate a chip select signal.

The external bus timing is related to the rising edge of the reference clock output
CLKOUT. The external bus protocol is compatible with that of the standard C166 Family.

1) Bus modes are switched dynamically if several address windows with different mode settings are used.

Data Sheet 24 V1.2, 2006-03

XC167-16

Derivatives

Functional Description

The EBC also controls accesses to resources connected to the on-chip LXBus. The
LXBus is an internal representation of the external bus and allows accessing integrated
peripherals and modules in the same way as external components.

The TwinCAN module is connected and accessed via the LXBus.

Data Sheet 25 V1.2, 2006-03