INFINEON XC164CM User Manual

Data Sheet, V1.2, March 2006

XC164CM

16-Bit Single-Chip Microcontroller with C166SV2 Core

Microcontrollers

Edition 2006-03

Published by Infineon Technologies AG 81726 München, Germany

Legal Disclaimer

The information given in this document shall in no event be regarded as a guarantee of conditions or characteristics (“Beschaffenheitsgarantie”). With respect to any examples or hints given herein, any typical values stated herein and/or any information regarding the application of the device, Infineon Technologies hereby disclaims any and all warranties and liabilities of any kind, including without limitation warranties of noninfringement of intellectual property rights of any third party.

Information

For further information on technology, delivery terms and conditions and prices please contact your nearest Infineon Technologies Office (www.infineon.com).

Warnings

Due to technical requirements components may contain dangerous substances. For information on the types in question please contact your nearest Infineon Technologies Office.

Infineon Technologies Components may only be used in life-support devices or systems with the express written approval of Infineon Technologies, if a failure of such components can reasonably be expected to cause the failure of that life-support device or system, or to affect the safety or effectiveness of that device or system. Life support devices or systems are intended to be implanted in the human body, or to support and/or maintain and sustain and/or protect human life. If they fail, it is reasonable to assume that the health of the user or other persons may be endangered.

Data Sheet, V1.2, March 2006

XC164CM

16-Bit Single-Chip Microcontroller with C166SV2 Core

Microcontrollers

XC164CM Revision History: V1.2, 2006-03

Previous Version(s): V1.1, 2005-11 (intermediate version) V1.0, 2005-05

Page Subjects

Major Changes from V1.1 to V1.2

all Document reworked according to documentation rules

8, 29 Figures reworked according to drawing rules

48 Section “Quality Declarations” replaced by footnote

Major Changes from V1.0 to V1.1

XC164CM

Derivatives

5, 16, 17 Flash memory differences between 8F and 4F variants stated explicitly

17 Joined adjacent reserved address spaces

7 Added Temperature Range in Table 1

8, 14 Corrected usage of

10 Added missing pin numbers for

Added missing V Fixed pin numbers of TRST

DDI

pins

symbol

AREF

, RSTIN and NMI

and V

AGND

Removed negation of XTAL1 and XTAL2 Added notes on configuration values for P1H.4, P1H.5, P9.4, P9.5

21 Corrected EXxIN and SSC1 Transmit Interrupt Trap Numbers, Control

Registers and Vector Locations

51 Added

CPUH

and I

parameters

CPUL

52 Added note on increased leakage current of P3.15

53 Corrected

parameter value

DDI

53 Removed reference to auxiliary oscillator

55 Removed

PDAmax

from Figure 12

55 Replaced IPDO with IPDL in Figure 13

62 Added On-chip Flash Operation chapter (Chapter 4.4.2)

Data Sheet V1.2, 2006-03

XC164CM

Derivatives

We Listen to Your Comments

Any information within this document that you feel is wrong, unclear or missing at all? Your feedback will help us to continuously improve the quality of this document. Please send your proposal (including a reference to this document) to:

mcdocu.comments@infineon.com

Data Sheet V1.2, 2006-03

XC164CM

Derivatives

Table of Contents

1 Summary of Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5

2 General Device Information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8

2.1 Pin Configuration and Definition . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9

3 Functional Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15

3.1 Memory Subsystem and Organization . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16

3.2 Central Processing Unit (CPU) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18

3.3 Interrupt System . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20

3.4 On-Chip Debug Support (OCDS) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25

3.5 Capture/Compare Unit (CAPCOM2) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26

3.6 The Capture/Compare Unit CAPCOM6 . . . . . . . . . . . . . . . . . . . . . . . . . . . 29

3.7 General Purpose Timer (GPT12E) Unit . . . . . . . . . . . . . . . . . . . . . . . . . . . 30

3.8 Real Time Clock . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 34

3.9 A/D Converter . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 36

3.10 Asynchronous/Synchronous Serial Interfaces (ASC0/ASC1) . . . . . . . . . . 37

3.11 High Speed Synchronous Serial Channels (SSC0/SSC1) . . . . . . . . . . . . 38

3.12 TwinCAN Module . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 39

3.13 LXBus Controller (EBC) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 40

3.14 Watchdog Timer . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 41

3.15 Clock Generation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 42

3.16 Parallel Ports . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 43

3.17 Power Management . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 44

3.18 Instruction Set Summary . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 45

4 Electrical Parameters . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 48

4.1 General Parameters . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 48

4.2 DC Parameters . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 51

4.3 Analog/Digital Converter Parameters . . . . . . . . . . . . . . . . . . . . . . . . . . . . 56

4.4 AC Parameters . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 59

4.4.1 Definition of Internal Timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 59

4.4.2 On-chip Flash Operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 62

4.4.3 External Clock Drive XTAL1 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 64

5 Package and Reliability . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 65

5.1 Packaging . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 65

5.2 Flash Memory Parameters . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 66

Data Sheet 4 V1.2, 2006-03

XC164CM16-Bit Single-Chip Microcontroller with C166SV2 Core

XC166 Family

1 Summary of Features

For a quick overview or reference, the XC164CM’s properties are listed here in a condensed way.

• High Performance 16-bit CPU with 5-Stage Pipeline – 25 ns Instruction Cycle Time at 40 MHz CPU Clock (Single-Cycle Execution) – 1-Cycle Multiplication (16 × 16 bit), Background Division (32 / 16 bit) in 21 Cycles – 1-Cycle Multiply-and-Accumulate (MAC) Instructions – Enhanced Boolean Bit Manipulation Facilities – Zero-Cycle Jump Execution – Additional Instructions to Support HLL and Operating Systems – Register-Based Design with Multiple Variable Register Banks – Fast Context Switching Support with Two Additional Local Register Banks – 16 Mbytes Total Linear Address Space for Code and Data – 1024 Bytes On-Chip Special Function Register Area (C166 Family Compatible)

• 16-Priority-Level Interrupt System with up to 63 Sources, Sample-Rate down to 50 ns

• 8-Channel Interrupt-Driven Single-Cycle Data Transfer Facilities via Peripheral Event Controller (PEC), 24-Bit Pointers Cover Total Address Space

• Clock Generation via on-chip PLL (factors 1:0.15 … 1:10), or via Prescaler (factors 1:1 … 60:1)

• On-Chip Memory Modules – 2 Kbytes On-Chip Dual-Port RAM (DPRAM) – 2 Kbytes On-Chip Data SRAM (DSRAM, XC164CM-8F only) – 2 Kbytes On-Chip Program/Data SRAM (PSRAM) – 64 Kbytes (XC164CM-8F) or 32 Kbytes (XC164CM-4F) On-Chip Program Memory

(Flash Memory)

• On-Chip Peripheral Modules – 14-Channel A/D Converter with Programmable Resolution (10-bit or 8-bit) and

Conversion Time (down to 2.55 µs or 2.15 µs) – 16-Channel General Purpose Capture/Compare Unit (CAPCOM2) – Capture/Compare Unit for flexible PWM Signal Generation (CAPCOM6) – Multi-Functional General Purpose Timer Unit with 5 Timers – Two Synchronous/Asynchronous Serial Channels (USARTs) – Two High-Speed-Synchronous Serial Channels – On-Chip TwinCAN Interface (Rev. 2.0B active) with 32 Message Objects

(Full CAN/Basic CAN) on Two CAN Nodes, and Gateway Functionality – On-Chip Real Time Clock, Driven by the Main Oscillator

• Idle, Sleep, and Power Down Modes with Flexible Power Management

Data Sheet 5 V1.2, 2006-03

XC164CM

Derivatives

Summary of Features

• Programmable Watchdog Timer and Oscillator Watchdog

• Up to 47 General Purpose I/O Lines, partly with Selectable Input Thresholds and Hysteresis

• On-Chip Bootstrap Loader

• On-Chip Debug Support via JTAG Interface

Ordering Information

The ordering code for Infineon microcontrollers provides an exact reference to the required product. This ordering code identifies:

• the derivative itself, i.e. its function set, the temperature range, and the supply voltage

• the package and the type of delivery.

For the available ordering codes for the XC164CM please refer to the “Product Catalog Microcontrollers”, which summarizes all available microcontroller variants.

This document describes several derivatives of the XC164CM group. Table 1 enumerates these derivatives and summarizes the differences. As this document refers to all of these derivatives, some descriptions may not apply to a specific product.

For simplicity all versions are referred to by the term XC164CM throughout this document.

Data Sheet 6 V1.2, 2006-03

Table 1 XC164CM Derivative Synopsis

Derivative

Temp. Range

Program Memory

XC164CM

Derivatives

Summary of Features

On-Chip RAM Interfaces

SAK-XC164CM-8F40F SAK-XC164CM-8F20F

-40 to 125 °C 64 Kbytes Flash

2 Kbytes DPRAM, 2 Kbytes DSRAM, 2 Kbytes PSRAM

SAF-XC164CM-8F40F SAF-XC164CM-8F20F

-40 to 85 °C 64 Kbytes Flash

2 Kbytes DPRAM, 2 Kbytes DSRAM, 2 Kbytes PSRAM

SAK-XC164CM-4F40F SAK-XC164CM-4F20F

SAF-XC164CM-4F40F SAF-XC164CM-4F20F

1) This Data Sheet is valid for devices starting with and including design step AA.

-40 to 125 °C 32 Kbytes Flash

-40 to 85 °C 32 Kbytes Flash

2 Kbytes DPRAM, 2 Kbytes PSRAM

ASC0, ASC1, SSC0, SSC1, CAN0, CAN1

Data Sheet 7 V1.2, 2006-03

XC164CM

Derivatives

General Device Information

2 General Device Information

The XC164CM derivatives are high-performance members of the Infineon XC166 Family of full featured single-chip CMOS microcontrollers. These devices extend the functionality and performance of the C166 Family in terms of instructions (MAC unit), peripherals, and speed. They combine high CPU performance (up to 40 million instructions per second) with high peripheral functionality and enhanced IO-capabilities. They also provide clock generation via PLL and various on-chip memory modules such as program Flash, program RAM, and data RAM.

XTAL1

XTAL2

NMI

RSTIN Port 5

14 bit

Figure 1 Logic Symbol

AREF

AGND

XC164CM

DDI/P

MCA05554_XC164CM

PORT1 14 bit

Port 3 13 bit

Port 9 6 bit

TRST

Data Sheet 8 V1.2, 2006-03

XC164CM

Derivatives

General Device Information

2.1 Pin Configuration and Definition

The pins of the XC164CM are described in detail in Table 2, including all their alternate functions. Figure 2 summarizes all pins in a condensed way, showing their location on the 4 sides of the package. E* marks pins to be used as alternate external interrupt inputs.

P1H.0/CC6POS0/EX0IN/CC23IO

P1H.1/CC6POS1/EX1IN/MRST1 P1H.2/CC6POS2/EX2IN/MTRS1

P1 H. 3/ EX3I N/ T7 IN /SC LK1

P1H.4/CC24IO/EX4IN

P5.0/AN0 P5.1/AN1

P5.2/AN2 P5.3/AN3

P5.4/AN4 P5.5/AN5

DDP

P5 .1 0/ AN1 0/ T6 EUD P5 .1 1/ AN1 1/ T5 EUD

1 2 3 4 5 6 7

8 9 10 11 12 13 14

15 16

DDPVDDIVSS

P1L.7/CTRAP/CC22IO

TRST

RSTIN

NMI

XTA L1

XTA L2

P1L.6/COUT63

P1L.3/COUT61

P1L.4/CC62

P1L.5/COUT62

XC164CM

DDI

DDP

AR EF

AG ND

P5 .6 /AN6

P5 .7 /AN7

P1L.0/CC60

P1L.1/COUT60

P1L.2/CC61

49505152535455565758596061626364

P9.5/CC21IO

P9.4/CC20IO

47 46

P9.3/CC19IO/CAN1_TxD P9.2/CC18IO/CAN1_RxD/E

P9.1/CC17IO/CAN2_TxD

P9.0/CC16IO/CAN2_RxD/E

43 42

P3.15/CLKOUT/FOUT

DDP

P3.13/SCLK0/E*

P3.11/RxD0/E* P3.10/TxD0/E*

P3.9/MTSR0

P3.8/MRST0

P3.7/T2IN/BRKIN

34 33

32313029282726252423222120191817

P3.6/T3IN

P5. 12/AN1 2/ T6IN

P5. 13/AN1 3/ T5IN

P5.14/AN14/T4EUD

P5.15/AN15/T2EUD

P3.2/CAPIN/TDI

P3.3/T3OUT/TDO

P3.4/T3EUD/TMS

P3.1/T 6OUT/RxD1/TCK/E*

P3.5/T4IN/TxD1/BRKOUT

mc_xc 164cm _pinout .vs d

Figure 2 Pin Configuration (top view)

Data Sheet 9 V1.2, 2006-03

Table 2 Pin Definitions and Functions

XC164CM

Derivatives

General Device Information

Symbol

Pin Num.

Input Outp.

Function

RSTIN 63 I Reset Input with Schmitt-Trigger characteristics. A low-level

at this pin while the oscillator is running resets the XC164CM. A spike filter suppresses input pulses < 10 ns. Input pulses > 100 ns safely pass the filter. The minimum duration for a safe recognition should be 100 ns + 2 CPU clock cycles.

Note: The reset duration must be sufficient to let the

hardware configuration signals settle. External circuitry must guarantee low-level at the RSTIN

pin at least until both power supply voltages

have reached the operating range.

NMI

64 I Non-Maskable Interrupt Input. A high to low transition at this

pin causes the CPU to vector to the NMI trap routine. When the PWRDN (power down) instruction is executed, the NMI pin must be low in order to force the XC164CM into power down mode. If NMI

is high, when PWRDN is executed, the part will continue to run in normal mode. If not used, pin NMI

should be pulled high externally.

Port 9

P9.0

P9.1

P9.2

P9.3

P9.4 P9.5

43-48

47 48

I/O I I I/O O I/O I I I/O O I/O I/O

Port 9 is a 6-bit bidirectional I/O port. Each pin can be programmed for input (output driver in high-impedance state) or output (configurable as push/pull or open drain driver). The input threshold of Port 9 is selectable (standard or special). The following Port 9 pins also serve for alternate functions: CC16IO: (CAPCOM2) CC16 Capture Inp./Compare Outp., CAN2_RxD: (CAN Node 2) Receive Data Input

, EX5IN: (Fast External Interrupt 5) Input (alternate pin B) CC17IO: (CAPCOM2) CC17 Capture Inp./Compare Outp., CAN2_TxD: (CAN Node 2) Transmit Data Output, CC18IO: (CAPCOM2) CC18 Capture Inp./Compare Outp., CAN1_RxD: (CAN Node 1) Receive Data Input

, EX4IN: (Fast External Interrupt 4) Input (alternate pin B) CC19IO: (CAPCOM2) CC19 Capture Inp./Compare Outp., CAN1_TxD: (CAN Node 1) Transmit Data Output, CC20IO: (CAPCOM2) CC20 Capture Inp./Compare Outp. CC21IO: (CAPCOM2) CC21 Capture Inp./Compare Outp.

Note: At the end of an external reset P9.4 and P9.5 also may

input startup configuration values.

Data Sheet 10 V1.2, 2006-03

Table 2 Pin Definitions and Functions (cont’d)

XC164CM

Derivatives

General Device Information

Symbol

Port 5

P5.0 P5.1 P5.2 P5.3 P5.4 P5.5 P5.10 P5.11 P5.6 P5.7 P5.12 P5.13 P5.14 P5.15

Pin Num.

9-18, 21-24

9 10 11 12 13 14 15 16 17 18 21 22 23 24

Input Outp.

I I I I I I I I I I I I I I

Function

Port 5 is a 14-bit input-only port. The pins of Port 5 also serve as analog input channels for the A/D converter, or they serve as timer inputs: AN0 AN1 AN2 AN3 AN4 AN5 AN10 (T6EUD): GPT2 Timer T6 Ext. Up/Down Ctrl. Inp. AN11 (T5EUD): GPT2 Timer T5 Ext. Up/Down Ctrl. Inp. AN6 AN7 AN12 (T6IN): GPT2 Timer T6 Count/Gate Input AN13 (T5IN): GPT2 Timer T5 Count/Gate Input AN14 (T4EUD): GPT1 Timer T4 Ext. Up/Down Ctrl. Inp. AN15 (T2EUD): GPT1 Timer T2 Ext. Up/Down Ctrl. Inp.

TRST

62 I Test-System Reset Input. A high level at this pin activates the

XC164CM’s debug system. For normal system operation, pin TRST

should be held low.

Data Sheet 11 V1.2, 2006-03

Table 2 Pin Definitions and Functions (cont’d)

XC164CM

Derivatives

General Device Information

Symbol

Port 3

P3.1

P3.2

P3.3

P3.4

P3.5

P3.6 P3.7

P3.8 P3.9 P3.10

P3.11

P3.13

P3.15

Pin Num.

28-39, 42

33 34

35 36 37

Input Outp.

O I/O I I I I O O I I I O O I I I I/O I/O O I I/O I I/O I O O

Function

Port 3 is a 13-bit bidirectional I/O port. Each pin can be programmed for input (output driver in high-impedance state) or output (configurable as push/pull or open drain driver). The input threshold of Port 3 is selectable (standard or special).The following Port 3 pins also serve for alternate functions: T6OUT: [GPT2] Timer T6 Toggle Latch Output, RxD1: [ASC1] Data Input (Async.) or Inp./Outp. (Sync.), EX1IN: [Fast External Interrupt 1] Input (alternate pin A), TCK: [Debug System] JTAG Clock Input CAPIN: [GPT2] Register CAPREL Capture Input, TDI: [Debug System] JTAG Data In T3OUT: [GPT1] Timer T3 Toggle Latch Output, TDO: [Debug System] JTAG Data Out T3EUD: [GPT1] Timer T3 External Up/Down Control Input, TMS: [Debug System] JTAG Test Mode Selection T4IN: [GPT1] Timer T4 Count/Gate/Reload/Capture Inp. TxD1: [ASC0] Clock/Data Output (Async./Sync.), BRKOUT

: [Debug System] Break Out T3IN: [GPT1] Timer T3 Count/Gate Input T2IN: [GPT1] Timer T2 Count/Gate/Reload/Capture Inp. BRKIN

: [Debug System] Break In MRST0: [SSC0] Master-Receive/Slave-Transmit In/Out. MTSR0: [SSC0] Master-Transmit/Slave-Receive Out/In. TxD0: [ASC0] Clock/Data Output (Async./Sync.), EX2IN: [Fast External Interrupt 2] Input (alternate pin B) RxD0: [ASC0] Data Input (Async.) or Inp./Outp. (Sync.), EX2IN: [Fast External Interrupt 2] Input (alternate pin A) SCLK0: [SSC0] Master Clock Output / Slave Clock Input., EX3IN: [Fast External Interrupt 3] Input (alternate pin A) CLKOUT: System Clock Output (= CPU Clock), FOUT: Programmable Frequency Output

Data Sheet 12 V1.2, 2006-03

Table 2 Pin Definitions and Functions (cont’d)

XC164CM

Derivatives

General Device Information

Symbol

PORT1

P1L.0 P1L.1 P1L.2 P1L.3 P1L.4 P1L.5 P1L.6 P1L.7

P1H.0

P1H.1

P1H.2

P1H.3

P1H.4

P1H.5

Pin Num.

1-6, 49-56

49 50 51 52 53 54 55 56

Input Outp.

I/O O I/O O I/O O O I

I/O I I I/O I I I/O I I I/O I I/O I I/O I I/O I

Function

PORT1 consists of one 8-bit and one 6-bit bidirectional I/O port P1L and P1H. Each pin can be programmed for input (output driver in high-impedance state) or output. The following PORT1 pins also serve for alt. functions: CC60: [CAPCOM6] Input / Output of Channel 0 COUT60: [CAPCOM6] Output of Channel 0 CC61: [CAPCOM6] Input / Output of Channel 1 COUT61: [CAPCOM6] Output of Channel 1 CC62: [CAPCOM6] Input / Output of Channel 2 COUT62: [CAPCOM6] Output of Channel 2 COUT63: Output of 10-bit Compare Channel CTRAP

: [CAPCOM6] Trap Input CTRAP is an input pin with an internal pull-up resistor. A low level on this pin switches the CAPCOM6 compare outputs to the logic level defined by software (if enabled). CC22IO: [CAPCOM2] CC22 Capture Inp./Compare Outp. CC6POS0

: [CAPCOM6] Position 0 Input, EX0IN: [Fast External Interrupt 0] Input (default pin), CC23IO: [CAPCOM2] CC23 Capture Inp./Compare Outp. CC6POS1

: [CAPCOM6] Position 1 Input, EX1IN: [Fast External Interrupt 1] Input (default pin), MRST1: [SSC1] Master-Receive/Slave-Transmit In/Out. CC6POS2

: [CAPCOM6] Position 2 Input, EX2IN: [Fast External Interrupt 2] Input (default pin), MTSR1: [SSC1] Master-Transmit/Slave-Receive Out/Inp. T7IN: [CAPCOM2] Timer T7 Count Input, SCLK1: [SSC1] Master Clock Output / Slave Clock Input, EX3IN: [Fast External Interrupt 3] Input (default pin), CC24IO: [CAPCOM2] CC24 Capture Inp./Compare Outp., EX4IN: [Fast External Interrupt 4] Input (default pin) CC25IO: [CAPCOM2] CC25 Capture Inp./Compare Outp., EX5IN: [Fast External Interrupt 5] Input (default pin)

Note: At the end of an external reset P1H.4 and P1H.5 also

may input startup configuration values

Data Sheet 13 V1.2, 2006-03

Table 2 Pin Definitions and Functions (cont’d)

XC164CM

Derivatives

General Device Information

Symbol

Pin Num.

XTAL2 XTAL16160

AREF

AGND

DDI

DDP

19 – Reference voltage for the A/D converter

20 – Reference ground for the A/D converter

26, 58 – Digital Core Supply Voltage (On-Chip Modules):

8, 27, 40, 57

Input

Function

Outp.

O I

XTAL2: Output of the oscillator amplifier circuit XTAL1: Input to the oscillator amplifier and input to the internal clock generator To clock the device from an external source, drive XTAL1, while leaving XTAL2 unconnected. Minimum and maximum high/low and rise/fall times specified in the AC Characteristics must be observed.

+2.5 V during normal operation and idle mode. Please refer to the Operating Condition Parameters

– Digital Pad Supply Voltage (Pin Output Drivers):

+5 V during normal operation and idle mode. Please refer to the Operating Condition Parameters

7, 25, 41, 59

– Digital Ground

Connect decoupling capacitors to adjacent as close as possible to the pins. All

pins must be connected to the ground-line or ground-

plane.

1) The CAN interface lines are assigned to port P9 under software control.

DD/VSS

pin pairs

Data Sheet 14 V1.2, 2006-03

XC164CM

Derivatives

Functional Description

3 Functional Description

The architecture of the XC164CM combines advantages of RISC, CISC, and DSP processors with an advanced peripheral subsystem in a very well-balanced way. In addition, the on-chip memory blocks allow the design of compact systems-on-silicon with maximum performance (computing, control, communication).

The on-chip memory blocks (program code-memory and SRAM, dual-port RAM, data SRAM) and the set of generic peripherals are connected to the CPU via separate buses. Another bus, the LXBus, connects additional on-chip resources (see Figure 3).

This bus structure enhances the overall system performance by enabling the concurrent operation of several subsystems of the XC164CM.

The following block diagram gives an overview of the different on-chip components and of the advanced, high bandwidth internal bus structure of the XC164CM.

XTAL

PSRAM

2 Kbytes

ProgMem

Flash

64 Kbytes (8F device) 32 Kbytes (4F device)

OCDS

Debug Support

Osc / PLL

Clock Generation

ADC

8/10-Bit

Channels

GPT

RTC WDT

ASC0

(USART)

BRGen

ASC1

(USART)

BRGen

PMU

SSC0

(SPI)

BRGen

DPRAM

2 Kbytes

CPU

C166SV2-Core

Inte rrupt & PE C

SSC1

(SPI)

BRGen

DMU

Interrupt Bus

P eripheral D ata Bus

CC2

CC6

T12

T13

DSRAM

2 Kbytes

(8F device)

reduced

LXBus

EBC

Control

Twin

LXB us

CAN

A B

Port 5

PORT1Port 3Port 9

mc_xc164cm_bl ock.vs d

Figure 3 Block Diagram

Data Sheet 15 V1.2, 2006-03

XC164CM

Derivatives

Functional Description

3.1 Memory Subsystem and Organization

The memory space of the XC164CM is configured in a von Neumann architecture, which means that all internal and external resources, such as code memory, data memory, registers and I/O ports, are organized within the same linear address space. This common memory space includes 16 Mbytes and is arranged as 256 segments of 64 Kbytes each, where each segment consists of four data pages of 16 Kbytes each. The entire memory space can be accessed byte wise or word wise. Portions of the on-chip DPRAM and the register spaces (E/SFR) have additionally been made directly bit addressable.

The internal data memory areas and the Special Function Register areas (SFR and ESFR) are mapped into segment 0, the system segment.

The Program Management Unit (PMU) handles all code fetches and, therefore, controls accesses to the program memories, such as Flash memory and PSRAM.

The Data Management Unit (DMU) handles all data transfers and, therefore, controls accesses to the DSRAM and the on-chip peripherals.

Both units (PMU and DMU) are connected via the high-speed system bus to exchange data. This is required if operands are read from program memory, code or data is written to the PSRAM, or data is read from or written to peripherals on the LXBus (such as TwinCAN). The system bus allows concurrent two-way communication for maximum transfer performance.

64 or 32 Kbytes of on-chip Flash memory store code or constant data. The on-chip Flash memory is organized as four 8-Kbyte sectors and one 32-Kbyte (XC164CM-8F only) sector. Each sector can be separately write protected

, erased and programmed (in blocks of 128 Bytes). The complete Flash area can be read-protected. A password sequence temporarily unlocks protected areas. The Flash module combines very fast 64-bit one-cycle read accesses with protected and efficient writing algorithms for programming and erasing. Thus, program execution out of the internal Flash results in maximum performance. Dynamic error correction provides extremely high read data security for all read accesses. Programming typically takes 2 ms per 128-byte block (5 ms max.), erasing a sector typically takes 200 ms (500 ms max.).

2 Kbytes of on-chip Program SRAM (PSRAM) are provided to store user code or data. The PSRAM is accessed via the PMU and is therefore optimized for code fetches.

2 Kbytes of on-chip Data SRAM (DSRAM) are provided as a storage for general user data. The DSRAM is accessed via the DMU and is therefore optimized for data accesses. DSRAM is only available in the XC164CM-8F derivatives.

2 Kbytes of on-chip Dual-Port RAM (DPRAM) are provided as a storage for user defined variables, for the system stack, general purpose register banks. A register bank

1) Each two 8-Kbyte sectors are combined for write-protection purposes.

Data Sheet 16 V1.2, 2006-03

XC164CM

Derivatives

Functional Description

can consist of up to 16 word wide (R0 to R15) and/or byte wide (RL0, RH0, …, RL7, RH7) so-called General Purpose Registers (GPRs). The upper 256 bytes of the DPRAM are directly bit addressable. When used by a GPR, any location in the DPRAM is bit addressable.

1024 bytes (2 × 512 bytes) of the address space are reserved for the Special Function Register areas (SFR space and ESFR space). SFRs are word wide registers which are used for controlling and monitoring functions of the different on-chip units. Unused SFR addresses are reserved for future members of the XC166 Family. Therefore, they should either not be accessed, or written with zeros, to ensure upward compatibility.

Table 3 XC164CM Memory Map

Address Area Start Loc. End Loc. Area Size

Flash register space FF’F000

FF’FFFF

4 Kbytes

Notes

Reserved (Acc. trap) F8’0000

Reserved for PSRAM E0’0800

Program SRAM E0’0000

Reserved for pr. mem. C1’0000

Program Flash C0’0000

C0’0000

Reserved 20’0800

TwinCAN registers 20’0000

Reserved 01’0000

SFR area 00’FE00

Dual-Port RAM 00’F600

Reserved for DPRAM 00’F200

ESFR area 00’F000

XSFR area 00’E000

Reserved 00’C800

FF’FFFF

F7’FFFF

E0’07FF

DF’FFFF

C0’FFFF

C0’7FFF

BF’FFFF

20’07FF

1F’FFFF

00’FFFF

00’FDFF

00’F5FF

00’F1FF

00’EFFF

00’DFFF

508 Kbytes –

< 1.5 Mbytes Minus PSRAM

2 Kbytes –

< 2 Mbytes Minus Flash

64 Kbytes XC164CM-8F

32 Kbytes XC164CM-4F

< 10 Mbytes Minus TwinCAN

2 Kbytes Accessed via EBC

< 2 Mbytes Minus segment 0

0.5 Kbyte –

2 Kbytes –

1 Kbyte –

0.5 Kbyte –

4 Kbytes –

6 Kbytes –

Data SRAM 00’C000

Reserved for DSRAM 00’8000

Reserved 00’0000

1) The areas marked with “<” are slightly smaller than indicated, see column “Notes”.

2) Not defined register locations return a trap code (1E9BH).

00’C7FF

00’BFFF

00’7FFF

2 Kbytes XC164CM-8F only

16 Kbytes –

32 Kbytes –

Data Sheet 17 V1.2, 2006-03

XC164CM

Derivatives

Functional Description

3.2 Central Processing Unit (CPU)

The main core of the CPU consists of a 5-stage execution pipeline with a 2-stage instruction-fetch pipeline, a 16-bit arithmetic and logic unit (ALU), a 32-bit/40-bit multiply and accumulate unit (MAC), a register-file providing three register banks, and dedicated SFRs. The ALU features a multiply and divide unit, a bit-mask generator, and a barrel shifter.

CPU

Prefetch

Branch

Multiply

Unit

FIFO

IDX0 IDX1

QX0 QX1

+/-

Unit

+/-

CSP IP CPUCON1

CPUCON2

Return

Stack

QR0 QR1

+/-

MRW

MCW MSW

IFU

DPP0 DPP1 DPP2 DPP3

Division Unit M ultip ly U n it

MDC PSW

VECSEG

TFR

Injection/

Exception

Handler

SPSEG

SP STKOV STKUN

Bit-Mask-Gen.

Barrel-Shifter

+/-

ADU

PMU

2-Stage

5-Stage

R15 R14

GPRs

R1 R0

Prefetch

Pipeline

R15

R14

GPRs

PSRAM

Flash/ROM

DPRAM

IPIP

R15 R14

GPRs

R1 R0

MAC

MAH

MAL

MDH

ZEROS

MDL

ONES

ALU

Buffer

DMU

DSRAM

EBC

Peripherals

mca04917_x.vsd

Figure 4 CPU Block Diagram

Based on these hardware provisions, most of the XC164CM’s instructions can be executed in just one machine cycle which requires 25 ns at 40 MHz CPU clock. For

Data Sheet 18 V1.2, 2006-03

XC164CM

Derivatives

Functional Description

example, shift and rotate instructions are always processed during one machine cycle independent of the number of bits to be shifted. Also multiplication and most MAC instructions execute in one single cycle. All multiple-cycle instructions have been optimized so that they can be executed very fast as well: for example, a 32-/16-bit division is started within 4 cycles, while the remaining 15 cycles are executed in the background. Another pipeline optimization, the branch target prediction, allows eliminating the execution time of branch instructions if the prediction was correct.

The CPU has a register context consisting of up to three register banks with 16 word wide GPRs each at its disposal. One of these register banks is physically allocated within the on-chip DPRAM area. A Context Pointer (CP) register determines the base address of the active register bank to be accessed by the CPU at any time. The number of register banks is only restricted by the available internal RAM space. For easy parameter passing, a register bank may overlap others.

A system stack of up to 32 Kwords is provided as a storage for temporary data. The system stack can be allocated to any location within the address space (preferably in the on-chip RAM area), and it is accessed by the CPU via the stack pointer (SP) register. Two separate SFRs, STKOV and STKUN, are implicitly compared against the stack pointer value upon each stack access for the detection of a stack overflow or underflow.

The high performance offered by the hardware implementation of the CPU can efficiently be utilized by a programmer via the highly efficient XC164CM instruction set which includes the following instruction classes:

• Standard Arithmetic Instructions

• DSP-Oriented Arithmetic Instructions

• Logical Instructions

• Boolean Bit Manipulation Instructions

• Compare and Loop Control Instructions

• Shift and Rotate Instructions

• Prioritize Instruction

• Data Movement Instructions

• System Stack Instructions

• Jump and Call Instructions

• Return Instructions

• System Control Instructions

• Miscellaneous Instructions

The basic instruction length is either 2 or 4 bytes. Possible operand types are bits, bytes and words. A variety of direct, indirect or immediate addressing modes are provided to specify the required operands.

Data Sheet 19 V1.2, 2006-03

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