Infineon Traveo User Manual

Auto Training: Traveo™ II SDL – restricted

AUTO TRAINING: TRAVEO(TM) II

Sample Driver Library

Rammohan K N (ATV MC BCH)

September 2020

Agenda

What is SDL? What does the SDL include? Supported Toolchain Folder Structure, Drivers, Middleware Startup Sequence

Sample Blinky Main Workspaces – Open, Build, Download, Debug, Run, Pause, Reset, and Stop

External Links Support

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Target Products

Target product list for this training material

Family Category

Series

Code Flash Memory Size

Traveo™

II Automotive Body Controller Entry

CYT2B7

to 1088KB

Traveo

II Automotive Body Controller Entry

CYT2B9

to 2112KB

Traveo

II Automotive Body Controller Entry

CYT2BL

Up to 4160KB

Traveo

II Automotive Body Controller High

CYT3BB/4BB

Up to 4160KB

Traveo

II Automotive Body Controller High

CYT4BF

Up to 8384KB

Traveo

II Automotive Cluster

CYT3DL

Up to 4160KB

Traveo

II Automotive Cluster

CYT4DN

Up to 6336KB

What is SDL

› Infineon’s Sample Driver Library (SDL) simplifies software development for

Traveo™ II devices

– Drivers for the extensive set of peripherals supported – Arm®Cortex®Microcontroller Software Interface Standard (CMSIS) core access header

files directly from the CMSIS 5.0 release

– CMSIS complaint device header files, startup code (platform initialization), and device

configuration header files

– SDL Application Programming Interface Reference Manual – Examples to evaluate various peripherals

› SDL is provided as an executable, tested on Windows 10 with a minimum

installation size requirement of around 350MB.

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Disclaimer

› SDL sample software is available for evaluation purposes only › It does not adhere to any industry standard and it is not a production software › Infineon may, but is not required to, provide technical support for the SDL

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What does the SDL Include

› The SDL contains

– Device-specific header files that provide a complete definition of all peripheral registers

and bits in the device

– CMSIS-compliant startup code to initialize the system after device reset, and transfer the

code execution to main()

– Linker files for each supported device and toolchain (IAR and GHS)

– SVD files with a detailed description of peripherals, registers, fields, and bit values – GRD files to support register level debugging in GHS

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Supported Toolchain

› Green Hills MULTI: 7.1.4, Compiler: 2017.1.4, Probe Version: 5.6.5

– Development Autobuild 5.6 634260/AB as of patch #12996, or higher

– Flash loaders are not available as part of SDL and will be provided on case by case basis

through Infineon Customer Support (since the patches are in GBs, SDL becomes bulky)

› IAR Embedded Workbench for Arm 8.42.1 (EWARM-CD-8421-xxxxx.exe),

IAR I-Jet Debugger

– Flash loaders are available at the location

“\misc\tools\iar\ IAR_EWARM_8421_FlashLoader_Patch_TraveoII”

– Refer to “\misc\tools\iar\Readme_Patch.txt” to update the Traveo II patch for IAR

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SDL Patch for the Tools

› Green Hills Tool Chain

– Install GHS MULTI, set license, and set probe firmware in advance

– Using the scripts tvii_detect.py and multi.irc, in \misc\tools\ghs\debugging\AppData_GHS,

execute the run process

– Copy the files to the <%APPDATA%\GHS> folder

(C:\Users\<LOGIN_NAME>\AppData\Roaming\GHS) on the PC

› IAR Patch: /misc/tools/iar/IAR_EWARM_8421_FlashLoader_Patch_TraveoII.7z

– Copy files of \misc\tools\iar\IAR_EWARM_8421_FlashLoader_Patch_TraveoII.7z to the

IAR install folder (do not copy anything at folder level)

– Restart IAR EWARM – Rebuild All – Download & Debug

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SDL Folder Structure (1/2)

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Path/Folder Description common/ hdr/cmsis CMSIS core access headers common/ src/drivers Drivers common across all the devices

common/ src/mw Middleware common across all the devices

common/ src/startup Tool specific startup code for all the devices docs SDL API Documentation misc/tools GHS/IAR specific flash loaders tviibe1m/tviibe2m/tviibe4m hdr Device specific header files, BSP for TV II Base Board, GPIO assignments hdr/ip Device IP specific headers hdr/mcureg IP Specific Register Addresses

src/drivers Driver source and respective headers specific to TVIIBE1M/2M/4M device

src/examples Code examples in accordance to TVIIBE1M/2M/4M device src/system TVIIBE1M/2M/4M system specific code and system header for clock configurations src/main_cm0plus.c Sample main source file for CM0+ core src/cy_interrupt_map_cm0plus.h User interrupt mapping file used in case “CY_LINK_SYSTEM_IRQ_TABLE_TO_RAM” not defined src/main_cm4.c Sample main source file for CM4 core src/cy_interrupt_map_cm4.h User interrupt mapping file used in case “CY_LINK_SYSTEM_IRQ_TABLE_TO_RAM” not defined tools/ghs GHS MULTI workspaces for SRAM/Flash for CM0+/CM4 cores, linker specific files, CMSIS SVD files, and GRD files

tools/iar IAR workspaces for SRAM/Flash for CM0+/CM4 cores, linker specific files, CMSIS SVD files

SDL Folder Structure (2/2)

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Path/Folder Description tviibh4m/tviibh8m/tviic2d4m/tviic2d6m hdr Device specific header files, BSP for TV II Base Board, GPIO assignments hdr/ip Device IP specific headers hdr/mcureg IP Specific Register Addresses src/drivers Driver source and respective headers specific to TVIIBH4M/TVIIBH8M/TVIIC2D4M/TVIIC2D6M devices src/mw/ Middleware support

src/examples Code examples in accordance device specific

src/system Device system specific code and system header for clock configurations

src/main_cm0plus.c Sample main source file for CM0+ core

src/cy_interrupt_map_cm0plus.h User interrupt mapping file used in case “CY_LINK_SYSTEM_IRQ_TABLE_TO_RAM” not defined

src/main_cm7_0.c Sample main source file for CM7_0 core

src/cy_interrupt_map_cm7_0.h User interrupt mapping file used in case “CY_LINK_SYSTEM_IRQ_TABLE_TO_RAM” not defined

src/main_cm7_1.c Sample main source file for CM7_0 core

src/cy_interrupt_map_cm7_1.h User interrupt mapping file used in case “CY_LINK_SYSTEM_IRQ_TABLE_TO_RAM” not defined tools/ghs

GHS MULTI workspaces for SRAM/Flash for CM0+/CM7_0/CM7_1 cores, linker specific files, CMSIS SVD files, and GRD files

tools/iar IAR workspaces for SRAM/Flash for CM0+/CM7_0/CM7_1 cores, linker specific files, CMSIS SVD files

SDL Drivers (1/3)

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Driver Description API Functionality ADC Analog to Digital Converter Manage ADC operations

Audioss

Sound Subsystem for I2S, DAC, Mixer, PWM,

SG, TDM (TVIIC2D6M only)

Manages I2S, Audio DAC, Mixer, PCM-PWM, Sound Generator, TDM as part of sound

subsystem

AXIDMA M-DMA on AXI bus Memory to memory transfer over AXI bus CAN FD Controller Area Network Flexible Data-Rate Manages Classic and FD operations CPU CPU driver Enables core of CPU specific features CRYPTO Cryptographic Operations Perform cryptographic operations on user-designated data. Available as libraries CXPI Clock eXtension Peripheral Interface Manages communication over CXPI interface

DMA Direct Access Memory

Perform memory-to-memory (M-DMA) and peripheral-to-memory (P-DMA) (and vice versa)

operations

ETHERNET Ethernet Basic ethernet driver supporting automotive and gigabit ethernet PHYs EVTGEN Event Generator Performs event generation for interrupts and triggers in active power mode FLASH Flash Memory Manage code/work flash memory operations FLEXRAY FlexRay Interface Manages FlexRay communication FPDLINK FDP-Link or LVDS Analog LVDS video driver GPIO General Purpose I/O Ports Configure and access device input/output pins GFX_ENV Graphics Environment Setup Sets up the Graphics environment

I2S Inter-IC Sound (TVII-B-H-8M Only)

Manage Inter-IC Sound. I2S is used to send digital audio streaming data to external I2S devices, such as audio codecs or simple DACs. It can also receive digital audio streaming data

SDL Drivers (2/3)

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Driver Description API Functionality

IPC

Inter Process Communication

Manage data transfer between CPUs or processes in a device

LIN

Local Interconnect Network

Provides master and slave data transfer capabilities

LVD

Low Voltage Detection

Provides LVD capabilities

MCWDT

Multi

-counter Watchdog timer

Provides control and status capabilities

MIPICSI2

Video Input

Manage and control analog video inputs

MPU

Memory Protection Unit

Manages the configuration of MPU

PROT

Memory and Peripheral Protection

Manage the MPU, Shared MPU (SMPU), and Peripheral Protection Unit (PPU)

SCB

Serial Communication Block

Manage serial communication as I2C, SPI, or UART

SD_HOST

Secure

Digital Host Controller

Manages SD and eMMC devices

SMART IO

Smart I/O

Configure and access the Smart I/O hardware present between the GPIOs (pins) and HSIOMs (pin muxes) on select device ports. It can be used to perform simple logic operations on peripheral and GPIO signals at the GPIO port

SMIF

Serial Memory Interface

SPI

-based communication interface for interfacing external memory devices to TVII. The SMIF

supports Octal

-SPI, Dual Quad-SPI, Quad-

SPI, DSPI, and SPI. This interface also supports Hyper Bus

interfaces like HyperRAM and HyperFlash devices.

SROM

Internal SROM driver

APIs to support some basic access to SROM System calls

SYSCLK

System Clock

Provides APIs to control and read status of various clocking capabilities of the device

SYSFLT

System Fault

Controls CPUs fault processing Subsystem

SYSINT

System Interrupt

Manage interrupts and exceptions, in conjunction with the CMSIS core NVIC API

SYSLIB

System Library

Utility functions to handle delays, register read/write, asserts, silicon unique ID, and more

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