Infineon TLI493D-A2B6 User Manual

User Manual 1 Ver. 1.11

www.infineon.com/sensors 2019-05-28

TLI493D-A2B6

Low Power 3D Hall Sensor with I2 C Interface

User Manual

About this document

Scope and purpose

This document provides product information and descriptions regarding:

2

•I

C Registers

2

•I

C Interface

• Diagnostic

Intended audience

This document is aimed at engineers and developers of hard and software using the sensor TLI493D-A2B6.

TLI493D-A2B6

Table of contents

Table of contents

1I

2

C Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3

1.1 Registers overview . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3

1.2 Register descriptions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4

1.2.1 Bit types . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4

1.2.2 Measurement data and registers combined in the I

2

1.2.3 Configuration registers combined in the I

1.2.4 Mode registers combined in the I

2

C parity flag “FF” . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8

C parity flag “CF” . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7

2

C parity bit “P” . . . . . . . . . . . . . . . . . . . . . . . . . . 4

1.2.5 Diagnostic, status and version registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10

2I

2.1 I

2

C Interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13

2

C protocol description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13

2.1.1 General description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13

2.1.2 I2C write command . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13

2.1.3 I2C read commands . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17

2.1.3.1 2-byte read command . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17

2.1.3.2 1-byte read command . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17

2.2 Collision avoidance and clock stretching . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19

2.2.1 Collision avoidance (CA bit = 0

2.2.2 Clock stretching (CA bit = 0

2.3 Sensor reset by I

2

C . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21

and INT bit = 0B) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19

B

and INT bit = 1B) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20

B

2.4 Sensor Initialization and Readout example . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22

2.5 Loss of V

impact on I2C bus . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23

DD

3 Diagnostic . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24

3.1 Parity bits and parity flags . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24

3.2 Power-down flags . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24

3.3 Frame Counter . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24

4 Terminology . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25

5 Revision history . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26

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76543210 76543210

Bx (00

)0C

By (01H)0D

Bz (02H)0E

Temp (03H)0F

Bx2 (04H)Config (10

)DTAM X2 CP

w

Temp2 (05H)MOD1 (11

)FP PR CAINT

rw rw rw rw rw rw

rrrrrr

07

MOD 2 (13H)PRD

rw

08

14

09

15

0A

Ver (16H)

Reserved

Reserved

Reserved

Reserved

Reserved

Reserved

TL_mag

Reserved

Reserved Type HWV

Bz (11…4)

Temp (11…4)

r

Bx (3…0) By (3…0)

Bx (11…4)

Reserved

TRIG

r

By (11…4)

Temp (3…2) ID

Reserved

Bz (3…0)

r

Reserved

Reserved

MOD E

r

IICadr

rrw

Colour legend for the Bitmap

Magnetic values Configuration Diagnosis
Temperature values Confi guration bus Res erved bits Parity bits and related registers (colour)

TLI493D-A2B6

I2C Registers

1I

2

C Registers

The TLI493D-A2B6 includes several registers that can be accessed via Inter-Integrated Circuit interface (I2C) to
read data as well as to write and configure settings.

1.1 Registers overview

A bitmap overview is presented in Figure 1. Basically the following sections are available:

• measurement data (green bits in registers 00

• sensor status and diagnostics (grey bits in registers 05

• configuration parameters such as the power mode (orange bits in registers 10

H

r

r

r

till 05H)

H

, 06H, 10H and 11H)

H

H

H

H

H

, 11H and 13H)

H

H

rr

Diag (06H)P FFCF TPD3PD0 12

H

H

Figure 1 TLI493D-A2B6 Bitmap

The diagnostic register 06
and marks the relationship of the sections to this flags with different colored lines/frames around the bit

H

H

0B

H

H

Reserved

contains parity information as a diagnostic mechanism. The bitmap illustrates this

FRM

rw r

H

H

H

H

rw

rr

rw rw

Reserved

rw

contents.

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TLI493D-A2B6

I2C Registers

Table 1 Registers overview

Register name Register long name Address

Bx, By and Bz Magnetic values MSBs 00

Temp Temperature value MSBs 03

Bx2 Magnetic values LSBs 04

Temp2 Temperature and magnetic LSBs and device address 05

Diag Sensor diagnostic and status register 06

Config Configuration register 10

MOD1 Power mode, interrupt, address, parity 11

MOD2 Low Power Mode update rate 13

Ver Version register 16

, 01H, 02

H

H

H

H

H

H

H

H

H

H

1.2 Register descriptions

The I2C registers can be read or written at any time. It is recommended to read measurement data in a
synchronized fashion, i.e. after an interrupt pulse (/INT). This avoids reading inconsistent sensor or diagnostic
data, especially in fast mode. Additionally, several flags can be checked to ensure the register values are
consistent and the ADC was not running at the time of readout.

1.2.1 Bit types

The TLI493D-A2B6 contains read bits, write bits and reserved bits.

Table 2 Bit Types

Abbreviation Function Description

r Read Read-only bits

rw Read Write Readable and writable bit

Reserved Bits that must keep the default values (read prior to write required)

1.2.2 Measurement data and registers combined in the I2C parity bit “P”

The I2C communication of the registers in this chapter is protected with the parity bit “P”, described in the Diag
register with the address 06

To make sure all data is consistent, the registers from 00
Otherwise, the sampled data (X, Y, Z, Temperature) may correspond to different conversion cycles.

. See also Figure 1 - parity bits and related registers.

H

to 06H should be read with the same I2C command.

H

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7 0

Bx, By and Bz (11...4)

7 0

Temp (11...4)

7 0

Bx (3...0)

By (3...0)

43

TLI493D-A2B6

I2C Registers

Magnetic values MSBs

Register names Address Reset Value

Bx, By and Bz 00

01H 02

H

Field Bits Type Description

Bx, By and Bz 7:0 r Bx, By and Bz values

Signed value as two’s complement from the HALL probes in the x, y and z­direction of the magnetic field. Contains the eight Most Significant Bits.
If Bz is deactivated the Bz value is the reset value.

H

80

H

Back to TLI493D-A2B6 Bitmap.

Temperature value MSBs

Register name Address Reset Value

Temp 03

H

80

Field Bits Type Description

Temp 7:0 r Temperature value

Signed value as two’s complement.
If the temperature measurement is deactivated, the Temp value is the
reset value.

Back to TLI493D-A2B6 Bitmap.

H

Magnetic values LSBs

Register name Address Reset Value

Bx2 04

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H

00

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H

7 0

Bz (3...0)

43

Temp (3...2)

ID

65

TLI493D-A2B6

I2C Registers

Field Bits Type Description

Bx 7:4 r Bx value

Signed value as two’s complement from the HALL probes in the x­direction of the magnetic field.
Contains the four Least Significant Bits.

By 3:0 r By value

Signed value as two’s complement from the HALL probes in the y­direction of the magnetic field.
Contains the four Least Significant Bits.

Back to TLI493D-A2B6 Bitmap.

Temperature and magnetic LSBs and device address

Register name Address Reset Value

Temp2 05

H

00

Field Bits Type Description

Temp 7:6 r Temperature value

Signed value as two’s complement.
If the temperature measurement is deactivated, the Temp value is the
reset value.

ID 5:4 r ID

Readback of the sensor ID, from IICadr. µC shall verify the address sent by
the sensor. See Table 4.

Bz 3:0 r Bz value

Signed value as two’s complement from the HALL probes in the z­direction of the magnetic field.
Contains the four Least Significant Bits.
If Bz is deactivated the Bz value is 0

.

H

H

Back to TLI493D-A2B6 Bitmap.

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7 0

CP

6

5

4

3

21

TL_magX2AMDT TRIG

TLI493D-A2B6

I2C Registers

1.2.3 Configuration registers combined in the I2C parity flag “CF”

The I2C communication of the registers in this chapter is protected by the parity bit CF, which is described in
the Diag register with the address 06

Configuration register

Register name Address Reset Value

Config 10

. See also Figure 1 - parity bits and related registers.

H

H

00

H

Field Bits Type Description

DT 7rwDisable Temperature

temperature measurement is enabled.

If 0

B

If 1

temperature measurement is disabled. This means the Bx, By and Bz

B

channels are measured. The Temp channel is disabled and contains the
reset value until a new conversion with Temp is done.

AM 6rwX/Y Angular Measurement

the Bz measurement is enabled.

If 0

B

If 1

and the DT bit = 1B the Bz measurement is disabled. This means the

B

Bx and By channel is measured. The channels Bz and Temp contain the
reset values until a new conversion with Bz and Temp is done.
Note: If the DT bit = 0

, the AM bit don’t care.

B

TRIG 5:4 rw Trigger options

If PR bit = 1

(1-byte read protocol), the TRIG bits define the trigger mode

B

of the device:
If 00

no ADC trigger on read.

B

If 01

ADC trigger on read before first MSB.

B

ADC trigger on read after register 05H.

If 1x

B

If PR bit = 0

these bits have no effect.

B

X2 3rwShort-range sensitivity

When this bit is set, the sensitivity of the Bx, By, and Bz ADC-conversion is
doubled by a longer ADC integration time. The Temp result will not
change, neither in sensitivity nor conversion time. See Table 3.

TL_mag 2:1 rw Magnetic temperature compensation

There are two bits for setting the sensitivity over temperature of the
sensor to compensate a magnet temperature coefficient.
If 00

→ TC0 (no compensation)

B

→ TC1

If 01

B

If 10

→ TC2

B

If 11

→ TC3

B

CP 0rwConfiguration parity

The register 10
this parity is OK and the CF bit in the status register 06

User Manual 7 Ver. 1.11

is even parity protected with this bit. On startup or reset,

H

is set.

H

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7 0

FP

6 321

PR INT MODE

54

IICadr CA

TLI493D-A2B6

I2C Registers

Back to TLI493D-A2B6 Bitmap.

Table 3 X2 bit

X2 bit Bx (11 ... 0) By (11 ... 0) Bz (11 ... 0) T (11 ... 2)

0

B

1

B

Bx full-range By full-range Bz full-range T full-range

Bx short-range By short-range Bz short-range T full-range

1.2.4 Mode registers combined in the I2C parity flag “FF”

The I2C communication of the registers in this chapter is protected with the parity bit “FF”, described in the
Diag register with the address 06

. See also Figure 1 - parity bits and related registers.

H

Power mode, interrupt, address, parity

Register name Address Reset Value

MOD1 11

H

00

Field Bits Type Description

H

FP 7rwFuse parity

The registers 11

and 13H (bit 7) are odd parity protected with this bit.

H

If this parity bit is incorrect please see FF bit.
To exit this state a sensor reset is necessary.

IICadr 6:5 rw I

2

C address

Bits can be set to 00

, 01B, 10B or 11B to define the slave address in bus

B

configuration.
See Table 4 and data sheet.

PR 4rwI2C 1-byte or 2-byte read protocol

this is the 2-byte read protocol:

If 0

B

<start> <I2Cadr.> <reg.adr.> <data of reg.adr.> <data of reg.adr.+1> ….
<stop>
If 1

this is the 1-byte read protocol:

B

<start> <I2Cadr.> <data of reg.00
See Chapter 2.1.3

CA 3rwCollision avoidance

Clock stretching only in master-controlled and low-power mode, not in
fast mode.
The CA bit interacts with the INT bit, see Table 5 and Chapter 2.2.

> <data of reg.01H> …. <stop>

H

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TLI493D-A2B6

I2C Registers

Field Bits Type Description

INT 2rwInterrupt enabled

/INT disabled

If 1

B

If 0

/INT enabled: After a completed measurement and ADC-conversion,

B

an /INT pulse will be generated.
For bus configurations /INT timing constraints between I
and interrupt pulses must be monitored and aligned.
The INT bit interacts with the CA bit, see Table 5.

MODE 1:0 rw Power mode

Low Power Mode:

If 00

B

Cyclic measurements and ADC-conversions with a update rate, defined in
the PRD registers. “No ADC trigger” must be used, see Table 6 and TRIG.
If 01

Master Controlled Mode (Power Down mode):

B

Measurement triggering depends on the PR bit and is possible with I
sub address byte (see Table 6) or TRIG bits.
If 10

is reserved and must not be used.

B

If 11

Fast Mode:

B

The measurements and ADC-conversions are running continuously. It is
recommended to set INT = 0

2

C data transfers

and use a I2C clock speed ≥ 800 kHz.

B

2

C

Back to TLI493D-A2B6 Bitmap.

Table 4 Device address overview

The addresses are selected to ensure a minimum Hamming distance of 4 between them.

Address write Address read IICadr (bit-6) IICadr (bit-5) ID (bit-5) ID (bit-4)

1)

6A

H

44

H

F0

H

88

H

1) Default address after start up or reset.

6B

45

F1

89

1)

H

H

H

H

0

B

0

B

1

B

1

B

0

B

1

B

0

B

1

B

0

B

0

B

1

B

1

B

0

B

1

B

0

B

1

B

Table 5 /INT (interrupt) and clock stretching

In case the microcontroller tries to read sensor data the clock stretching pulls the SCL /INT line to low, as long
as the measurement and ADC-conversion is not finished.

CA INT Configuration

0

0

B

/INT is enabled and will not be transmitted between <START> and <STOP>.

B

/INT collision avoidance active.

1

0

B

/INT disabled. Clock stretching enabled.

B

Suppress sensor read out during ongoing ADC conversion.
This configuration must not be used with the “read” trigger-bits (7:5) = 010
or with the trigger option TRIG bit = 01

1

0

B

/INT is enabled and will be transmitted between <START> and <STOP>.

B

/INT may collide with I

2

C clock from microcontroller.

.

B

or 011B (see Table 6)

B

1

1

B

/INT disabled. Clock stretching disabled.

B

Unsynchronized sensor readouts may collide with ADC conversion.

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