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TLE987xQX
User Manual
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Infineon TLE987xQX User Manual

Application Note 1 Rev. 1.1
www.infineon.com/embeddedpower 2020-12-08
Z8F56887800
FAQ Application Note for TLE986xQX, TLE987xQX
Frequently Asked Questions and Application Hints

About this document

Scope and purpose
Note: The following information is given as a hint for the implementation of the device only and shall not
be regarded as a description or warranty of a certain functionality, condition or quality of the device.
Intended audience
This template is intended for Customer and FAE to document frequently asked question and answers for the embedded Power IC, TLE986xQX and TLE987xQX device family.
FAQ Application Note for TLE986xQX, TLE987xQX
Z8F56887800

Table of Contents

About this document . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1
Table of Contents . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2
1 Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1
2 Collection of Questions and Topics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1
3 GPIO Port Map and Alternate Functions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3
3.1 Description: GPIO Register description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3
3.2 Implementation: Alternate Function configuration example . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3
3.3 Implementation: Port Map of Alternate Functions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3
4 SWD (Serial Wire Debug) Interface Circuitry . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5
4.1 Description: SWD (Serial Wire Debug) Interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5
4.2 Implementation: SWD Interface connection to TLE986x/ TLE987x . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5
5 Bootup Configuration . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6
5.1 Description: BSL Connection Window . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6
5.1.1 None-Activity-Counter - NAC . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6
5.1.2 Node Address - NAD . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7
5.1.3 LIN slope after NAC . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7
5.2 Implementation: Write NAC NAD values to the correct position in Flash . . . . . . . . . . . . . . . . . . . . . . . . 8
6 Watchdog Handling WDT1 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10
6.1 Description: Window Watchdog Timer WDT1 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10
6.2 Implementation: Watchdog Handling µVision 5 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10
6.3 Implementation: WDT1 Hints . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11
6.3.1 Potential WDT1 Traps . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11
6.3.2 Consequence . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11
6.3.3 Root Cause . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11
6.3.4 Solution: . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11
7 Device state after system overtemperature . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12
7.1 Description: System overtemperature detection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12
7.2 Implementation: Cyclic wake period . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13
8 BEMF comparator demag-pulse filter . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14
8.1 Describtion: Demag-pulse filter . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14
8.2 Implementation: Demag-pulse filter output . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14
9 VQFN vs TQFP package . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16
9.1 Implementation: Additional parameters and test conditions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16
10 BDRV on-state vs off-state diagnosis . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17
10.1 Description: diagnosis features in the BDRV . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17
10.1.1 On-state diagnosis . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17
10.1.2 Off-state diagnosis . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17
10.2 Implementation: Register settings and status registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17
11 Internal voltage regulators . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18
11.1 Description: internal voltage generation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18
12 ASIL rating of TLE986x/7x . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18
12.1 Description: Functional safety with TLE986x/7x . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18
Application Note 2 Rev. 1.1
2020-12-08
FAQ Application Note for TLE986xQX, TLE987xQX
Z8F56887800
13 Power dissipation inside TLE986x/7 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18
14 Very high/low duty cycle PWM . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19
14.1 Description: CCU6 PWM generation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19
14.2 Implementation: 100% duty-cycle . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20
15 Revision History . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22
Application Note 3 Rev. 1.1
2020-12-08
FAQ Application Note for TLE986xQX, TLE987xQX
Z8F56887800
Introduction

1 Introduction

This Application Note lists topics emerged from frequently asked questions of users or from changed user requirements. Each topic is organized in three sections:
• Topic:
– Short description of the issue.
• Description:
– More details about the topic
• Implementation hint (optional):
– Instruction how to handle this topic

2 Collection of Questions and Topics

This chapter gives an overview of the collected Questions and Topics.
Table 1 Table of Questions
Topic Chapter Page
What PIN is connected to which peripheral?
GPIO Port Map and Alternate Functions
How to connect the Debug Interface?
SWD (Serial Wire Debug) Interface Circuitry
Why does the chip not start up, after reset?
Bootup Configuration
Why does the LIN slope change after a NAC?
Bootup Configuration
Why does the chip do resets every second?
Watchdog Handling WDT1
Does the NAC affect the LIN slope?
LIN slope after NAC
What state does the device enter after system overtemperature?
Device state after system overtemperature
What is the demagnetization filter and how does it work?
BEMF comparator demag-pulse filter
What is the difference between the VQFN and TQFP package variants?
VQFN vs TQFP package
Chapter 3 Page 3
Chapter 4 Page 5
Chapter 5 Page 6
Chapter 5 Page 7
Chapter 6 Page 10
Chapter 5 Page 7
Chapter 7 Page 12
Chapter 8 Page 14
Chapter 9 Page 16
What is the difference between the on and off-state diagnosis in the bridge-driver module?
BDRV on-state vs off-state diagnosis
What can the internal voltage regulators be used for?
Internal voltage regulators
Which ASIL rating does the TLE9876x/7x have?
BEMF comparator demag-pulse filter
Application Note 1 Rev. 1.1
Chapter 10 Page 17
Chapter 11 Page 18
Chapter 12 Page 18
2020-12-08
FAQ Application Note for TLE986xQX, TLE987xQX
Z8F56887800
Collection of Questions and Topics
Table 1 Table of Questions
Topic Chapter Page
How can the power dissipation inside the TLE986x/7x be calculated?
Power dissipation inside TLE986x/7
How can very high/low PWM duty cycles be acchieved?
Very high/low duty cycle PWM
Chapter 13 Page 18
Chapter 14 Page 19
Application Note 2 Rev. 1.1
2020-12-08
FAQ Application Note for TLE986xQX, TLE987xQX
Z8F56887800
GPIO Port Map and Alternate Functions

3 GPIO Port Map and Alternate Functions

What PIN is connected to which peripheral?
The TLE986xQX and TLE987xQX have 15 port pins organized in three parallel ports: Port 0 (P0), Port 1 (P1) and Port 2 (P2). Each port pin has a pair of internal pull-up and pull-down devices that can be individually enabled or disabled. Either pull-up or pull-down devices can be enabled at a time, for a single port pin. P0 and P1 are bidirectional and can be used as general purpose input/output (GPIO) or to perform alternate input/output functions for the on-chip peripherals. When configured as an output, the open drain mode can be selected. On Port 2 (P2) analog inputs are shared with general purpose input.

3.1 Description: GPIO Register description

Each port consists of 8-bit control and data registers. The registers are defined in Table 2.
Table 2 Port Register
Register Short Name Register Long Name Description
Px_DATA Port x Data Register x = {0,1,2}
Px_DIR Port x Direction Register x = {0,1,2}
Px_OD Port x Open Drain Control Register x = {0,1}
Px_PUDSEL Port x Pull-Up/Pull-Down Select Register x = {0,1,2}
Px_PUDEN Port x Pull-Up/Pull-Down Enable Register x = {0,1,2}
Px_ALTSEL0 Port x Alternate Select Register 0 x = {0,1}
Px_ALTSEL1 Port x Alternate Select Register 1 x = {0,1}

3.2 Implementation: Alternate Function configuration example

The ports P0 and P1 can be configured to four different output functions. The default configuration is the GPIO function. The three remaining functions are alternate output functions.
The alternate output function selection is splitted in two bitfields (e.g. P1_ALTSEL0 and P1_ALTSEL1). ALTSEL1 contains the most significant bit. ALTSEL0 contains the least significant bit. The given example code shows how to configure these bitfields to connect UART2 module (TXD, RXD) with the GPIOs (P1.0, P1.1).
/* connect UART2 to GPIO */
/* set P1.1 to UART2_TXD: */
PORT->P1_DIR.bit.P1 = 1u; /* PORT P1.1 output configuration */
PORT->P1_ALTSEL0.bit.P1 = 1u; /* UART2_TXD alternate function 3 */
PORT->P1_ALTSEL1.bit.P1 = 1u; /* UART2_TXD alternate function 3 */
/* Set P1.2 to UART2_RXD: */
PORT->P1_DIR.bit.P2 = 0u; /* PORT P1.2 input configuration */

3.3 Implementation: Port Map of Alternate Functions

Graphical Portmap of Alternate Functions
Each pin is able to handle multiple purposes. Figure 1 shows the internal signals mapped to GPIOs. The arrow boxes contain the signal names and indicate the data flow direction.
Application Note 3 Rev. 1.1
2020-12-08
FAQ Application Note for TLE986xQX, TLE987xQX
Timer:
Analog Inputs:
Communication:
GND
P1.4
Legend
P0.2
OP1
P2.5
P2.4
GND_REF
VAREF
P2.3
OP2
MON
GND
TLE987xQX
EXINT1 _1
EXINT2 _3
ADC1 / CH0
ADC1 / CH3
ADC1 / CH4
ADC1 / CH2
ADC1 / CH1
CP1L
VCP
CP2H
CP2L
GL3
GL2
CP1H
VSD
VS
VDH
LIN
GND_LIN
T2EUDA
MRST_1_2
RXD
TXD
OP2
P2.3
GND_REF
P2.4
P2.5
P2.2/XTAL2
P2.0/XTAL1
P1.3
P0.2
P0.3
P0.0
P0.1
RESET
TMS
GND
P0.4
P1.2
P1.1
P1.0
MON
GL1
T2_0
T21_0
EXF21 _0
CAPINA
T6OUT
T4INA
T3OUT
T12HR_0
SL
GH1
SH1
GH2
SH2
GH3
GND
P1.4
VAREF
OP1
SH3
VDDEXT
VDDP
GND
VDDC
High Voltage IOs
VS
Input only PINs
P2.4
PIN numbers
1
5V PINs and GPIOs
P1.0
Internal LDOs
VDDC
ADC1 / CH5
ADC2 / CH6
ADC2 / CH1
ADC2 / CH2
ADC2 / CH3
ADC2 / CH4
ADC2 / CH5
ADC2 / CH6
ADC2 / CH8
T13HR_0
EXINT0 _2
T21EX_0
EXF2_0
COUT60_0
CCPOS2_1
CAPINB
CCPOS0_1
EXF21 _2
T6OUT
CCPOS1_1T21_2
EXINT2 _2
T3EUDA
T4EUDB
EXINT1 _2 EXF21 _3
T6EUDA
T21_1
EXINT1 _0
COUT61_0
TXD
T2INA
T21EX_3
CCPOS2_2
EXINT0 _1
COUT63_0
T3OUT
T6INB, T6EUDB
CCPOS0_2
EXF21_ 1
TXD
EXINT2 _1
T21EX_1
RXD
CCPOS1_2
MRST_1_3
T12HR_2, CC61_2
EXINT0 _0
CTRAP#_1, CC60_1T21EX_2
EXINT0 _3
T2EUDBMRST_1_1
EXINT1 _3
RXD
T3EUDB
MRST_2_1
T2_1
SCK_2
MTSR_2
MRST_2_0
MRST_1_0
SCK_1
MTSR_1
CC61_0
CTRAP#_0
CLKOUT_1
CLKOUT_0
COUT62_0
ADC1 ADC2
UART1 UART2
SSC1 SS C2
External
Interrupt
Timer 2x
GPT12 CCU6
SCU
Hall
Inputs
CCPOS1_0
CCPOS2_3
T13HR_2, CC62_2
CCPOS0_3
CC62_0
CC60_0
T5EUDA
T2INB
T6INA
T3INC
T4INC
T5INA
T4EUDA
T2 T3 T4 T5 T6
T2EX_1
T21T2
Z8F56887800
GPIO Port Map and Alternate Functions
Figure 1 Port Map of Alternate Functions
Application Note 4 Rev. 1.1
2020-12-08
FAQ Application Note for TLE986xQX, TLE987xQX
TLE9879QX SWD Connector
PIN 40 VDDP PIN 1
PIN 20 TMS PIN 2
GND PIN 3, 5, 7, 9
PIN 21 P0.0 PIN 4
PIN 22 RESET PIN 10
Schematic Layout
PIN 1 PIN 2
Z8F56887800
SWD (Serial Wire Debug) Interface Circuitry

4 SWD (Serial Wire Debug) Interface Circuitry

How to connect the Debug Interface?
The Serial Wire Debug interface is used to download code to the embedded Power IC or to debug the chip. This Topic explains how to implement the circuitry around the chip to achieve a successfull SWD connection.

4.1 Description: SWD (Serial Wire Debug) Interface

Serial Wire Debug (SWD) provides a debug port for severely pin limited packages, often the case for small package microcontrollers but also complex ASICs where limiting pin-count is critical and can be the controlling factor in device costs.
For SWD the TLE9879 uses the pins TMS (data) and P0.0 (clock). On the Evaluation boards, the signals are routed through a 5x2 pinheader (SWD connector). The following Implementation explains the connection between embedded Power IC and SWD Interface.

4.2 Implementation: SWD Interface connection to TLE986x/ TLE987x

The SWD Interface can be directly connected to the TLE987x and TLE986x family. The use of external pull up or pull down resistors is not needed, due to internal pull down resistors. Figure 2 shows the interconnections between TLE Device and and SWD Connector.
Figure 2 SWD Connection to the TLE987x and TLE986x Device
On TLE9879 and TLE9869 Evalkit SWD Interface PIN 9 is used to deactivate the onboard debugging circuit. For a typical implementation this PIN is used as GND. The Pinout is shown in Figure 3.
Figure 3 SWD Interface implementation for application
Application Note 5 Rev. 1.1
2020-12-08
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