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User Manual Please read the Important Notice and Warnings at the end of this document Rev. 1.0
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TLE986x EvalBoard User Manual
About this document
Scope and purpose
This user manual is intented to help users using the TLE986x Evalboard. This Evalboard is designed to evaluate
hardware and software functionalities of the TLE986x device family.
This manual provides additional information about the board’s layout, jumper settings, interface and debug
options. It introduces the evaluation platform as well as how to write software and download it to the TLE986x.
Intended audience
This document is for everyone who works with the TLE986x Evalboard.
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About this document
Abbreviations and definitions
Table 1 Abbreviations
Abbreviation
Definition
BLDC
Brushless direct current
BSL
Bootstrap loader
GH 1, 2
Gate high-side MOSFET for phases 1, 2
GL 1, 2
Gate low-side MOSFET for phase 1, 2
GPIO
General purpose input / output
ISP
In-system programmer
LIN
Local interconnect network
MON
Monitor
n.c.
Not connected
n/u
Not used
OP1
Negative operational amplifier input
OP2
Positive operational amplifier input
RST
Reset
SL
Source low-side MOSFETs
SWD
Arm® serial wire debug
TMS
Test mode select
UART
Universal asynchronous receiver transmitter
VAREF
Reference voltage
VBAT
Battery voltage supply
VCOM
Virtual COM-port
VCP
Voltage charge pump
VDDC
Core supply
VDDEXT
External voltage supply output
VDDP
I/O port supply
VDH
Voltage drain high-side MOSFET
VS
Battery supply input
VSD
Battery supply input for MOSFET driver
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Table of contents
Table of contents
About this document ....................................................................................................................... 1
Table of contents ............................................................................................................................ 3
1 Concept ................................................................................................................................ 4
2 Interconnects ........................................................................................................................ 5
3 Test points and LEDs ............................................................................................................... 7
4 Jumper settings ..................................................................................................................... 8
5 Communication interfaces ..................................................................................................... 10
5.1 LIN (via banana jack and uIO BSL) ........................................................................................................ 10
5.2 UART ...................................................................................................................................................... 10
5.3 Debugging .............................................................................................................................................. 10
6 Software toolchain ................................................................................................................ 11
6.1 Keil µVision 5 ......................................................................................................................................... 11
6.2 Infineon ConfigWizard ........................................................................................................................... 11
6.3 TLE986x SDK .......................................................................................................................................... 11
6.4 Debug connection setup ....................................................................................................................... 11
7 Technical data ...................................................................................................................... 13
8 Optional additional placements .............................................................................................. 14
9 Schematics and layout ........................................................................................................... 15
9.1 Schematic .............................................................................................................................................. 15
9.2 Layout .................................................................................................................................................... 18
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Concept
1 Concept
Figure 1 Board concept
This board is designed to provide a simple, easy-to-use tool for getting familiar with Infineon’s Embedded
Power IC TLE986x devices. A socket provides the possibility to test and evaluate all ICs of the TLE986x family.
Every pin of the IC is connectable via rows of pin headers. The board is protected against reverse polarity of
input voltage supply.
Two MOSFET half bridges are assembled on the board to drive a DC motor. The board is ready to be connected
to a car supply or similar and offers a SWD port to connect an external debugger.
The evaluation board can be operated by standard laboratory equipment as power supply and LIN
communication are working via banana jacks.
There is a battery LED that indicates that the board is connected to supply in the correct way. Otherwise
reverse polarity protection secures the board from damage by cross connection.
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Interconnects
2 Interconnects
Figure 2 Interconnects
Banana jacks for ground, supply and LIN
There are jacks in different colors for ground, supply (max. 28 V) and LIN communication via banana jack. The
following jacks are available: GND (marked purple), VBAT (marked red), motor phase 1 & 2 (marked red) and LIN
(marked green).
Banana jacks for motor connection (marked red)
The two jacks Phase1 and Phase2 provide access to the two half bridges and are intended to connect a motor.
uIO Stick connector (marked green)
This uIO bootstrap loader is a 16-pin header (2 x 8) with 2.54 mm pitch.
It is intended to connect additional hardware for bootstrap loading. This interface can be used to program the
TLE986x via LIN (see www.infineon.com/uio or www.hitex.com/uio).
GND
Phase 2
Phase 1
SWD
UART-Serial
VBAT
LIN
uIO
Stick
VBAT
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Interconnects
Figure 3 Pin configuration uIO BSL
Pin header for SWD (marked blue)
There is a 10 pin header (2 x 5) with 1.27 mm pitch on the evaluation board. This interface is meant to be used
for debugging.
Figure 4 Pin configuration SWD interface
5 V 1 2
3 4
5 6
7 8
GND
GND
n.c.
SWDIO (TMS)
SWCLK (P0.0)
n.c.
n.c.
9 10DBPRE RESET
LIN
RESET
GND
VS
TXD1
RXD1
VDD5
GPIO3
1
2
3
4
5
6
7
8
9
11
10
13
14
15
16
GPIO2
GPIO1
SCS
SCLK
MISO
MOSI
AD0
GPIO0
12
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Test points and LEDs
3 Test points and LEDs
Figure 5 Test points
Several ground test points are provided.
Test point LIN_INT is used to measure the LIN voltage.
Test point VDH is used to measure the voltage on the VDH pin.
Tests points Motor 1 and Motor 2 can be used to measure the voltage at phase 1 and 2 of the motor.
There are 11 LEDs for visual validations on the board:
LED 1 to 8 can be connected to GPIOs (see Table 3).
LED 9 (Vbat LED) indicates power supply.
LED 10 (Motor Status 1) lights up if the motor is running forward.
LED 11 (Motor Status 2) lights up if the motor is running backward.
Motor
Status 1
Motor
Status 2
GND
Motor 2
VDH
Motor 1
Vbat LED
GND
GND
LIN_INT
LEDs 1-8
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Jumper settings
4 Jumper settings
Figure 6 Jumpers
Table 2 Jumpers
JP7
Close this jumper to connect MON button to MON input. Open it to disconnect MON
button from MON input.
JP8 / JP11
Open or close these jumpers to enable or disable the measurement shunt of the current
sense amplifier.
JP9
Close this jumper to connect RESET button to RESET input. Open it to disconnect RESET
button from RESET input.
JP10
Close this jumper to connect an additional 1 kΩ pull-up resistor. This is intended for LIN
master communication. Open the jumper to use the TLE986x as slave in a LIN network.
Software for LIN low level driver can be found at the homepage of IHR (www.ihr.de).
JP12
Close this jumper to enable UART communication.
JP13
This jumper is closed by default. If this jumper is left open the device is not supplied. It is
intended to open the VSD line in order to measure the current flowing into the TLE986x
device.
JP14
Open or close these jumpers to connect or disconnect the LEDs (see Table 3).
JP15
Close this jumper to enable UART communication.
+5V_AUX_SEL
JP18
JP15
JP12
JP14
JP7 JP9
JP17
JP11
JP8
JP13
JP16
JP10
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Jumper settings
JP16
This jumper is closed by default. If this jumper is left open the device is not supplied. It is
intended to open the VS line in order to measure the current flowing into the TLE986x
device.
JP17
Close this jumper to connect the motor status LEDs. Open it to disconnect the LEDs.
JP18
Close this Jumper to connect the potentiometer to P2.4. Open this jumper to disconnect
the potentiometer.
+5V_AUX_SEL
Open this jumper to disable the board’s voltage regulator.
Table 3 GPIOs’ function
P0.1
LED 1
P0.2
LED 2
P0.3
LED 3
P0.4
LED 8
P1.0
LED 5
P1.1
UART
P1.2
LED 4 / UART
P1.3
LED 6
P1.4
LED 7
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Communication interfaces
5 Communication interfaces
5.1 LIN (via banana jack and uIO BSL)
The device integrated LIN transceiver is connected to a banana jack and additionally to the uIO BSL interface.
To integrate the device in a LIN network it is sufficient to use the single wire banana interface. The BSL interface
is intended to program the device via LIN. For further information about the uIO interface see
www.infineon.com/uio or www.hitex.com/uio.
5.2 UART
A RS232 connector on the board enables a serial communication.
5.3 Debugging
Debugging is possible via the SWD interface; the signals are routed through the 10 pin header SWD interface
(see Figure 4).
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Software toolchain
6 Software toolchain
6.1 Keil µVision 5
The recommended Integrated Software Development Environment is Keil® µVision5®.
Infineon’s Embedded Power family is supported. For more information about the installation process, go to
www.keil.com.
6.2 Infineon ConfigWizard
In addition to the IDE, Infineon provides ConfigWizard. The tool is designed for code configuration, in
combination with the IDE. Infineon ConfigWizard can be downloaded via the Infineon Toolbox. The Infineon
Toolbox is a central place to download and update all your Infineon tools. It can be downloaded from
www.infineon.com/toolbox.
6.3 TLE986x SDK
All Embedded Power products can be installed to Keil® µVision5® via “Pack Installer”. Browsing to the Infineon
chapter in “All Devices” will lead to the “TLE98xx Series”. The “.pack” file comes with several code examples, to
provide an easy start up and speed up software development.
6.4 Debug connection setup
For a proper Flash and Debug Connection, install V5.10 (or newer) from: www.segger.com/jlink-
software.html. Keil® µVision5® has to be configured in the IDE Menu “Options for Target”. After connecting the
USB-cable and power up the EvalBoard, go to the “Debug” register-card, choose “J-LINK / J-TRACE Cortex” and
press “Settings”.
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Software toolchain
Figure 7 Debug and flash configuration
If the board is connected successfully, the Arm® IDCODE will be visible in the SW Device Window. If connection
fails, “Connect & Reset Options” and “Port” window has to be checked.
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Technical data
7 Technical data
Table 4 Technical data
Voltage supply:
max. 28 V
Motor current:
max. 20 A
Pin ports:
5 V
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Optional additional placements
8 Optional additional placements
Figure 8 Additional placements’ positions
Values for these optional additional placements have to be determined depending on application.
Table 5 Additional placements
Component
Description
Value
Q1
External oscillator
/
C_DG_H1(NB)
Gate drain capacitor high-side MOSFET phase 1
33 - 330 pF
C_DG_L1(NB)
Gate drain capacitor low-side MOSFET phase 1
33 - 330 pF
C_DG_H2(NB)
Gate drain capacitor high-side MOSFET phase 2
33 - 330 pF
C_DG_L2(NB)
Gate drain capacitor low-side MOSFET phase2
33 - 330 pF
Q1
C DG L2(NB) C DG H2(NB)
C DG L1(NB)
C DG H1(NB)
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Schematics and layout
9 Schematics and layout
9.1 Schematic
Figure 9 Schematics: Sheet 1
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Schematics and layout
Figure 10 Schematics: Sheet 2
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Schematics and layout
Figure 11 Schematics: Sheet 3
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Schematics and layout
9.2 Layout
Figure 12 Top layer
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Schematics and layout
Figure 13 Bottom layer
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Trademarks
All referenced product or service names and trademarks are the property of their respective owners.
Edition 2019-04-04
Published by
Infineon Technologies AG
81726 Munich, Germany
© 2019 Infineon Technologies AG.
All Rights Reserved.
Do you have a question about this
document?
Email: erratum@infineon.com
Document reference
IMPORTANT NOTICE
The information given in this document shall in no
event be regarded as a guarantee of conditions or
characteristics (“Beschaffenheitsgarantie”).
With respect to any examples, hints or any typical
values stated herein and/or any information
regarding the application of the product, Infineon
Technologies hereby disclaims any and all
warranties and liabilities of any kind, including
without limitation warranties of non-infringement
of intellectual property rights of any third party.
In addition, any information given in this document
is subject to customer’s compliance with its
obligations stated in this document and any
applicable legal requirements, norms and
standards concerning customer’s products and any
use of the product of Infineon Technologies in
customer’s applications.
The data contained in this document is exclusively
intended for technically trained staff. It is the
responsibility of customer’s technical departments
to evaluate the suitability of the product for the
intended application and the completeness of the
product information given in this document with
respect to such application.
For further information on the product, technology,
delivery terms and conditions and prices please
contact your nearest Infineon Technologies office
(www.infineon.com).
WARNINGS
Due to technical requirements products may
contain dangerous substances. For information on
the types in question please contact your nearest
Infineon Technologies office.
Except as otherwise explicitly approved by Infineon
Technologies in a written document signed by
authorized representatives of Infineon
Technologies, Infineon Technologies’ products may
not be used in any applications where a failure of
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