infineon TLE9869 User Manual
TLE9869 EvalKit v1.0
User Manual v1.1
Contents
Abbreviations .......................................................................................................................................... 2
1 Concept ................................................................................................................................................ 3
2 Interconnects ........................................................................................................................................ 4
3 Test Points ............................................................................................................................................ 5
4 Jumper Settings .................................................................................................................................... 6
5 Communication Interfaces ................................................................................................................... 7
5.1 LIN (via Banana jack and uIO BSL) ................................................................................................. 7
5.2 UART (via USB)............................................................................................................................... 7
5.3 Debugging (via USB or SWD-Interface) ......................................................................................... 8
6 Technical Data ...................................................................................................................................... 8
7 Optional Additional Placements ........................................................................................................... 9
8 Schematics and Layout ....................................................................................................................... 10
TLE9869 EvalKit v1.0 User Manual v1.1
Abbreviations
BLDC
Brushless Direct Current
BSL
Bootstrap Loader
GH1,2
Gate High side MOSFET for Phases 1, 2
GL1,2
Gate Low side MOSFET for Phases 1, 2
GPIO
General Port Input / Output
ISP
In-system Programmer
LIN
Local Interconnect Network
MON
Monitor
n.c.
not connected
n/u
not used
OP1
Negative operational Amplifier Input
OP2
Positive operational Amplifier Input
RST
Reset
SL
Source Low side MOSFET
SWD
ARM Serial Wire Debug
TMS
Test Mode Select
UART
Universal Asynchronous Receiver Transmitter
VAREF
Reference Voltage
VBAT
Battery Voltage Supply
VCOM
Virtual COM-Port
VCP
Voltage Charge Pump
VDDC
Core Supply
VDDEXT
External Voltage Supply Output
VDDP
I/O Port Supply
VDH
Voltage Drain High side MOSFET
VS
Battery Supply Input
VSD
Battery Supply Input for MOSFET Driver
Table 1: Abbreviations
TLE9869 EvalKit v1.0 User Manual v1.1
1 Concept
Figure 1: Board Concept
This board is intended to provide a simple, easy-to-use tool for getting familiar with Infineon’s
embedded power IC TLE9869. It contains the TLE9869 and its typical application circuit including two
MOSFET half bridges to instantly drive a DC motor. The board is ready to connect with car supply or
similar and has an implemented Segger for debugging on board.
All relevant chip pins are connected to pin headers at the edge of the board, where signals can be
probed or applied directly (see Table 2, Table 3). By different jumper settings LEDs can be put in parallel
to several ports and selected functions can be configured (see Table 6). Push button switches allow
easy hardware reset and triggering of the MON input. There are intended test points for all four gate
driver pins, for measurements at the shunt, VDDC and several ground points on the evaluation board
(see Figure 3). For testing analog signals ADC inputs can be varied by the potentiometer on board. Two
phases of motor current can be picked off at a terminal block to connect a DC motor.
The evaluation board can be operated by standard laboratory equipment as power supply and LIN
communication are working via banana jacks. Debugging and UART are provided via an USB interface
combined with onboard Segger J-Link (XMC4200). Bidirectional level shifters ensure that the respective
XMC pins are in tristate as long as UART or debugging is not used.
In case the user wants to use another ISP than the onboard Segger the SWD interface can be used. To
program the TLE9869 via LIN there is an additional uIO BSL interface (see Table 4).
There is a battery LED that indicates that the board is connected to supply the right way. Otherwise
reverse polarity protection secures the board from damage by cross connection.
TLE9869 EvalKit v1.0 User Manual v1.1
2 Interconnects
Figure 2: Interconnects
Banana jacks (marked yellow)
There are jacks in different colors for ground, supply (max.28V) and LIN communication via banana
jack: GND (black), VBAT (red), LIN (green)
Pin Ports X4 and X5 (marked red)
Soldering pin headers with 2,54mm pitch for X4 (1x10) and X5(1x16) yields test points for the TLE9869
pins. Following signals are connected to the pins:
X4:
1 2 3 4 5 6 7 8 9
10
GND
VCP
VSD
VS
VDH
LIN
VDDEXT
VDDP
VAREF
GND
Table 2: Pin Configuration Top Line Pin Port (X4)
X5:
1 2 3 4 5 6 7 8 9
10
11
12
13
14
15
16
GND
MON
RST
P0.0
P1.1
P0.1
P0.2
P0.3
P1.2
P1.0
P1.3
P1.4
P0.4
P2.3
P2.4
P2.5
Table 3: Pin Configuration Bottom Line Pin Port (X5)
Terminal block for connecting the motor (marked blue)
The two pins of the terminal block provide access to the two half bridges and are intended to connect
a DC motor.
USB for UART and Debugging (marked green)
With this Micro USB PC and evaluation board can get connected.
TLE9869 EvalKit v1.0 User Manual v1.1
uIO BSL for LIN (marked orange)
This uIO bootstrap loader is an 8 pin header (2x4) with 2,54mm pitch.
It is intended to connect additional hardware for bootstrap loading. For programming the TLE9869 via
LIN this uIO interface can be used (see www.infineon.com/uio).
n.c.
1 2 GND
n.c.
3 4 n.c.
LIN
5 6 VS
RESET
7 8 n.c.
Table 4: Pin Configuration uIO BSL
Pin Header for SWD (marked purple)
There is a 10 pin header (2x5) with 1,27mm pitch on the evaluation board. For debugging with another
ISP than the onboard Segger this interface can be used.
DBPRE will be implicitly connected to GND by connecting the external ISP. This keeps the XMC in reset
state to prevent interference of the SWD communication.
5V
1 2 SWDIO (TMS)
GND
3 4 SWCLK (P0.0)
GND
5 6 n.c.
n.c.
7 8 n.c.
DBPRE
9
10
RESET
Table 5: Pin Configuration SWD Interface
3 Test Points
Figure 3: Test Points
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