Infineon TLE9278-3BQX Datasheet

Datasheet Rev. 1.5

www.infineon.com 1 2019-09-27

TLE9278-3BQX

Multi-CAN Power+ System Basis Chip

1 Overview

Features

• SMPS with integrated switches up to 750 mA (DC/DC buck) with 5.0 V output voltage

• DC/DC Boost converter for low V at 6.5 V, 8 V, 10 V and 12 V

• Low-Drop Voltage Regulator with external PNP device with configurable 5.0 V, 3.3 V, 1.8 V and 1.2 V output voltage, protected for off-board usage

supply voltage with integrated switch

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• Very low quiescent current consumption in Stop and Sleep Mode

• Dedicated pin for I/O voltage supply selection

• Four CAN Transceivers compliant to CAN Flexible Data-rate (FD)

• ISO 11898-2: 2016 standard up to 5 Mb

• Partial Networking (PN) support

• One universal High-Voltage Wake Input for voltage level monitoring including wake up capability

• Cyclic wake feature via an integrated timer

• Reset Output to ensure stable supply to the MCU

• Fail Output to activate external load in case of system malfunctions are detected

• Output voltage supervision functions in all output supply voltages

• Fast Battery Voltage Monitoring Feature

• 16-bit Serial Perpheral Interface (SPI)

• Overtemperature and short circuit protection feature

• Wide input voltage and temperature range

• Software Compatibility to other SBC family members for the TLE926x and TLE927x families

• Green Product (RoHS compliant) & AEC Qualified

• 7 × 7 mm PG-VQFN-48 package

Potential applications

•Gateways

• Body control modules

• Driver assistance

• Chasis control

TLE9278-3BQX

Multi-CAN Power+ System Basis Chip

Overview

Product validation

Qualified for automotive applications. Product validation according to AEC-Q100/101.

Description

Infineon’s TLE9278-3BQX offers the highest level of integration at smallest footprint for automotive applications requiring multiple channels of CAN transceivers like gateways and high-end Body Control Modules (BCM). A high-efficient Switch Mode Power Supply (SMPS) buck regulator provides an external 5.0 V output voltage at up to 750 mA while an additional DC/DC boost converter supports applications or conditions at low supply input voltages. The device is controlled and monitored via a 16-bit Serial Peripheral Interface (SPI). Additional features include a time-out/window watchdog circuit with reset, fail output and undervoltage reset. The device offers low-power modes in order to support applications that are connected permanently to the battery. A wake-up from the low-power mode is possible via a message on the buses, via the bi-level sensitive monitoring/wake-up input as well as via the timer. The TLE9278-3BQX is offered in a very small footprint, exposed pad PG-VQFN-48 (7 × 7 mm) power package.

Type Package Marking

TLE9278-3BQX PG-VQFN-48 TLE9278-3BQX

Datasheet 2 Rev. 1.5

2019-09-27

TLE9278-3BQX

Multi-CAN Power+ System Basis Chip

1 Overview . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1

Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1

Potential applications . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1

Product validation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2

Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2

Table of Contents . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3

2 Block Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7

3 Pin Configuration . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8

3.1 Pin Assignment . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8

3.2 Pin Definitions and Functions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9

3.3 Unused Pins . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11

4 General Product Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12

4.1 Absolute Maximum Ratings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12

4.2 Functional Range . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14

4.3 Thermal Resistance . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15

4.4 Current Consumption . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15

5 System Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19

5.1 State Machine Description and SBC Mode Control . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19

5.1.1 Device Configuration and SBC Init Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22

5.1.1.1 Supply and Power up configurability . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22

5.1.1.2 Watchdog trigger failure configuration . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22

5.1.1.3 SBC Init Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24

5.1.2 SBC Normal Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25

5.1.3 SBC Stop Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25

5.1.4 SBC Sleep Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26

5.1.5 SBC Restart Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26

5.1.6 SBC Fail-Safe Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 27

5.1.7 SBC Development Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 28

5.2 Wake Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 29

5.2.1 Cyclic Wake . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 29

5.2.2 Internal Timer . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 29

5.3 CAN Partial Networking . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 30

5.3.1 CAN Partial Networking - Selective Wake Feature . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 30

5.3.2 SBC Partial Networking Function . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 31

5.3.2.1 Activation of SWK . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 32

5.3.2.2 Wake-up Pattern (WUP) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 33

5.3.2.3 Wake-up Frame (WUF) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 33

5.3.2.4 CAN Protocol Error Counter . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 34

5.3.3 Diagnoses Flags . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 35

5.3.3.1 PWRON/RESET-FLAG . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 35

5.3.3.2 BUSERR-Flag . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 35

5.3.3.3 TxD Dominant Time-out flag . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 35

5.3.3.4 WUP_x Flag . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 35

Datasheet 3 Rev. 1.5

2019-09-27

TLE9278-3BQX

Multi-CAN Power+ System Basis Chip

5.3.3.5 WUF Flag (WUF_x) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 35

5.3.3.6 SYSERR Flag (SYSERR_x) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 35

5.3.3.7 Configuration Error . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 36

5.3.3.8 CAN BUS Time-out-Flag (CANTO_x) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 36

5.3.3.9 CAN BUS Silence-Flag (CANSIL_x) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 36

5.3.3.10 SYNC-FLAG (SYNC_x) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 36

5.3.3.11 SWK_SET FLAG (SWK_SET_x) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 36

5.3.4 SBC Modes for Selective Wake (SWK) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 37

5.3.4.1 SBC Normal Mode with SWK . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 37

5.3.4.2 SBC Stop Mode with SWK . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 38

5.3.4.3 SBC Sleep Mode with SWK . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 39

5.3.4.4 SBC Restart Mode with SWK . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 40

5.3.4.5 SBC Fail-Safe Mode with SWK . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 41

5.3.5 Wake-up . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 41

5.3.6 Configuration for SWK . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 41

5.3.7 CAN Flexible Data Rate (CAN FD) Tolerant Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 42

5.3.8 Clock and Data Recovery . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 43

5.3.8.1 Configuring the Clock Data Recovery for SWK . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 43

5.3.8.2 Setup of Clock and Data Recovery . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 43

5.3.9 Electrical Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 45

6 DC/DC Regulator . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 47

6.1 Block Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 47

6.1.1 Functional Description of the Buck Converter . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 48

6.1.1.1 Startup Procedure (Soft Start) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 49

6.1.1.2 Buck regulator Status register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 49

6.1.1.3 External components . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 49

6.1.2 Functional Description of the Boost Converter . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 50

6.1.2.1 Boost Regulator Status register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 51

6.1.2.2 External Components . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 51

6.2 Power Scenarios . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 52

6.2.1 Buck behavior in SBC Normal Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 52

6.2.2 Buck behavior in SBC Stop Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 52

6.2.2.1 Automatic Transition from PFM to PWM in SBC Stop Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 52

6.2.2.2 Manual Transition from PFM to PWM in SBC Stop Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 53

6.2.2.3 SBC Stop to Normal Mode transition . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 53

6.2.3 Buck behavior in SBC Sleep or Fail Safe Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 53

6.2.3.1 SBC Sleep/Fail Safe Mode to SBC Normal Mode transition . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 53

6.3 Electrical Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 54

7 External Voltage Regulator . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 57

7.1 Block Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 57

7.2 General Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 58

7.2.1 Functional Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 58

7.3 External Components . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 59

7.4 Calculation of R

7.5 Unused Pins . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 60

7.6 Electrical Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 61

. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 60

SHUNT

Datasheet 4 Rev. 1.5

2019-09-27

TLE9278-3BQX

Multi-CAN Power+ System Basis Chip

8 High Speed CAN Transceiver . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 63

8.1 Block Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 63

8.2 Functional Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 63

8.2.1 CAN OFF Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 65

8.2.2 CAN Normal Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 65

8.2.3 CAN Receive Only Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 65

8.2.4 CAN Wake Capable Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 66

8.2.5 TXD Time-out Feature . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 67

8.2.6 Bus Dominant Clamping . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 67

8.2.7 Undervoltage Detection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 67

8.3 Electrical Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 68

9 Wake Input . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 75

9.1 Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 75

9.2 Functional Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 75

9.2.1 Wake Input Configuration . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 76

9.3 Electrical Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 78

10 Interrupt Function . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 79

10.1 Block and Functional Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 79

10.2 Electrical Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 81

11 Fail Output . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 82

11.1 Functional Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 82

11.2 Electrical Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 84

12 Supervision Functions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 85

12.1 Reset Function . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 85

12.1.1 Reset Output Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 85

12.1.2 Soft Reset Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 86

12.2 Watchdog . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 86

12.2.1 Time-Out Watchdog . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 87

12.2.2 Window Watchdog . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 88

12.2.3 Checksum . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 88

12.2.4 Watchdog during Stop Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 89

12.2.4.1 Watchdog Start in SBC Stop Mode due to BUS Wake . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 89

12.3 V

12.4 Measurement Interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 91

12.5 Fast Battery Voltage Monitoring . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 92

12.6 VBSENSE Boost deactivation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 92

12.7 VIO Undervoltage and Undervoltage Prewarning . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 93

12.8 VIO Overvoltage . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 93

12.9 VIO Short Circuit . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 94

12.10 VEXT Undervoltage . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 94

12.11 Thermal Protection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 94

12.11.1 Temperature Prewarning . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 95

12.12 Electrical Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 96

Power ON Reset . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 90

13 Serial Peripheral Interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 100

13.1 SPI Protocol Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 100

13.2 Failure Signalization in the SPI Data Output . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 101

Datasheet 5 Rev. 1.5

2019-09-27

TLE9278-3BQX

Multi-CAN Power+ System Basis Chip

13.3 SPI Programming . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 103

13.4 SPI Bit Mapping . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 105

13.4.1 SPI Mapping Structure . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 105

13.4.2 SPI Register Banking . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 105

13.4.3 SPI Mapping Tables . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 106

13.5 SPI Control Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 108

13.5.1 General Control Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 109

13.5.2 Selective Wake Control Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 123

13.5.3 Selective Wake Trimming and Calibration Control Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 144

13.6 SPI Status Information Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 152

13.6.1 General Status Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 153

13.6.2 Selective Wake Status Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 167

13.6.3 Family and Product Information Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 183

13.7 Electrical Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 184

14 Application Information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 186

14.1 Application Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 186

14.2 ESD Tests . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 190

14.3 Thermal Behavior of Package . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 191

15 Package Outlines . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 192

16 Revision History . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 193

Datasheet 6 Rev. 1.5

2019-09-27

CC1

Buck

ext

SPI

Interrupt

Control

SBC

STATE

MACHINE

SDI

SDO

CLK CSN

BCKSW

Window Watchdog

TXDCAN2

RXDCAN2

VCAN

CANH2

CANL2

RESET

GENERATOR

INTN

WAKE

Vint.

Fail Safe

RSTN

FO/TEST

GND

VCC 1

Boost

BSTD

GND

VEXTIN

Selective W ake

Logic

VEXT REF

VEXTSH

VEXT B

TXDCAN3

RXDCAN3

CANH3

CANL3

TXDCAN0

RXDCAN0

CANH0

CANL0

TX D CA N1

RXDCAN1

CANH1

CANL1

VBSENSE

CAN

Module 2

CAN

Module 3

CAN

Module 1

CAN

Module 0

BSTD

PCFG

VIO

TLE9278-3BQX

Multi-CAN Power+ System Basis Chip

Block Diagram

2 Block Diagram

Figure 1 Block Diagram

Datasheet 7 Rev. 1.5

2019-09-27

1 CANH0

2 CANL0

3 GND

4 CANL1

5 CANH1

6 GND

7 CANH2

8 CANL2

9 GND

10 CANL 3

11 CANH3

12 PCFG

FO/TEST 48

VEXTREF 47

VEXTB 46

VEXTSH 45

VEXTIN 44

WK 42

GND 41

CLK 40

SDI 39

SDO 38

CSN 37

14 RXDCAN0

15 TXDCAN1

16 RXDCAN1

17 TXDCAN2

18 RXDCAN2

19 VCAN

20 TXDCAN3

21 RXDCAN3

22 VCC1

23 VIO

25 INTN

26 GND

28 n.c.

29 VS

30 VS

31 n.c.

32 GND

33 GND

34 n.c.

35 BSTD

TLE9278

PG-VQFN-48

24 RSTN

13 TX DCAN0

36 BSTD

27 BCKSW

VBSENSE 43

TLE9278-3BQX

Multi-CAN Power+ System Basis Chip

Pin Configuration

3 Pin Configuration

3.1 Pin Assignment

Figure 2 Pin Configuration TLE9278-3BQX

Datasheet 8 Rev. 1.5

2019-09-27

TLE9278-3BQX

Multi-CAN Power+ System Basis Chip

Pin Configuration

3.2 Pin Definitions and Functions

Pin Symbol Function

1CANH0 CAN High 0 Bus Pin.

2CANL0 CAN Low 0 Bus Pin.

3 GND Ground. CAN0 and CAN1 common ground.

4CANL1 CAN Low 1 Bus Pin.

5CANH1 CAN High 1 Bus Pin.

6GND Ground. Analog GND.

7CANH2 CAN High 2 Bus Pin.

8CANL2 CAN Low 2 Bus Pin.

9 GND Ground. CAN2 and CAN3 common ground.

10 CANL3 CAN Low 3 Bus Pin.

11 CANH3 CAN High 3 Bus Pin.

12 PCFG Configuration pin. For power up hardware configuration (refer to Chapter 5.1.1).

13 TXDCAN0 Transmit CAN0.

14 RXDCAN0 Receive CAN0.

15 TXDCAN1 Transmit CAN1.

16 RXDCAN1 Receive CAN1.

17 TXDCAN2 Transmit CAN2.

18 RXDCAN2 Receive CAN2.

19 VCAN Supply Input for internal HS-CAN modules.

20 TXDCAN3 Transmit CAN3.

21 RXDCAN3 Receive CAN3.

22 VCC1 Buck Regulator. Input feedback for Buck Converter.

23 VIO I/O voltage supply, reference voltage for over-/undervoltage monitoring

(see Chapter 5.1.1).

24 RSTN Reset Output. Active LOW, internal pull-up.

25 INTN Interrupt Output. Active LOW.

26 GND Ground. Buck regulator ground.

27 BCKSW Buck regulator switch node output.

28 n.c. not connected. Not bondend internally.

29 VS Buck Supply Voltage. Connected to Battery Voltage or Boost output voltage

with reverse protection diode. Use a filter against EMC in case that the Boost is not used.

30 VS Buck Supply Voltage. Connected to Battery Voltage or Boost output voltage

with reverse protection diode. Use a filter against EMC in case that the Boost is not used.

31 n.c. not connected. Not bondend internally.

32 GND Ground. Boost regulator ground.

33 GND Ground. Boost regulator ground.

Datasheet 9 Rev. 1.5

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TLE9278-3BQX

Multi-CAN Power+ System Basis Chip

Pin Configuration

Pin Symbol Function

34 n.c. not connected. Not bondend internally.

35 BSTD Boost Transistor Drain. Connected between inductor and diode for boost

functionality (refer to Chapter 14.1 for additional information). Connect to ground if the Boost regulator is not used.

36 BSTD Boost Transistor Drain. Connected between inductor and diode for boost

functionality (refer to Chapter 14.1 for additional information). Connect to ground if the Boost regulator is not used.

37 CSN SPI Chip Select Not Input.

38 SDO SPI Data Output. Out of SBC (=MISO).

39 SDI SPI Data Input. Into SBC (=MOSI).

40 CLK SPI Clock Input.

41 GND Ground. Common digital ground.

42 WK Wake Input.

43 VBSENSE Battery Voltage Monitoring Input.

44 VEXTIN Input Supply Voltage for VEXT. Connected to Battery Voltage with Reverse

Protection Diode and Filter against EMC.

45 VEXTSH VEXTSH. Emitter connection for external PNP, shunt connection to VEXTIN.

46 VEXTB VEXTB. Base connection for external PNP.

47 VEXTREF VextREF. Collector connection for external PNP, reference input.

48 FO/TEST Fail Output. active LOW, open-drain;

TEST. Connect to GND to activate SBC Development Mode; Integrated pull-up resistor. Connect to VS with a pull-up resistor or leave open for normal operation.

Cooling Tab

1) The exposed die pad at the bottom of the package allows better power dissipation of heat from the SBC via the PCB. The exposed die pad is not connected to any active part of the IC and can be left floating or it can be connected to GND (recommended) for the best EMC performance.

Note: All VS pins must be connected to battery potential or insert a reverse polarity diodes where required;

GND Cooling Tab - Exposed Die Pad; For cooling purposes only, do not use as an

electrical ground.

All GND pins as well as the Cooling Tab must be connected to one common GND potential.

Datasheet 10 Rev. 1.5

2019-09-27

TLE9278-3BQX

Multi-CAN Power+ System Basis Chip

Pin Configuration

3.3 Unused Pins

It must be ensured that the correct configurations are also selected, i.e. in case functions are not used that they are disabled via SPI:

• CANHx, CANLx, TXDCANx, RXDCANx: leave pins open.

•BSTD: connect to GND.

• WK: connect to GND and disable WK input via SPI.

• RSTN / INTN: leave open.

• FO/TEST: connect to GND during power-up to activate SBC Development Mode; connect to VS or leave open for normal user mode operation.

• VBSENSE: connect to VS in case that Fast Battery Voltage Monitoring and Boost deactivation features are not used and keep them disabled.

• VEXT: See Chapter 7.5.

• n.c.: leave open.

• Unused pins routed to an external connector which leaves the ECU should feature a zero ohm jumper (depopulated if unused) or ESD protection.

Datasheet 11 Rev. 1.5

2019-09-27

TLE9278-3BQX

Multi-CAN Power+ System Basis Chip

General Product Characteristics

4 General Product Characteristics

4.1 Absolute Maximum Ratings

Table 1 Absolute Maximum Ratings

Tj = -40°C to +150°C; all voltages with respect to ground, positive current flowing into pin

(unless otherwise specified)

Parameter Symbol Values Unit Note or

Min. Typ. Max.

Test Condition

Voltages

Supply Voltage VS and

S1, max

-0.3 – 28 V – P_4.1.1

VEXTIN pin

Supply Voltage VS and VEXTIN pin

Boost drain Voltage BSTD

S2, max

BSTD2, max

-0.3 – 40 V Load Dump, max. 400 ms

-0.3 – 28 V – P_4.1.3

Boost drain Voltage BSTD pin

Buck switch BCKSW pin V

Buck Regulator feedback,

BSTD2, max

BCKSW, max

CC1, max

-0.3 – 40 V Load Dump, max. 400 ms

-0.3 – VS+0.3 V – P_4.1.8

-0.3 – 5.5 V – P_4.1.9

pin VCC1

External Voltage Regulator (VEXTREF)

EXTREF, max

-0.3 – 28 V V

= 40 V for

EXTREF

Load Dump, max. 400 ms

Number

P_4.1.2

P_4.1.4

P_4.1.26

External Voltage Regulator (VEXTB)

External Voltage Regulator (VEXTSH)

Battery Voltage Monitoring V

Wake Input V

Fail Pins FO/TEST V

Interrupt/Configuration Pin INTN

Configuration Pin PCFG V

Configuration Pin VIO V

CANH, CANL V

Digital Input / Output pin’s V

VCAN Input Voltage V

Maximum Differential CAN Bus Voltage

EXTB, max

EXTSH, maxVEXTIN

-0.3 – V

-0.3

VBSENSE,

max

WK, max

HV, max

INTN, max

PCFG, max

VIO, max

BUS, max

IO, max

VCAN, max

CAN_DIFF,

max

-18 – 40 V – P_4.1.12

-0.3 – 40 V – P_4.1.13

-0.3 – 40 V – P_4.1.14

-0.3 – 5.5 V – P_4.1.15

-0.3 – 40 V – P_4.1.25

-0.3 – 5.5 V – P_4.1.28

-40 – 40 V – P_4.1.16

-0.3 – 5.5 V – P_4.1.17

-0.3 – 5.5 V – P_4.1.18

-5 – 10 V – P_4.1.30

– V

EXTIN

+10

EXTIN

+0.3

V V

= 40 V for

EXTB

Load Dump, max. 400 ms

V– P_4.1.11

P_4.1.27

Datasheet 12 Rev. 1.5

2019-09-27

TLE9278-3BQX

Multi-CAN Power+ System Basis Chip

General Product Characteristics

Table 1 Absolute Maximum Ratings1) (cont’d)

= -40°C to +150°C; all voltages with respect to ground, positive current flowing into pin

(unless otherwise specified)

Parameter Symbol Values Unit Note or

Min. Typ. Max.

Test Condition

Number

Temperatures

Junction Temperature T

Storage Temperature T

stg

-40 – 150 °C – P_4.1.19

-55 – 150 °C – P_4.1.20

ESD Susceptibility

ESD Resistivity to GND V

ESD Resistivity to GND,

ESD

-2 – 2 kV HBM

-8 – 8 kV HBM

2)3)

P_4.1.21

P_4.1.22

CANH, CANL

ESD Resistivity to GND V

ESD Resistivity Pin 1, 12,13,24,25,36,37,48 (corner

ESD

ESD1,12,13,2

4,25,36,37,48

-500 – 500 V CDM

-750 – 750 V CDM

P_4.1.23

P_4.1.24

pins) to GND

1) Not subject to production test, specified by design.

2) ESD susceptibility, HBM according to ANSI/ESDA/JEDEC JS-001 (1.5 kΩ, 100 pF).

3) ESD “GUN” Resistivity with ±6 KV (according to IEC61000-4-2 “GUN test” (300 Ω, 150 pF)) it is shown in Application Information and test will be provided from IBEE institute.

4) ESD susceptibility, Charged Device Model “CDM” EIA/JESD22-C101 or ESDA STM5.3.1, usually not tested but rather ESD SDM.

Notes

1. Stresses above the ones listed here may cause permanent damage to the device. Exposure to absolute maximum rating conditions for extended periods may affect device reliability.

2. Integrated protection functions are designed to prevent IC destruction under fault conditions described in the data sheet. Fault conditions are considered as “outside” normal operating range. Protection functions are not designed for continuous repetitive operation.

Datasheet 13 Rev. 1.5

2019-09-27

TLE9278-3BQX

Multi-CAN Power+ System Basis Chip

General Product Characteristics

4.2 Functional Range

Table 2 Functional Range

Parameter Symbol Values Unit Note or

Test Condition

see section

POR

Supply Voltage V

S,func

Min. Typ. Max.

POR

–28V1) V

Number

P_4.2.1

Chapter 12.12

CANx Supply Voltage V

SPI frequency f

CAN

SPI

4.75 – 5.25 V – P_4.2.2

––4MHz see

P_4.2.3

Chapter 13.7 for

SPI,max

Junction Temperature T

1) Including Power-On Reset, Over- and Undervoltage Protection.

-40 – 150 °C – P_4.2.4

Note: Within the functional range the IC operates as described in the circuit description. The electrical

characteristics are specified within the conditions given in the related electrical characteristics table.

Device Behavior Outside of Specified Functional Range:

• 28 V < V

< 40 V: Device will still be functional; the specified electrical characteristics might not be

S,func

ensured anymore. The absolute maximum ratings are not violated. However, a thermal shutdown might occur due to high power dissipation.

• V

< 4.75 V: The undervoltage bit VCAN_UV will be set in the SPI register BUS_STAT_0 and the transmitter

CAN

will be disabled as long as the UV condition is present.

• 5.25 V < V

< 5.5 V: CANx transceiver still functional. However, the communication might fail due to out-

CAN

of-spec operation.

•V

< VS < 5.5 V: Device will be still functional; the specified electrical characteristics might not be ensured

POR,f

anymore:

– The voltage regulators will enter the low-drop operation mode.

– VIO_UV reset could be triggered depending on the VRTx settings.

Datasheet 14 Rev. 1.5

2019-09-27

TLE9278-3BQX

Multi-CAN Power+ System Basis Chip

General Product Characteristics

4.3 Thermal Resistance

thJSP

thJA

Number

Min. Typ. Max.

Test Condition

–7 –K/WExposed PadP_4.3.1

–33–K/W

P_4.3.2

Table 3 Thermal Resistance

Parameter Symbol Values Unit Note or

Junction to Soldering Point R

Junction to Ambient R

1) Not subject to production test, specified by design.

2) According to Jedec JESD51-2,-5,-7 at natural convection on FR4 2s2p board for 1.5 W. Board: 76.2 × 114.3 × 1.5 mm3 with 2 inner copper layers (35 µm thick), with thermal via array under the exposed pad . Top and bottom layers are 70 µm thick.

4.4 Current Consumption

Table 4 Current Consumption

Current consumption values are specified at T (unless otherwise specified)

Parameter Symbol Values Unit Note or

SBC Normal Mode

= 25°C, VS = 13.5 V, all outputs open

Min. Typ. Max.

Number

Test Condition

Normal Mode current consumption

SBC Stop Mode

Stop Mode current Consumption

Stop Mode current Consumption, T

= 85°C

Normal

Stop,25

Stop,85

– 1016mAVS = 5.5 V to 28 V;

= -40°C to +150°C;

BOOST/VEXT/CANx = OFF

– 5570µA1) Buck in PFM

BOOST/VEXT = OFF; No load on VCC1

VBSENSE_EN = 0

CANx/WK not wake capable Watchdog = OFF

–95–µA2) Tj = 85°C;

Buck in PFM BOOST/VEXT = OFF; No load on VCC1

VBSENSE_EN = 0

CANx/WK not wake capable Watchdog = OFF

P_4.4.1

P_4.4.2

P_4.4.3

SBC Sleep Mode

Sleep Mode current consumption

Sleep,25

– 3050µABOOST/VEXT = OFF;

VBSENSE_EN = 0

P_4.4.4

CANx/WK not wake capable

Datasheet 15 Rev. 1.5

2019-09-27

TLE9278-3BQX

Multi-CAN Power+ System Basis Chip

General Product Characteristics

Table 4 Current Consumption (cont’d)

Current consumption values are specified at T (unless otherwise specified)

= 25°C, VS = 13.5 V, all outputs open

Parameter Symbol Values Unit Note or

Test Condition

BOOST/VEXT = OFF;

Sleep Mode current consumption, T

= 85°C

Sleep,85

Min. Typ. Max.

–65–µA2) Tj = 85°C;

VBSENSE_EN = 0

CANx/WK not wake capable

Feature Incremental Current Consumption

Current consumption per CAN module, recessive state

CAN,rec

–23mASBC Normal Mode;

CAN Normal Mode;

= 5 V;

CAN

TXDCAN

no RL on CANx

Current consumption per CAN module, dominant state

CAN,dom

–34.5mA2) SBC Normal Mode;

CAN Normal Mode;

= 5 V;

CAN

TXDCAN

no RL on CANx

Current consumption per CAN module, Receive Only Mode, SBC Normal Mode

CAN,RcvOnly,N

–0.40.6mA2) CAN Receive Only

Mode; V

TXDCAN

no RL on CANx

= VIO;

= GND;

= 5 V;

CAN

= VIO;

Number

P_4.4.5

P_4.4.6

P_4.4.7

P_4.4.8

Current consumption per CAN module, Receive Only Mode, SBC Stop Mode

Current consumption during CAN Partial Networking frame detect mode for one CAN module

CAN,RcvOnly,St

CAN,SWK,25

CAN,SWK,85

–11.4mA2) CAN Receive Only

Mode; V

TXDCAN

= 5 V;

CAN

= VIO;

no RL on CANx

– 700 790 µA

2)3)4)

Tj = 25°C;

VEXT = OFF; WK not wake capable; CAN SWK wake capable, SWK Receiver enabled, WUF detect; no RL on CANx

– 750 830 µA

2)3)4)

Tj = 85°C;

VEXT= OFF; WK not wake capable; CAN SWK wake capable, SWK Receiver enabled, WUF detect; no RL on CANx

P_4.4.25

P_4.4.9

P_4.4.10

Datasheet 16 Rev. 1.5

2019-09-27

TLE9278-3BQX

Multi-CAN Power+ System Basis Chip

General Product Characteristics

Table 4 Current Consumption (cont’d)

Current consumption values are specified at T (unless otherwise specified)

= 25°C, VS = 13.5 V, all outputs open

Parameter Symbol Values Unit Note or

Test Condition

Tj = 25°C; SBC Stop

Mode; VEXT = OFF; WK not wake capable;

Current consumption during CAN Partial Networking frame detect mode per additional CAN module

CAN,SWK2,25

Min. Typ. Max.

– 250 300 µA

CAN SWK wake capable, WUF detect; no RL on CANx

Current consumption for WK wake capability

Current consumption for WK wake capability T

= 85°C

Wake,WK,25

Wake,WK,85

–0.51.5µA

–2.04.0µA

4)5)

SBC Sleep Mode;

CANx = OFF

2)4)5)

SBC Sleep Mode;

= 85°C;

CANx = OFF

Current consumption for CAN wake capability

Wake,CAN,25

Wake,CAN,85

–4.56µA

–610µA

1)4)

SBC Sleep Mode;

WK = OFF

SILENCE

1)2)4)

SBC Sleep Mode;

= 85°C;

WK = OFF

SILENCE

Current consumption for VEXT in SBC Sleep Mode

Sleep,VEXT,25

– 4560µA4) SBC Sleep Mode;

VEXT = ON (no load); CANx / WK = OFF

Current consumption for VEXT in SBC Sleep Mode,

= 85°C

Sleep,VEXT,85

– 5570µA

2)4)

SBC Sleep Mode;

= 85°C; VEXT = ON

(no load); CANx / WK = OFF

Current consumption for cyclic wake function

Current consumption for cyclic wake function,

= 85°C

Current consumption for watchdog active in Stop

Stop,C25

Stop,C85

Stop,WD25

– 2026µA

– 2435µA

– 2026µA2) SBC Stop Mode;

4)6)

SBC Stop Mode;

WD = OFF

2)4)6)

SBC Stop Mode;

= 85°C;

WD = OFF

Watchdog running

Mode

Number

P_4.4.22

P_4.4.11

P_4.4.12

P_4.4.13

expired

P_4.4.14

expired

P_4.4.15

P_4.4.16

P_4.4.17

P_4.4.18

P_4.4.19

Current consumption for watchdog active in Stop Mode

Current consumption for active fail output (FO)

Stop,WD85

Stop,FO

– 2435µA2) SBC Stop Mode;

= 85°C;

Watchdog running

–0.51.5mA2) All SBC Modes;

= 25°C;

P_4.4.20

P_4.4.21

FO = ON (no load);

Datasheet 17 Rev. 1.5

2019-09-27

TLE9278-3BQX

Multi-CAN Power+ System Basis Chip

General Product Characteristics

Table 4 Current Consumption (cont’d)

Current consumption values are specified at T (unless otherwise specified)

= 25°C, VS = 13.5 V, all outputs open

Parameter Symbol Values Unit Note or

Min. Typ. Max.

Current consumption Fast

Stop,FBM

–5–µA2) SBC Stop Modes; Battery Monitoring in SBC Stop Mode

Additional V

current

BOOST,ON

– 1020mA2) SBC Normal / Stop consumption with Boost Module Active

1) Current consumption for CANx transceiver and WK input to be added if set to be wake capable or receiver only.

2) Not subject to production test, specified by design.

3) Current consumption adder applies during WUF detection (frame detect mode) when CAN Partial Networking is

activated. The current consumption will be reduced per module when multiple CAN transceivers are activated for SWK.

4) Current consumption adders of features defined for SBC Sleep Mode also apply for SBC Stop Mode and vice versa

(unless otherwise specified).

5) No pull-up or pull-down configuration selected.

6) Cyclic wake configuration: Timer with 20 ms period.

Test Condition

VBSENSE_EN = 1

Tj = 25°C;

Modes;

< VS< V

BSTx

BOOST_EN = 1

BST,thx

Number

P_4.4.30

P_4.4.31

;

Datasheet 18 Rev. 1.5

2019-09-27

TLE9278-3BQX

Multi-CAN Power+ System Basis Chip

System Features

5 System Features

This chapter describes the system features and behavior of the TLE9278-3BQX:

• State machine and SBC mode control.

• Device configurations.

• State of supply and peripherals.

• Wake features.

• Supervision and diagnosis functions.

The System Basis Chip is controlled via a 16-bit SPI interface. A detailed description can be found in

Chapter 13. The configuration as well as the diagnosis is handled via the SPI. The SPI mapping of the TLE9278-

3BQX is compatible to other devices of TLE926x and TLE927x family.

The System Basis Chip (SBC) offers six operating modes:

• SBC Init Mode: power-up of the device and after soft reset.

• SBC Normal Mode: the main operating mode of the device.

• SBC Stop Mode: the first-level power saving mode with the main voltage regulator enabled.

• SBC Sleep Mode: the second-level power saving mode with Buck regulator disable.

• SBC Restart Mode: an intermediate mode after a wake event from SBC Sleep or SBC Fail-Safe Mode or after

a failure (e.g. WD failure in config 1/3) to bring the microcontroller into a defined state via a reset. Once the failure condition is not present anymore, the device will automatically change to SBC Normal Mode after a delay time (t

• SBC Fail-Safe Mode: a safe-state mode after critical failures (e.g. TSD2 thermal shutdown) to bring the

system into a safe state and to ensure a proper restart of the system. Buck regulator is disabled.

A special mode called SBC Development Mode is available during software development or debugging of the system. All of the operating modes mentioned above can be accessed in this mode. However, the watchdog counter is stopped and does not need to be triggered. This mode can be accessed by setting the TEST pin to GND during SBC Init Mode.

RD1

5.1 State Machine Description and SBC Mode Control

The different SBC Modes are selected via SPI by setting the respective SBC MODE bits in the register

M_S_CTRL.

The SBC MODE bits are cleared when going trough SBC Restart Mode, so the current SBC mode is always shown.

Figure 3Figure 4 shows the SBC State Diagram.

Datasheet 19 Rev. 1.5

2019-09-27

SBC Init Mode

(Long open window )

VCC1 ON

(2)

inact.

CAN

OFF

(3)

Wake up event

via CANx or WK

Any SPI

command

SPI cmd

WD trigger

First battery connection

VIO Undervolta ge

Automatic

SBC Soft Reset

§ Reset is released

§ WD starts with long open window

(1) After Fail-Safe Mode entry, the device will stay for at least typ. 1s in this mode (with RO low) after a TSD2 event and min. typ. 100ms af ter other Fail -Safe Ev ents. Only t hen the dev ice can l eave the mode via a wake -up event. Wake ev ents are stored during this time .

(2) The behaviour depends of the PCFG configuration . If PCFG is open, the VEXT is by default off and it can be acivated from the µC with one of the four configurable output voltages . If PCFG = GND, the VEXT follows the VCC1 in the state machine with fixed output voltage value at 3.3V.

(3) Fo r SBC Developm ent Mode C AN is in N ormal Mode in SBC Init Mode and will stay ON when going from there to SBC Normal Mode

(4) See chapter CAN for detailed behavior in SBC Restart Mode

(5) CA N transceiver can be SWK capab le , depending on configurat ion

(6) Th e Boost regul ator activati on depends from the VS value .

SBC Normal Mode

act/inact

CAN

Config.

(3)

Boost

(6)

conf./OFF

SBC Restart Mode

(RO pin is as serted)

Config.: settings can be configur ed in this SBC mode;

Fixed: set tings stay as defined in SBC Normal Mode

The SBC Development Mode is a

super set of state machi ne where the

WD ti mer is stopped and CANx

behavior differs in SBC Init Mode.

Otherwi se, there are no diff erences in

behavior ( see also Chapter 5.1.7).

Cyc.Wake

OFF

Cyc.Wake

config .

CANx, WK wake-up event

VIO over v oltage

Config 1/3 (if VIO_OV_RST set)

Watc hdog Failure :

Config 1/3 (MAX_3_RST not set)

& 1st WD failure in Config4

Boost

OFF

VEXT

(2)

def.

by PCFG pin

VCC1

(2)

VEXT

(2)

def.

by PCFG pin

SBC Stop Mode

Cyc.Wake

fixed

Boost

(6)

fixed/OFF

CAN

(5)

fixed

VCC1

(2)

VEXT

(2)

def.

by PCFG pin

SBC Sleep Mode

Boost

OFF

Cyc.Wake

OFF

CAN

(5)

Wake

cap./OFF

fixed

VCC1

OFF

SPI cmd

1st W atchdog Failure Config 2,

2nd Watchdog F ailure, Config 4

VIO Short to GND

SBC Fail-Saf e Mode

(1)

TSD2 event

VIO over volt age

Config 2/4 (if VIO_OV_RST set)

4th consec utive VIO under vol tage ev ent (if VS > VS_UV_TO)

VCC1

OFF

fixed

Boost

OFF

VEXT

OFF

Cyc.Wake

OFF

CAN

Wake

capable

VCC1

(2)

VEXT

(2)

def.

by PCFG pin

Boost

(6)

fixed/OFF

active /

fixed

Cyc.Wake

OFF

CAN

(4)

Woken /

OFF

VEXT

(2)

def.

by PCFG pin

Config.

OFF

fixed

OFF

TLE9278-3BQX

Multi-CAN Power+ System Basis Chip

System Features

Figure 3 State Diagram showing the SBC Operating Modes

Datasheet 20 Rev. 1.5

2019-09-27

SBC Init Mode

(Long open window )

VCC1 ON

(2)

inact.

CAN

OFF

(3)

Wake up event

via CANx or WK

Any SPI

command

SPI cmd

WD trigger

First battery connection

VIO Undervolta ge

Automatic

SBC Soft Reset

§ Reset is released

§ WD starts with long open window

(3) Fo r SBC Developm ent Mode C AN is in N ormal Mode in SBC Init Mode and will stay ON when going from there to SBC Normal Mode

(4) See chapter CAN for detailed behavior in SBC Restart Mode

(5) Th e Boost regul ator activati on depends from the VS value .

SBC Normal Mode

act/inact

CAN

Config.

(3)

Boost

(5)

conf./OFF

SBC Restart Mode

(RO pin is as serted)

Config.: settings can be configur ed in this SBC mode;

Fixed: set tings stay as defined in SBC Normal Mode

The SBC Development Mode is a

super set of state machi ne where the

WD ti mer is stopped and CANx

behavior differs in SBC Init Mode.

Otherwi se, there are no diff erences in

behavior ( see also Chapter 5.1.7).

Cyc.Wake

OFF

Cyc.Wake

config .

CANx, WK wake-up event

VIO over v oltage

Config 1/3 (if VIO_OV_RST set)

Watc hdog Failure :

Config 1/3 (MAX_3_RST not set)

& 1st WD failure in Config4

Boost

OFF

VEXT

(2)

def.

by PCFG pin

VCC1

(2)

VEXT

(2)

def.

by PCFG pin

SBC Stop Mode

Cyc.Wake

fixed

Boost

(5)

fixed/OFF

CAN fixed

fixed

VCC1

(2)

VEXT

(2)

def.

by PCFG pin

SBC Sleep Mode

Boost

OFF

Cyc.Wake

OFF

CAN

Wake

cap./OFF

fixed

VCC1

OFF

SPI cmd

1st W atchdog Failure Config 2,

2nd Watchdog F ailure, Config 4

VIO Short to GND

SBC Fail-Saf e Mode

(1)

TSD2 event

VIO over volt age

Config 2/4 (if VIO_OV_RST set)

4th consec utive VIO under vol tage ev ent (if VS > VS_UV_TO)

VCC1

OFF

fixed

Boost

OFF

VEXT

OFF

Cyc.Wake

OFF

CAN

Wake

capable

VCC1

(2)

VEXT

(2)

def.

by PCFG pin

Boost

(5)

fixed/OFF

active /

fixed

Cyc.Wake

OFF

CAN

(4)

Woken /

OFF

VEXT

(2)

def.

by PCFG pin

Config.

OFF

fixed

OFF

TLE9278-3BQX

Multi-CAN Power+ System Basis Chip

System Features

Figure 4 State Diagram showing the SBC Operating Modes

Datasheet 21 Rev. 1.5

2019-09-27

TLE9278-3BQX

Multi-CAN Power+ System Basis Chip

System Features

5.1.1 Device Configuration and SBC Init Mode

The SBC Init Mode is the mode where the hardware configuration of the SBC is stored and where the microcontroller finishes the initialization phase.

The SBC starts up in SBC Init Mode after crossing the power-on reset V and the watchdog will start with a long open window (t

typical 200ms) after the RSTN is released.

threshold (see also Chapter 12.3)

POR,r

During this power-on phase following configurations are stored in the device:

• Supply and Power up configurability.

• The device behavior regarding a watchdog trigger failure and a VIO overvoltage condition is determined by

the external circuitry on the INTN pin (see below).

• The selection of the normal device operation or the SBC Development Mode (watchdog disabled for

debugging purposes) will be set depending on the voltage level of the FO/TEST pin (see also

Chapter 5.1.7).

5.1.1.1 Supply and Power up configurability

The TLE9278-3BQX has the possibility to define the level of the digital IO’s using a dedicated pin (VIO). A separate pin (PCFG) is available to store the I/O supply voltage configuration during power-up. The respective configuration will be stored for all conditions and can only be changed by powering down the device (V

POR,f

Depending of the configuration, the supervision functions can refer to VCC1 or VEXT.

The Table 5 shows the only allowed combinations and related behavior.

Table 5 Supply and power up Configurability

VCC1 Output

PCFG pin VIO Supply µC Supply VEXT

Output voltage

VEXT Behavior

Supervision Functions

Voltage

= 5 V Open VCC1 VCC1 Configurable via

CC1

SPI using

VEXT_VCFG

SPI configurable, OFF after Power Up

Supervision functions on VIO with 5 V level;

VREG_UV SPI

status bit active

= 5 V GND VEXT VEXT V

CC1

= 3.3 V

EXT

(fixed)

Follow the VCC1 (ON at Power up /SBC Normal / Stop / Sleep / Fails-Safe Mode)

Supervision functions on VIO with 3.3 V level;

VREG_UV status

not active but rerouted to VCC1

Note: VIO can be connected only to VCC1 or VEXT.

5.1.1.2 Watchdog trigger failure configuration

There are four different device configurations (Table 6) available defining the watchdog failure and the VIO overvoltage behavior. The configurations can be selected via the external connection on the INTN pin and the SPI bit CFG2 in the HW_CTRL_0 register (see also Chapter 13.4):

• A watchdog trigger failures leads to SBC Restart Mode (Config 1/3) and depending on CFG2 the Fail Output

(FO) are activated after the 1st or 2nd watchdog trigger failure;

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2019-09-27

TLE9278-3BQX

Multi-CAN Power+ System Basis Chip

System Features

If VIO_OV_RST is set and in Config 1/3, then SBC Restart Mode will be entered in case of VIO_OV and the FO is activated.

• A watchdog trigger failures leads to SBC Fail-Safe Mode (Config 2/4) and depending on CFG2 the Fail

Output (FO) are activated after the 1st or 2nd watchdog trigger failure. The first watchdog trigger failure in Config 4 will lead to SBC Restart Mode; If VIO_OV_RST is set and in Config 2/4, then SBC Fail-Safe Mode will be entered in case of VIO_OV and the FO is activated.

The respective device configuration can be identified by reading the SPI bits CFG2_STATE and CFG1_STATE in the WK_LVL_STAT register.

Table 6 Watchdog Trigger Failure Configuration

Config Event FO Activation SBC Mode Entry SPI Bit CFG2 INTN Pin

(CFG1_STATE)

1 1 × Watchdog Failure after 1st WD Failure SBC Restart Mode 1 External pull-up

2 1 × Watchdog Failure after 1st WD Failure SBC Fail-Safe Mode 1 No ext. pull-up

3 2 × Watchdog Failure after 2nd WD Failure SBC Restart Mode 0 External pull-up

4 2 × Watchdog Failure after 2nd WD Failure SBC Fail-Safe Mode 0 No ext. pull-up

The respective configuration will be stored for all conditions and can only be changed by powering down the device (V

< V

POR,f

Table 7 shows the possible SBC hardware configurations.

Table 7 SBC Configuration

Configuration Description FO/Test

Config 0 SBC Development Mode: no reset is

0- XX triggered in case of watchdog trigger failure. After the Power Up, one arbitrary SPI command must be sent.

Config 1 After missing the WD trigger for the first

time, the state of VCC1 remains

Open or

TEST,H

unchanged, FO pin is active, SBC in Restart Mode

INTN Pin (CFG1_ST

ATE)

External pull-up to

CFG2_STATECFG1_STA

Config 2 After missing the WD trigger for the first

time,VCC1 turns OFF, FO pin are active,

Open or

TEST,H

Open or GND

SBC in Fail-Safe mode

Config 3 After missing the WD trigger for the

second time, the state of VCC1 remains unchanged, FO pin is active, SBC in

Open or

TEST,H

External pull-up to

Restart Mode

Config 4 After missing the WD trigger for the

second time,VCC1 turns OFF, FO pin is

Open or

TEST,H

Open or GND

active, SBC in Fail-Safe mode

Datasheet 23 Rev. 1.5

2019-09-27

VIO

RSTN

POR,r

RD1

RT1,r

CFG_F

Configuration selection monitoring period

Config Select filter time

TLE9278-3BQX

Multi-CAN Power+ System Basis Chip

System Features

In case of 3 consecutive resets due to WD fail, it is possible in Config 1 and 3 not to generate additional reset by setting the MAX_3_RST on WD_CTRL.

Figure 5 shows the timing diagram of the hardware configuration selection. The hardware configuration is

defined during SBC Init Mode. The INTN pin is internally pulled LOW with a weak pull-down resistor during the reset delay time t INTN pin is monitored during this time and the configuration (depending on the voltage level at INTN) is read and stored at the rising edge of RSTN (with a filter time of t

, i.e. after VIO crosses the reset threshold VRT1 and before the RSTN pin goes HIGH. The

RD1

CFG_F

Figure 5 Hardware Selection Timing Diagram

Note: If the POR bit is not cleared then the internal pull-down resistor will be reactivated every time RSTN

is pulled LOW the configuration will be updated at the rising edge of RSTN. Therefore it is recommended to clear the POR bit right after initialization.

5.1.1.3 SBC Init Mode

In SBC Init Mode, the device waits for the microcontroller to finish its startup and initialization sequence. In the SBC Init Mode any SPI command will bring the SBC to SBC Normal Mode. During the long open window the watchdog has to be triggered. Thereby the watchdog will be automatically configured. A missing watchdog trigger during the long open window will cause a watchdog failure and the device will enter SBC Restart Mode.

Wake events are ignored during SBC Init Mode and will therefore be lost.

Note: Any SPI command will bring the SBC to SBC Normal Mode even if non-valid (see Chapter 13.2).

Note: For a safe start-up, it is recommended to use the first SPI command to trigger and to configure the

watchdog (see Chapter 12.2).

Datasheet 24 Rev. 1.5

2019-09-27

TLE9278-3BQX

Multi-CAN Power+ System Basis Chip

System Features

RT1

, the

Note: At power up, no VIO_UV will be issued nor will FO be triggered as long as VIO is below the V

threshold and V low as long as VIO is below the selected V RSTN is released after t

is below the VIO short circuit detection threshold V

threshold. As soon as the VIO is higher than V

RT1

RD1

. The RSTN pin will be kept

S,UV

5.1.2 SBC Normal Mode

The SBC Normal Mode is the standard operating Mode for the SBC. All configurations have to be done in SBC Normal Mode before entering a low-power mode (see also Chapter 5.1.6 for the device configuration defining the Fail-Safe Mode behavior). A wake-up event on CANx and WK will create an interrupt on pin INTN however, no change of SBC Mode will occur. The configuration options are listed below:

• VCC1 is active, Buck in PWM Mode.

• VEXT can be switched ON or OFF in accordance with Table 5.

• CANx is configurable (OFF coming from SBC Init Mode; OFF or wake capable coming from SBC Restart

Mode, see also Chapter 5.1.5).

• Wake pin level can be monitored and can be selected to be wake capable.

• Cyclic wake period can be configured using TIMER_CTRL_0 and enabled by setting TIMER1_WK_ EN.

• Watchdog is configurable.

• FO is OFF by default.

In SBC Normal Mode, there is the possibility of testing the FO output, i.e. to verify if setting the FO pin to low will create the intended behavior within the system. The FO output can be enabled and then disabled again by the microcontroller by setting the FO_ON SPI bit. This feature is only intended for testing purposes.

5.1.3 SBC Stop Mode

The SBC Stop Mode is the first level technique to reduce the overall current consumption. All kind of settings have to be done before entering SBC Stop Mode. In SBC Stop Mode any kind of SPI write commands are ignored and the SPI_FAIL bit is set, except for changing to SBC Normal Mode, triggering a SBC Soft Reset, refreshing the watchdog, changing modulation of the buck. The configuration options are listed below:

• VCC1 is ON, Buck in PFM Mode if I

• VEXT is fixed ON or OFF in accordance with Table 5 and SPI configuration.

• CANx can be selected for ‘Receive Only Mode’, to be wake capable or OFF.

• WK pin can be selected to be wake capable, PWM_BY_WK (switch PFM/PWM buck modulation) or OFF.

• Wake capability via cyclic wake can be selected.

• Watchdog is fixed or OFF (if WD disable sequence was executed).

A wake-up event on CANx and WK will create an interrupt on pin INTN however, no change of SBC Mode will occur.

In SBC Stop Mode, it is allowed to use the Boost module (enabled before to enter in SBC Stop Mode) in case of the V

is dropping. The Boost works only in PWM and therefore the total amount of current consumption will

increase.

Note: It is not possible to switch directly from SBC Stop Mode to SBC Sleep Mode. Doing so will also set the

SPI_FAIL flag and will bring the SBC into Normal Mode via SBC Restart Mode.

VCC1

< I

PFM-PWM,TH

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TLE9278-3BQX

Multi-CAN Power+ System Basis Chip

System Features

5.1.4 SBC Sleep Mode

The SBC Sleep Mode is the second level technique to reduce the overall current consumption to a minimum needed to react on wake-up events.

All settings must be done before entering SBC Sleep Mode. In case that SPI configurations in Sleep Mode have been sent to the SBC, the commands are ignored and no reactions from the SBC.

The configuration options are listed below:

•VCC1 is OFF.

• VEXT is fixed ON or OFF in accordance with Table 5 and SPI configuration.

• CANx can be selected to be wake capable or OFF.

• WK pin can be selected to be wake capable or OFF.

A wake-up event on CANx or WK pin will bring the device via SBC Restart Mode into SBC Normal Mode again and signal the wake event and corresponding sources.

It is not possible to switch off all wake sources in Sleep Mode. This will lead to SBC Normal Mode via SBC Restart Mode instead.

In order to enter SBC Sleep Mode successfully, all wake source signalization flags from WK_STAT_0 and

WK_STAT_2 need to be cleared. If a failure to do so, will result in an immediate wake-up from SBC Sleep Mode

by going via SBC Restart to Normal Mode.

Note: As soon as the Sleep Command is sent, the Reset will go low to avoid any undefined behavior

between SBC and microcontroller.

5.1.5 SBC Restart Mode

There are multiple reasons to enter the SBC Restart Mode. The purpose of the SBC Restart Mode is to reset the microcontroller:

• From SBC Normal and Stop Mode, it is reached in case of undervoltage on VIO. In case of 4 consecutive

VIO_UV events, SBC Fail-Safe Mode is entered.

• From SBC Normal and Stop Mode it is reached in case of overvoltage on VIO in config 1/3 if VIO_OV_RST is

set.

• Incorrect Watchdog triggering (depending of the configuration).

• From SBC Sleep and Fail-Safe Mode to ramp up VIO supply after wake event.

From SBC Restart Mode, the SBC goes automatically to SBC Normal Mode, i.e the mode is left automatically by the SBC without any microcontroller influence once the VIO_UV condition is not present anymore and when the reset delay time (t

Entering or leaving the SBC Restart Mode will not result in deactivation of the Fail output.

The following functions are not changed in SBC Restart mode:

• VEXT is fixed ON or OFF in accordance with Table 5 and SPI configuration.

• VCC1 is ON or ramping up.

) has expired. The Reset Output (RSTN) is released at the transition.

RD1

•BOOST is fixed or OFF.

Table 8 contains detailed descriptions of the reason to restart:

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TLE9278-3BQX

Multi-CAN Power+ System Basis Chip

System Features

Table 8 Reasons for Restart - State of SPI Status Bits after Return to Normal Mode

SBC Mode Event DEV_STAT WD_FAIL VIO_UV VIO_OV

Normal Watchdog Failure 01 01 x x

Normal VIO undervoltage reset 01 xx 1 x

Normal VIO overvoltage (VIO_OV_RST=1) 01 xx x 1

Sleep Mode Wake-up event 10 xx x x

Stop Mode Watchdog Failure 01 01 x x

Stop Mode VIO undervoltage reset 01 xx 1 x

Stop Mode VIO overvoltage (VIO_OV_RST=1) 01 xx x 1

Fail-Safe Wake-up event 01 see “Reasons for Fail-Safe, Table 9”

5.1.6 SBC Fail-Safe Mode

The purpose of this mode is to bring the system in a safe status after a failure condition by turning off the VCC1 and VEXT supply and the FO pin is automatically activated. After a wake-up event the system is then able to restart again.

The Fail-Safe Mode is automatically reached in case of:

• Overtemperature condition (TSD2).

• After 1 or 2 watchdog fails (depending on config setting).

• At the 4th consecutive VIO undervoltage event.

• From SBC Normal and Stop Mode, in case of overvoltage on VIO in config 2/4, if VIO_OV_RST is set.

• VIO is shorted to GND.

• VIO is below the VRTx for time longer than t

In this case, the default wake sources are activated, the wake-up events are cleared in the register WK_STAT_0 and WK_STAT_2. The mode will be maintained for at least t to avoid any fast toggling behavior. All wake sources will be masked during this time but the wake-up events will be stored. Stored wake-up events and wake-up event after this minimum waiting time, will lead to SBC Restart Mode. Leaving the SBC Fail-Safe Mode will not result in deactivation of the Fail Output pin.

The following functions are influenced during SBC Fail-Safe Mode:

• FO output is activated.

•VCC1 is OFF.

VIO,SC

in case of TSD2 event and t

TSD2

in case of other failure events

FS,min

• VEXT is OFF.

•CANx is wake capable.

•WK is wake capable (in case that PWM_BY_WK was set, moving to SBC Fail-Safe Mode will clear the bit).

•Cyclic wake is disabled.

Table 9 Reasons for Fail-Safe - State of SPI Status Bits after Return to Normal Mode

Mode Config Event DEV_STAT TSD2 WD_FAIL VIO_UV VIO_SC VIO_OV

Normal 2 1 × watchdog

failure

Normal 4 2 × watchdog

failure

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01 x 01 x 0 x

01 x 10 x 0 x

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TLE9278-3BQX

Multi-CAN Power+ System Basis Chip

System Features

Table 9 Reasons for Fail-Safe - State of SPI Status Bits after Return to Normal Mode (cont’d)

Mode Config Event DEV_STAT TSD2 WD_FAIL VIO_UV VIO_SC VIO_OV

Normal 1, 2, 3, 4 TSD2 01 1 xx x 0 x

Normal 1, 2, 3, 4 VIO short to GND 01 x xx 1 1 x

Normal 2, 4 VIO overvoltage

(VIO_OV_RST=1,

CFG2=1)

Stop Mode 2 1 × watchdog

failure

Stop Mode 4 2 × watchdog

failure

Stop Mode 1, 2, 3, 4 TSD2 01 1 xx x 0 x

Stop Mode 1, 2, 3, 4 VIO short to GND 01 x xx 1 1 x

Stop Mode 2, 4 VIO overvoltage

(VIO_OV_RST=1,

CFG2=1)

01 x xx x 0 1

01 x 01 x 0 x

01 x 10 x 0 x

01 x xx x 0 1

5.1.7 SBC Development Mode

The SBC Development Mode is used during development phase of the application, especially for software development.

Compared to the default SBC user mode operation, this mode is a super set of the state machine. The device will start also in SBC Init Mode and it is possible to use all the SBC Modes and functions with following differences:

• Watchdog is stopped and does not need to be triggered. Therefore no reset is triggered due to watchdog failure.

• SBC Fail-Safe and Restart Mode are not reached due to watchdog failure but the other reasons to enter these modes are still valid.

• CANx default value in SBC INIT MODE is ON instead of OFF.

The mode is reached by setting the FO/TEST pin to LOW for the entire SBC INIT Mode and by sending an arbitrary SPI command. The SBC Init Mode is reachable after the power-up or sending a software reset.

SBC Development Mode can only be left by a power-down or by providing a SBC Software Reset using the

MODE bits on M_S_CTRL register regardless the FO/TEST pin level.

When the FO/TEST pin is left open, or connected to V operation. The FO/TEST pin has an integrated pull-up resistor (switched ON only during SBC Init Mode) to prevent the SBC device from starting in SBC Development Mode during normal life of the vehicle. To avoid any disturbances, the FO/TEST pin is monitored during the SBC Init Mode when the RSTN is HIGH until SBC Init Mode is left. Only if the FO/TEST pin is LOW for the Init Mode time when the RSTN is HIGH, SBC Development Mode is reached and stored.

during the start-up, the SBC starts into normal

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Cyclic Wake Configuration

Cyclic Wake starts / ends by

setting / clearing On-time

INT is pulled low at every rising edge

of On-time except first one

Select Timer Period in

TIMER_CTRL_0

Periods: 10 , 20 , 50, 100, 200ms, 1s, 2s

Reset the TIMER1_WK_EN bit on

WK_CTRL_0 register

To avoid unintentional inter rupts

Set the TIMER1_WK_EN bit on

WK_CTRL_0 register

No interrupt will be generated,

if the timer is not enabled as a wake source

TLE9278-3BQX

Multi-CAN Power+ System Basis Chip

System Features

5.2 Wake Features

Following wake sources are implemented in the device:

• Static Sense: WK input is permanently active (see Chapter 9).

• Cyclic Wake: internal wake source controlled via internal timer (see Chapter 5.2.1).

• CANx wake: wake-up via CAN message (see Chapter 8).

The wake source must be set before entering in SBC Sleep Mode. In case of critical situation, when the device will be set into SBC Fail-Safe mode, all default wake sources will be activated. For additional information about setting, refer to the respective chapters.

5.2.1 Cyclic Wake

The cyclic wake feature is intended to reduce the quiescent current of the device and application.

When the cyclic wake is enabled, a periodic INTN is generated in SBC Normal and Stop Mode based on the setting of TIMER_CTRL_0.

The correct sequence to configure the cyclic wake is shown in Figure 6. The sequence is as follows:

• Disable the cyclic wake feature to ensure that there is not unintentional interrupt when activating cyclic wake (TIMER1_WK_ EN = 0).

• Configure the cyclic wake timer period in TIMER_CTRL_0 register.

• Enable the cyclic wake as a wake-up source in the register WK_CTRL_0 (TIMER1_WK_ EN = 1).

Figure 6 Cyclic Wake: Configuration and Sequence

5.2.2 Internal Timer

The integrated timer is typically used to wake up the microcontroller periodically (cyclic wake).

Following periods can be selected via the register TIMER_CTRL_0:

• Period: 10ms / 20ms / 50ms / 100ms / 200ms / 1s / 2s

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Multi-CAN Power+ System Basis Chip

5.3 CAN Partial Networking

5.3.1 CAN Partial Networking - Selective Wake Feature

The CAN Partial Networking feature can be activated for SBC Normal Mode, in SBC Sleep Mode and in SBC Stop Mode. For SBC Sleep Mode the Partial Networking has to be activated before sending the SBC to Sleep Mode. For SBC Stop Mode the Partial Networking has to be activated before going to SBC Stop Mode.

There are 2 detection mechanism available:

• WUP (Wake-Up Pattern) this is a CAN wake, that reacts on the CAN dominant time, with 2 dominant signals as defined in ISO WG11898-6.

• WUF (Wake-Up frame) this is the wake-up on a CAN frame that matches the programmed message filter configured in the SBC via SPI.

The default baud rate is set to 500 kBaud. Besides the commonly used baud rate of 125 kBaud and 250 kBaud, other baud rate up to 1 MBaud can be selected (see Chapter 13.5.2 and Chapter 13.6.2 for more details).

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