Infineon TLE9272QXV33 Datasheet

Datasheet Rev. 1.5

www.infineon.com 1 2019-09-27

TLE9272QXV33

High-End System Basis Chip Family

1 Overview

Features

Key Features

• Very low quiescent current consumption in SBC Stop and Sleep Mode

• Periodic Cyclic Wake in SBC Normal and Stop Mode

• SMPS 750mA (DC/DC buck) voltage regulator 3.3V to supply high current load with high efficiency

• DC/DC Boost converter for low battery supply voltage

• Low-Drop Voltage Regulator 5V/100mA, protected for off-board usage

• High-Speed CAN Transceiver:

– fully compliant to ISO11898-2:2016

– supporting CAN FD communication up to 5Mbps

• Up to 3 LIN Transceivers LIN2.2, SAE J2602 with programmable TXD timeout feature and LIN Flash Mode

• Compliant with “Hardware Requirements for LIN, CAN and FlexRay Interfaces in Automotive Applications” Revision 1.3, 2012-05-04

• One universal High-Voltage Wake Input for voltage level monitoring

• Configurable wake-up sources

• Reset Output

• Configurable timeout and window watchdog

• Fail-Safe Input to monitor MCU hardware functionality

• Up to three Fail-Safe Outputs (depending on configurations) to activate external loads in case of system malfunctions are detected

• Overtemperature and short circuit protection feature

• Wide input voltage and temperature range

•Software compatible with latest Infineon SBC families

• Green Product (RoHS compliant) & AEC Qualified

• PG-VQFN-48-31 leadless exposed-pad power package with Lead Tip Inspection (LTI)

Scalable System Basis Chip (SBC) Family

• Product family with various products for complete scalable application coverage

• Dedicated Datasheets are available for the different product variants

TLE9272QXV33

Overview

• Complete compatibility (hardware and software) across the family

• TLE9273 with 4 LIN transceivers, SMPS Boost with 2 output voltage configurations

• TLE9272 with 3 LIN transceivers, SMPS Boost with 2 output voltage configurations

• TLE9271 with 2 LIN transceivers, SMPS Boost with 2 output voltage configurations

• Product variants for 5V (TLE927xQX) and 3.3V (TLE927xQXV33) output voltage for main voltage regulator

Potential applications

•Body control modules

•Gateway

• HVAC ECU and Control panel

Product validation

Qualified for automotive applications. Product validation according to AEC-Q100/101.

Description

The TLE9272QXV33 is a monolithic integrated circuit in an exposed pad PG-VQFN-48-31 (7mm x 7mm) leadless package with Lead Tip Inspection (LTI) feature supporting Automatic Optical Inspection (AOI).

The device is designed for various CAN-LIN automotive applications as the main supply for the microcontroller and as the interface for LIN and CAN bus networks.

The System Basis Chip (SBC) provides the main functions for supporting these applications, such as a Switch Mode Power Supply regulator (SMPS) for on-board 3.3V supply, another 5V low-dropout voltage regulator with off-board protection, e.g. sensor supply, a DC/DC Boost converter for low supply voltage, an HS-CAN transceiver supporting CAN FD, a LIN transceiver for data transmission and a 16-bit Serial Peripheral Interface (SPI) to control and monitor the device. Additional feature include a timeout / window watchdog circuit with a reset feature, Fail-Safe Input and Fail-Safe Outputs and undervoltage reset features.

The device offers low-power modes in order to minimize current consumption on applications that are connected permanently to the battery. A wake-up from the low-power mode is possible via a message on the buses, via the bi-level sensitive monitoring/wake-up input as well as via cyclic wake.

The device is designed to withstand the severe conditions of automotive applications.

Type Package Marking

TLE9272QXV33 PG-VQFN-48-31 TLE9272QXV33

Datasheet 2 Rev. 1.5

2019-09-27

TLE9272QXV33

1 Overview . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1

Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1

Potential applications . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2

Product validation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2

Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2

Table of Contents . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3

2 Block Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6

3 Pin Configuration . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7

3.1 Pin Assignment . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7

3.2 Pin Definitions and Functions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8

3.3 Hints for Unused Pins . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10

4 General Product Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11

4.1 Absolute Maximum Ratings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11

4.2 Functional Range . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13

4.3 Thermal Resistance . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14

4.4 Current Consumption . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15

5 System Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18

5.1 State Machine Description and SBC Mode Control . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18

5.1.1 SBC Init Mode and Device Configuration . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19

5.1.2 SBC Normal Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21

5.1.3 SBC Stop Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21

5.1.4 SBC Sleep Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22

5.1.5 SBC Restart Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23

5.1.6 SBC Fail-Safe Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24

5.1.7 SBC Development Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25

5.2 Wake Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26

5.2.1 Cyclic Wake . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26

5.2.2 Internal Timer . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 27

5.3 Supervision Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 27

6 DC/DC Regulator . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 28

6.1 Block Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 28

6.2 Functional Description Buck converter . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 29

6.2.1 Startup Procedure (Soft Start) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 30

6.2.2 Buck regulator Status register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 30

6.2.3 External components . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 31

6.3 Functional Description Boost . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 32

6.3.1 Boost Regulator Status register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 33

6.3.2 External Components . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 33

6.3.2.1 Peak Overcurrent Detection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 33

6.4 Power Scenarios . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 34

6.4.1 Buck and Boost in SBC Normal Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 34

6.4.2 Buck and Boost in SBC Stop Mode Operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 34

6.4.2.1 Automatic Transition from PFM to PWM in SBC Stop Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 34

Datasheet 3 Rev. 1.5

2019-09-27

TLE9272QXV33

6.4.2.2 Manual Transition from PFM to PWM in SBC Stop Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 35

6.4.2.3 SBC Stop to Normal Mode Transition . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 36

6.4.3 Buck and Boost in SBC Sleep and Fail Safe Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 36

6.4.3.1 SBC Sleep/Fail Safe Mode to Normal Mode Transition . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 36

6.5 Electrical Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 37

7 Voltage Regulator 2 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 40

7.1 Block Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 40

7.2 Functional Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 41

7.3 Electrical Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 42

8 High Speed CAN Transceiver . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 44

8.1 Block Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 44

8.2 Functional Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 44

8.2.1 CAN OFF Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 46

8.2.2 CAN Normal Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 46

8.2.3 CAN Receive Only Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 47

8.2.4 CAN Wake Capable Mode (Wake-up Pattern) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 47

8.2.5 TXDCAN Time-out Feature . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 48

8.2.6 Bus Dominant Clamping . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 49

8.2.7 VCAN Undervoltage Detection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 49

8.3 Electrical Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 50

9 LIN Transceiver . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 58

9.1 Block Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 58

9.1.1 LIN Specifications . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 58

9.2 Functional Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 59

9.2.1 LIN OFF Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 59

9.2.2 LIN Normal Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 60

9.2.3 LIN Receive Only Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 60

9.2.4 LIN Wake Capable Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 60

9.2.5 TXDLIN Time-Out Feature . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 61

9.2.6 Bus Dominant Clamping . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 62

9.2.7 Undervoltage Detection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 62

9.2.8 Slope Selection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 62

9.2.9 Flash Programming via LIN . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 63

9.3 Electrical Characteristics of the LIN Transceiver . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 64

10 Wake Input . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 69

10.1 Block Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 69

10.2 Functional Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 70

10.2.1 Wake Input Configuration . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 71

10.3 Electrical Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 72

11 Interrupt Function . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 73

11.1 Block and Functional Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 73

11.2 Electrical Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 75

12 Fail-Safe Outputs and Fail-Safe Input . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 76

12.1 Functional Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 76

12.2 Fail-Safe Input . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 77

Datasheet 4 Rev. 1.5

2019-09-27

TLE9272QXV33

12.3 Electrical Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 78

13 Supervision Functions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 79

13.1 Reset Function . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 79

13.1.1 Reset Output Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 79

13.1.2 Reset Clamp to high . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 80

13.1.3 Soft Reset Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 80

13.2 Watchdog Function . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 81

13.2.1 Time-Out Watchdog . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 82

13.2.2 Window Watchdog . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 82

13.2.3 Watchdog Setting Check Sum . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 83

13.2.4 Watchdog during SBC Stop Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 83

13.2.4.1 WD Start in SBC Stop Mode due to BUS Wake . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 84

13.3 VS Power ON Reset . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 86

13.4 Under Voltage VLIN . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 86

13.5 Buck Regulator Monitoring Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 87

13.5.1 VCC1 Under Voltage . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 87

13.5.2 VCC1 Overvoltage . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 87

13.5.3 VCC1 Short Circuit . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 88

13.5.4 SMPS Status register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 88

13.6 VCC2 Undervoltage . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 88

13.7 VCAN Undervoltage . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 88

13.8 Thermal Protection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 89

13.8.1 Individual Thermal Shutdown . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 89

13.8.2 Temperature Prewarning . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 89

13.8.3 SBC Thermal Shutdown . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 89

13.9 Electrical Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 90

14 Serial Peripheral Interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 92

14.1 SPI Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 92

14.2 Failure Signalization in the SPI Data Output . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 93

14.3 SPI Programming . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 93

14.4 SPI Bit Mapping . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 95

14.5 SPI Control Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 97

14.6 SPI Status Information Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 105

14.7 Electrical Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 113

15 Application Information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 115

15.1 Application Diagram with Boost Module . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 115

15.2 Application Diagram without Boost Module . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 118

15.3 ESD Tests . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 121

15.4 Thermal Behavior of Package . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 122

16 Package Outlines . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 123

17 Revision History . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 124

Datasheet 5 Rev. 1.5

2019-09-27

CC1

Buck

CC2

SPI

Interrupt

Control

SBC

STATE

MACHINE

SDI

SDO

CLK

CSN

BCKSW

VCC2

CAN cell

LIN cell 1

Window Watchdog

TXDLIN

RXDLIN

TXDCAN

RXDCAN

VCAN

CANH

CANL

WK1

RESET

GENERATOR

INT

WAKE

Vint.

Fail Safe

FO1

LIN cell 2

TXDLIN

RXDLIN

LIN cell 3

TXDLIN

RXDLIN

GND

VCC1

Boost

BSTD

BSTG

SNSP

SNSN

CFG

VLIN

VS2

VSENSE

FO2/FSI

FO3/TEST

LIN1

LIN2

LIN3

TLE9272QXV33

Block Diagram

2 Block Diagram

Figure 1 Block Diagram

Datasheet 6 Rev. 1.5

2019-09-27

1 LIN1

2 GND

3 LIN2

4 n.c.

5 LIN3

6 GND

7 n.c.

8 GND

9 CANH

10 CANL

11 GND

12 TXDLIN1

FO3/TEST 48

FO2/FSI 47

FO1 46

VLIN 45

VS2 44

VCC2 43

GND 42

CLK 41

SDI 40

SDO 39

CSN 38

CFG 37

13 RXDLIN1

14 TXDLIN2

15 RXDLIN2

16 TXDLIN3

17 RXDLIN3

18 N.U.

19 N.U.

20 VCAN

21 TXDCAN

22 RXDCAN

23 VCC1

24 RO

25 INT

26 GND

27 BCKSW

28 VS

29 VS

30 VSENSE

31 n.c.

32 SNSN

33 SNSP

34 BSTG

35 BSTD

36 WK

TLE9272QXV33

PG-VQFN-48

TLE9272QXV33

Pin Configuration

3 Pin Configuration

3.1 Pin Assignment

Figure 2 Pin Configuration

Datasheet 7 Rev. 1.5

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TLE9272QXV33

Pin Configuration

3.2 Pin Definitions and Functions

Pin Symbol Function

1LIN1 LIN Bus 1. Bus line for the LIN interface, according to ISO. 9141 and LIN

specification 2.1 as well as SAE J2602-2.

2GND Ground: LIN1 and LIN2 common ground.

3LIN2 LIN Bus 2. Bus line for the LIN interface, according to ISO. 9141 and LIN

specification 2.1 as well as SAE J2602-2.

4n.c. not connected. Not bonded internally

5LIN3 LIN Bus 3. Bus line for the LIN interface, according to ISO. 9141 and LIN

specification 2.1 as well as SAE J2602-2.

6GND Ground. LIN3 and LIN4 common ground.

7n.c. not connected. Not bonded internally

8GND Ground.

9CANH CAN High Bus Pin.

10 CANL CAN Low Bus Pin.

11 GND Ground. CAN common ground.

12 TXDLIN1 Transmit LIN1.

13 RXDLIN1 Receive LIN1.

14 TXDLIN2 Transmit LIN2.

15 RXDLIN2 Receive LIN2.

16 TXDLIN3 Transmit LIN3.

17 RXDLIN3 Receive LIN3.

18 N.U. Not Used. Used for internal testing purpose. Do not connect, leave open.

19 N.U. Not Used. Used for internal testing purpose. Do not connect, leave open.

20 VCAN Supply Input for internal HS-CAN module.

21 TXDCAN Transmit CAN.

22 RXDCAN Receive CAN.

23 VCC1 Buck Regulator. Input feedback for Buck regulator

24 RO Reset Output. Active LOW, internal pull-up

25 INT Interrupt Output. Active LOW output

26 GND Ground. Buck regulator ground

27 BCKSW Buck regulator switch node output.

28 VS Buck Supply Voltage. Connected to battery voltage or Boost output voltage

with reverse protection diode. Use a filter against EMC in case the Boost is not used.

29 VS Buck Supply Voltage. Connected to battery voltage or Boost output voltage

with reverse protection diode. Use a filter against EMC in case the Boost is not used.

Datasheet 8 Rev. 1.5

2019-09-27

TLE9272QXV33

Pin Configuration

Pin Symbol Function

30 VSENSE Sense Input Voltage for Boost.

Boost regulator feedback input. Connect with VS.

31 n.c. not connected. Not bonded internally

32 SNSN Ground. Boost regulator ground.

33 SNSP Boost Transistor Source. Source connection for external MOSFET, sense

resistor connection. Connect to GND if Boost regulator is not used.

34 BSTG Boost Transistor Gate. Gate connection for external MOSFET. Connect to GND

or leave open if Boost regulator is not used.

35 BSTD Boost Transistor Drain. Drain connection for external MOSFET. Connect to VS if

Boost regulator is not used.

36 WK Wake Input.

37 CFG Hardware initialization pin.

external pull-up to VCC1 needed. Refer to Chapter 15.

38 CSN SPI Chip Select Not Input.

39 SDO SPI Data Output. Out of SBC (=MISO)

40 SDI SPI Data Input. Into SBC (=MOSI)

41 CLK SPI Clock Input.

42 GND Ground.

43 VCC2 Voltage Regulator Output 2.

44 VS2 Supply Voltage for VCC2. Connected to battery voltage with reverse protection

diode and filter against EMC.

45 VLIN Reference Voltage for LIN. Connected to battery voltage with reverse

protection diode and filter against EMC.

46 FO1 Fail Output 1. active LOW, open drain.

47 FO2/FSI Fail Output 2 - Side Indicator. Side Indicator 1.25Hz 50% duty cycle output;

active LOW, open drain. FSI. Fail-Safe Input (default configuration); connect to GND if not used.

48 FO3/TEST Fail Output 3 - Pulsed Lighted Output. Break/rear light 100Hz 20% duty cycle

output; active LOW, open-drain. TEST. Connect to GND to activate SBC Development Mode; integrated pull-up resistor. Connect to VS with a pull-up resistor or leave open for normal operation.

Coolin g Tab

1) The exposed die pad at the bottom of the package allows better power dissipation of heat from the SBC via the PCB.

Datasheet 9 Rev. 1.5

GND Cooling Tab - Exposed Die Pad; for cooling purposes, do not use as the only

electrical ground.

The exposed die pad is not connected to any active part of the IC. However it should be connected to GND for the best EMC performance.

2019-09-27

TLE9272QXV33

Pin Configuration

3.3 Hints for Unused Pins

It must be ensured that the correct configurations are also selected, i.e. in case functions are not used that they are disabled via SPI:

• WK: connected to GND and disable the WK input via SPI;

• LINx, RXDLINx, TXDLINx, RXDCAN, TXDCAN, CANH, CANL: leave all pins open;

• BSTD: connect to VS in case the Boost regulator is not used and keep disabled;

• BSTG: connect to GND or leave open in case the Boost regulator is not used and keep disabled;

• SNSP, SNSN: connect to GND in case the Boost regulator is not used;

•RO / FOx: leave open;

•INT: leave open;

• TEST: connect to GND during power-up to activate SBC Development Mode; connect to VS or leave open for normal user mode operation;

• VCC2: leave open and keep disabled;

• VCAN: connect to VCC1;

• n.c.: not connected, not bonded internally, connected to GND;

• Unused pins routed to an external connector which leaves the ECU should feature a zero ohm jumper (depopulated if unused) or ESD protection.

Datasheet 10 Rev. 1.5

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TLE9272QXV33

General Product Characteristics

4 General Product Characteristics

4.1 Absolute Maximum Ratings

Table 1 Absolute Maximum Ratings

Tj = -40 °C to +150 °C; all voltages with respect to ground, positive current flowing into pin (unless otherwise

specified)

Parameter Symbol Values Unit Note or

Min. Typ. Max.

Test Condition

Number

Voltages

Supply Voltage VS pin V

Supply Voltage VS2 pin V

Supply Voltage VS pin V

S, max

S2, max

S, max

-0.3 – 28 V – P_4.1.1

-0.3 – 28 V – P_4.1.25

-0.3 – 40 V Load Dump,

P_4.1.2

max. 400 ms

Supply Voltage VS2 pin V

S2, max

-0.3 – 40 V Load Dump,

P_4.1.26

max. 400 ms

LIN Supply Voltage VLIN pin V

Boost drain Voltage BSTD

LIN, max

BSTD, max

-0.3 – 40 V – P_4.1.12

-0.3 – 28 V – P_4.1.19

Boost drain Voltage BSTD pin

Boost Gate Voltage BSTG pin V

Supply Voltage SNSP pin V

Sense Voltage VSENSE pin V

Buck switch BCKSW pin V

Buck Regulator feedback,

BSTD, max

BSTG, max

SNSP, max

SENSE, max

BCKSW, max

CC1, max

-0.3 – 40 V Load Dump, max. 400 ms

-0.3 – 40 V – P_4.1.21

-0.3 – 40 V – P_4.1.22

-0.3 – 40 V – P_4.1.23

-0.3 – VS+0.3 V – P_4.1.24

-0.3 – 5.5 V – P_4.1.3

P_4.1.20

pin VCC1

Voltage Regulator 2 Output,

CC2, max

-0.3 – 40 V – P_4.1.5

pin VCC2

Wake Input V

Fail Pins FO1, FO2/FSI,

WK, max

FOx, max

-0.3 – 40 V – P_4.1.6

-0.3 – 40 V – P_4.1.7

FO3/TEST

Configuration Pin CFG V

CFG, max

-0.3 – VCC1

V – P_4.1.8

+ 0.3

LINx, CANH, CANL V

=CANH-CANL V

diff

Logic Input Voltage V

BUS, max

DIFF

I, max

-27 – 40 V – P_4.1.9

-5 – 10 V – P_4.1.28

-0.3 – VCC1

V – P_4.1.10

+ 0.3

Datasheet 11 Rev. 1.5

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TLE9272QXV33

General Product Characteristics

Table 1 Absolute Maximum Ratings1) (cont’d)

= -40 °C to +150 °C; all voltages with respect to ground, positive current flowing into pin (unless otherwise

specified)

Parameter Symbol Values Unit Note or

Test Condition

Logic Output Voltage V

O, max

Min. Typ. Max.

-0.3 – VCC1

V – P_4.1.27

Number

+ 0.3

VCAN Input Voltage V

VCAN, max

-0.3 – 5.5 V – P_4.1.11

Temperatures

Junction Temperature T

Storage Temperature T

stg

-40 – 150 °C – P_4.1.13

-55 – 150 °C – P_4.1.14

ESD Susceptibility

ESD Resistivity to GND V

ESD Resistivity to GND,

ESD

-2 – 2 kV HBM

-8 – 8 kV HBM

3)2)

P_4.1.15

P_4.1.16

CANH, CANL, LINx

ESD Resistivity to GND V

ESD Resistivity Pin 1, 12,13,24,25,36,37,48 (corner

ESD

ESD1,12,13,24,

25,36,37,48

-500 – 500 V CDM

-750 – 750 V CDM

P_4.1.17

P_4.1.18

pins) to GND

1) Not subject to production test, specified by design.

2) ESD susceptibility, “HBM” according to ANSI/ESDA/JEDEC JS-001 (1.5kΩ, 100pF).

3) For ESD GUN Resistivity, tested at 6KV (according to IEC61000-4-2 “gun test” (330Ω, 150pF)), it is shown in Application Information and test report, provided from IBEE, is available.

4) ESD susceptibility, Charged Device Model “CDM” EIA/JESD22-C101 or ESDA STM5.3.1.

Notes

1. Stresses above the ones listed here may cause permanent damage to the device. Exposure to absolute maximum rating conditions for extended periods may affect device reliability.

2. Integrated protection functions are designed to prevent IC destruction under fault conditions described in the data sheet. Fault conditions are considered as “outside” normal operating range. Protection functions are not designed for continuous repetitive operation.

Datasheet 12 Rev. 1.5

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TLE9272QXV33

General Product Characteristics

4.2 Functional Range

Table 2 Functional Range

Parameter Symbol Values Unit Note or

Test Condition

see section

POR

Supply Voltage V

S,func

Min. Typ. Max.

POR

–28V1) V

Number

P_4.2.1

Chapter 13.9

LIN Supply Voltage (VLIN

REF,LIN

5.5 – 18 V P_4.2.2

pin)

CAN Supply Voltage V

CFG external pull-up R

SPI frequency f

CAN

CFG

SPI

4.75 – 5.25 V – P_4.2.3

10 – 22 kΩ –P_4.2.6

––4MHzsee

P_4.2.4

Chapter 14.7 for

SPI,max

Junction Temperature T

1) Including Power-On Reset, Over- and Under voltage Protection

-40 – 150 °C – P_4.2.5

Note: Within the functional range the IC operates as described in the circuit description. The electrical

characteristics are specified within the conditions given in the related electrical characteristics table.

Device Behavior Outside of Specified Functional Range:

• 28V < V

< 40V: Device will still be functional; the specified electrical characteristics may not be ensured

S,func

anymore. The Buck and VCC2 will work, however, a thermal shutdown may occur due to high power dissipation. The specified SPI communication speed is ensured. The absolute maximum ratings are not violated, however the device is not intended for continuous operation of VS >28V. Operating the device at high junction temperatures for prolonged periods of time may reduce the life of the device.

• 18V < V

<28V: The LIN transceiver is still functional. However, the communication may fail due to out-of-

LIN

LIN-spec operation;

• V

LIN,UVD

< V

< 5.5V: The LIN transceiver is still functional. However, the communication may fail due to

LIN

out-of-LIN-spec operation;

• V

< 4.75V: The undervoltage bit VCAN_UV will be set in the SPI register BUS_STAT_1 and the transmitter

CAN

will be disabled as long as the UV condition is present;

• 5.25V < V

< 5.50V: CAN transceiver still functional. However, the communication may fail due to out-of-

CAN

spec operation;

• V

< VS < 5.5V: Device will be still functional; the specified electrical characteristics may not be ensured

POR,f

anymore:

– The voltage regulators will enter the low-drop operation mode;

–A VCC1_UV reset could be triggered depending on the Vrtx settings;

– The LIN transmitter will be disabled if V

LIN

< V

is reached and VLIN_UV bit on SUP_STAT is set;

LIN,UVD

– FOx outputs will remain ON if they were enabled;

– The specified SPI communication speed is ensured.

Datasheet 13 Rev. 1.5

2019-09-27

TLE9272QXV33

General Product Characteristics

4.3 Thermal Resistance

Table 3 Thermal Resistance

Parameter Symbol Values Unit Note or

Junction to Soldering Point R

Junction to Ambient R

1) Not subject to production test, specified by design.

2) According to Jedec JESD51-2,-5,-7 at natural convection on FR4 2s2p board for 1.5W. Board: 76.2x114.3x1.5mm3 with 2 inner copper layers (35µm thick), with a thermal via array under the exposed pad contacting the first inner copper layer and 300mm2 cooling area on the bottom layer (70µm). For more details, refer to Chapter 15.4.

thJSP

thJA

Number

Min. Typ. Max.

– 6 – K/W Exposed Pad P_4.3.1

–33–K/W

Test Condition

P_4.3.2

Datasheet 14 Rev. 1.5

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TLE9272QXV33

General Product Characteristics

4.4 Current Consumption

Table 4 Current Consumption

Current consumption values are specified at T

= 25°C, VS = 13.5V, all outputs open (unless otherwise specified)

Parameter Symbol Values Unit Note or Test Condition Number

Min. Typ. Max.

SBC Normal Mode

Normal Mode current consumption

Normal

– 5 10 mA 5.5V < VS < 28V

no load on VCC1

= -40°C to +150°C

P_4.4.1

VCC2 / CAN / LIN / BOOST = OFF

SBC Stop Mode

Stop Mode current consumption

Stop,25

– 5065µA

1)2)

Tj = 25°C

Buck module in PFM

P_4.4.2

no load on VCC1 VCC2 = OFF; CAN / LINx = OFF Watchdog = OFF WK enabled

Stop Mode current consumption

Stop,85

–95–µA

BOOST = OFF

1)2)3)

Tj = 85°C;

Buck module in PFM

P_4.4.3

no load on VCC1 VCC2 = OFF; CAN / LINx = OFF Watchdog = OFF WK enabled BOOST = OFF

Stop Mode current consumption, VCC2 enabled

Stop,VCC2,25

– 7095µA

1)2)

Tj = 25°C Buck module in PFM no load on VCC1

P_4.4.4

VS2 = VS VCC2 = ON (no load); CAN / LINx = OFF Watchdog = OFF WK enabled BOOST = OFF

Datasheet 15 Rev. 1.5

2019-09-27

TLE9272QXV33

General Product Characteristics

Table 4 Current Consumption (cont’d)

Current consumption values are specified at T

Parameter Symbol Values Unit Note or Test Condition Number

Min. Typ. Max.

Stop Mode current

Stop,C25

– 6585µA consumption, cyclic wake

SBC Sleep Mode

= 25°C, VS = 13.5V, all outputs open (unless otherwise specified)

1)2)

Tj = 25°C

P_4.4.5 Buck module in PFM no load on VCC1 VCC2 = OFF; CAN / LINx = OFF Watchdog = ON WK enabled BOOST = OFF

Sleep Mode current

Sleep,25

consumption

Sleep Mode current

Sleep,85

consumption

Sleep Mode current

Sleep,VCC2,25

consumption, VCC2 enabled

Incremental Current Consumption

Current consumption for

CAN,rec

CAN, recessive state

– 3050µA1) Tj = 25°C

VCC1,VCC2 = OFF CAN / LINx = OFF, WK enabled

–80–µA

1)3)

Tj = 85°C VCC1,VCC2 = OFF CAN / LINx = OFF WK enabled

– 5075µA1) Tj = 25°C

VCC1= OFF VS2 = VS VCC2 = ON (no load) CAN / LINx = OFF WK enabled

– 2 3 mA VCAN = VCC2

SBC Normal Mode CAN Normal mode VTXDCAN = 5V no RL on CAN

P_4.4.6

P_4.4.13

P_4.4.7

P_4.4.8

Current consumption for CAN, dominant state

CAN,dom

–34.5mA3)VCAN = 5V

SBC Normal Mode

P_4.4.14

CAN Normal mode VTXDCAN = GND no RL on CAN

Current consumption for CAN module, Receive Only Mode

CAN,RevOnly

–12mA1) VCAN = VCC2

SBC Normal / Stop Mode CAN Receive Only Mode

P_4.4.9

VTXDCAN = 5V no RL on CAN

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TLE9272QXV33

General Product Characteristics

Table 4 Current Consumption (cont’d)

Current consumption values are specified at T

Parameter Symbol Values Unit Note or Test Condition Number

Min. Typ. Max.

= 25°C, VS = 13.5V, all outputs open (unless otherwise specified)

Current consumption for CAN module wake capability

Current consumption per LIN module, recessive state

Current consumption per LIN module, dominant state

Current consumption per LIN module, Receive Only Mode

Current consumption per LIN module wake capability

CAN,wake

LIN,rec

LIN,dom

LIN,RcVOnly

LIN,wake

–4.56µA1) SBC Stop / Sleep / Fail-

Safe Mode; CAN wake capable; LIN1..4 = OFF

– 0.1 1.0 mA SBC Normal Mode

LIN Normal Mode; VTXDLIN = VCC1; no RL on LIN

–1.01.5mA3)SBC Normal Mode

LIN Normal Mode; VTXDLIN = GND; no RL on LIN

–0.10.2mA3)SBC Normal / Stop

Mode LIN Receive Only Mode; VTXDLIN = VCC1; no RL on LIN

–0.22µA1)SBC Stop / Sleep / Fail-

Safe Mode; CAN wake capable; LIN Wake capable

P_4.4.10

P_4.4.15

P_4.4.16

P_4.4.17

P_4.4.11

WK pin current consumption Wake Capable

WK,wake

– 0.2 2 µA SBC Normal / Stop /

Sleep / Fail-Safe Mode; WK wake capable;

P_4.4.12

LIN1..4, CAN = OFF

Additional Vs current consumption with Boost Module Active

BOOST,ON

–510mA3) SBC Normal / Stop

Mode VBSTx < VS < VBST,thx

P_4.4.18

BOOST = ON

1) Current consumption for CAN,LIN transceivers and WK input to be added if set to be wake capable or receiver only.

2) If the Buck regulator is working in PWM, the P_4.4.1 has to be added.

3) Specified by design; not subject to production test.

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TLE9272QXV33

System Features

5 System Features

This chapter describes the system features and behavior of the TLE9272QXV33:

• State machine and SBC mode control

• Device configurations

• State of supply and peripherals

• Wake features

• Supervision and diagnosis functions

The System Basis Chip (SBC) offers six operating modes:

• SBC Init Mode: power-up of the device and after soft reset;

• SBC Normal Mode: the main operating mode of the device;

• SBC Stop Mode: the first-level power saving mode with the main voltage regulator VCC1 enabled;

• SBC Sleep Mode: the second-level power saving mode with VCC1 disable;

• SBC Restart Mode: an intermediate mode after a wake event from SBC Sleep or SBC Fail-Safe Mode or after a failure (e.g. WD failure, VCC1 undervoltage reset) to bring the microcontroller into a defined state via a reset. Once the failure condition is not present anymore, the device will automatically change to SBC Normal Mode after a delay time (t

• SBC Fail-Safe Mode: a safe-state mode after critical failures (e.g. TSD2 thermal shutdown, VCC1 short to GND) to bring the system into a safe state and to ensure a proper restart of the system. VCC1 is disabled. This is a permanent state until either a wake event (via CAN, LINx or WK pin) occurs and the overtemperature condition is not present anymore.

A special mode called SBC Development Mode is available during software development or debugging of the system. All of the operating modes mentioned above can be accessed in this mode. However, the watchdog counter is stopped and does not need to be triggered. This mode can be accessed by setting the TEST pin to GND during SBC Init Mode.

The System Basis Chip is controlled via a 16-bit SPI interface. A detailed description can be found in

Chapter 14. The configuration as well as the diagnosis is handled via the SPI. The SPI mapping of the High End

SBC Family TLE927xQX is compatible with the latest Infineon SBC devices.

RD1

5.1 State Machine Description and SBC Mode Control

The different SBC Modes are selected via SPI by setting the respective SBC MODE bits in the register

M_S_CTRL. The SBC MODE bits are cleared when going trough SBC Restart Mode, so the current SBC mode is

always shown.

The Figure 3 shows the SBC State Diagram.

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WD Failure (Config 1/3)

Any SPI

command

WD trig

First battery con nection

VCC1

Underv oltage

VCC1 Short to GND

SBC Soft Reset

TSD2 event

* The SBC Development Mode

is a super set of state machine

where the WD timer is stopped.

Otherwise, there are no differences in behavior.

CAN, W K, LINx w ake-up ev ent

SBC Init M ode *

(Long open window)

VCC1ONVCC2

OFF

Boost

OFF

inact.

CAN OFF

LINx OFF

config.

Cyc.Wake

OFF

SBC Normal Mod e

VCC1ONVCC2

OFF/ON

Boost

conf./OFF

act. /Inac t.

CAN

config.

LINx

config.

Cyc.Wake

config.

The Boost regulator activation depends from the VS value.

See chapter CAN and LIN for detailed behaviour in SBC Restart Mode

See Chapter 5.1.5 and 12.1 for detailed FOx behavior

Must be set to CAN wake capable / CAN OFF mode before entering SBC sleep mode

SBC Stop Mode

VCC1ONVCC2

OFF/ON

Boost

fixed/OFF

act./I nact.

CAN fixed

LINx fixed

fixed/OFF

Cyc.Wake

fixed

SBC Sleep Mode

VCC1

OFF

VCC2

OFF/ON

Boost

OFF

act./I nact.

CAN

Wake

cap./OFF

LINx

Wake

cap./OFF

OFF

Cyc.Wake

OFF

SPI cmd SPI cmd

SPI cmd

SBC Restart Mode

(RO pin is asserted)

VCC1

ON/

ramping

VCC2

OFF

Boost

fixed/OFF

act./I nact.

CAN

woken/

OFF

LINx

woken/

OFF

Cyc.Wake

OFF

CAN, W K, LIN1..4 wake-up

event

Automatic

 Reset is released  WD s tarts with long open window

SBC Fail-Safe Mode

VCC1

OFF

VCC2

OFF

Boost

OFF

active

CAN

wake

capable

LINx

wake

capabl e

OFF

Cyc.Wake

OFF

VCC1 over voltage

(if VCC1_OV_RST set)

TLE9272QXV33

System Features

Figure 3 State diagram showing the SBC operating modes

5.1.1 SBC Init Mode and Device Configuration

The SBC Init Mode is the mode where the hardware configuration of the SBC is stored and where the microcontroller finishes the initialization phase. During the SBC Init Mode, the SBC can be configured in normal operation or in SBC development mode (see also Chapter 5.1.7).

The hardware configuration is done monitoring the level of FO3/TEST pin. The pin FO3/Test is set as an input and one internal pull-up resistor is activated (R

). The Table 5 shows possible hardware configurations.

TEST

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VCC1

POR,r

RD1

RT1,r

Configuration selection monitoring period

TLE9272QXV33

System Features

Table 5 SBC Configuration

Configuration Description FO3/Test Pin TEST CFG2_ STATE

Config 0 SBC Development Mode: no reset is triggered

01X in case of a watchdog trigger failure. After the Power-up, one arbitrary SPI command must be sent.

Config 1 After missing the WD trigger for the first time,

the state of V

remains unchanged, FOx pins

CC1

Open or

TEST,H

are active, SBC Restart Mode

Config 3 After missing the WD trigger for the second

time, the state of V

remains unchanged,

CC1

Open or

TEST,H

FOx pins are active, SBC Restart Mode

An external pull-up resistor on CFG pin (R

) is needed for proper SBC configuration. The Config 1 or 3 is

CFG

selectable via SPI using CFG2 bit on HW_CTRL register.

The timing diagram for hardware configuration is shown in Figure 4.

The SBC starts up in SBC Init Mode after crossing the V

threshold (see also Chapter 13.3) or after a

POR,r

software reset command. As soon as the VCC1 voltage reaches the rising reset threshold V configuration selection monitoring period starts for t released and the window watchdog starts with a long open window t

(Reset Delay Time). After this time, the reset pin is

RD1

RT1,r

, the

Figure 4 Hardware Configuration Selection Timing Diagram

During the long open window, the microcontroller shall finish its startup and initialization sequence. From this transition mode, the SBC can be set, via SPI command, to SBC Normal Mode.

Any SPI command will bring the SBC to SBC Normal Mode even if it is an illegal SPI command (Chapter 14.2).

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TLE9272QXV33

System Features

No watchdog trigger during the long open window, will cause a watchdog failure and the device will enter in SBC Restart Mode as shown in Table 5 and one reset event is generated.

In case of 3 consecutive reset events due to WD failures, it is possible not to generate additional reset by setting the MAX_3_RST on WD_CTRL and the SBC will remain in SBC Normal or Stop Mode (SBC Restart Mode not entered anymore). If the MAX_3_RST is set to 0, one reset event is generated for each missing watchdog trigger.

Wake-up events are ignored during SBC Init Mode and will therefore be lost.

Note: Any SPI command will bring the SBC to SBC Normal Mode even if it is an illegal SPI command (see

Chapter 14.2)

Note: For a safe start-up, it is recommended to use the first SPI commands to trigger and to configure the

watchdog

Note: At power up no VCC1_UV will be issued nor will the FOx be triggered as long as VCC1 is below V

threshold and below the VS threshold for VS under voltage time out V as long as VCC1 is below the selected V released after t

(Reset Delay Time).

RD1

threshold. When VCC1 is above the V

RT1,r

. The RO pin will be kept low

S,UV_TO

threshold, the RO is

RT1,r

5.1.2 SBC Normal Mode

The SBC Normal Mode is the standard operating Mode for the SBC. All configurations have to be done in SBC Normal Mode before entering a low-power mode. A wake-up event on CAN LIN1, LIN2, LIN3 and WK will create an interrupt on pin INT however, no changes of SBC Mode will occur. The configuration options are listed below:

• VCC1 is active (Buck regulator in PWM Mode)

• Boost Regulator can be configured and enabled or disabled. The module will start to work as soon as the

VS value is dropping below the selected threshold. For additional information, refer to Chapter 6.3.

• VCC2 can be switched ON or OFF (default off)

• CAN is configurable (OFF coming from SBC Init Mode; OFF or wake capable coming from SBC Restart Mode,

5.1.3 SBC Stop Mode

The SBC Stop Mode is the first level technique to reduce the overall current consumption. In this mode VCC1 regulator is still active and supplying the microcontroller, which can enter into a power down mode. The VCC2

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TLE9272QXV33

System Features

could be enabled or disabled, CAN & LIN can be configured as Receive Only Mode, or wake capable or disable. All kind of settings have to be done before entering SBC Stop Mode. In SBC Stop Mode any kind of SPI WRITE commands are ignored and the SPI_FAIL bit is set, except for changing to SBC Normal Mode, triggering a SBC Soft Reset, refreshing the watchdog, write the SYS_STAT_CTRL register as well as reading and clearing the SPI status registers. A wake-up event on CAN, LIN1, LIN2, LIN3 and WK will create an interrupt on pin INT however, no change of SBC Mode will occur. The configuration options are listed below:

• VCC1 is ON (Buck regulator in PFM Mode)

• Boost regulator is fixed as configured in SBC Normal Mode. The module will start to work as soon as the VS value drops below the selected threshold.

• VCC2 is fixed as configured in SBC Normal Mode

• CAN is fixed as configured in SBC Normal Mode

• LIN is fixed as configured in SBC Normal Mode

• WK is fixed as configured in SBC Normal Mode

• Cyclic wake is fixed as configured in SBC Normal Mode

Note: It is not possible to switch directly from SBC Stop Mode to SBC Sleep Mode. Doing so will also set the

SPI_FAIL flag and will bring the SBC into Restart Mode.

5.1.4 SBC Sleep Mode

The SBC Sleep Mode is the second level technique to reduce the overall current consumption to a minimum needed to react on wake-up events. In this mode, VCC1 regulator is OFF and not supplying the microcontroller anymore.The VCC2 supply can be configured to stay enabled. A wake-up event on CAN, LIN1, LIN2, LIN3 or WK pin return the device to SBC Normal Mode via SBC Restart Mode and signal the wake source.

The configuration options are listed below:

•VCC1 is OFF

• Boost regulator is OFF

• VCC2 is fixed as configured in SBC Normal Mode

• Can must be set to CAN wake capable / CAN off before entering SBC Sleep Mode

• LIN is fixed as configured in SBC Normal Mode

• WK is fixed as configured in SBC Normal Mode

It is not possible to switch off all wake sources in SBC Sleep Mode. When a CAN or LIN transceiver is in its Normal or Receive Only Mode, it counts as a wake source. In that case it changes automatically to Wake Capable when the SBC enters SBC Sleep Mode.

All settings must be made before entering SBC Sleep Mode. If SPI configurations were sent to the SBC in SBC Sleep Mode, the commands are ignored and there is no response from the SBC.

In order to enter SBC Sleep Mode successfully, all wake source signaling flags from WK_STAT_1 and

WK_STAT_2 need to be cleared. Otherwise, the device will immediately wake-up from SBC Sleep Mode by

going via SBC Restart to Normal Mode.

Note: As soon as the Sleep Command is sent, the Reset will go low to avoid any undefined behavior between SBC

and microcontroller

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TLE9272QXV33

System Features

5.1.5 SBC Restart Mode

There are multiple reasons to enter the SBC Restart Mode. The purpose of the SBC Restart Mode is to reset the microcontroller:

• From SBC Normal and Stop Mode:

– Undervoltage on VCC1;

– Overvoltage on VCC1 (if VCC1_OV_ RST is set);

– Incorrect Watchdog triggering.

• From SBC Sleep and Fail-Safe Mode:

– Wake-up event on CAN or LINx or WK;

– After TDS2 (only from SBC Fail-Safe Mode. See also Chapter 13.8).

Table 6 contains detailed descriptions of the reason to restart.

Table 6 Reasons for Restart - State of SPI Status Bits after Return to Normal Mode

SBC Mode Event DEV_STAT WD_FAIL VCC1_UV VCC1_OV VCC1_SC

Normal Watchdog failure 01 01 or 10 0 x x

Normal VCC1 undervoltage reset 01 xx 1 0 x

Normal VCC1 overvoltage reset 01 xx 0 1 x

Sleep Mode Wake-up event 10 00 0 x x

Stop Mode Watchdog failure 01 01 or 10 0 x x

Stop Mode VCC1 undervoltage reset 01 xx 1 0 x

Stop Mode VCC1 overvoltage reset 01 xx 0 1 x

Fail-Safe Wake-up event 01 see “Reasons for Fail-Safe,

It is possible to change the entering into SBC Restart Mode due to watchdog trigger failure using MAX_3_RST on WD_CTRL register. If the MAX_3_RST is set, after three consecutive resets, no further reset events are generated in case of missing watchdog trigger (see also Chapter 13.2).

From SBC Restart Mode, the SBC automatically enters to SBC Normal Mode, i.e. the mode is left automatically by the SBC without any microcontroller influence once the reset condition is no longer present and when the reset delay time (t

Entering or leaving SBC Restart Mode will not disable the Fail outputs.

The following functions are activated / deactivated in SBC Restart mode:

• VCC1 is ON or ramping up

• Boost Regulator is fixed as configured in SBC Normal Mode. The module will start to work as soon as the VS value drops below the selected threshold.

• VCC2 will be disabled if it was activated

• CAN is “woken” due to a wake-up event or OFF depending on previous SBC and transceiver mode (see also

Chapter 8). It is wake capable when it was in CAN Normal, Receive Only or wake capable mode before SBC

Restart Mode

) has expired. The Reset Output (RO) is released at the transition.

RD1

Table 7”

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TLE9272QXV33

System Features

• LINx are “woken” due to a wake-up event or OFF depending on previous SBC and transceiver mode (see also Chapter 9). It is wake capable when it was in LINx Normal, Receive Only or wake capable mode before SBC Restart Mode

• RO is pulled low during SBC Restart Mode

• SPI communication is ignored by the SBC, i.e. it is not interpreted

• SBC Restart Mode is signalled in the SPI register DEV_STAT by DEV_STAT bits.

Note: The VCC1 overvoltage reset is by default disabled. To enable it, the VCC1_OV_ RST has to be set. For

additional information, refer to Chapter 13.5.2.

5.1.6 SBC Fail-Safe Mode

The purpose of this mode is to bring the system in a safe status after a failure condition by turning off the VCC1 regulator and the RO will be LOW. After a wake-up event, the system can restart.

The Fail-Safe Mode is automatically reached in case of following events:

• overtemperature (TSD2) (see also Chapter 13.8);

• VCC1 is shorted to GND (see also Chapter 13.5.3).

In this case, the default wake sources are activated and the voltage regulators are switched OFF. The mode will be maintained for at least typical 1s (t other failure events to avoid any fast toggling behavior. All wake sources will be disabled during this time but wake-up events will be stored. Stored wake-up events and wake-up events after this minimum waiting time will lead to SBC Restart Mode. Leaving the SBC Fail-Safe Mode will not result in deactivation of the FOx pins.

The following functions are influenced during SBC Fail-Safe Mode:

• FO outputs are activated (see also Chapter 12)

•VCC1 is OFF

• Boost Regulator is OFF

•VCC2 is OFF

• CAN is wake capable

•LINx are wake capable

•WK is wake capable

• Cyclic wake is disabled, static sense is active with default filter time

• SPI communication is disabled because VCC1 is OFF

Table 7 Reasons for Fail-Safe - State of SPI Status Bits after Return to Normal Mode

) for a TSD2 event and typical 100ms (t

TSD2

FS,min

) for the

Mode Config Event DEV_STAT TSD2 WD_FAIL VCC1_UV VCC1_SC

Normal 1, 3 TSD2 01 1 xx x 0

Normal 1, 3, 4 VCC1 short to GND 01 x xx 1 1

Stop Mode 1, 3 TSD2 01 1 xx x 0

Stop Mode 1, 3 VCC1 short to GND 01 x xx 1 1

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TLE9272QXV33

System Features

5.1.7 SBC Development Mode

The SBC Development Mode is used during development phase of the application, especially for software development. The mode is reached by setting the FO3/TEST pin to LOW when the device is in SBC Init Mode and by sending an arbitrary SPI command. The SBC Init Mode is reached after the power-up.

When sending a software reset, it is no longer possible to enter SBC Development Mode.

The software reset is the SPI command that set the MODE bits in M_S_CTRL register.

SBC Development Mode can only be left by a power-down while FO3/TEST pin is high or open, or by setting the MODE bits on M_S_CTRL SBC Software Reset regardless of the state of FO3/TEST.

In this mode, the watchdog does not need to be triggered. No reset is triggered because of watchdog failure.

When the FO3/TEST pin is left open, or connected to Vs during the start-up, the SBC starts into normal operation. The FO3 pin has an integrated pull-up resistor, R prevent the SBC device from starting in SBC Development Mode during normal life of the vehicle.

, (switched ON only during SBC Init Mode) to

TEST

Datasheet 25 Rev. 1.5

2019-09-27

Cyclic Wake Configuration

Cyclic Wake starts automatically

INT is pulled low at the end of every

period

Select Timer Period in TIMER1_ CTRL

Periods: 10, 20 , 50 , 100 , 200ms, 1s, 2s

Select Timer1 as a wake source in

WK_CTRL_1

No interrupt will be generated,

if the t imer is not enabled as a wake source

TLE9272QXV33

System Features

5.2 Wake Features

The following wake sources are implemented in the device:

• Static Sense: WK input is permanently active (see Chapter 10)

• Cyclic Wake: internal wake source controlled via internal timer (see Chapter 5.2.1)

• CAN wake: Wake-up via CAN pattern (see Chapter 8)

• LIN wake: Wake-up via LIN bus (see Chapter 9)

The wake source must be set before entering in SBC Sleep Mode. In case of critical situation when the device will be set into SBC Fail-Safe mode, all default wake sources will be activated.

5.2.1 Cyclic Wake

The cyclic wake feature is intended to reduce the quiescent current of the device and application.

For the cyclic wake feature, Timer 1 is configured as internal wake-up source and will periodically trigger an interrupt in SBC Normal and Stop Mode based on the setting of TIMER1_CTRL.

The correct sequence to configure the cyclic wake is shown in Figure 5.

The sequence is as follows:

• Configure the respective period of Timer1 in the register TIMER1_CTRL.

• Enable Timer1 as a wake-up source in the register WK_CTRL_1.

Figure 5 Cyclic Wake: Configuration and Sequence

The cyclic wake function will start as soon as the Timer1 is enabled as wake-up source. An interrupt is generated at the end of every period.

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TLE9272QXV33

System Features

5.2.2 Internal Timer

The integrated timer is typically used to wake up the microcontroller periodically (cyclic wake).

The following periods can be selected via the register TIMER1_CTRL:

• Period: 10ms / 20ms / 50ms / 100ms / 200ms / 1s / 2s

5.3 Supervision Features

The device offers various supervision features to support functional safety requirements. Refer to Chapter 13 for more information.

Datasheet 27 Rev. 1.5

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GND

Buck

Converter

VCC1

BCKSW

Feedforward

Soft Sta rt

Ramp

Generator

Bandgap

Reference

C1 C3

Boost

Converter

SNSN

Comparator

Logic

SPI

Vbat

BSTG

BSTD

SNSP

VSENSE

Rsense

SUP

TLE9272QXV33

DC/DC Regulator

6 DC/DC Regulator

6.1 Block Description

The SMPS module in the TLE9272QXV33 is implemented as a cascade of a step-up pre-regulator followed by a step-down post-regulator. The step-up pre-regulator (DC/DC Boost converter) provides a VS level which permits the step-down post-regulator (DC/DC Buck converter) to regulate without entering a low-drop condition.

The SMPS module is active in SBC Normal, Stop and Restart Mode. In SBC Sleep and Fail-Safe Mode, the SMPS module is disabled.

Figure 6 DC/DC Block Diagram

Functional Features:

•

3.3V SMPS (DC/DC) Buck converter with integrated high-side and low-side power switching transistor;

• SMPS (DC/DC) Boost converter as pre-regulator for low VSUP supply voltage (down to 3V) with configurable output voltage via SPI;

• Fixed switching frequency for Buck and Boost converter in SBC Normal Mode in PWM (Pulse Width Modulation);

• PFM (Pulse Frequency Modulation) for Buck converter in SBC Stop Mode to reduce the quiescent current;

Datasheet 28 Rev. 1.5

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GND

Buck

Converter

VCC1

BCKSW

Feedforward

Soft St art

Ramp

Generator

Bandgap

Reference

Logic

SPI

C1 C2

Vbat

SUP

TLE9272QXV33

DC/DC Regulator

• Automatic transition PFM to PWM in SBC Stop Mode;

• Soft start-up;

• Edge Shaping for better EMC performances for Buck and Boost regulator;

• Undervoltage monitoring on V

•Overvoltage detection on V

with adjustable reset level (refer to Chapter 13.5.1);

CC1

(refer to Chapter 13.5.2);

CC1

• Buck short circuit detection;

• Boost current peak detection with external shunt resistor.

6.2 Functional Description Buck converter

Figure 7 Buck Block Diagram

The DC/DC Buck converter is intended as post-regulator (VCC1) and it provides a step down converter function transferring energy from VS to a lower output voltage with high efficiency (typically more than 80%). The output voltage is

3.3V in a current range up to 750mA. It is regulated via a digital loop with a precision of ±2%.

It requires an external inductor and capacitor filter on the output switching pin (BCKSW). The Buck regulator has two integrated power switches. The compensation of the regulation loop is done internally and no additonal external components are needed.

A typical application example and external components proposal is available in Chapter 15.

The Buck converter is active in SBC Normal, Stop and Restart Mode and it is disabled in SBC Sleep and Fail safe Mode.

Depending on the SBC Mode, the Buck converter works in two different modes:

• PWM Mode (Pulse Width Modulation): This mode is available in SBC Normal Mode, SBC Restart Mode and SBC Stop Mode (only for automatic or manual PFM to PWM transitions. Please ref to Chapter 6.4.2). In PWM, the Buck converter operates with a fix switching frequency (f internally based on input voltage, output voltage and output current. The precision is ±2% or ±3% based

Datasheet 29 Rev. 1.5

). The duty cycle is calculated

BCK

2019-09-27

Coil Current

Tristate TristateHS LS

Feedback Voltage VCC 1

PFM active

LVL

UCL

LCL

start biasing

oscillator

Quies cent Current

Iq Iq

OFF ON ONOFF

TLE9272QXV33

DC/DC Regulator

on input supply and output current range (refer to Figure 9 for more information). In PWM Mode, the Buck converter is capable of a 100% duty cycle in case of low VS conditions. In order to reduce EMC, edge shaping feature has been implemented to control the activation and deactivation of the two power switches.

• PFM Mode (Pulse Frequency Modulation): This mode is activated automatically when the SBC Stop Mode is entered. The PFM Mode is an asynchronous mode. PFM Mode does not have a controller switching frequency. The switching frequency depends on conditions of the Buck regulator such as the following: input supply voltage, output voltage, output current and external components. A typical timing diagram is shown in Figure 8. The Buck converter in PFM Mode has a tolerance of ±4%. The transition from PFM mode to PWM mode is described in Chapter 6.4.2.

Figure 8 Typical PFM timing diagram

6.2.1 Startup Procedure (Soft Start)

The Startup Procedure (Soft Start) permits to achieve the Buck regulator output voltage avoiding large overshoot on the output voltage. This feature is activated during the power-up, from SBC Sleep to Restart Mode and from SBC Fail-Safe to SBC Restart Mode.

When the Buck regulator is activated, it starts with a minimum duty cycle and the regulation loop maintains it for a limited number of switching periods. After this first phase, the duty cycle is increased by a fixed value and kept for a limited number of switching periods. This procedure is repeated until the target output voltage value of the Buck regulator is reached. As soon as the Buck regulator output voltage is reached, the regulation loop starts to operate normally using PWM Mode adjusting the duty cycle according the Buck input and output voltages and the Buck regulator output current.

6.2.2 Buck regulator Status register

The register SMPS_STAT contains information about the open or short conditions on BCKSW pin and if the Buck regulator is outside the 12% nominal output voltage range. No SBC Mode or configuration is triggered if one bit is set in the SMPS_STAT register.

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+ 96 hidden pages