INFINEON TLE 6286 User Manual

现货库存、技术资料、百科信息、热点资讯，精彩尽在鼎好!

LIN-Transceiver LDO TLE 6286

Target Data Sheet

1Overview

1.1 Features

• Single-wire transceiver, suitable for LIN protocol

• Transmission rate up to 20 kBaud

• Compatible to LIN specification

• Compatible to ISO 9141 functions

• Very low current consumption in sleep mode

• Control output for voltage regulator

• Short circuit proof to ground and battery

• Overtemperature protection

• Output voltage tolerance ≤ ± 2 %

• 200 mA output current capability

• Low-drop voltage

• Very low standby current consumption

• Overtemperature protection

• Reverse polarity protection

• Short-circuit proof

•Watchdog

• Wide temperature range

• Suitable for use in automotive electronics

P-DSO-16-4

Type Ordering Code Package

TLE 6286 G on request P-DSO-16-4

1.2 Description

The TLE 6286 is a single-wire transceiver with a LDO. It is chip by chip integrated circuit
in a P-DSO-16-4 package. It works as an interface between the protocol controller and
the physical bus. The TLE 6286 is especially suitable to drive the bus line in LIN systems
in automotive and industrial applications. Further it can be used in standard ISO9141
systems.

In order to reduce the current consumption the TLE 6286 offers a sleep operation mode.
In this mode a voltage regulator can be controlled in order to minimize the current
consumption of the whole application. The on-chip voltage regulator is designed for this

Version 1.02 1 2001-10-15

Target Data TLE 6286

application but it is also possible to use an external voltage regulator. A wake-up caused
by a message on the bus enables the voltage regulator and sets the RxD output low until
the device is switched to normal operation mode.

®

The IC is based on the Smart Power Technology SPT

which allows bipolar and CMOS
control circuitry in accordance with DMOS power devices existing on the same
monolithic circuit.

The TLE 6286 is designed to withstand the severe conditions of automotive applications.

Version 1.02 2 2001-10-15

1.3 Pin Configuration (top view)

Target Data TLE 6286

GND

RD

V

INHO

RxD

ENLIN

GND

GND

1

2

3

CC

4

5

6

7

89

P-DSO-16-4

116

Leadframe

16

15

14

13

12

11

10

GND

RO

INHIWD

V

BAT

BUS

TxD

V

GND

S

GND

Figure 1 Pinout

RD

WD

V

CC

INHO

RxD

ENLIN

GND

2

Chip:

Voltage

Regulator

4

5

6

7 10

8

Chip:

Transceiver

P-DSO-16-4

15

RO

143

INHI

13

V

BAT

12

BUS

11

TxD

V

S

9

GND

Version 1.02 3 2001-10-15

Target Data TLE 6286

1.4 Pin Definitions and Functions:

Pin No. Symbol Function

1,8,9,16 GND Ground; place to cooling tabs to improve thermal behavior

2RDReset delay; connected to ground with capacitor

3WDWindow Watchdog; rising-edge triggered, for monitoring a

microcontroller

4V

CC

5V Output; connected to GND with 22µF capacitor, ESC<3Ω

5 INHO Inhibit LIN Output; to control a voltage regulator

6RxDReceive Data Output; internal 30kΩ pull up to Vs, LOW in

dominat state

7ENLINEnable LIN Input; integrated 30kΩ pull down, transceiver in

normal operation mode when HIGH

10 V

S

5V Supply Input; VCC input to supply the LIN transceiver

11 TxD Transmit Data Input; internal 30kΩ pull up to Vs, LOW in

dominant state

12 BUS LIN BUS Output/Input; internal 30kΩ pull up to Vs, LOW in

dominant state

13 V

BAT

Battery Supply Input; a reverse current protection diode is
required, block GND with 100nF ceramic capacitor and 22µF
capacitor

14 INHI Inhibit Voltage Regulator Input; TTL compatible, low active

input

15 RO Reset Output; open collector output connected to the output via

a resistor of 30kΩ

Version 1.02 4 2001-10-15

1.5 Functional Block Diagram

Target Data TLE 6286

V

Bus

BAT

13

12

TLE 6259 G

30 k

5

INHO

10

V

S

Ω

Output

Stage

Driver

Mode

Control

30 k

Ω

7

ENLIN

Temp.-

Protection

11

TxD

Receiver

6

RxD

5

GND

WD

3

Temperature

Sensor

13

V

BAT

Bandgap

Reference

Adjustment

Figure 2 Block Diagram

Control

Amplifier

INHI

Buffer

Saturation

Control

and

Protection

Circuit

Watchdog

Generator

TLE 4263 G

114

GND

Reset

4

V

CC

2

RD

15

RO

Version 1.02 5 2001-10-15

Target Data TLE 6286

2 Circuit Description

The TLE 6286 is a single-wire transceiver combined with a LDO. It is a chip by chip
integrated circuit in a P-DSO-16-4 package. It works as an interface between the
protocol controller and the physical bus. The TLE 6286 is especially suitable to drive the
bus line in LIN systems in automotive and industrial applications. Further it can be used
in standard ISO9141 systems. The on-chip voltage regulator with watchdog is designed
for sleep mode applications but it is also possible to use an external voltage regulator.

Start Up

Power Up

Normal Mode

ENLIN

INHO

high high

ENLIN

low

ENLIN
(V

CC

high
ON)

Sleep Mode

ENLIN

INHO

low floating

1)

after wake-up via bus

2)

ON when INHO not connected to INHI

3)

after start up

Figure 3 Operation Mode State Diagram

V

CC

ON

V

CC

OFF

2)

ENLIN high

Stand-By

INHO

ENLIN

low high

Wake Up
t > t

WAKE

RxD

low
high

V

CC

1)

ON

3)

2.1 Operation Modes

In order to reduce the current consumption the TLE 6286 offers a sleep operation mode.
This mode is selected by switching the enable input EN low (see figure 3, state
diagram). In the sleep mode a voltage regulator can be controlled via the INH output in
order to minimize the current consumption of the whole application. A wake-up caused
by a message on the communication bus automatically enables the voltage regulator by
switching the INH output high. In parallel the wake-up is indicated by setting the RxD
output low. When entering the normal mode this wake-up flag is reset and the RxD
output is released to transmit the bus data.

Version 1.02 6 2001-10-15

Target Data TLE 6286

In case the voltage regulator control input is not connected to INH output or the
microcontroller is active respectively, the TLE6286 can be set in normal operation mode
without a wake-up via the communication bus.

2.2 LIN Transceiver

The LIN Transceiver has already a pull up resistor of 30kΩ as termination implemented.
There is also a diode in this path, to protect the circuit from feedback of voltages from
the bus line to the power supply. To configure the TLE 6286 as a master node, an
additional external termination resistor of 1kΩ is required. To avoid reverse currents from
the bus line into the battery supply line in case of an unpowered node, it is also
recommended to place a diode in series to the external pull up. For small systems (low
bus capacitance) the EMC performance of the system is supported by an additional
capacitor of at least 1nF in the master node (see figure 6, application circuit).

An capacitor of 10µF at the supply voltage input V

buffers the input voltage. In

S

combination with the required reverse polarity diode this prevents the device from
detecting power down conditions in case of negative transients on the supply line.

2.3 Voltage Regulator

The control amplifier compares a reference voltage, which is kept highly accurate by
resistance adjustment, to a voltage that is proportional to the output voltage and drives
the base of the series transistor via a buffer. Saturation control as a function of the load
current prevents any over-saturation of the power element. If the externally scaled down
output voltage at the reset threshold input drops below 1.35 V, the external reset delay
capacitor is discharged by the reset generator. When the voltage of the capacitor

V

reaches the lower threshold
until the upper threshold

V

DU

, a reset signal occurs at the reset output and is held

DRL

is exceeded. If the reset threshold input is connected to
GND, reset is triggered at an output voltage of typ. 4.65 V. A connected microcontroller
will be monitored through the watchdog logic. In case of missing pulses at pin W, the
reset output is set to low. The pulse sequence time can be set in a wide range with the
reset delay capacitor. The IC can be switched at the TTL-compatible, low-active inhibit
input. The IC also incorporates a number of internal circuits for protection against
overload, overtemperature, reverse polarity

2.4 Input Capacitor

C

The input capacitor
of approx. 1 Ω in series with

is necessary for compensation of line influences. Using a resistor

I

C

, the oscillating circuit consisting of input inductivity and

I

input capacitance can be damped. The output capacitor is necessary for the stability of
the regulating circuit. Stability is guaranteed at values ≥ 22 µF and an ESR of ≤ 3 Ω
within the operating temperature range. For small tolerances of the reset delay the
spread of the capacitance of the delay capacitor and its temperature coefficient should
be noted.

Version 1.02 7 2001-10-15

Target Data TLE 6286

2.5 Reset Timing

The power-on reset delay time is defined by the charging time of an external capacitor

C

which can be calculated as follows:

D

C

=(trd× I

D

D,ch

)/∆V

Definitions:CD= delay capacitor

t

= reset delay time

rd

I

= charge current, typical 60 µA

D,ch

∆

V = V

V

DU

, typical 1.70 V

DU

= upper delay switching threshold at CD for reset delay time

2.6 Watchdog Timing

The frequency of the watchdog pulses has to be higher than the minimum pulse
sequence which is set by the external reset delay capacitor

C

. Calculation can be done

D

according to the formulas given in Figure 5.

Version 1.02 8 2001-10-15

Target Data TLE 6286

3 Electrical Characteristics

3.1 Absolute Maximum Ratings

Parameter Symbol Limit Values Unit Remarks

min. max.

Voltages

Supply voltage

Battery supply voltage

Bus input voltage

Bus input voltage

V

V

Logic voltages at

V

V

V

EN, TxD, RxD

Input voltages at INH

Output current at INH

Reset output voltage

V

I

V

Reset delay voltage V

Output voltage Vcc

V

INHIBIT voltage V

Watchdog voltage V

Electrostatic discharge

V

voltage at Vs, Bus

CC

S

bus

bus

I

INH

INH

R

D

Q

INH

W

ESD

-0.3 6 V

-0.3 40 V

-20 32 V

-20 40 V t < 1 s

-0.3 V

CC

V0 V <

V

CC

< 5.5 V

+ 0.3

-0.3 V

S

V

+ 0.3

1mA

– 0.3 42 V –

– 0.3 42 V

– 0.3 7 V –

– 42 45 V –

– 0.3 6 V –

-4 4 kV human body model
(100 pF via 1.5 kΩ)

Electrostatic discharge
voltage

V

ESD

-2 2 kV human body model
(100 pF via 1.5 kΩ)

Temperatures

Junction temperature

Note: Maximum ratings are absolute ratings; exceeding any one of these values may cause

irreversible damage to the integrated circuit.

Version 1.02 9 2001-10-15

T

j

-40 150 °C –

Target Data TLE 6286

3.2 Operating Range

Parameter Symbol Limit Values Unit Remarks

min. max.

Supply voltage

Battery Supply Voltage

Junction temperature

V

V

T

CC

S

j

4.5 5.5 V

620V

– 40 150 °C

Thermal Shutdown (junction temperature)

Thermal shutdown temp.

T

Thermal shutdown hyst. ∆

jSD

T – 10 – K

150 170 190 °C

Thermal Resistances

Junction ambient

R

thj-a

– 115 K/W

–

–

Version 1.02 10 2001-10-15

3.3 Electrical Characteristics

Target Data TLE 6286

4.5 V < VCC<5.5V; 6.0V<VS<20V; RL=1kΩ; VEN> V
to ground; positive current flowing into pin; unless otherwise specified.

; -40 °C<Tj<125°C; all voltages with respect

EN,ON

Parameter Symbol Limit Values Unit Remarks

min. typ. max.

Current Consumption

Current consumption

Current consumption I

Current consumption I

Current consumption I

Current consumption I

Current consumption I

I

CC

S

CC

S

S

S

0.5 1.5 mA

0.5 1.0 mA

0.7 2.0 mA

0.7 1.5 mA

20 30 µA

20 40 µA

recessive state;
V

= V

TxD

recessive state;
V

TxD

dominant state;
V

TxD

dominant state;
V

TxD

sleep mode;

T

j

sleep mode

= V

= 0 V

= 0 V

=25°C

CC

CC

Receiver Output R×D

HIGH level output current

I

LOW level output current I

Bus receiver

Receiver threshold voltage,

V

recessive to dominant edge

Receiver threshold voltage,

V

dominant to recessive edge

Receiver hysteresis V

wake-up threshold voltage V

Transmission Input T×D

RD,H

RD,L

bus,rd

bus,dr

bus,hys

wake

-0.7 -0.4 mA

0.4 0.7 mA

0.44

V

x

0.02

V

x

0.40

V

x

0.48

V

x

S

S

S

S

0.52

V

x

S

0.04

V

x

S

0.55

V

x

S

0.56

V

x

0.06

V

x

0.70

V

x

V

V

S

mV

S

V

S

VRD = 0.8 x VCC,

VRD = 0.2 x VCC,

-8 V < V

V

bus,rec

V

bus,hys

V

bus,rec

bus

< V

=

- V

< V

< 20 V

bus

bus,dom

bus,dom

HIGH level input voltage

V

threshold

TxD input hysteresis V

TD,H

TD,hys

2.9 0.7 x

V

CC

V

300 600 mV

recessive state

Version 1.02 11 2001-10-15

3.3 Electrical Characteristics (cont’d)

Target Data TLE 6286

4.5 V < VCC<5.5V; 6.0V<VS<20V; RL=1kΩ; VEN> V
to ground; positive current flowing into pin; unless otherwise specified.

; -40 °C<Tj<125°C; all voltages with respect

EN,ON

Parameter Symbol Limit Values Unit Remarks

min. typ. max.

LOW level input voltage
threshold

TxD pull up current I

V

TD

TD,L

0.3 x

V

CC

2.1 V

-150 -110 -80 µA

dominant state

V

< 0.3 Vcc

TxD

Bus transmitter

V

Bus recessive output voltage

V

Bus dominant output voltage V

Bus short circuit current I

Leakage current I

bus,rec

bus,dom

bus,sc

bus,lk

0.9 x

V

S

V

S

V

01.5V

40 85 125 mA

-350 -100 µA

520µA

= V

TxD

V

TxD

V

bus,short

VCC=0V, VS=0V,
V

bus

VCC=0V, VS=0V,
V

bus

CC

= 0 V;

= 13.5 V

= -8 V, Tj<85°C

= 20 V, Tj<85°C

Bus pull up resistance R

Enable input (pin ENLIN)

HIGH level input voltage

V

threshold

LOW level input voltage

V

threshold

EN input hysteresis V

EN pull down resistance

R

Inhibit output (pin INHO)

HIGH level drop voltage

∆V

INH = VS

− V

INH

∆V

Leakage current I

bus

EN,on

EN,off

EN,hys

EN

INH

INH,lk

20 30 47 kΩ

0.3 x

V

CC

2.8 0.7 x

V

CC

2.2 V

V

300 600 mV

15 30 60 kΩ

0.5 1.0 V

- 5.0 5.0 µA

normal mode

low power mode

I

= - 0.15 mA

INH

sleep mode;

V

= 0 V

INHO

Version 1.02 12 2001-10-15

3.3 Electrical Characteristics (cont’d)

Target Data TLE 6286

4.5 V < VCC<5.5V; 6.0V<VS<20V; RL=1kΩ; VEN> V
to ground; positive current flowing into pin; unless otherwise specified.

; -40 °C<Tj<125°C; all voltages with respect

EN,ON

Parameter Symbol Limit Values Unit Remarks

min. typ. max.

Vcc Output (pin Vcc)

Output voltage

V

Output voltage V

Output current I

Current consumption;

I

= II – I

q

Q

Q

I

q

I

q

I

q

I

q

Drop voltage V

Load regulation ∆V

Line regulation ∆V

Power Supply Ripple

PSRR – 54 – dB

Rejection

Q

Q

4.90 5.00 5.10 V

4.90 5.00 5.10 V

200 250 – mA

–

–
–
–

dr

Q,lo

Q.li

– 0.35 0.50 V

––25 mV

– 325mV

0

900
10
15

50

1300
18
23

µA

µA

mA
mA

5 mA ≤ IQ ≤ 150 mA;
6 V ≤ V

6 V ≤ VI ≤ 32 V;

I

Q

T

1)

V

I

Q

I

Q

I

Q

IQ = 150 mA

IQ = 5 mA to 150 mA

VI = 6 V to 28 V;
I

Q

fr = 100 Hz; Vr =

0.5 V

≤ 28 V

I

= 100 mA;

= 100 °C

j

= 0

INH

= 0 mA
= 150 mA
= 150 mA; VI = 4.5 V

= 150 mA

PP

1)

Reset Genarator (pin RD)

Switching threshold

Reset adjust threshold

Reset low voltage V

Saturation voltage V

Upper timing threshold V

Lower reset timing threshold V

Charge current I

Reset delay time t

Reset reaction time t

V

Q,rt

V

RADJ,th

RO,l

D,sat

DU

DRL

D,ch

rd

rr

Version 1.02 13 2001-10-15

4.5 4.65 4.8 V

1.26 1.35 1.44 V

– 0.10 0.40 V

– 50 100 mV

1.45 1.70 2.05 V

0.20 0.35 0.55 V

40 60 85 µA

1.3 2.8 4.1 ms

0.5 1.2 4 µs

VQ > 3.5 V

IRO = 1 mA

VQ < V

R,th

–

–

–

CD = 100 nF

CD = 100 nF

3.3 Electrical Characteristics (cont’d)

Target Data TLE 6286

4.5 V < VCC<5.5V; 6.0V<VS<20V; RL=1kΩ; VEN> V
to ground; positive current flowing into pin; unless otherwise specified.

; -40 °C<Tj< 125 °C; all voltages with respect

EN,ON

Parameter Symbol Limit Values Unit Remarks

min. typ. max.

Watchdog (pin WD)

Discharge current

I

Upper timing threshold V

Lower timing threshold V

Watchdog trigger time T

D,wd

DU

DWL

WI,tr

4.40 6.25 9.10 µA

1.45 1.70 2.05 V

0.20 0.35 0.55 V

16 22.5 27 ms

VD = 1.0 V

–

–

CD = 100 nF

Inhibit Input (INHI)

Switching voltage

V

Turn-OFF voltage V

Input current I

Note: The reset output is low within
the range V

1)

Drop voltage = Vi – VQ (measured
when the output voltage has
dropped 100 mV
from the nominal value obtained at
6 V input)

= 1 V to V

Q

Q,rt

INH,ON

INH,OFF

INH

3.6 ––V

––0.8 V

51025µA

IC turned on

IC turned off

V

= 5 V

INH

Version 1.02 14 2001-10-15

3.3 Electrical Characteristics (cont’d)

Target Data TLE 6286

4.5 V < VCC<5.5V; 6.0V<VS<20V; RL=1kΩ; VEN> V
to ground; positive current flowing into pin; unless otherwise specified.

; -40 °C<Tj<125°C; all voltages with respect

EN,ON

Parameter Symbol Limit Values Unit Remarks

min. typ. max.

Dynamic Transceiver Characteristics

falling edge slew rate

rising edge slew rate S

Propagation delay
TxD-to-RxD LOW (recessive
to dominant)

Propagation delay
TxD-to-RxD HIGH (dominant
to recessive)

S

bus(L)

bus(H)

t

d(L),TR

t

d(H),TR

-3 -2.0 -1 V/µs

1 1.5 3 V/µs

2510µs

2510µs

80% > V

C

bus

T

ambient

V

CC

20% < V

C

bus

V

CC

C

bus

V

CC

C

RxD

C

bus

V

CC

C

RxD

bus

= 3.3 nF;

<85°C;

= 5 V; VS = 13.5 V

bus

= 3.3 nF;

= 5 V; VS = 13.5 V

= 3.3nF;

= 5 V; VS = 13.5 V

= 20 pF

= 3.3 nF;

= 5 V; VS = 13.5 V

= 20 nF

> 20%

< 80%

Propagation delay
TxD LOW to bus

Propagation delay
TxD HIGH to bus

Propagation delay
bus dominant to RxD LOW

Propagation delay
bus recessive to RxD HIGH

Receiver delay symmetry t

Transmitter delay symmetry t

Wake-up delay time t

t

d(L),T

t

d(H),T

t

d(L),R

t

d(H),R

sym,R

sym,T

wake

14µs

14µs

14µs

14µs

-2 2 µs

-2 2 µs

30 100 200 µs

VCC = 5 V

VCC = 5 V

VCC = 5V;

C

= 20pF

RxD

VCC = 5 V;

C

= 20 pF

RxD

t

= t

sym,R

t

sym,T

= t

d(L),R

d(L),T

- t

- t

d(H),R

d(H),T

Version 1.02 15 2001-10-15

4 Diagrams

V

I

V

Q

V

Q, rt

V

D

V

DU

V

DRL

t t

rd

V

RO

Target Data TLE 6286

<

t

rr

V

d

=

t

d

rr

I

D, ch

C

t

t

D

t

Power-ON

Figure 4

V

DU

V

DWL

Reset

Over-

temperature

Voltage Drop

at Input

Under-

Secondary

voltage Spike

Load

Bounce

Time Response, Watchdog with High-Frequency Clock

V

W

V

Ι

V

Q

V

D

V

RO

T

WD, p

t

WD, L

T

WI, tr

t

AET03066

t

t

t

t

T =

WI, tr

VV(

DU-DWL

Ι

D, wd

VDU-V

)

T

C

D

()

=

WD, p

DWL

Ι

D, wc

Ι

(

D, wc+D, wd

Ι

x

D, wd

)

Ι

t =

CD;;

WD, L

Ι

VV(DU-

DWL

D, wc

)

C

D

AED03099

t

Figure 5 Timing of the Watchdog FunctionReset

Version 1.02 16 2001-10-15

5 Application

Target Data TLE 6286

V

bat

LIN bus

master node

22 µF

1 k

C

D

100 nF

W

13

12

14

100 nF

5

2

V

BAT

Bus

INHO

INHI

RD

ENLIN

TLE 6286 G

GND

1,8,9, 16

WD

RO

RxD

TxD

V

3

15

7

6

11

V

10

S

100 nF

5V

4

CC

100 nF

µP

GND

22 µF

ECU 1

slave node

22 µF

C

D

Figure 6 Application Circuit

100 nF

100 nF

13

12

5

14

INHI

RD

2

V

BAT

Bus

INHO

TLE 6286 G

GND

ENLIN

RxD

1,8,9, 16

WD

RO

TxD

V

V

3

15

7

6

11

10

S

100 nF

5V

4

CC

100 nF

µP

GND

22 µF

ECU X

Version 1.02 17 2001-10-15

6 Package Outlines

P-DSO-16-4

(Plastic Dual Small Outline Package)

Pictures of the housing will be added in near future!

Target Data TLE 6286

Sorts of Packing

Package outlines for tubes, trays etc. are contained in our
Data Book “Package Information”.

SMD = Surface Mounted Device

Dimensions in mm

Version 1.02 18 2001-10-15

Target Data TLE 6286

Edition 1999-10-12

Published by Infineon Technologies AG
St.-Martin-Strasse 53
D-81541 München

© Infineon Technologies AG1999

All Rights Reserved.

Attention please!

The information herein is given to describe certain components and shall not be considered as warranted characteristics.

Terms of delivery and rights to technical change reserved.

We hereby disclaim any and all warranties, including but not limited to warranties of non-infringement, regarding circuits, descriptions and
charts stated herein.

Infineon Technologies is an approved CECC manufacturer.

Information

For further information on technology, delivery terms and conditions and prices please contact your nearest Infineon Technologies Office
in Germany or our Infineon Technologies Representatives worldwide (see address list).

Warnings

Due to technical requirements components may contain dangerous substances. For information on the types in question please contact
your nearest Infineon Technologies Office.

Infineon Technologies Components may only be used in life-suppor t devices or systems with the express written approval of Infineon Tech­nologies, if a failure of such components can reasonably be expected to cause the failure of that life-support device or system, or to affect
the safety or effectiveness of that device or system. Life suppor t devices or systems are intended to be implanted in the human body, or to
support and/or maintain and sustain and/or protect human life. If they fail, it is reasonable to assume that the health of the user or other
persons may be endangered.

Version 1.02 19 2001-10-15