INFINEON TLE 6266 G User Manual
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System Basis Chip TLE 6266 G
Target Datasheet
1Features
• Standard Fault Tolerant differential CAN-Transceiver
• Bus Failure Management
• Low current consumption mode <70µA
• CAN Data Transmission Rate up to 125 kBaud
• Low-Dropout Voltage Regulator 5V ± 2%
• Two Low Side Switches
• Three High Side Switches with internal Charge Pump
• Power On and Under-Voltage Reset Generator
• Vcc Supervisor
• Window Watchdog
• Flash Program Mode
• Programable Cyclic Wake Timing via SPI
• Integrated Fail-Safe Mechanism
• Standard 16 bit SPI-Interface
• Wide Input Voltage and Temperature Range
• Thermal Protection
• Enhanced Power P-DSO-Package
• Wakeup Input Pin
P-DSO-28-6
Enhanced Power
Type Ordering Code Package
TLE 6266 G on request P-DSO-28-6
2 Description
The TLE 6266 G is a monolithic integrated circuit in an enhanced power P-DSO-28-6
package, which incorporates a failure tolerant low speed CAN-transceiver for differential
mode data transmission, a low dropout voltage regulator for internal and external 5V
supply as well as a 16 bit SPI interface to control and monitor the IC. Further there are
integrated additional features like three high side switches, two low side switches, a
window watchdog circuit and a reset circuit. The IC offers a low current consumption
mode, that reduces the current to typ. 70µA.
The IC is designed to withstand the severe conditions of automotive applications and is
optimized for low-speed data transmission (up to 125 kBaud).
Version 1.06 2 2002-11-26
3 Pin Configuration
(top view)
Target Datasheet TLE 6266
CANH
CANL
OUTH1
1
2
RTH
3
RO
4
5
RTL
6
GND GND
7
GND
8
GND GND
9
GND
10
28
27
26
25
24
23
22
21
20
19
WK
PWM
TxD
RxD
Vcc
GND
GND
CLK
OUTL1
OUTL2
OUTH2
OUTH3
11
12
13
14
(enhanced power package)
Figure 1 TLE 6266 Block Diagram
P-DSO-28-6
18
17
16
15
DI
DO
CSN
Vs
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Target Datasheet TLE 6266
4 Pin Definitions and Functions
Pin No. Symbol Function
1CANHCAN-H bus line; HIGH in dominant state
2RTHCANH-Termination input; connected to CANH via external
termination resistor
3ROReset output; open drain output; integrated pull up; active LOW
4CANLCAN-L bus line; LOW in dominant state
5RTLCANL-Termination input; connected to CANL via external
termination resistor
6, 7, 8, 9,
20, 21,
GND Ground; to reduce thermal resistance place cooling areas on
PCB close to this pins.
22, 23
10 OUTH1 High side output 1; controlled via PWM input and/or SPI input,
short circuit protected
11 OUTL1 Low side output 1; SPI controlled, with active zener
12 OUTL2 Low side output 2; SPI controlled, with active zener
13 OUTH2 High side output 2; SPI controlled
14 OUTH3 High side output 3; SPI controlled, in cyclic wake mode
controlled by an internal autotiming function
15
VS Power supply; block to GND directly at the IC with ceramic
capacitor
16 CSN SPI interface Chip Select Not; CSN is an active low input; serial
communication is enabled by pulling the CSN terminal LOW.
CSN input should only be transitioned when CLK is LOW. CSN
has an internal active pull up and requires CMOS logic level
inputs. See Figure 11 for more details.
17 DO SPI interface Data Out; DO is a tristate output that transfers
diagnosis data to the control device. Serial data transfered from
DO is a 16 bit diagnosis word with the Least Significant Bit (LSB)
transmitted first. The output will remain 3-stated unless the device
is selected by a LOW on Chip-Select-Not (CSN). DO will accept
data on the rising edge of CLK-signal; see Table 6 for output data
protocol and Figure 11 for more timing details.
Version 1.06 4 2002-11-26
Target Datasheet TLE 6266
4 Pin Definitions and Functions (cont’d)
Pin No. Symbol Function
18 DI SPI interface Data In; DI receives serial data from the control
device. Serial data transmitted to DI is a 16 bit control word with
the Least Significant Bit (LSB) transferred first. The input has an
active pull down and requires CMOS logic level inputs. DI will
accept data on the falling edge of CLK-signal; see Table 6 for
input data protocol and Figure 11 for more details.
19 CLK SPI interface clock input; clocks the shiftregister; CLK has an
internal active pull down and requires CMOS logic level inputs
24 V
CC
Output voltage regulator; 5V logic supply, block to GND with an
100nF external ceramic capacitor directly at the IC + external
capacitor C
³ 22 µF
Q
25 RxD CAN Receive data output; push-pull output;
LOW: bus becomes dominant, HIGH: bus becomes recessive
26 TxD CAN Transmit data input; integrated pull up;
LOW: bus becomes dominant, HIGH: bus becomes recessive
27 PWM Pulse Width Modulation control; integrated pull down, active
HIGH. To PWM-control highside-switch HS1
28 WK Wake-Up input; for detection of external wake-up events within
cyclic wake mode, integrated pull down, active HIGH, switches on
rising edge
Version 1.06 5 2002-11-26
5 Functional Block Diagram
Target Datasheet TLE 6266
OUTL1
Vs
PW M
Charge
Pump
UVL O
Band
Vs
Vcc
Gap
Dr ive
Dr ive
Protection + Drive
Dr ive
Dr ive
-
+
LDO
Sw itch
Fail De tec t
SPI
Timer
Res et
Generator
+
Window
Watchdog
Mode Control
Vcc
Os c illato r
OUTL2
OUTH1
OUTH2
OUTH3
CSN
CLK
DI
DO
Vcc
RO
WK
RTL
CA NH
CA NL
RTH
H Output Stage
Filter
L Output Stage
Rec e ive r
CA N Fail Det ec t
Dr ive r
Temp.
Protect
Fail Management
Input
Stage
GND
Vcc
Tx D
Vcc
Rx D
Figure 2 TLE 6266 G Functional Block Diagram
Version 1.06 6 2002-11-26
Target Datasheet TLE 6266
6 Circuit Description
The TLE 6266 G is a monolithic IC, which incorporates a failure tolerant low speed CANtransceiver for differential mode data transmission, a low dropout voltage regulator for
internal and external 5V supply as well as a SPI interface to control and monitor the IC.
Further there are three high side switches, two low side switches, a window watchdog
circuit and a reset circuit integrated. Figure 2 shows the block diagram of the TLE 6266.
6.1 Operation Modes
The TLE 6266 offers four different operation modes (see Figure 3), that are controlled
via the SPI input bits 9,10 (mode bits M0,M1) as shown in Table 1: the normal operation
mode, the receive-only mode, the V
stand-by mode and the cyclic wake operation
bat
mode.
The cyclic wake mode itself is subdivided into two modes: the cyclic HS OFF and the
cyclic HS ON mode. Cyclic wake and V
stand-by mode are both designed for periods
bat
that do not require communication on the CAN-Bus but offer a low power mode. The
lowest current consumption is achieved in the cyclic wake mode(<70µA).
Table 1 Operation modes bit settings
Mode Bit M1
(SPI Bit 10)
Mode Bit M0
(SPI Bit 9)
Normal operation 1 1
Cyclic Wake 1 0
RxD only 0 1
stand-by 0 0
V
bat
Normal Operation Mode
The normal operation mode is designed to receive and transmit data messages as well
as to supply the ECU and control loads via HS- and LS- switches. RTL is switched to
, RTH to GND. Table 3 gives an overview about the available functions in this mode.
V
CC
RxD-only Mode
In the receive-only mode the receiver stage is activated and the transmitter stage is
deactivated. This means that data at the TxD input is not transmitted to the CAN bus but
receiving of data is still possible. The CANL line is pulled-up to VCC via the RTL output
and CANH is pulled to GND via RTH. This mode is useful in combination to a dedicated
network-management software that allows separate diagnosis for all nodes (see
Chapter 6.2). Table 3 gives an overview about the available functions in this mode.
Version 1.06 7 2002-11-26
Target Datasheet TLE 6266
V
stand-by Mode
bat
In the
V
stand-by mode the CAN transmitter and receiver stage are deactivated, to
bat
achieve a low power consumption. All other functions are active as in the normal mode
(see Table 3). The CANL line is pulled-up to battery supply voltage via the RTL output
and CANH pulled to GND via RTH. A wake-up request via a CAN message on the bus
is immediately reported to the microcontroller by setting RxD=LOW. The wake pin WK
V
is not active in this mode. A power-on condition (
V
automatically switches the TLE 6266 to
stand-by mode. Also if the supply voltage
bat
pin is supplied) or a watchdog reset,
bat
drops below the specified limits (undervoltage reset), the transceiver is automatically
V
switched to
stand-by mode or power down mode, respectively.
bat
Cyclic Wake Modes
In the cyclic wake operation mode the lowest power consumption is achieved. This mode
consists of two states, the Cyclic HS ON and the Cyclic HS OFF mode.
In the HS ON state the transmitter, receiver and all switches, except the HS3 switch, are
deactivated. The CANL line is pulled-up to battery supply voltage via the RTL output and
CANH pulled to GND via RTH. A wake-up via CAN bus message sets the RxD output to
LOW. In the HS ON state, a long open window is started. If there is no valid watchdog
trigger or a PWM transition into the HS OFF state during this time, a watchdog reset is
activated. Only a correct trigger signal on the PWM Pin causes a transition into the cyclic
HS OFF state. This is called the “failsafe PWM” feature.
In the HS OFF state, almost all functions of the IC are deactivated(also HS3-switch).
Only the wake-up input, the oscillator and the power-on reset circuit are activated. The
oscillator is used to realize the HS3-cyclic wake function.This automatically switches to
HS ON state after a programed time, to enabled HS3 (see Table 2).The CANL line is
pulled-up to battery supply voltage via the RTL output and CANH pulled to GND via RTH.
Only the wake up via CAN message sets the RxD to low (visible in HS ON state).
There are three possibilities to enter the cyclic HS ON mode from the HS OFF mode:
• the cyclic wake function
• a falling edge at the wake-up pin
• a CAN bus wake
Table 2 SPI Bit settings for the cyclic wake function
Input Bit 13 Input Bit12 Period # of Cycles
(1 cycle = 512µs typ.)
0 0 48ms 94
0 1 96ms 188
1 0 192ms 376
1 1 no cyclic wake-up -
Version 1.06 8 2002-11-26
Target Datasheet TLE 6266
SPI
SPI
Power Down
Normal Mode
M1 = 1
all functions active
SPI
RxD-Only
M1 = 0
all functions active
SPI
Cyclic Wake
Cyclic HS OFF
M1 = 1
Vcc = OFF/ON
RTL = 12V
WD = OFF
HS3 = OFF
M0 = 1
SPI
M0 = 1
M0 = 0
POR = ON
RxD = H
1)
3V SV
= ON
Start Up
Power Up
SPI
SPI
SPI
SPI
V
Stand-By
bat
M1 = 0
Vcc = ON
RTL = 12V
WD = ON
Watch
POR = ON
PWM HS1
3VSU = ON
RxD = H/L
t>T
WDR
dog
Reset
Power
ON
Reset
M0 = 0
2)
automatic transition after:
- cyclic wake time
- WK pin = H
- CAN bus wake
Cyclic HS ON
M1 = 1
Vcc = ON
RTL = 12V
WD = ON
HS3 = ON
Mode Bits:
M0 = SPI Input Bit 9
M1 = SPI Input Bit 10
Figure 3 State Diagram
3)
PWM
M0 = 0
POR = ON
RxD = H/L
1)
= ON
3V SV
1) 3V supervisor feature only active if selected via SPI
2) HS1 is controlled by the SPI input bit 1(activate HS1) and also the PWM
input pin27 if the SPI input bit 11 (PWM enable) is set. In case both
controls are active, the HS1 switch is masked by the SPI input bit 1 (see
figure 12)
3) this function makes sure that the cyclic HS OFF mode can only be
entered via a correct signal at the PWM pin
SPI
SPI
Version 1.06 9 2002-11-26
Table 3 Operation mode table
Target Datasheet TLE 6266
Feature Normal
mode
RxD only
mode
V
bat
stand-by
mode
Cyclic
Wake
HS ON
Cyclic
Wake
HS OFF
LDO ONONONONOFF/ON
Reset ONONONONON
Watchdog ON ON ON ON OFF
SPI ONONONONOFF
Oscillator ONONONONON
CAN transmit ON OFF OFF OFF OFF
CAN receive ON ON OFF OFF OFF
OUTHS 1
PWM HS1
OUTHS 2
OUTHS 3
1) 2) 3)
2)
1) 3)
1) 3)
OUTHS 3 cycl. HS
1) 3)
ON
OUTLS 1
OUTLS 2
1) 3)
1) 3)
ON ON ON OFF OFF
ON ON ON OFF OFF
ON ON ON OFF OFF
ON ON ON OFF OFF
OFF OFF OFF ON OFF
ON ON ON OFF OFF
ON ON ON OFF OFF
OUT HS 3
ON ON ON OFF OFF
Timebase-Test
Wake Pin OFF OFF OFF OFF ON
Failsafe PWM
3V Supervisor
4)
1) ON
RTL output
RxD output
1)
only active when selected via SPI
2)
HS1 is controlled by the SPI input bit 1(activate HS1) and also the PWM input pin27 if the SPI input bit 11 (PWM
enable) is set. In case both controls are active, the HS1 switch is masked by the SPI input bit 1 (see figure 12)
3)
automatically disabled when a reset resp. watchdog reset occurs
4)
this function makes sure that the cyclic HS OFF mode can only be entered via a correct signal at the PWM pin
OFF OFF OFF ON OFF
switched to
Vcc
L = bus
dominant;
H = bus
recessive
ON
switched to
Vcc
L = bus
dominant;
H = bus
recessive
ON
switched to Vsswitched to
active low on
CAN message
wake-up
ON
Vs
active low on
CAN message
wake-up
ON
switched to
Vs
active low on
CAN message
wake-up
Version 1.06 10 2002-11-26
Target Datasheet TLE 6266
6.2 LS CAN Transceiver
The CAN transceiver TLE 6266 works as the interface between the CAN protocol
controller and the physical CAN bus-lines. Figure 4 shows the principle configuration of
a CAN network.
Controller 1
RxD1
Transceiver1
TxD1
BUS Line
Controller 2
RxD2
Transceiver2
TxD2
Figure 4 CAN Network Example
In normal operation mode a differential signal is transmitted/received. When bus wiring
failures are detected, the device automatically switches in a dedicated single-wire mode
to maintain communication. While no data is transferred, the power consumption can be
minimized by multiple low power operation modes. Further a receive-only mode is
implemented that allows a separate CAN node diagnosis. During normal and RxD-only
mode, RTL is switched to V
and RTH to GND. During V
CC
wake mode, RTL is switched to V
and RTH to GND.
S
stand-by and the cyclic
bat
Receive-only Mode
The receive only mode is designed for a special test procedure to check the bus
connections. Figure 5 shows a network consisting of 5 nodes. If the connection between
node 1 and node 3 shall be tested, the nodes 2,4 and 5 are switched into receive only
mode. Node 1 and node 3 are in normal mode. If node 1 sends a message, node 3 is the
only node which can acknowledge the message, the other nodes can only listen but
cannot send an acknowledge bit. If node 1 receives the acknowledge bit from node 3,
the connection is OK.
Electromagnetic Emmision (EME)
To reduce radiated electromagnetic emission (EME), the dynamic slopes of the CANL
and CANH signals are both limited and symmetric. This allows the use of an unshielded
twisted or parallel pair of wires for the bus. During single-wire transmission (one of the
Version 1.06 11 2002-11-26
Target Datasheet TLE 6266
bus lines is affected by a bus line failure) the EME performance of the system is
degraded from the differential mode.
5
1
2
4
3
Figure 5 Testing the Bus Connection in Receive-only Mode
6.3 Bus Failure Management
There are 9 different CAN bus wiring failures defined by the ISO 11519-2 standard.
These failures are devided into 7 failure groups (see Table 4). When a bus wiring failure
is detected the device automatically switches to a dedicated CANH or CANL single-wire
mode to maintain the communication if necessary. Therefore it is equipped with one
differential receiver and four single ended comparators (two for each bus line).
To avoid false triggering by external RF influences, the single wire modes are activated
after a certain delay time. As soon as the bus failure disappears the transceiver switches
back to differential mode after another time delay.
The bus failures are monitored via the diagnosis protocoll of the SPI. Therefore it is
possible to distinguish 6 CAN bus failures or failure groups on the SPI output bits 8 to 13
(see Table 4 and 5). The failures are reported until transmission of the next CAN word
begins.The SPI output bit 0 for CAN bus wiring failure can be read out without SPI
transmission directly via the CSN pin (CSN=LOW). A transition of the CSN pin signal
from LOW to HIGH resets the SPI diagnosis bit 0.
The differential receiver threshold is set to typ. -2.5V. This ensures correct reception in
the normal operation mode as well as in the failure cases 1, 2, 3a and 4 with a noise
margin as high as possible. When one of the bus failures 3, 5, 6, 6a, and 7 is detected,
the defective bus wire is disabled by switching off the affected bus termination and output
stage. Simultaneously the multiplexing output of the receiver circuit is switched to the
unaffected single ended comparator.
Version 1.06 12 2002-11-26
Target Datasheet TLE 6266
Table 4 CAN bus line failure cases (according to ISO 11519-2)
Failure
Failure Description
#
1 CANL line interrupted
2 CANH line interrupted
3 CANL shorted to V
(no ISO failure) CANL shorted to V
3a
, CANL > 7.2 V
bat
; 3.2 V < CANL < 7.2 V
cc
4 CANH shorted to GND
5 CANL shorted to GND
6 CANH shorted to V
6a
(no ISO failure) CANH shorted to V
; CANH > 7.2 V
bat
; 1.8 V < CANH < 7.2 V
cc
7 CANL shorted to CANH
In case the transmission data input TxD is permanently dominant, both, the CANH and
CANL transmitting stage are disabled after a certain delay time t
. This is necessary
TxD
to prevent the bus from being blocked by a defective protocol unit or short to GND at the
TxD input.
In order to protect the transceiver output stages from being damaged by shorts on the
bus lines, current limiting circuits are integrated. The CANL and CANH output stage
respectively are protected by an additional temperature sensor, that disables them as
soon as the junction temperature exceeds the maximum value. In the temperature shutdown condition of the CAN output stages receiving messages from the bus lines is still
possible. A thermal shutdown of the CAN-transceiver circuit is monitored via the SPI
output bit 15. The CANH and CANL pins are also protected against electrical transients
which may occur in the severe conditions of automotive environments.
Table 5 SPI output bits for bus failure diagnosis
OBIT Bus Failure
13 CAN Failure 2 and 4
12 CAN Failure 1 and 3a
11 CAN Failure 6
10 CAN Failure 6a
9 CAN Failure 5 and 7
8 CAN Failure 3
0 CAN Bus Failure
Version 1.06 13 2002-11-26
Target Datasheet TLE 6266
6.4 Low Dropout Voltage Regulator
The TLE6266 is able to drive external 5V loads up to 45 mA. Its output voltage tolerance
is less than ± 2%. In addition the regulator circuit drives the internal loads like the CANtransceiver circuit. In the cyclic wake HS OFF operation mode the voltage regulator is
switched on and off by a control mechanism (see Chapter 6.5).
The current limitation of the LDO is set to typ. 180mA, to grant that the external capacitor
can be charged quickly. In normal operating mode the external current should be less
then 45mA. This has to guaranteed by the system architecture.
An external reverse current protection is recommended to prevent the output capacitor
from being discharged by negative transients or low input voltage.
Stability of the output voltage is guaranteed for output capacitors C
³ 100 nF.
VCC
Nevertheless a lot of applications require a much larger output capacitance to buffer the
output voltage in case of low input voltage or negative transients. Furthermore the due
function of e.g. the reset and 3V-supervisor circuit are supported by a larger output
capacitance because of their reaction times. Therefore a output capacitance
C
³ 22 µF is recommended.
VCC
6.5 LDO activation during Cyclic Wake HS OFF
During the cyclic wake HS OFF mode, the LDO is switched on and off, depending on the
output voltage level, which is monitored internaly. Figure 6 shows a detailed flowchart
of the V
mode. The voltage regulator is switched on as soon as the voltage at V
control loop and also a graph of the Vcc voltage and the thresholds in this
cc
falls below the
CC
load-threshold to charge an external capacitor for 1ms. When the nominal voltage level
is reached again, the voltage regulator is automatically deactivated to minimize the
current consumption. The period of charging/decharging is dependant on the external
stabilization capacitor at V
CC
.
6.6 3V-Supervisor
If the output voltage falls below the 3V-supervisor threshold V
, an internal flip-flop is
ST
set LOW. The SPI output bit 7 monitors this. In normal operation this flip-flop has to be
activated via the SPI input bit 7. This feature is useful e.g. to monitor that the RAM data
of the microcontroller might be damaged or the application is connected to V
the first
S
time.
The 3V supervisor uses a comparator to monitor the voltage. Additional, there is a
possibility to disable this comparator in order to reduce the current consumption. To do
this, set SPI input bit 15 first and in the next step set SPI input bit 7.
Version 1.06 14 2002-11-26
Target Datasheet TLE 6266
Vcc
5
4
t
CHARGE
Charge Diagram
Yes
V
CC TH
V
RESET TH
t
Vcc< reset threshold
V
RESET TH
for t > 3µs ?
Yes
RESET after filtering-
time
No
Monitor V
in Cyclic wake
cc
HS OFF Mode
Vcc
Vcc > load threshold
V
CC TH
No
Charge of V
cc
(Switch on LDO)
?
Vcc
for 1ms
Figure 6 LDO activation flowchart for the cyclic wake HS OFF mode
6.7 SPI (serial peripheral interface)
The 16-bit wide programming word or input word (see Table 6) is read in via the data
input DI, and this is synchronized with the clock input CLK supplied by the µC. The
diagnosis word appears synchroniously at the data output DO (see Table 7).
The transmission cycle begins when the chip is selected by the chip select not input CSN
(H to L). After the CSN input returns from L to H, the word that has been read in becomes
the new control word. The DO output switches to tristate status at this point, thereby
releasing the DO bus for other usage.
The state of DI is shifted into the input register with every falling edge on CLK. The sate
of DO is shifted out of the output register after every rising edge on CLK. For more details
of the SPI timing please refer to Figure 11 to 15.
CAN Bus Wiring Failure direct Read-out
The SPI output bit 0 for CAN bus wiring failure can be read out without SPI transmission
directly via the CSN pin (CSN=LOW). A transition of the CSN pin signal from LOW to
HIGH resets the SPI diagnosis bit 0.
SPI CLK Monitoring during Cyclic Wake Mode
The TLE 6266 offers a feature to monitor the SPI clock signal (CLK pin) during the cyclic
wake mode. If there are edges on the CLK signal, the IC performs a reset and the RO
Version 1.06 15 2002-11-26
Target Datasheet TLE 6266
pin is set to LOW for t= t
WDR
(after t
a long open window is started and RO is HIGH
WDR
again). This feature is activated if the CSN pin is set to HIGH.
Table 6 SPI Input Data Protocol Table 7 SPI Output Data Protocol
IBIT Input Data OBIT Output Data
15 Disable 3V Reset Comparator 15 Thermal Shutdown Transceiver
14 not used 14 Thermal Shutdown Switches
13 Cyclic Wake Time Bit2 13 CAN Failure 2 and 4
12 Cyclic Wake Time Bit1 12 CAN Failure 1 and 3a
11 PWM Enable HS1 11 CAN Failure 6
10 Mode 1 10 CAN Failure 6a
9 Mode 0 9 CAN Failure 5 and 7
8 not used 8 CAN Failure 3
7 Supervisor Enable 7 3V Supervisor (Vcc < 3V)
6 LS-Switch 2 6 Status LS2
5 LS-Switch 1 5 Status LS1
4 Timebase Test 4 Temperature Prewarning for all
Switches
3 HS-Switch 3 3 Vs Undervoltage Lockout
2 HS-Switch 2 2 Window Watchdog Reset
1 HS-Switch 1 1 Overcurrent HS1
0 Watchdog Trigger 0 CAN Bus Failure
H=ON
L=OFF
H=ON
L=OFF
6.8 Oscillator
The TLE 6266 has an internal oscillator with +/-15% accuracy. The typ. frequency of the
oscillator is 125kHz. After an internal 64-times frequency divider, this gives an typ. cycle
time t
the
= 0.512ms. The frequency of the oscillator can be measured within the normal,
cyc
V
stand-by and the RxD-only mode. This is a timebase test (see Chapter 6.15),
bat
activated via SPI input bit 3 and 4. During this test, the HS3-switch will be activated
cyclically.
Version 1.06 16 2002-11-26
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