Infineon TLE4997 User Manual

TLE4997

Configuration and Calibration of Linear Hall Sensor

User’s Manual

v01_01, 2019-08

Sense & Control

Edition 2019-08

Published by Infineon Technologies AG 81726 Munich, Germany

Legal Disclaimer

The information given in this document shall in no event be regarded as a guarantee of conditions or characteristics. With respect to any examples or hints given herein, any typical values stated herein and/or any information regarding the application of the device, Infineon Technologies hereby disclaims any and all warranties and liabilities of any kind, including without limitation, warranties of non-infringement of intellectual property rights of any third party.

Information

For further information on technology, delivery terms and conditions and prices, please contact the nearest Infineon Technologies Office (www.infineon.com).

Warnings

Due to technical requirements, components may contain dangerous substances. For information on the types in question, please contact the nearest Infineon Technologies Office.

Infineon Technologies components may be used in life-support devices or systems only with the express written approval of Infineon Technologies, if a failure of such components can reasonably be expected to cause the failure of that life-support device or system or to affect the safety or effectiveness of that device or system. Life support devices or systems are intended to be implanted in the human body or to support and/or maintain and sustain and/or protect human life. If they fail, it is reasonable to assume that the health of the user or other persons may be endangered.

TLE4997

User’s Manual

Table of Contents

Table of Contents . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3

1Scope . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4

2 TLE4997 Signal Processing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4

3 TLE4997 Programming . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5

3.1 Programmer Connection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5

3.2 Programming Interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6

3.2.1 Communication Scheme . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6

3.3 Command Frame . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7

3.3.1 Data Frame . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8

3.3.2 Interface Specification . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8

3.4 Register Map . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11

3.5 EEPROM Map . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13

3.6 Programming Flow . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14

3.6.1 Setting the TEST register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16

3.6.2 Readout of the EEPROM Content . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16

3.6.3 Setting the EEPROM Content . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16

3.6.4 Calculation of Bits to Erase . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16

3.6.5 Calculation of Bits to Write . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16

3.6.6 Margin Voltage Check . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17

3.6.7 DATA access example . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17

3.6.8 Temporary overwrite of EEPROM data . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18

3.6.9 DAC setup example . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19

4 Configuration & Calibration Parameters . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20

4.1 Magnetic Field Range - R . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20

4.2 Gain Setting - G . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20

4.3 Offset Setting - OS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20

4.4 Low-Pass Filter - LP . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21

4.5 DAC Input Interpolation Filter . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22

4.6 Clamping - CH, CL . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23

4.7 Temperature Compensation - TL, TQ & TT . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24

5 Calibration of TLE4997 Temperature Compensation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25

5.1 Integrated Temperature Polynomial . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25

5.2 Application Sensitivity Polynomial . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25

5.3 Determination of Sensitivity Polynomial from Measurement . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 27

5.4 Calculation of Final Temperature Compensation Parameters . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 28

5.4.1 Algorithm for Finding the Optimum Temperature Coefficient Set . . . . . . . . . . . . . . . . . . . . . . . . . . 28

5.4.2 Example Implementation Code for Temperature Calibration . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 29

5.5 Usage of Infineon’s Temperature Calibration Tool . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 32

6 Calibration of TLE4997 Output Characteristic . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 34

6.1 Two-Point Calibration Procedure . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 34

6.2 Two-Point Calibration Examples . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 35

6.2.1 Calibration with Application Readout . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 35

6.2.2 Calibration without Application Readout . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 36

User’s Manual 3 v01_01, 2019-08

TLE4997

Stored in

EEPROM

Memory

Hall

Sensor

Limiter

(Clamp)

Out

Range LP

Offset

Gain

Clamping Low

Clamping High

TADC TCAL

Temperature

Sensor

Norm-

alize

T-Polynomial

HADC

HCAL

VOUT

VDAC

User’s Manual

Scope

1Scope

This document is valid for all TLE4997 variants and derivates. It gives a detailed description of the configuration and calibration procedure, which is recommended to configure the TLE4997 for optimum accuracy in a sensing application.

2 TLE4997 Signal Processing

The TLE4997 uses a fully digital signal processing concept. Analog values from the Hall probe are directly converted to raw digital signals by the Hall ADC and then compensated and processed in the digital signal processing unit (DSP) using configuration parameters stored in the EEPROM and the temperature data acquired by an integrated temperature sensor. A configurable second-order temperature polynomial is implemented to compensate the thermal reduction of the remanent magnetic flux of a permanent magnet used in a position sensing application. Additionally, an application-specific output characteristic can be set by configuring the EEPROM parameters of Gain and Offset.

Figure 2-1 Signal Flow Diagram of the TLE4997

Figure 2-1 shows the signal flow diagram for temperature compensation and output characteristic in the DSP, and

the influence of the relevant configuration parameters stored in the EEPROM. The Hall signal is processed in the following sequence of steps:

1. The analog Hall signal is converted by the Hall ADC, which operates at the configured magnetic range setting.

2. The digital value is filtered by a digital low-pass filter, which operates at a configurable filter frequency given by the “LP filter”-setting. The output of the filter is stored in the HADC register.

3. The HADC value is multiplied by the temperature compensation polynomial and stored in the HCAL register. The first order (TL) and second order (TQ) coefficients of the polynomial are configurable. The third order coefficient (TT) is fixed.

4. The HCAL value is multiplied by the configured gain value.

5. The configured offset value is added to the HCAL value.

6. The digital Hall value is clamped according to the configured upper and lower clamping limits. The output value of the clamping stage is converted from digital to analog.

7. An output voltage is transmitted on the OUT pin and is proportional to the supply voltage (ratiometric DAC).

User’s Manual 4 v01_01, 2019-08

TLE4997

optional

VDD

I/O 1

I/O2

GND

47nF

PROGRAMMER

TLE

4997x

out

GND

TLE

4997x

out

GND

application module

User’s Manual

TLE4997 Programming

3 TLE4997 Programming

3.1 Programmer Connection

Figure 3-1 shows the connection of the TLE4997 to a programmer. The pins VDD and OUT of the sensor IC are

used for the digital programming interface as described in Table 3-1 (See datasheet of corresponding TLE4997 type for pinout).

Figure 3-1 Connection of TLE4997 to Programmer

Table 3-1 Pin Functions for Programming Interface

Pin Programming Function

VDD Programming interface clock

GND Ground

OUT Programming interface data I/O

User’s Manual 5 v01_01, 2019-08

TLE4997

VDD

Vout

LSB MSB

duri ng first transmission , the output stage is stil l switch ed on

power up

interface activated

internal buffer on

VDD

Vout

LSB MSB

during transmission the buffer is switched off internal buffer on

interface

active

interface

active

protocol

output

leading driver

off pulse

protocol

output

User’s Manual

TLE4997 Programming

3.2 Programming Interface

3.2.1 Communication Scheme

The digital programming interface uses specific frames, which can have one of the two following functions:

• Command frames contain a specific task (e.g. read/write data, select EEPROM programming etc.) and a corresponding address

• Data frames contain a 16 bit data value sent to or received from the device - these frames can only follow a proper command frame for reading or writing data

A valid frame has the following properties:

• A frame consists of 21 bits in total

• A bit is shifted in or out via the output line with a rising clock edge on the supply line

• A frame always starts and ends with a '1' (frame bits)

• The LSB of a frame transmitted to the sensor is shifted in first

• The LSB of a frame replied by the sensor is shifted out first

• The whole frame sent to the device, including frame bits, is protected with an even positional and an odd positional parity bit

The first frame sent has to be a valid command to activate the interface mode and it has to be sent within 19ms after power up. As an additional protection, the device does not deactivate its output stage during this transmission (using 21 clock pulses) as shown in Figure 3-2. This means that the interface driver of the programmer needs to overrule the open drain output stage of the sensor during this initial transmission.

Figure 3-2 First Frame Transmission to the Sensor

Attention: Overruling Vout requires a strong driver on the programmer, since the OUT line must be driven

to low levels close to GND for any “0”-bit and close to VDD for any “1”-bit in order to ensure a proper communication with the sensor.

After the first frame, to avoid additional power consumption in the output stage of the device, the internal driver is deactivated in programming mode while the sensor is receiving a frame. It is activated again after completion of the transmission. This is illustrated in Figure 3-3.

Figure 3-3 Further Frame Transmisson from the Programmer to the Sensor (Write Access)

User’s Manual 6 v01_01, 2019-08

TLE4997

VDD

Vout

LSB

MSB

digital data readout, buffer in I/O mode

inte rnal buffer o n internal buffer on

tailing driver on

pulse

1 1

POP

0 0 ADDR (6bit) 1 0 CMD (6bit) 1

MSB (bit 20) LSB (bit 0)

User’s Manual

TLE4997 Programming

In case of a wrong command or data frame, the interface is immediately locked and the device falls back to its normal application mode. The read access to the device is triggered by clock pulses on the supply line as shown in Figure 3-4. The timing of read and write accesses is described in Chapter 3.3.2.

Figure 3-4 Frame Transmisson from the Sensor to the Programmer (Read Access)

3.3 Command Frame

The structure of a command frame is shown in Figure 3-5. Available commands are given in Table 3-2. The parity bits PE (bit 17) and PO (bit 18) have to be set in the follwing way (bit 0 is the LSB, bit 20 is the MSB):

bit0 XOR bit2 XOR bit4 XOR …. XOR bit20 = 0

bit1 XOR bit3 XOR bit5 XOR …. XOR bit19 = 0

Figure 3-5 Command Frame Structure

Table 3-2 List of Available Commands

Command Bits (MSB...LSB) Function

000000 Leave programming mode

000001 Single data readout from given address without increment (sensor

response: one data frame)

000011 Data readout from given address with increment (readout finishes

when address “xxx111

” is reached)

001001 Single data write to given address without increment (followed by

one data frame)

001011 Data write to given address with increment (followed by multiple data

frames; finishes at address “xxx111

command frame)

1) not to be followed by any data frame

2) followed by application of a programming pulse

3) followed by application of a margin voltage level before the last clock pulse falling edge

001100 Enable EEPROM write mode (programs “1”-bits)

001101 Enable EEPROM erase mode (programs “0”-bits)

001110 Enable EEPROM margin check mode (programs level check)

001111 EEPROM refresh (update EEPROM registers)

” or by sending another

1)2)

1)3)

User’s Manual 7 v01_01, 2019-08

TLE4997

1 0

POP

DATA (16bit) 1

MSB (bit 20) LSB (bit 0)

1 ADR (3 LSBs) DATA (16bit) 1

MSB (bit 20) LSB (bit 0)

User’s Manual

TLE4997 Programming

3.3.1 Data Frame

The structure of a data frame sent to the device is shown in Figure 3-6. The parity bits PE (bit 17) and PO (bit 18) have to be set in the same way as for the command frame (bit 0 is the LSB, bit 20 is the MSB):

bit0 XOR bit2 XOR bit4 XOR …. XOR bit20 = 0

bit1 XOR bit3 XOR bit5 XOR …. XOR bit19 = 0

Figure 3-6 Data Frame to Sensor

Figure 3-7 shows a the structure data frame received from the sensor. Instead of a zero bit followed by two parity

bits, the least significant 3 bits of the address used for the readout are transmitted together with the data. This is to check the plausibility of the received data.

Figure 3-7 Data Frame from Sensor

3.3.2 Interface Specification

Table 3-3 specifies the operating conditions of the programming interface, which must be met in order to ensure

correct operation of the TLE4997 during programming. All specified parameters refer to these operating conditions, unless otherwise noted.

Table 3-3 Operating Range of the Programming Interface

Parameter Symbol Values Unit Note / Test Condition

Min. Typ. Max.

Supply voltage V

Supply buffer capacitance C

Load capacitance C

Ambient temperature T

Number of programming

PRG

cycles

Programming time

Programming start time

1) >47nF soldered to the device required in case that connectivity failures can influence the programming voltage.

PRG

PRG_START

4.5 – 5.5 V –

47 – 1000 nF VDD to GND

0.0

– 210 nF OUT to GND

10 – 60 °C during programming

10 Cycles Programming is allowed only at

start of lifetime

– 100 – ms For complete memory

– – 19 ms To start programming mode, a

first read command shall be sent within this time window after power-up

The specification for timings and electrical levels of the programming interface is shown in Table 3-4. The meaning of the timing parameters is illustrated in Figure 3-8.

User’s Manual 8 v01_01, 2019-08

TLE4997

VDD

Vout

LSB MSB

tsut

hldt

del

hlm

LSB

set t

set

min

init

fram e

data read

frame

User’s Manual

TLE4997 Programming

Figure 3-8 Frame Timing

Table 3-4 Electrical and Timing Specification of the Programming Interface

Parameter Symbol Values Unit Note / Test Condition

Min. Typ. Max.

clock high level V

DD,CLKHI

8.8 9.4 10 V specification of VDD operating range does not apply to clock

clock low level V

OUT data out high level V

OUT data out low level V

OUT data in high level V

OUT data in low level V

OUT data input current I

VDD clock high time t

clock low time t

Data in setup time t

Data in hold time t

Data out settling time t

Time between frames t

Buffer off delay t

Buffer on delay t

DD,CLKLOW

O,OHIGH

O,OLOW

O,IHIGH

O,ILOW

HLD

SET

MIN

DEL

HLM

1) capacity of external driver, especially during initial interface access (to overwrite ratiometric device output).

2) to reduce collisions with the ext. driver, it must be switched on slower than t charge/discharge behaviour on V

OUT

3) to reach again a valid and stable ratiometric V

4.8 5 5.2 V

VDD - 2 – V

DD,CLKHI

V OUT follows V

0–2.0 V

3.0 V

VDD + 0.1 V

-0.2 0.0 0.1 V

-50 – 50 mA

2.4 50 100 µs 5k...250kBit/s

1.6 4.0 100 µs 5k...250kBit/s

1.5 2.0 – µs to rising V

2.3 3.0 – µs after rising V

– 1.0 1.7 µs after rising V

10.0 – – µs

10.0 25.0 – µs

– 5.0 10.0 µs

depends also on capacitive output load.

signal state, please check the power-on time in the data sheet.

OUT

DEL

2)3)

min. and switched off faster than t

if ‘high’

HLM max.

;

User’s Manual 9 v01_01, 2019-08

TLE4997

VDD

Vout

MSB

HLD

LSB

MIN

next command

frame

MIN

erase or write command frame

(buffer stays off)

prog

puls e

O,PROG

(rise)

O,PROG

(fall)

PROG,WR

or t

PROG,ER

HLD

VDD

Vout

MSB LSB

MARG

next command

frame

min

margin

command frame

(buff er sta ys off)

Vdd/t (fall)

hld

apply V

O,MARG

and

capture EEPROM data

min

User’s Manual

TLE4997 Programming

In order to permanently store a programmed parameter set to the EEPROM, the “EEPROM erase” and “EEPROM write” commands shall be sent, followed by a programming pulse. Figure 3-9 shows the timing of the programming pulse.

Figure 3-9 Programming Pulse Timing

After programming, a margin check is necessary to test the stability of the programmed data. The margin check is initiated by an “EEPROM margin check” command followed by a margin voltage.

Figure 3-10 Margin Check Timing

The margin voltage is varied during subsequent steps within the threshold margin level range. A too low margin voltage value indicates a too short programming pulse duration or a too low programming voltage. A too high margin voltage value indicates a too long programming pulse duration or a too high programming voltage.

Table 3-5 gives the electrical and timing specifications of the programming pulse and the margin voltage check

procedure.

Table 3-5 Electrical and Timing Specification of the Programming Pulse and Margin Voltage

Parameter Symbol Values Unit Note / Test Condition

OUT data input current I

OUT margin level V

Threshold margin level V

Margin setup time t

OUT program level V

User’s Manual 10 v01_01, 2019-08

Min. Typ. Max.

O,MARG

MARG

slope for margin VDD/t 5 10 150 V/µs

O,PROG

0 – 20 mA during application of

-0.1 – 7 V

2.23 – 4.5

0.4

200 – – µs

19.2 19.3 19.4 V

V V

programming pulse or margin voltage

check “1” check “0”

TLE4997

User’s Manual

TLE4997 Programming

Table 3-5 Electrical and Timing Specification of the Programming Pulse and Margin Voltage (cont’d)

Parameter Symbol Values Unit Note / Test Condition

Min. Typ. Max.

OUT program slope

(rise)

OUT program slope

(fall)

OUT write time t

OUT erase time t

1) faster slope may lead to permanent damage of the EEPROM.

O,PROG

PROG,WR

PROG,ER

/t – – 2 V/µs time to reach V

O,PROG

shall not

exceed 50 µs

/t -10 – – V/µs time to reach 1v max. shall not

exceed 50 µs

9.9 10.0 10.1 ms

79.2 80.0 80.8 ms

3.4 Register Map

Table 3-6 shows the internal registers of the TLE4997 (compare also Figure 2-1).

Table 3-6 TLE4997 Register Map

Address Symbol Function R/W

...19

HCAL Calibrated Hall value read only

TCAL Calibrated temperature value, including reference temperature T0read only

VDAC Calculated DAC value, incl. clampling read only

HADC Uncalibrated Hall ADC value read only

TADC Uncalibrated temperature ADC value read only

STATUS Status register read only

EEPROM EEPROM registers (see Chapter 3.5) read/write

DAC_SET Direct setup of DAC value read/write

TEST Test mode register read/write

Note: To access the registers (except STATUS, HADC, TADC, VADC, DAC_SET and TEST), the digital signal

processing unit (DSPU) has to be disabled first via the TEST register.

HCAL

This register contains the temperature compensated magnetic measurement as a 16bit signed value. This value is in the range of +/- 30000.

TCAL

This register contains a 16 bit signed value and delivers the current junction temperature of the device. The junction temperature in °C is calculated from the register value by: T

= (TCAL/16+48) [°C].

VDAC

This register contains a 12 bit unsigned decimal result applied to the internal DAC for the ratiometric output stage. The value range is from 0 to 4095 and corresponds to 0% to 100% of V

HADC

This register contains a 16bit signed value that corresponds to the raw Hall cell measurement value. This value is in the range of +/- 20000.

User’s Manual 11 v01_01, 2019-08

TLE4997

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0

LSB

ROMSIG4

perr_more

LOCKED

perr_adr0

CRC ok

perr_adr1

perr_adr2

perr_adr3

HWver0

ROMSIG3

ROMSIG2

ROMSIG1

ROMSIG0

HWver1

HWver2

perr_col

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0

LSB

FEC off

DAC test

DSP stop

REF off

DSP off

MSB

User’s Manual

TLE4997 Programming

TADC

This register contains a 15bit unsigned raw temperature value.

STATUS

The content of the status register is shown in Figure 3-11.

Figure 3-11 Status Register

• CRC ok has to be “1”, otherwise the DSP built-in self-test was failed and the device is defective

• LOCKED must be ’0’ as long as the lockbits are not programmed. After setting the lockbits the lock can be verified by refreshing the EEPROM content and checking this bit before the supply of the device is removed or the interface is closed.

• perr_adr has to be on address F

(“1111B”), otherwise it shows the first EEPROM address where the internal

parity check failed.

• perr_more must be “0”, otherwise more than one EEPROM address has a parity error.

• perr_col must be “0”, otherwise one or more EEPROM columns have a parity error.

• HWver contains the actual silicon revision starting with 0 (=”000”). The latest version from 8’ manufacturing line is version 3 (=”011”, availability from mid 2006 and released for productive use).

• ROMSIG has to be 1F

, otherwise the DSP ROM is not valid and the device is defective.

DAC_SET

This register contains a 12 bit unsigned decimal value. When the DAC test bit is set, the value of this register is used on the ratiometric output.

TEST

The content of the test register is shown in Figure 3-12. All bits are “0” after reset. All bits not described or used shall be kept at “0”.

Figure 3-12 Test Register

• “Margin zero on” is used to select the margin test mode. It is set to ‘1’ for testing the EEPROM threshold voltages of cells programmed to ‘0’, and it is set to ‘0’ for testing the EEPROM threshold voltages of cells programmed to ‘1’.

• “FEC off” switches off the error correction of the EEPROM. This bit has to be set when reading the EEPROM content.

• “REF off” switches off the automatic (cyclic) refresh performed by the DSP to actualize the EEPROM registers from the EEPROM cells. This bit has to be set when writing new values to the EEPROM registers.

User’s Manual 12 v01_01, 2019-08

+ 26 hidden pages

Infineon TLE4997 User Manual

Specifications and Main Features

Frequently Asked Questions

User Manual

Table of Contents

1Scope

2 TLE4997 Signal Processing

3 TLE4997 Programming

3.1 Programmer Connection

3.2 Programming Interface

3.2.1 Communication Scheme

3.3 Command Frame

3.3.1 Data Frame

3.3.2 Interface Specification

3.4 Register Map