Infineon TLE493D-P2B6 User Manual
Usermanual TLE493D-P2B6
High Accuracy Low Power 3D Hall Sensor with I²C Interface
About this document
Scope and purpose
This document provides product information and descriptions regarding:
• I2C Registers
• I2C Interface
• Wake Up mode
• Diagnostic and Tests
Intended audience
This document is aimed at engineers and developers of hard and soware using the sensor TLE493D-P2B6.
Usermanual Please read the Important Notice and Warnings at the end of this document Ver. 1.0
www.infineon.com 2020-12-11
Usermanual TLE493D-P2B6
High Accuracy Low Power 3D Hall Sensor with I²C Interface
Table of contents
Table of contents
About this document . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1
Table of contents . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2
1 I2C Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .4
1.1 Register overview . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .4
1.2 Register description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5
1.2.1 Bit types . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5
1.2.2 Measurement data and registers combined in the I²C parity bit “P” . . . . . . . . . . . . . . . . . . . . . . . . . 5
1.2.3 Wake Up and registers combined in the I2C parity flag “CF" . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .8
1.2.4 Mode registers combined in the I²C parity flag “FF” . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .13
1.2.5 Diagnostic, status and version registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15
2 I²C Interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .18
2.1 I²C protocol description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18
2.1.1 General description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18
2.1.2 I²C write command . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18
2.1.3 I²C read commands . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22
2.1.3.1 2-byte read command . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22
2.1.3.2 1-byte read command . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22
2.2 Collision avoidance and clock stretching . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .24
2.2.1 Collision avoidance (CA bit = 0B and INT bit = 0B) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24
2.2.2 Clock stretching (CA bit = 0B and INT bit = 1B) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25
2.3 Sensor reset by I²C . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26
2.4 Sensor Initialization and Readout example . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .27
2.5 Loss of VDD impact on I²C bus . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 28
3 Wake Up mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 29
3.1 Wake Up activation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 30
3.2 Wake Up constraints . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 30
3.3 Wake Up in combination with the angular mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .31
4 Diagnostic and tests . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 32
4.1 Diagnostic functions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .32
4.1.1 Parity bits and parity flags . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 32
4.1.2 Test mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 32
4.1.3 Power-down flags . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 32
4.1.4 Frame counter . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .32
4.1.5 Device address . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 32
4.2 Test functions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 32
4.2.1 Vhall/Vext test mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 33
4.2.1.1 Test description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 33
4.2.1.2 Test implementation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .33
Usermanual 2 Ver. 1.0
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Usermanual TLE493D-P2B6
High Accuracy Low Power 3D Hall Sensor with I²C Interface
Table of contents
4.2.1.3 Test reference values . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 33
4.2.2 Spintest mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .34
4.2.2.1 Test description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 34
4.2.2.2 Test implementation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .36
4.2.2.3 Test reference values . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 36
4.2.3 SAT-test mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 37
4.2.3.1 Test description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 37
4.2.3.2 Test implementation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .37
4.3 Magnetic measurement implementation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 38
5 Terminology . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 39
6 Revision history . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 40
Disclaimer . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 41
Usermanual 3 Ver. 1.0
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Colour legend for the Bitmap
Magnetic values Configuration Diagnosis
Wake Up
Temperature values Configuration bus Reserved bits Parity bits and related registers (colour)
Usermanual TLE493D-P2B6
High Accuracy Low Power 3D Hall Sensor with I²C Interface
1 I2C Register
1 I2C Register
The TLE493D-P2B6 includes several registers that can be accessed via Inter-Integrated Circuit interface (I2C) to
read data as well as to write and configure settings.
1.1 Register overview
A bitmap overview is presented in Figure 1. Basically the following sections are available:
• measurement data (green bits in registers 00H till 05H)
• sensor status and diagnostics (grey bits in registers 05H, 06H, 0EH, 0FH, 10H and 11H)
• configuration parameters such as the power mode (orange bits in registers 10H, 11H and 13H)
• Wake Up values in registers (blue bits in registers 07H till 0FH)
Figure 1 TLE493D-P2B6 Bitmap
The diagnostic register 06H contains parity information as a diagnostic mechanism. The bitmap illustrates this
and marks the relationship of the sections to this flags with dierent colored lines/frames around the bit
contents.
Usermanual 4 Ver. 1.0
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Usermanual TLE493D-P2B6
High Accuracy Low Power 3D Hall Sensor with I²C Interface
1 I2C Register
Table 1 Register overview
Register name Register long name Address
Bx, By and Bz Magnetic values MSBs 00H, 01H, 02
Temp Temperature value MSBs 03
Bx2 Magnetic values LSBs 04
Temp2 Temperature and magnetic LSBs and device address 05
Diag Sensor diagnostic and status register 06
H
H
H
H
XL, YL and ZL Wake Up lower threshold MSBs 07H, 09H, 0B
XH, YH and ZH Wake Up upper threshold MSBs 08H, 0AH, 0C
WU Wake Up enable and X thresholds LSBs 0D
TMode Test Mode and Wake Up Y thresholds LSBs 0E
TPhase Test Phase and Wake Up Z thresholds LSBs 0F
Config Configuration register 10
MOD1 Power mode, interrupt, address, parity 11
MOD2 Low Power Mode update rate 13
Ver Version register 16
H
H
H
H
H
H
H
1.2 Register description
H
H
H
The I2C registers can be read or written at any time. It is recommended to read measurement data in a
synchronized fashion, i.e. aer an interrupt pulse (/INT). This avoids reading inconsistent sensor or diagnostic
data, especially in fast mode. Additionally, several flags can be checked to ensure the register values are
consistent and the ADC was not running at the time of readout.
1.2.1 Bit types
The TLE493D-P2B6 contains read bits, write bits and reserved bits.
Table 2 Bit types
Abbreviation Function Description
r Read Read-only bits
rw Read Write Readable and writable bit
Reserved Bits that must keep the default values (read prior to write required)
1.2.2 Measurement data and registers combined in the I²C parity bit “P”
The I2C communication of the registers in this chapter is protected with the parity bit “P”, described in the Diag
register with the address 06H. See also Figure 1 - parity bits and related registers.
To make sure all data is consistent, the registers from 00H to 06H should be read with the same I2C command.
Otherwise, the sampled data (X, Y, Z, Temperature) may correspond to dierent conversion cycles.
Usermanual 5 Ver. 1.0
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7
0
Bx, By and Bz (11...4)
7
0
Temp (11...4)
7
0
Bx (3...0)
By (3...0)
4 3
Usermanual TLE493D-P2B6
High Accuracy Low Power 3D Hall Sensor with I²C Interface
1 I2C Register
Magnetic values MSBs
Register names Address Reset Value
Bx, By and Bz 00H, 01H, 02
H
80
Field Bits Type Description
Bx, By and Bz 7:0 r Bx, By and Bz values
Signed value as two’s complement from the HALL probes in the
x, y and z-direction of the magnetic field. Contains the eight Most
Significant Bits. If Bz is deactivated the Bz value is the reset value.
Back to TLE493D-P2B6 Bitmap.
Temperature value MSBs
Register name Address Reset Value
Temp 03
H
80
Field Bits Type Description
H
H
Temp 7:0 r Temperature value
Signed value as two’s complement. If the temperature
measurement is deactivated, the Temp value is the reset value.
Back to TLE493D-P2B6 Bitmap.
Magnetic values LSBs
Register name Address Reset Value
Bx2 04
H
00
Field Bits Type Description
Bx 7:4 r Bx value
Signed value as two’s complement from the HALL probes in the xdirection of the magnetic field. Contains the four Least Significant
Bits.
By 3:0 r By value
Signed value as two’s complement from the HALL probes in the ydirection of the magnetic field. Contains the four Least Significant
Bits.
H
Back to TLE493D-P2B6 Bitmap.
Usermanual 6 Ver. 1.0
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7
0
Bz (3...0)
4 3
Temp (3...2)
ID
6
5
Usermanual TLE493D-P2B6
High Accuracy Low Power 3D Hall Sensor with I²C Interface
1 I2C Register
Temperature and magnetic LSBs and device address
Register name Address Reset Value
Temp2 05
H
Field Bits Type Description
Temp 7:6 r Temperature value
Signed value as two’s complement. If the temperature
measurement is deactivated, the Temp value is the reset value.
ID 5:4 r ID
Readback of the sensor ID, from IICadr . µC shall verify the address
sent by the sensor. See Table 4 .
Bz 3:0 r Bz value
Signed value as two’s complement from the HALL probes in the zdirection of the magnetic field. Contains the four Least Significant
Bits. If Bz is deactivated the Bz value is 0H.
(Product Type A0) 00
(Product Type A1) 10
(Product Type A2) 20
(Product Type A3) 30
H
H
H
H
Back to TLE493D-P2B6 Bitmap.
Usermanual 7 Ver. 1.0
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7
0
XL, YL and ZL (11...4)
7
0
XH, YH and ZH (11...4)
7
0
6
5 3
2
XL (3...1)XH (3...1)WUWA
Usermanual TLE493D-P2B6
High Accuracy Low Power 3D Hall Sensor with I²C Interface
1 I2C Register
1.2.3 Wake Up and registers combined in the I2C parity flag “CF"
The I2C communication of the registers in this chapter is protected by the parity bit CF, which is described in the
Diag register with the address 06H. See also Figure 1 - parity bits and related registers.
Wake Up lower threshold MSBs
Register names Address Reset Value
XL, YL and ZL 07H 09H 0B
H
80
Field Bits Type Description
XL, YL and ZL 7:0 rw Wake Up lower threshold
Defines the lower threshold MSBs of the magnetic field in the x, y
and z-direction at or below which the sensor enables the /INT, if
INT bit = 0B.
See Equation 2.
Back to TLE493D-P2B6 Bitmap.
Wake Up upper threshold MSBs
Register names Address Reset Value
XH, YH and ZH 08H 0AH 0C
H
7F
H
H
Field Bits Type Description
XH, YH and ZH 7:0 rw Wake Up upper threshold
Defines the upper threshold MSBs of the magnetic field in the x,
y and z direction at or above which the sensor enables the /INT, if
INT bit = 0B. See Equation 2.
Back to TLE493D-P2B6 Bitmap.
Wake Up enable and X thresholds LSBs
Register name Address Reset Value
WU 0D
Usermanual 8 Ver. 1.0
H
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38
H
7
0
6
5 3
2
YL (3...1)YH (3...1)TST
Usermanual TLE493D-P2B6
High Accuracy Low Power 3D Hall Sensor with I²C Interface
1 I2C Register
Field Bits Type Description
WA 7 r Wake Up mode active
Flag that reports whether the Wake Up mode is disabled or
enabled.
If 0B the Wake Up mode is disabled.
If 1B the Wake Up mode is enabled.
This bit can be checked if the Wake Up function is disabled or
enabled. As long as the WA bit = 0B, the /INT will be asserted
according Table 5.
WU 6 rw Enables Wake Up mode
If 0B the Wake Up mode will be disabled.
If 1B the Wake Up mode will be enabled.
The following conditions must be fulfilled:
• Test modes must be disabled (T bit = 0B)
• CP parity bit (register 10H) must be odd
• Configuration parity must be flagged (CF bit = 1B)
Interrupts /INT will be sent when the measurement data is ≥ upper
or ≤ lower Wake Up threshold.
XH 5:3 rw Wake Up X upper threshold
Defines the upper threshold LSBs of the magnetic field in the
x-direction at or above the sensor enables the /INT, if INT bit = 0B.
See Equation 2.
XL 2:0 rw Wake Up X lower threshold
Defines the lower threshold LSBs of the magnetic field density in
the x-direction at or below the sensor enables the /INT, if INT bit =
0B. See Equation 2.
Back to TLE493D-P2B6 Bitmap.
Test Mode and Wake Up Y thresholds LSBs
Register name Address Reset Value
TMode 0E
H
Field Bits Type Description
TST 7:6 rw Test mode
Dierent test modes can be enabled, see Table 3:
If 00B no test active (normal sensor operation and T bit = 0B). In the
following test modes the T bit = 1B and the test result overwrites
the measurement data register:
If 01B Vhall/Vext test starts: measure the Hall bias voltage on all
Hall plates and VDD.
If 10B Spintest starts: the PH bits select the channel to diagnose
with the Spin-switch and Hall-oset test.
If 11B SAT test starts: a test of the whole digital path, generates
patterns, defined by the PH bits during conversion.
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38
H
7
0
6
5 3
2
ZL (3...1)ZH (3...1)PH
7
0
CP
6
5
4
3
2
1
TL_magX2AMDT TRIG
Usermanual TLE493D-P2B6
High Accuracy Low Power 3D Hall Sensor with I²C Interface
1 I2C Register
Field Bits Type Description
YH 5:3 rw Wake Up Y upper threshold
Defines the upper threshold LSBs of the magnetic field in the
y-direction at or above which the sensor enables the /INT, if INT bit
= 0B.
See Equation 2.
YL 2:0 rw Wake Up Y lower threshold
Defines the lower threshold LSBs of the magnetic field density in
the y-direction at or below which the sensor enables the /INT, if INT
bit = 0B. See Equation 2.
Back to TLE493D-P2B6 Bitmap.
Test Phase and Wake Up Z thresholds LSBs
Register name Address Reset Value
TPhase 0F
H
Field Bits Type Description
PH 7:6 rw Test phase selection
In the Spintest these bits define the channel. In the digital test,
specific patterns are defined. See Test phase selection Table 3.
The PH bits have no eect in the voltage measurement test (Vext)
and in normal operating mode TST bit=00B and T bit=0B).
See Equation 2.
ZH 5:3 rw Wake Up Z upper threshold
Defines the upper threshold LSBs of the magnetic field in the
z-direction at or above which the sensor enables the /INT, if INT bit
= 0B.
See Equation 2.
ZL 2:0 rw Wake Up Z lower threshold
Defines the lower threshold LSBs of the magnetic field density in
the z-direction at or below which the sensor enables the /INT, if INT
bit = 0B. See Equation 2.
38
H
Back to TLE493D-P2B6 Bitmap.
Configuration register
Register names Address Reset Value
Config 10
Usermanual 10 Ver. 1.0
H
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01
H
Usermanual TLE493D-P2B6
High Accuracy Low Power 3D Hall Sensor with I²C Interface
1 I2C Register
Field Bits Type Description
DT 7 rw Disable Temperature
If 0B temperature measurement is enabled.
If 1B temperature measurement is disabled. This means the Bx, By
and Bz channels are measured. The Temp channel is disabled and
contains the reset value until a new conversion with Temp is done.
AM 6 rw X/Y Angular Measurement
If 0B the Bz measurement is enabled.
If 1B and DT bit = 1B: the Bz measurement is disabled. This means
the Bx and By channel is measured. The channels Bz and Temp
contain the reset values until a new conversion with Bz and Temp
is done
If 1B and DT bit = 0B: must not be used.
TRIG 5:4 rw Trigger options
If PR bit = 1B (1-byte read protocol), the TRIG bits define the trigger
mode of the device:
If 00B no ADC trigger on read
If 01B ADC trigger on read before first MSB.
If 1xB ADC trigger on read aer register 05H.
If PR bit = 0B these bits have no eect.
X2 3 rw Short range sensitivity
When this bit is set, the sensitivity of the Bx, By, and Bz ADCconversion is doubled by a longer ADC integration time. The Temp
result will not change, neither in sensitivity nor conversion time.
See Table 3.
TL_mag 2:1 rw Magnetic temperature compensation
There are two bits for setting the sensitivity over temperature of
the sensor to compensate a magnet temperature coeicient.
If 00B → TC0 (no compensation)
If 01B → TC
If 10B → TC
If 11B → TC
1
2
3
CP 0 rw Wake Up and configuration parity
The registers 07H through 10H (including 10H) without WA TST and
PH bit are odd parity protected with this bit. On startup or reset,
this parity is false and the CF bit in the status register 06H is
cleared. Thus the CP bit has to be corrected once aer startup or a
reset.
If this parity bit is incorrect during a write cycle, the Wake Up is
disabled.
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Usermanual TLE493D-P2B6
High Accuracy Low Power 3D Hall Sensor with I²C Interface
1 I2C Register
Table 3 Test mode interaction of TST, PH and X2 bits
TST bits PH bits X2 bit Bx (11...0) By (11...0) Bz (11...0) T (11...2)
00
00
01
10
10
10
10
11
11
11
11
11
11
11
11
B
B
B
B
B
B
B
B
B
B
B
B
B
B
B
don´t care 0
don´t care 1
B
B
don´t care don´t care Vhall X Vhall Y Vhall Z Voltage V
00
01
10
11
00
01
10
11
00
01
10
11
B
B
B
B
B
B
B
B
B
B
B
B
don´t care Spintest-Bx,
don´t care Spintest-By,
don´t care Spintest-Bz,
don´t care Spintest-T,
0
B
0
B
0
B
0
B
1
B
1
B
1
B
1
B
Bx full-range By full-range Bz full-range T full-range
Bx short-range By short-range Bz short-range T full-range
DD
spin-0 disabled
spin-0 disabled
spin-0 disabled
setting1
7F9
H
806
H
7FF
H
800
H
7FF
H
800
H
7FF
H
800
H
Spintest-Bx,
spin-1 disabled
Spintest-By,
spin-1 disabled
Spintest-Bz,
spin-1 disabled
Spintest-T,
setting2
806
H
7F9
H
800
H
7FF
H
800
H
7FF
H
800
H
7FF
H
Spintest-Bx,
spin-2 disabled
Spintest By,
spin-2 disabled
Spintest-Bz,
spin-2 disabled
Spintest-T,
setting2
7FF
H
800
H
7F9
H
806
H
7FF
H
800
H
7FF
H
800
H
Spintest-Bx,
spin-3 disabled
Spintest By,
spin-3 disabled
Spintest-Bz,
spin-3 disabled
Spintest-T,
setting1
200
H
1FF
H
201
H
1FE
H
200
H
1FF
H
201
H
1FE
H
Back to TLE493D-P2B6 Bitmap.
Usermanual 12 Ver. 1.0
2020-12-11
7
0
FP
6 3 2 1
PR INT MODE
5 4
IICadr CA
Usermanual TLE493D-P2B6
High Accuracy Low Power 3D Hall Sensor with I²C Interface
1 I2C Register
1.2.4 Mode registers combined in the I²C parity flag “FF”
The I²C communication of the registers in this chapter is protected with the parity bit “FF”, described in the Diag
register with the address 06H. See also Figure 1 - parity bits and related registers.
Power mode, interrupt, address, parity
Register name Address Reset Value
MOD1 11
H
Field Bits Type Description
FP 7 rw Fuse parity
The registers 11H and 13H (bits 7:5) are odd parity protected with
this bit.
If this parity bit is incorrect please see FF bit.
To exit this state a sensor reset is necessary.
IICadr 6:5 rw I²C address
Bits can be set to 00B, 01B, 10B or 11B to define the slave address in
bus configuration.
See Table 4 and data sheet.
PR 4 rw I²C 1-byte or 2-byte read protocol
If 0B this is the 2-byte read protocol:
<start> <I²Cadr.> <reg.adr.> <data of reg.adr.> <data of reg.adr.+1>
…. <stop>
If 1B this is the 1-byte read protocol:
<start> <I²Cadr.> <data of reg.00H> <data of reg.01H> …. <stop>
See I²C read commands
(Product Type A0) 80
(Product Type A1) 20
(Product Type A2) 40
(Product Type A3) E0
H
H
H
H
CA 3 rw Collision avoidance
Clock stretching only in master-controlled and low-power mode,
not in fast mode.
The CA bit interacts with the INT bit, see Table 5 and Collision
avoidance and clock stretching.
INT 2 rw Interrupt enabled
If 1B /INT disabled
If 0B /INT enabled: Aer a completed measurement and ADC-
conversion, an /INT pulse will be generated.
For bus configurations /INT timing constraints between I²C data
transfers and interrupt pulses must be monitored and aligned.
Enabled Wake Up mode or Collision avoidance (CA bit = 0B and
INT bit = 0B) may suppress the /INT pulse.
The INT bit interacts with the CA bit, see Table 5 .
Usermanual 13 Ver. 1.0
2020-12-11
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