Infineon SPD100N03S2L-04 Schematic [ru]
)
)
j
j
g
OptiMOS
Power-Transistor
Feature
N-Channel
Enhancement mode
Logic Level
Preliminary data
SPD100N03S2L-04
Product Summary
V
DS
R
DS(on
I
D
30 V
4.2 m
100 A
Excellent Gate Charge x R
Superior thermal resistance
175°C operating temperature
Avalanche rated
dv/dt rated
DS(on
product (FOM)
Type Package Ordering Code
SPD100N03S2L-04 P-TO252-5-1 Q67042-S4128
Marking
PN03L04
P-TO252-5-1
6
1)
Gate
pin 1
n.c.: pin 2
1
3
2
Drain
pin 3,6
Source
pin 4,5
Maximum Ratings,at Tj = 25 °C, unless otherwise specified
Parameter Symbol Value Unit
Continuous drain current
TC=25°C2)
T
=100°C
C
Pulsed drain current
TC=25°C
I
D
I
D puls
100
100
400
A
5
4
Avalanche energy, single pulse
ID=80A, VDD=25V, RGS=25
Avalanche energy, periodic limited by T
Reverse diode dv/dt
IS=100A, VDS=24V, di/dt=200A/µs, T
jmax
=175°C
max
E
E
dv/dt 6 kV/µs
Gate source voltage V
Power dissipation
TC=25°C
P
Operating and storage temperature T
AS
AR
GS
tot
,
T
st
325 mJ
15
±20
150 W
-55... +175
V
°C
IEC climatic category; DIN IEC 68-1 55/175/56
Page 1
2001-12-04
Preliminary data
SPD100N03S2L-04
Thermal Characteristics
Parameter Symbol Values Unit
min. typ. max.
Characteristics
Thermal resistance, junction - case
SMD version, device on PCB:
@ min. footprint
@ 6 cm
2
cooling area
3)
R
R
thJC
thJA
- - 1 K/W
-
-
-
-
75
50
Electrical Characteristics, at Tj = 25 °C, unless otherwise specified
Parameter Symbol Values Unit
min. typ. max.
Static Characteristics
Drain-source breakdown voltage
VGS=0V, ID=1mA
Gate threshold voltage, VGS = V
I
= 100 µA
D
Zero gate voltage drain current
VDS=30V, VGS=0V, Tj=25°C
DS
V
(BR)DSS
V
GS(th)
I
DSS
30 - - V
1.2 1.6 2
-
0.01
1
µA
V
=30V, VGS=0V, Tj=125°C
DS
Gate-source leakage current
VGS=20V, VDS=0V
Drain-source on-state resistance
VGS=4.5V, ID=50A
Drain-source on-state resistance
VGS=10V, ID=50A
1
pin 1 and 2 have to be connected together on the PCB as well as pin 4 and 5.
2
Current limited by bondwire and calculated with max. source pin temperature of 85°C;
with a R
3
Device on 40mm*40mm*1.5mm epoxy PCB FR4 with 6cm² (one layer, 70 µm thick) copper area for drain
connection. PCB is vertical without blown air.
= 1K/W the chip is able to carry ID= 146A.
thJC
I
GSS
R
DS(on)
R
DS(on)
-
10
100
- 1 100 nA
- 5 6.3
- 3.4 4.2
m
Page 2
2001-12-04
Preliminary data
(p
)
SPD100N03S2L-04
Electrical Characteristics, at Tj = 25 °C, unless otherwise specified
Parameter Symbol Conditions Values Unit
min. typ. max.
Dynamic Characteristics
Transconductance g
Input capacitance C
Output capacitance C
Reverse transfer capacitance C
Turn-on delay time t
Rise time t
Turn-off delay time t
Fall time t
Gate Charge Characteristics
Gate to source charge Q
Gate to drain charge Q
Gate charge total Q
fs
iss
oss
rss
d(on)
r
d(off)
f
gs
gd
g
VDS
2*ID*R
DS(on)max
I
=100A
D
VGS=0V, VDS=25V,
f=1MHz
,
59 118 - S
- 2590 3450 pF
- 1025 1360
- 205 310
VDD=15V, VGS=10V,
I
=50A, RG=2.7
D
- 12 18 ns
- 245 365
- 45 67
- 24 36
VDD=24V, ID=100A - 9.7 12.9 nC
- 22.6 33.9
VDD=24V, ID=100A,
V
=0 to 10V
GS
- 72 96
Gate plateau voltage V
Reverse Diode
Inverse diode continuous
I
forward current
Inverse diode direct current,
I
pulsed
Inverse diode forward voltage V
Reverse recovery time t
Reverse recovery charge Q
S
SM
SD
rr
rr
lateau
VDD=24V, ID=100A - 3.6 - V
TC=25°C - - 100 A
- - 400
VGS=0V, IF=80A - 0.9 1.3 V
VR=15V, I
di
/dt=200A/µs
F
lS,
=
F
- 48 72 ns
- 100 150 nC
Page 3
2001-12-04
Loading...