wiring for the simultaneous max. short circuit
currents from channel 1 to 2 and also for low
thermal resistance
Input 1,2,3,4 activates channel 1,2,3,4 in case
of logic high signal
Output 1,2,3,4 protected high-side power output
of channel 1,2,3,4. Design the wiring for the
max. short circuit current
Diagnostic feedback 1/2,3/4 of channel 1,2,3,4
Ground of chip 1 (channel 1,2)
Ground of chip 2 (channel 3,4)
Pin configuration
(top view)
V
1 • 20 V
bb
GND1/2 2 19 Vbb
IN1 3 18 OUT1
ST1/2 4 17 OUT2
IN2 5 16 Vbb
GND3/4 6 15 Vbb
IN3 7 14 OUT3
ST3/4 8 13 OUT4
IN4 9 12 Vbb
Vbb 10 11 Vbb
bb
Infineon Technologies AG 3 of 14 2006-Mar-28
PROFET® ITS 724G
Maximum Ratings at T
= 25°C unless otherwise specified
j
Parameter Symbol Values Unit
Supply voltage (overvoltage protection see page 6) Vbb 43V
Supply voltage for full short circuit protection
T
=-40 ...+150°C
j,start
Vbb 36V
Load current (Short-circuit current, see page 6) IL self-limitedA
3
Load dump protection1)V
2)
R
= 2Ω, t
I
= 400ms; IN= low or high,
d
LoadDump
each channel loaded with R
= VA + Vs, VA = 13.5 V
=13.5 Ω,
L
Junction temperature
Operating temperature range
Storage temperature range
Power dissipation (DC)4) Ta = 25°C:
V
Loaddump
Tj
Ta
T
stg
P
3.6
tot
)
60V
(all channels active)Ta = 85°C:
Maximal switchable inductance, single pulse
V
=12V, T
bb
IL =3.3A, E
IL =4.7A, E
IL =7.3A, E
=150°C4), see diagrams on page 10
j,start
=120 mJ, 0Ω one channel:
AS
=140 mJ, 0Ω two parallel channels:
AS
=160 mJ, 0Ω four parallel channels:
AS
Electrostatic discharge capability (ESD) IN:
ZL
V
1.0
ESD
(Human Body Model) ST:
out to all other pins shorted:
acc. MIL-STD883D, method 3015.7 and ESD assn. std. S5.1-1993
R=1.5kΩ; C=100pF
Input voltage (DC) see internal circuit diagram page 9VIN -10 ... +16V
Current through input pin (DC)
Pulsed current through input pin
Current through status pin (DC)
5)
I
IN
I
INp
IST
+150
°C
-30 ... +85
-40 ... +105
W
1.9
16,5
mH
19
18
kV
4.0
8.0
±0.3
mA
±5.0
±5.0
1)
Supply voltages higher than V
resistor for the GND connection is recommended.
2)
RI = internal resistance of the load dump test pulse generator
3)
V
Load dump
4)
Device on 50mm*50mm*1.5mm epoxy PCB FR4 with 6cm
connection. PCB is vertical without blown air. See page 14
5)
only for testing
is setup without the DUT connected to the generator per ISO 7637-1 and DIN 40839
require an external current limit for the GND and status pins (a 150Ω
bb(AZ)
2
(one layer, 70µm thick) copper area for V
bb
Infineon Technologies AG 4 of 14 2006-Mar-28
PROFET® ITS 724G
Thermal Characteristics
Parameter and Conditions Symbol Values Unit
Thermal resistance
junction - soldering point
6)7)
each channel: R
junction – ambient6)
@ 6 cm2 cooling area one channel active:
all channels active:
min typ max
R
thjs
thja
-- -- 15
--
--
42
34
--
--
K/W
Electrical Characteristics
Parameter and Conditions, each of the four channels Symbol Values Unit
at Tj = -40...+150°C, V
Load Switching Capabilities and Characteristics
= 12 V unless otherwise specified
bb
min typ max
On-state resistance (Vbb to OUT); I
= 2 A
L
each channel, Tj = 25°C:
T
= 150°C:
j
two parallel channels, Tj = 25°C:
four parallel channels, Tj = 25°C:
see diagram, page 11
Nominal load currentone channel active:
two parallel channels active:four parallel channels active:
Device on PCB
Output current while GND disconnected or pulledup
V
= 32 V, V
bb
see diagram page 9
Turn-on time
Turn-off time IN to 10% VR
=12Ω
L
Slew rate on9)10 to 30% V
Slew rate off9)70 to 40% V
6)
, T
= 85°C, Tj ≤ 150°C
a
= 0,
IN
9)
IN to 90% V
, R
OUT
OUT
L
, R
8)
OUT
OUT
=12Ω: dV/dton 0.2 -- 1.0V/µs
=12Ω:-dV/dt
L
:
:
;
RON
I
I
ton
t
3.0
L(NOM)
L(GNDhigh)
off
-- -- 2mA
0.2 -- 1.1V/µs
off
--
--
--
--
4.3
6.5
--
--
70
140
35
17.5
3.3
4.7
7.3
100
100
mΩ
90
180
45
22.5
--
A
--
--
250
µs
270
6)
Device on 50mm*50mm*1.5mm epoxy PCB FR4 with 6cm
connection. PCB is vertical without blown air. See page 14
7)
Soldering point: upper side of solder edge of device pin 15. See page 14
8)
not subject to production test, specified by design
9)
See timing diagram on page 12.
2
(one layer, 70µm thick) copper area for V
bb
Infineon Technologies AG 5 of 14 2006-Mar-28
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