Electrostatic discharge voltage (Human Body Model)
V
ESD
according to ANSI EOS/ESD - S5.1 - 1993
ESD STM5.1 - 1998
Input pin
All other pins
1
defined by P
2
At VIN > Vbb, the input current is not allowed to exceed ±5 mA.
3
defined by P
4
Device on 50mm*50mm*1.5mm epoxy PCB FR4 with 6 cm2 (one layer, 70µm thick) copper area for Vbb
connection. PCB is vertical without blown air.
5
not subject to production test, specified by design
6
V
Loaddump
Supply voltages higher than V
150Ω resistor in GND connection. A resistor for the protection of the input is integrated.
tot
tot
is setup without the DUT connected to the generator per ISO 7637-1 and DIN 40839 .
require an external current limit for the GND pin, e.g. with a
bb(AZ)
±1
±5
kV
Page 3
2006-03-09
ITS 4142N
)
)
Electrical Characteristics
ParameterSymbolValuesUnit
at Tj = -40...125 °C, Vbb = 15...30 V unless otherwise specifiedmin.typ.max.
Thermal Characteristics
Thermal resistance @ min. footprintR
Thermal resistance @ 6 cm2 cooling area
1)
Thermal resistance, junction - soldering pointR
Load Switching Capabilities and Characteristics
On-state resistance
T
= 25 °C, IL = 0.5 A
j
T
= 125 °C
j
1)
2)
OUT
OUT
OUT
,
Nominal load current
Device on PCB
Turn-on time to 90% V
R
= 47 Ω, V
L
= 0 to 10 V
IN
Turn-off time to 10% V
R
= 47 Ω, V
L
= 10 to 0 V
IN
Slew rate on 10 to 30% V
R
= 47 Ω, V
L
= 15 V
bb
th(JA
R
th(JA
thJS
R
ON
I
L(nom)
t
on
t
off
dV/dt
on
--125K/W
--70
--7K/W
-
-
150
270
200
320
mΩ
1.4--A
µs
-50100
-75150
V/µs
-12
Slew rate off 70 to 40% V
R
= 47 Ω, V
L
1
Device on 50mm*50mm*1.5mm epoxy PCB FR4 with 6 cm2 (one layer, 70µm thick) copper area for Vbb
connection. PCB is vertical without blown air.
2
Nominal load current is limited by the current limitation ( see page 5 )
= 15 V
bb
OUT
,
-dV/dt
off
-12
Page 4
2006-03-09
ITS 4142N
)
)
)
j
j
Electrical Characteristics
ParameterSymbolValuesUnit
at Tj = -40...125 °C, Vbb = 15...30 V unless otherwise specifiedmin.typ.max.
Operating Parameters
Operating voltageV
Undervoltage shutdownV
Undervoltage restartV
Undervoltage hysteresis
∆V
bb(under)
= V
bb(u rst)
- V
bb(under)
Standby current
T
= -40...85 °C, V
j
Tj = 125 °C
1)
≤ 1,2 V
IN
Operating currentI
Leakage output current (included in I
V
≤ 1,2 V
IN
Protection Functions
2)
bb(off)
)
Initial peak short circuit current limit
T
= -40 °C, Vbb = 20 V, tm = 150 µs
j
T
= 25 °C
j
T
= 125 °C
j
bb(on
bb(under
bb(u rst
∆V
bb(under)
I
bb(off)
GND
I
L(off)
I
L(SCp)
12-45V
7-10.5
--11
-0.5-
-
-
10
25
-
50
-11.6mA
-3.510µA
-
-
1.4
-
3
-
4.5
-
-
µA
A
Repetitive short circuit current limit
I
L(SCr)
-2.2-
Tj = Tjt (see timing diagrams)
Output clamp (inductive load switch off)
at V
OUT
= Vbb - V
ON(CL)
, Ibb = 4 mA
Overvoltage protection 3)
V
ON(CL)
V
bb(AZ)
6268-V
47--
Ibb = 4 mA
Thermal overload trip temperature
Thermal hysteresis∆T
1
higher current due temperature sensor
2
Integrated protection functions are designed to prevent IC destruction under fault conditions
described in the data sheet. Fault conditions are considered as "outside" normal operating range.
Protection functions are not designed for continuous repetitive operation.
3
see also V
4
higher operating temperature at normal function available
ON(CL)
in circuit diagram
4)
Page 5
T
t
t
135--°C
-10-K
2006-03-09
ITS 4142N
)
)
)
)
)
Electrical Characteristics
ParameterSymbolValuesUnit
at Tj = -40...125 °C, Vbb = 15...30 V unless otherwise specifiedmin.typ.max.
Input
Continuous input voltage
1)
V
Input turn-on threshold voltageV
Input turn-off threshold voltageV
Input threshold hysteresis∆V
Off state input current
V
≤ 1,8 V
IN
On state input currentI
Input delay time at switch on V
bb
I
IN(off)
IN(on
t
d(Vbbon
Input resistance (see page 8)R
IN
IN(T+
IN(T-
IN(T
I
-10
2)
-
V
bb
--3.0
1.82--
-0.2-
20--
--110
150340-µs
1.535
V
µA
kΩ
Reverse Battery
Reverse battery voltage
R
R
GND
GND
= 0 Ω
= 150 Ω
3)2)
Continuous reverse drain current2)
T
= 25 °C
j
Drain-source diode voltage (V
I
= 1 A
F
OUT
> Vbb)
-V
I
S
-V
bb
ON
-
-
-
-
0.3
45
V
--1A
-0.61.2V
1
At VIN > Vbb, the input current is not allowed to exceed ±5 mA.
2
not subject to production test, guaranted by design
3
defined by P
tot
Page 6
2006-03-09
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