Datasheet IRF7807PBF Datasheet

HEXFET® Chip-Set for DC-DC Converters

G

A

• N Channel Application Specific MOSFETs

• Ideal for Mobile DC-DC Converters

• Low Conduction Losses

• Low Switching Losses

• Lead-Free

Description

These new devices employ advanced HEXFET
Power MOSFET technology to achieve an
unprecedented balance of on-resistance and gate
charge. The reduced conduction and switching losses
make them ideal for high efficiency DC-DC
Converters that power the latest generation of mobile
microprocessors.

A pair of IRF7807 devices provides the best cost/
performance solution for system voltages, such as 3.3V
and 5V .

IRF7807PbF

IRF7807APbF

1

S

2

S

3

S

4

SO-8

Device Features

IRF7807 IRF7807A
Vds 30V 30V
Rds(on) 25mΩ 25mΩ
Qg 17nC 17nC
Qsw 5.2nC
Qoss 16.8nC 16.8nC

PD – 95290

Top View

8

D

7

D

6

D

5

D

Absolute Maximum Ratings

Parameter Symbol IRF7807 IRF7807A Units

Drain-Source Voltage V
Gate-Source Voltage V
Continuous Drain or Source 25°C I
Current (V

≥ 4.5V) 70°C 6.6 6.6

GS

Pulsed Drain Current I
Power Dissipation 25°C P

DS

GS

D

DM

D

8.3 8.3 A

66 66

30 V

±12

2.5 W

70°C 1.6
Junction & Storage Temperature Range TJ, T
Continuous Source Current (Body Diode) I
Pulsed source Current I

STG

S

SM

–55 to 150 °C

2.5 2.5 A
66 66

Thermal Resistance

Parameter Max. Units

Maximum Junction-to-Ambient R

θJA

50 °C/W

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09/22/04

IRF7807/APbF

Electrical Characteristics

IRF7807 IRF7807A

Parameter Min Typ Max Min Typ Max Units Conditions

Drain-to-Source V
Breakdown Voltage*

(BR)DSS

30 – – 30 – – V VGS = 0V, ID = 250µA

Static Drain-Source RDS(on) 17 25 17 25 mΩ VGS = 4.5V , ID = 7A
on Resistance*

Gate Threshold Voltage* VGS(th) 1.0 1.0 V VDS = VGS, ID = 250µA
Drain-Source Leakage I

Current*

DSS

30 30 µA VDS = 24V, VGS = 0

150 150 V

= 24V , VGS = 0,

DS

Tj = 100°C

Gate-Source Leakage I

GSS

±100 ±100 nA VGS = ±12V

Current*

T otal Gate Charge* Q
Pre-Vth Q

Gate-Source Charge
Post-Vth Q

Gate-Source Charge
Gate to Drain Charge Q
Switch Charge* Q

(Q

+ Qgd)

gs2

Output Charge* Q
Gate Resistance R

g

gs1

gs2

gd

SW

oss

g

12 17 12 17 VGS = 5V , ID = 7A

2.1 2.1 VDS = 16V , ID = 7A

0.76 0.76 nC

2.9 2.9

3.66 5.2 3.66

14 16.8 14 16.8 VDS = 16V, VGS = 0

1.2 1.2 Ω

Turn-on Delay Time td(on) 12 12 VDD = 16V
Rise Time t
Turn-off Delay T ime t
Fall Time t

r

(off) 25 25 Rg = 2Ω

d

f

17 17 ns ID = 7A

66V

= 4.5V

GS

Resistive Load

Source-Drain Rating & Characteristics

Parameter Min Typ Max Min Typ Ma x Units Conditions

Diode Forward V
Voltage*

Reverse Recovery Q
Charge VDS = 16V , VGS = 0V , IS = 7A

Reverse Recovery Q
Charge (with Parallel

SD

rr

rr(s)

Schotkky)

1.2 1.2 V IS = 7A, VGS = 0V

80 80 nC di/dt = 700A/µs

50 50

di/dt = 700A/µs
(with 10BQ040)
V

= 16V, VGS = 0V, IS = 7A

DS

Notes:

 Repetitive rating; pulse width limited by max. junction temperature.
 Pulse width ≤ 300 µs; duty cycle ≤ 2%.
 When mounted on 1 inch square copper board, t < 10 sec.
 Typ = measured - Q

* Devices are 100% tested to these parameters.

oss

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P
P

f

)

Power MOSFET Selection for DC/DC

e

Converters

Control FET

Special attention has been given to the power losses
in the switching elements of the circuit - Q1 and Q2.
Power losses in the high side switch Q1, also called the
Control FET , are impacted by the R
but these conduction losses are only about one half of
the total losses.

of the MOSFET ,

ds(on)

V

GTH

t1

IRF7807/APbF

Drain Current

t2

t3

4

1

Gate V oltag

Power losses in the control switch Q1 are given by;

P

= P

loss

This can be expanded and approximated by;

P

loss

conduction

= I

()

rms

⎛
⎜

+ I ×

⎝

+ Qg× Vg× f

()

Q

⎛

+

⎝

This simplified loss equation includes the terms Q
and Q

that is included in all MOSFET data sheets. The impor­tance of splitting this gate-source charge into two sub
elements, Q

the gate driver between the time that the threshold volt­age has been reached (t1) and the time the drain cur­rent rises to I
begins to change. Minimizing Q
reducing switching losses in Q1.

capacitance of the MOSFET during every switching
cycle. Figure 2 shows how Q
lel combination of the voltage dependant (non-linear)
capacitance’s Cds and Cdg when multiplied by the power
supply input buss voltage.

which are new to Power MOSFET data sheets.

oss

Q

is a sub element of traditional gate-source charge

gs2

Q

indicates the charge that must be supplied by

gs2

Q

is the charge that must be supplied to the output

oss

+ P

2

× R

ds(on )

Q

gd

× Vin× f

i

g

oss

×Vin× f

2

and Q

gs1

gs2

(t2) at which time the drain voltage

dmax

switching

⎞
⎟

⎠

+ P

+ I ×

+ P

drive

⎛

Q

gs2

⎜

i

⎝

g

⎞
⎠

, can be seen from Fig 1.

is a critical factor in

gs2

is formed by the paral-

oss

output

× Vin× f

⎞
⎟

⎠

gs2

t0

2

GS1QGS2QGD

Q

Figure 1: Typical MOSFET switching waveform

Synchronous FET

The power loss equation for Q2 is approximated

by;

= P

loss

conduction

= I

loss

+ Qg× Vg× f

+

rms

()

⎛

Q

⎜
⎝

*dissipated primarily in Q1.

+ P

drive

2

× R

ds(on)()

oss

×Vin× f

2

Drain V oltage

*

+ P

output

⎞

+ Qrr× Vin×

(

⎠

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