Datasheet, V1.1, 21 May 2004
F3
ICE3AS02 / ICE3BS02
ICE3AS02G / ICE3BS02G
Off-Line SMPS Current Mode
Controller with integrated 500V
Startup Cell
Power Management & Supply
Never stop thinking.
F3
Revision History: 2004-05-21 Datasheet
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Edition 2004-05-21
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be endangered.
ICE3AS02 / ICE3BS02
Off-Line SMPS Current Mode Controller
with integrated 500V Startup Cell
Product Highlights
ICE3AS02G / ICE3BS02G
F3
• Leadfree DIP package
• Active Burst Mode to reach the lowest Standby Power
Requirements < 100mW
• Protection features (Auto Restart Mode) to increase
robustness and safety of the system
• Adjustable Blanking Window for high load jumps to
increase system reliability
Features
• Active Burst Mode for lowest Standby Power
@ light load controlled by Feedback Signal
• Fast load jump response in Active Burst Mode
• 500V Startup Cell switched off after Start Up
• 100/67kHz internally fixed switching frequency
• Auto Restart Mode for Overtemperature Detection
• Auto Restart Mode for VCC Overvoltage Detection
• Auto Restart Mode for Overload and Open Loop
• Auto Restart Mode for VCC Undervoltage
• Blanking Window for short duration high current
• User defined Soft Start
• Minimum of external components required
• Max Duty Cycle 72%
• Overall tolerance of Current Limiting < ±5%
• Internal PWM Leading Edge Blanking
• Soft switching for low EMI
Description
The F3 Controller provides Active Burst Mode to reach the
lowest Standby Power Requirements <100mW at no load.
As the controller is always active during Active Burst
Mode, there is an immediate response on load jumps
without any black out in the SMPS. In Active Burst Mode
the ripple of the output voltage can be reduced <1%.
Furthermore, to increase the robustness and safety of the
system, the device enters into Auto Restart Mode in the
cases of Overtemperature, VCC Overvoltage, Output
Open Loop or Overload and VCC Undervoltage. By
means of the internal precise peak current limitation, the
dimension of the transformer and the secondary diode can
be lowered which leads to more cost efficiency. An
adjustable blanking window prevents the IC from entering
Auto Restart Mode or Active Burst Mode unintentionally in
case of high load jumps.
Typical Appl icati on
85 ... 270 VAC
GND
C
Bulk
HV
Start up Cell
Power
Management
ICE3AS02/G ICE3BS02/G
VCC
PWM Controller
Curr ent Mode
Precise Lo w
Tolerance Peak
Current Limitation
Control Unit
Active Burst Mode
Auto Restart Mode
C
VCC
Snubber
Gate
CS
FB
Soft S
C
PG-DIP-8-6
test
P-DSO-8-8
+
Converter
DC Output
-
R
Sense
SoftS
Type Ordering Code F
OSC
Package
ICE3AS02 Q67040-S4661-A101 100kHz PG-DIP-8-6
ICE3BS02 Q67040-S4637-A101 67kHz PG-DIP-8-6
ICE3AS02G 100kHz P-DSO-8-8
ICE3BS02G 67kHz P-DSO-8-8
Version 1.1 3 21 May 2004
F3
ICE3AS02 / ICE3AS02G / ICE3BS02 / ICE3BS02G
Table of Contents Page
1 Pin Configuration and Functionality . . . . . . . . . . . . . . . . . . . . . . . . . . . . .5
1.1 Pin Configuration with PG-DIP-8-6 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .5
1.2 Pin Configuration with P-DSO-8-8 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .5
1.3 Pin Functionality . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .6
2 Representative Blockdiagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .7
3 Functional Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .8
3.1 Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .8
3.2 Power Management . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .8
3.3 Startup Phase . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .9
3.4 PWM Section . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .10
3.4.1 Oscillator . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .10
3.4.2 PWM-Latch FF1 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .10
3.4.3 Gate Driver . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .10
3.5 Current Limiting . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .11
3.5.1 Leading Edge Blanking . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .11
3.5.2 Propagation Delay Compensation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .11
3.6 Control Unit . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .12
3.6.1 Adjustable Blanking Window . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .12
3.6.2 Active Burst Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .13
3.6.2.1 Entering Active Burst Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .13
3.6.2.2 Working in Active Burst Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .13
3.6.2.3 Leaving Active Burst Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .13
3.6.3 Protection Mode(Auto Restart Mode). . . . . . . . . . . . . . . . . . . . . . . . . . . .14
4 Electrical Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .16
4.1 Absolute Maximum Ratings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .16
4.2 Operating Range . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .16
4.3 Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .17
4.3.1 Supply Section 1. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .17
4.3.2 Supply Section 2. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .17
4.3.3 Internal Voltage Reference . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .17
4.3.4 PWM Section . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .18
4.3.5 Control Unit . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .18
4.3.6 Current Limiting . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .19
4.3.7 Driver Section . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .20
5 Typical Performance Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . .21
6 Outline Dimension . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .22
Version 1.1 4 21 May 2004
ICE3AS02 / ICE3AS02G / ICE3BS02 / ICE3BS02G
Pin Configuration and Functionality
1 Pin Configuration and Functionality
1.1 Pin Configuration with PG-DIP-8-6
1.2 Pin Configuration with P-DSO-8-8
F3
Pin Symbol Function
1 SoftS Soft-Start
2 FB Feedback
3 CS Current Sense
4 HV High Voltage Input
5 HV High Voltage Input
6 Gate Driver Stage Output
7 VCC Controller Supply Voltage
8 GND Controller Ground
Package PG-DIP-8-6
FB
CS
HV
1
2
3
4
8
7
6
5
GNDSoftS
VCC
Gate
HV
Pin Symbol Function
1 SoftS Soft-Start
2 FB Feedback
3 CS Current Sense
4 Gate Driver Stage Output
5 HV High Voltage Input
6 N.C. Not connected
7 VCC Controller Supply Voltage
8 GND Controller Ground
Package P-DSO-8-8
FB
CS
Gate
1
2
3
4
8
7
6
5
GNDSoftS
VCC
N.C.
HV
Figure 1 Pin Configuration PG-DIP-8-6(top view)
Note: Pin 4 and 5 are shorted within the DIP
package.
Version 1.1 5 21 May 2004
Figure 2 Pin Configuration P-DSO-8-8(top view)
ICE3AS02 / ICE3AS02G / ICE3BS02 / ICE3BS02G
1.3 Pin Functionality
SoftS (Soft Start & Auto Restart Control)
The SoftS pin combines the functions of Soft Start
during Start Up and error detection for Auto Restart
Mode. These functions are implemented and can be
adjusted by means of an external capacitor at SoftS to
ground. This capacitor also provides an adjustable
blanking window for high load jumps, before the IC
enters into Auto Restart Mode.
FB (Feedback)
The information about the regulation is provided by the
FB Pin to the internal Protection Unit and to the internal
PWM-Comparator to control the duty cycle. The FBSignal controls in case of light load the Active Burst
Mode of the controller.
CS (Current Sense)
The Current Sense pin senses the voltage developed
on the series resistor inserted in the source of the
external PowerMOS. If CS reaches the internal
threshold of the Current Limit Comparator, the Driver
output is immediately switched off. Furthermore the
current information is provided for the PWMComparator to realize the Current Mode.
Gate
The Gate pin is the output of the internal driver stage
connected to the Gate of an external PowerMOS.
F3
Pin Configuration and Functionality
HV (High Voltage)
The HV pin is connected to the rectified DC input
voltage. It is the input for the integrated 500V Startup
Cell.
VCC (Power supply)
The VCC pin is the positive supply of the IC. The
operating range is between 8.5V and 21V.
GND (Ground)
The GND pin is the ground of the controller.
Version 1.1 6 21 May 2004
ICE3AS02 / ICE3AS02G / ICE3BS02 / ICE3BS02G
F3
2 Representative Blockdiagram
-
OUT
+
V
Converter
DC Output
Snubber
GND
VCC
VCC
C
VCC
Startup Cell
PWM Section
0.72
Duty Cycle Max
max
Duty Cycle
Oscillator
HV
6.5V
15V
Voltage
8.5V
Reference
Undervoltage Lockout
Gate
&
G9
Gate
Driver
Q
FF1
S
R
1
G8
Clock
&
G7
Soft-Start
Comparator
C7
Soft Start
PWM
Comparator
C8
Representative Blockdiagram
Sense
R
CS
D1
10k
1pF
Current Limiting
Edge
220ns
Leading
Blanking
csth
V
0.257V
C10
C12
Compensation
&
Propagation-Delay
G10
ICE3BS02/G
x3.7
0.85V
PWM OP
Current Mode
100kHz 67kHz
ICE3AS02/G
Mode
Bulk
C
85 ... 270 VAC
Power Management
6.5V
Reset
Internal Bias
Power-Down
8.0us
Spike
Blanking
>140°C
j
T
1V
T3
T1
T2
3.25k
SoftS
R
5k
SoftS
Thermal Shutdown
&
G1
C11
C1
VCC
SoftS
C
C2
17V
4.0V
4.0V
4.4V
Auto Restart
&
G5
1
G2
C3
C4
4.8V
5.4V
S1
5k
FB
R
6.5V
&
Mode
G11
Active Burst
&
G6
C5
C6a
C6b
3.4V
4.0V
1.32V
10pF
Control Unit
ICE3AS02/G ICE3BS02/G
FB
OSC
f
Figure 3 Representative Blockdiagram
Version 1.1 7 21 May 2004
ICE3AS02 / ICE3AS02G / ICE3BS02 / ICE3BS02G
3 Functional Description
All values which are used in the functional description
are typical values. For calculating the worst cases the
min/max values which can be found in section 4
Electrical Characteristics have to be considered.
3.1 Introduction
The F3 is the further development of the F2 to meet the
requirements for the lowest Standby Power at
minimum load and no load conditions. A new fully
integrated Standby Power concept is implemented into
the IC in order to keep the application design easy.
Compared to F2 no further external parts are needed to
achieve the lowest Standby Power. An intelligent
Active Burst Mode is used for this Standby Mode. After
entering this mode there is still a full control of the
power conversion by the secondary side via the same
optocoupler that is used for the normal PWM control.
The response on load jumps is optimized. The voltage
ripple on V
controlled in this mode.
The usually external connected RC-filter in the
feedback line after the optocoupler is integrated in the
IC to reduce the external part count.
Furthermore a high voltage startup cell is integrated
into the IC which is switched off once the Undervoltage
Lockout on-threshold of 15V is exceeded. The external
startup resistor is no longer necessary. Power losses
are therefore reduced. This increases the efficiency
under light load conditions drastically.
The Soft-Start capacitor is also used for providing an
adjustable blanking window for high load jumps. During
this time window the overload detection is disabled.
With this concept no further external components are
necessary to adjust the blanking window.
An Auto Restart Mode is implemented in the IC to
reduce the average power conversion in the event of
malfunction or unsafe operating condition in the SMPS
system. This feature increases the system’s
robustness and safety which would otherwise lead to a
destruction of the SMPS. Once the malfunction is
removed, normal operation is automatically initiated
after the next Start Up Phase.
The internal precise peak current limitation reduces the
costs for the transformer and the secondary diode. The
influence of the change in the input voltage on the
power limitation can be avoided together with the
integrated Propagation Delay Compensation.
Therefore the maximum power is nearly independent
on the input voltage which is required for wide range
SMPS. There is no need for an extra over-sizing of the
SMPS, e.g. the transformer or PowerMOS.
is minimized. V
out
is further on well
out
F3
Functional Description
3.2 Power Management
6.5V
which is
VCC
=8.5V the
CCoff
HV
SoftS
VCC
at
VCC
Start up Cell
Undervoltage Lockout
15V
8.5V
T1
SoftS
Power Management
Internal Bias
Voltage
Reference
Auto Restart Mode
Active Bur st Mode
Figure 4 Power Management
The Undervoltage Lockout monitors the external
supply voltage V
main line the internal Startup Cell is biased and starts
to charge the external capacitor C
connected to the VCC pin. This VCC charge current
which is provided by the Startup Cell from the HV pin is
1.05mA. When V
=15V the internal voltage reference and bias
V
CCon
circuit are switched on. Then the Startup Cell is
switched off by the Undervoltage Lockout and therefo re
no power losses present due to the connection of the
Startup Cell to the bus voltage (HV). To avoid
uncontrolled ringing at switch-on a hysteresis is
implemented. The switch-off of the controller can only
take place after Active Mode was entered and V
falls below 8.5V.
The maximum current consumption before the
controller is activated is about 160µA.
When V
VCC
internal reference is switched off and the Power Down
reset let T1 discharging the soft-start capaci tor C
pin SoftS. Thus it is ensured that at every startup cycle
the voltage ramp at pin SoftS starts at zero.
The internal Voltage Reference is switched off if Auto
Restart Mode is entered. The current consumption is
then reduced to 300µA.
. When the SMPS is plugged to the
VCC
exceeds the on-threshold
VCC
falls below the off-threshold V
Version 1.1 8 21 May 2004
F3
ICE3AS02 / ICE3AS02G / ICE3BS02 / ICE3BS02G
Once the malfunction condition is removed, this block
will then turn back on. The recovery from Auto Restart
Mode does not require disconnecting the SMPS from
the AC line.
When Active Burst Mode is entered, the internal Bia s is
switched off in order to reduce the current consumption
to below 1.05mA while keeping the Voltage Reference
active as this is necessary in this mode.
3.3 Startup Phase
6.5V
3.25k
R
T2
Sof tS
C
SoftS
Soft S
Soft Star t
C7
C2
4V
0.85V
PWM OP
Soft-Start
Comparator
&
G7
x3.7
T3
1V
Gat e Dri ver
CS
Functional Description
V
Sof tS
5.4V
4V
1V
max. Soft Start Phase
DC
max
DC
1
DC
2
Figure 6 Startup Phase
By means of this extra charge stage, there is no delay
in the beginning of the Startup Phase when there is still
no switching. Furthermore Soft Start is finished at 4V to
have faster the maximum power capability. The duty
cycles DC
the primary inductance of the transformer. The
limitation of the primary current by DC
V
current which is limited by the internal Current Limiting
with CS = 1V. Therefore the maximum Startup Phase
is divided into a Soft Start Phase until t1 and a phase
from t1 until t2 where maximum power is provided if
demanded by the FB signal.
and DC2 are depending on the mains and
1
= 4V. But DC1 is related to a maximum primary
SoftS
max. Start up Phase
t1 t2
is related to
2
t
t
Figure 5 Soft Start
At the beginning of the Startup Phase, the IC provides
a Soft Start duration whereby it controls the maximum
primary current by means of a duty cycle limitation. A
signal V
capacitor C
resistor R
exceeds 4V.
When the Soft Start begins, C
charged up to approx. 1V by T2. Therefore the Soft
Start Phase takes place between 1V and 4V. Above
V
SoftsS
DC
comparator C2 blocks the gate G7 (see Figure 5). The
maximum charge current in the very first stage when
V
SoftS
which is generated by the external
SoftS
in combination with the internal pull up
Softs
, determines the duty cycle until V
SoftS
is immediately
SoftS
= 4V there is no longer duty cycle limitation
which is controlled by comparator C7 since
max
is below 1V, is limited to 1.32mA.
SoftS
Version 1.1 9 21 May 2004
F3
ICE3AS02 / ICE3AS02G / ICE3BS02 / ICE3BS02G
3.4 PWM Section
Oscil lator
Duty
Cycle
max
Clock
Soft Start
Comparator
PWM
Comparator
Curre nt
Limiting
0.72
1
G8
S
R
FF1
Q
PWM Section
Gate
Drive r
&
G9
Gate
Figure 7 PWM Section
3.4.1 Oscillator
The oscillator generates a fixed frequency. The
switching frequency for ICE3AS02/G is f
and for ICE3BS02/G f
capacitor and a current source and current sink which
determine the frequency are integrated. The charging
and discharging current of the implemented oscillator
capacitor are internally trimmed, in order to achieve a
very accurate switching frequency. The ratio of
controlled charge to discharge current is adjusted to
reach a maximum duty cycle limitation of D
= 67kHz. A resistor, a
OSC
3.4.2 PWM-Latch FF1
The oscillator clock output provides a set pulse to the
PWM-Latch when initiating the external Power Switch
conduction. After setting the PWM-Latch can be reset
by the PWM comparator, the Soft Start comparator or
the Current-Limit comparator. In case of resetting, the
driver is shut down immediately.
3.4.3 Gate Driver
The Gate Driver is a fast totem pole gate drive whi ch is
designed to avoid cross conduction currents and which
is equipped with a zener diode Z1 (see Figure 8) in
order to improve the control of the Gate attached power
transistors as well as to protect them against
undesirable gate overvoltages.
= 100kHz
OSC
=0.72.
max
Functional Description
The Gate Driver is active low at voltages below the
undervoltage lockout threshold V
VCC
PWM-Latch
1
Figure 8 Gate Driver
The driver-stage is optimized to minimize EMI and to
provide high circuit efficiency. This is done by reducing
the switch on slope when exceeding the external
Power Switch threshold. This is achieved by a slope
control of the rising edge at the driver’s output (see
Figure 9).
Gate
ca. t = 130ns
V
5V
Figure 9 Gate Rising Slope
Thus the leading switch on spike is minimized. When
the external Power Switch is switched off, the falling
shape of the driver is slowed down when reaching 2V
to prevent an overshoot below ground. Furthermore the
driver circuit is designed to eliminate cross conduction
of the output stage. During powerup when VCC is
below the undervoltage lockout threshold V
output of the Gate Driver is low to disable power
transfer to the seconding side.
.
VCCoff
Z1
C
= 1nF
Load
Gate
t
, the
VCCoff
Version 1.1 10 21 May 2004
F3
ICE3AS02 / ICE3AS02G / ICE3BS02 / ICE3BS02G
3.5 Current Limiting
PWM Latch
FF1
Current Limiting
Propagation-Delay
Compensation
V
csth
C10
PWM-OP
&
G10
Active Burst
Mode
C12
10k
CS
Figure 10 Current Limiting Block
There is a cycle by cycle Current Limiting realized by
the Current-Limit comparator C10 to provide an
overcurrent detection. The source current of the
external Power Switch is sensed via an external sense
resistor R
is transformed to a sense voltage V
into the pin CS. If the voltage V
internal threshold voltage V
immediately turns off the gate drive by resetting the
PWM Latch FF1. A Propagation Delay Compensation
is added to support the immediate shut down without
delay of the Power Switch in case of Current Limiting.
The influence of the AC input voltage on the maximum
output power can thereby be avoided.
To prevent the Current Limiting from distortions caused
by leading edge spikes a Leading Edge Blanking is
integrated in the current sense path for the
comparators C10, C12 and the PWM-OP.
The output of comparator C12 is activated by the Gate
G10 if Active Burst Mode is entered. Once activated the
current limiting is thereby reduced to 0.257V. This
voltage level determines the power level when the
Active Burst Mode is left if there is a higher power
demand.
. By means of R
Sense
Sense
csth
Leading
Edge
Blanking
220ns
0.257V
1pF
D1
the source current
which is fed
Sense
exceeds the
Sense
the comparator C10
Functional Description
3.5.1 Leading Edge Blanking
V
Sense
V
csth
Figure 11 Leading Edge Blanking
Each time when the external Power Switch is switched
on, a leading edge spike is generated due to the
primary-side capacitances and secondary-side rectifier
reverse recovery time. This spike can cause the gate
drive to switch off unintentionally. To avoid a premature
termination of the switching pulse, this spike is blanked
out with a time constant of t
time, the gate drive will not be switched off.
3.5.2 Propagation Delay Compensation
In case of overcurrent detection, the switch-off of the
external Power Switch is delayed due to the
propagation delay of the circuit. This delay causes an
overshoot of the peak current I
the ratio of dI/dt of the peak current (see Figure 12).
I
Sense
I
peak2
I
peak1
I
Limit
Figure 12 Current Limiting
The overshoot of Signal2 is bigger than of Signal1 due
to the steeper rising waveform. This change in the
slope is depending on the AC input voltage.
Propagation Delay Compensation is integrated to limit
the overshoot dependency on dI/dt of the rising primary
current. That means the propagation delay time
between exceeding the current sense threshold V
and the switch off of the external Power Switch is
compensated over temperature within a wide range.
I
Overs hoot2
t
= 220ns
LEB
= 220ns. During this
LEB
which depends on
peak
Signal2Signal1
t
Propagation Delay
I
Overshoot1
t
t
csth
Version 1.1 11 21 May 2004
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ICE3AS02 / ICE3AS02G / ICE3BS02 / ICE3BS02G
Current Limiting is now possible in a very accurate way.
E.g. I
= 0.5A with R
peak
Delay Compensation the current sense threshold is set
to a static voltage level V
dI/dt = 0.4A/µs, that means dV
propagation delay time of i.e. t
leads then to an I
propagation delay compensation the overshoot is only
about 2% (see Figure 13).
V
1,3
1,25
1,2
1,15
Sense
1,1
V
1,05
1
0,95
0,9
0 0,2 0,4 0,6 0,8 1 1,2 1,4 1,6 1,8 2
peak
Figure 13 Overcurrent Shutdown
The Propagation Delay Compensation is realized by
means of a dynamic threshold voltage V
14). In case of a steeper slope the switch off of the
driver is earlier to compensate the delay.
V
OSC
max. Duty Cycle
V
Sense
V
csth
Signal1 Signal2
Figure 14 Dynamic Voltage Threshold V
= 2. Without Propagation
Sense
=1V. A current ramp of
csth
overshoot of 12%. By means of
with compensation
/dt = 0.8V/µs, and a
Sense
Propagation Delay
without compensation
dV
Sense
dt
off time
Propagation Delay
=180ns
(see Figure
csth
csth
V
s
µ
t
t
Functional Description
3.6 Control Unit
The Control Unit contains the functions for Acti ve Burst
Mode and Auto Restart Mode. The Active Burst Mode
and the Auto Restart Mode are combined with an
Adjustable Blanking Window which is depending on the
external Soft Start capacitor. By means of this
Adjustable Blanking Window, the IC avoids entering
into these two modes accidentally. Furthermore it also
provides a certain time whereby the overload detection
is delayed. This delay is useful for applications which
normally works with a low current and occasionally
require a short duration of high current.
3.6.1 Adjustable Blanking Window
SoftS
6.5V
R
SoftS
5k
4.4V
S1
5.4V
4.8V
FB
1.32V
Figure 15 Adjustable Blanking Window
V
is clamped at 4.4V by the closed switch S1 after
SoftS
the SMPS is settled. If overload occurs V
exceeding 4.8V. Auto Restart Mode can’t be ent ered as
the gate G5 is still blocked by the comparator C3. But
has exceeded 4.8V the switch S1 is opened
after V
FB
via the gate G2. The external Soft Start capacitor can
1
G2
C3
&
C4
C5
G5
Auto
Rest ar t
Mode
Act ive
Burs t
Mode
&
G6
Control Unit
FB
is
Version 1.1 12 21 May 2004
F3
ICE3AS02 / ICE3AS02G / ICE3BS02 / ICE3BS02G
now be charged further by the integrated pull up
resistor R
G5 and G6 once V
there is no entering of Auto Restart Mode possible
during this charging time of the external capacitor
C
SoftS
Soft Start capacitor if a low load condition is detected
by comparator C5 when V
Only after V
below 1.32V Active Burst Mode is entered.
3.6.2 Active Burst Mode
The controller provides Active Burst Mode for low load
conditions at V
significantly the efficiency at light load conditions while
supporting a low ripple on V
load jumps. During Active Burst Mode which is
controlled only by the FB signal the IC is always active
and can therefore immediately response on fast
changes at the FB signal. The Startup Cell is kept
switched off to avoid increased power losses for the
self supply.
SoftS
FB
Figure 16 Active Burst Mode
The Active Burst Mode is located in the Control Unit.
Figure 16 shows the related components.
. The comparator C3 releases the gates
SoftS
has exceeded 5.4V. Therefore
Softs
. The same procedure happens to the external
is falling below 1.32V.
has exceeded 5.4V and VFB is still
SoftS
OUT
5k
4.4V
S1
5.4V
4.8V
1.32V
C6a
4.0V
FB
. Active Burst Mode increases
and fast response on
OUT
6.5V
R
SoftS
Internal Bi as
Current
Limiting
Acti ve
Burst
Mode
&
G10
C3
C4
C5
&
G6
&
3.4V
C6b
Control Unit
G11
Functional Description
3.6.2.1 Entering Active Burst Mode
The FB signal is always observed by the comparator
C5 if the voltage level falls below 1.32V. In that case the
switch S1 is released which allows the capacitor C
to be charged starting from the clamped voltage level
at 4.4V in normal operating mode. If V
5.4V the comparator C3 releases the gate G6 to enter
the Active Burst Mode. The time window that is
generated by combining the FB and SoftS signals with
gate G6 avoids a sudden entering of the Active Burst
Mode due to large load jumps. This time window can be
adjusted by the external capacitor C
After entering Active Burst Mode a burst flag is set a nd
the internal bias is switched off in order to reduce the
current consumption of the IC down to approx. 1.05mA.
In this Off State Phase the IC is no longer self supplied
so that therefore C
(see Figure 17). Furthermore gate G11 is then rele ased
to start the next burst cycle once V
exceeded.
It has to be ensured by the application that the VCC
remains above the Undervoltage Lockout Level of 8.5V
to avoid that the Startup Cell is accidentally switched
on. Otherwise power losses are significantly increased.
The minimum VCC level during Active Burst Mode is
depending on the load conditions and the application.
The lowest VCC level is reached at no load conditions
at V
.
OUT
has to provide the VCC current
VCC
SoftS
.
FB
3.6.2.2 Working in Active Burst Mode
After entering the Active Burst Mode the FB voltage
rises as V
PWM section. Comparator C6a observes the FB signal
if the voltage level 4V is exceeded. In that case the
internal circuit is again activated by the internal Bias to
start with switching. As now in Active Burst Mode the
gate G10 is released the c ur r ent limit is only 0.257V to
reduce the conduction losses and to avoid audible
noise. If the load at V
for the Active Burst Mode the FB signal decreases
down to 3.4V. At this level C6b deactivates again the
internal circuit by switching off the internal Bias. The
gate G11 is released as after entering Active Burst
Mode the burst flag is set. If working in Active Burst
Mode the FB voltage is changing like a saw tooth
between 3.4V and 4V (see Figure 17).
starts to decrease due to the inactive
OUT
is still below the starting level
OUT
3.6.2.3 Leaving Active Burst Mode
The FB voltage immediately increases if there is a high
load jump. This is observed by comparator C4. As the
current limit is ca. 26% during Active Burst Mode a
certain load jump is needed that FB can exceed 4.8V.
At this time C4 resets the Active Burst Mode which also
exceeds
SoftS
has 3.4V
SoftS
Version 1.1 13 21 May 2004
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ICE3AS02 / ICE3AS02G / ICE3BS02 / ICE3BS02G
blocks C12 by the gate G10. Maximum current can now
be provided to stabilize V
V
FB
4.80V
4.00V
3.40V
1.32V
V
Sof tS
5.40V
4.40V
V
CS
1.00V
0.257V
V
VCC
8.5V
I
VCC
7.2mA
1.05mA
V
OUT
Enterin g Acti ve
Burst Mode
Blanki ng Window
Current li mi t level during
Active Burst Mode
Max. Ripple < 1%
Figure 17 Signals in Active Burst Mode
OUT
.
Leaving Act ive
Burst Mode
t
t
t
t
t
t
Functional Description
3.6.3 Protection Mode (Auto Restart Mode)
In order to increase the SMPS system’s robustness
and safety, the IC provides the Auto Restart Mode as a
protection feature. The Auto Restart Mode is entered
upon detection of the following faults in the system:
• VCC Overvoltage
• Overtemperature
• Overload
• Open Loop
• VCC Undervoltage
• Short Optocoupler
SoftS
4.4V
R
5k
VCC
17V
4.0V
4.8V
C
SoftS
S1
FB
5.4V
Figure 18 Auto Restart Mode
The VCC voltage is observed by comparator C1 if 17V
is exceeded. The output of C1 is combined with both
the output of C11 which checks for SoftS<4.0V, and the
output of C4 which checks for FB>4.8V. Therefore the
overvoltage detection is can only active during Soft
Start Phase(SoftS<4.0V) and when FB signal is
outside the operating range > 4.8V. This means any
small voltage overshoots of V
operating cannot trigger the Auto Restart Mode.
In order to ensure system reliability and prevent any
false activation, a blanking time is implemented before
the IC can enter into the Auto Restart Mode. The output
of the VCC overvoltage detection is fed into a spike
blanking with a time constant of 8.0µs.
The other fault detection which can result in the Auto
Restart Mode and has this 8.0µs blanking time is the
Overtemperature detection. This block checks for a
junction temperature of higher than 140°C for
malfunction operation.
SoftS
C1
C11
C4
C3
6.5V
&
Spike
G1
Blanking
8.0us
Thermal Shut down
Tj >140°C
&
G5
during normal
VCC
Contr ol Uni t
Auto Res tart
Mode
Volt age
Refe ren ce
Version 1.1 14 21 May 2004
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ICE3AS02 / ICE3AS02G / ICE3BS02 / ICE3BS02G
Once the Auto Restart Mode is entered, the internal
Voltage Reference is switched off in order to reduce the
current consumption of the IC as much as possible. In
this mode, the average current consumption is only
300µA as the only working block is the Undervoltage
Lockout(UVLO) which controls the Startup Cell by
switching on/off at V
As there is no longer a self supply by the auxiliary
winding, VCC starts to drop. The UVLO switches on the
integrated Startup Cell when VCC falls below 8.5V. It
will continue to charge VCC up to 15V whereby it is
switched off again and the IC enters into the Start Up
Phase.
As long as all fault conditions have been removed, the
IC will automaticlally power up as usual with switching
cycle at the GATE output after Soft Start duration. Thus
the name Auto Restart Mode.
Other fault detections which are active in normal
operation is the sensing for Overload, Open Loop and
VCC undervoltage conditions. In the first 2 cases, FB
will rise above 4.8V which will be observed by C4. At
this time, S1 is released such that V
its earlier clamp voltage of 4.4V. If V
which is observed by C3, Auto Restart Mode is entered
as both inputs of the gate G5 are high.
This charging of the Soft Start capacitor from 4.4V to
5.4V defines a blanking window which prevents the
system from entering into Auto Restart Mode unintentionally during large load jumps. In this event, F B
will rise close to 6.5V for a short duration before the
loop regulates with FB less than 4.8V. This is the same
blanking time window as for the Active Burst Mode and
can therefore be adjusted by the external C
In the case of VCC undervoltage, ie. VCC falls below
8.5V, the IC will be turn off with the Startup Cell
charging VCC as described earlier in this section. Once
VCC is charged above 15V, the IC will start a new
startup cycle. The same procedure applies when the
system is under Short Optocoupler fault condit ion, as it
will lead to VCC undervoltage.
VCCon/VVCCoff
.
SoftS
SoftS
can rise from
exceeds 5.4V
.
SoftS
Functional Description
Version 1.1 15 21 May 2004
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ICE3AS02 / ICE3AS02G / ICE3BS02 / ICE3BS02G
Electrical Characteristics
4 Electrical Characteristics
Note: All voltages are measured with respect to ground (Pin 8). The voltage levels are valid if other ratings are
not violated.
4.1 Absolute Maximum Ratings
Note: Absolute maximum ratings are defined as ratings, which when being exceeded may lead to destruction
of the integrated circuit. For the same reason make sure, that any capacitor that will be connected to pin
(VCC) is discharged before assembling the application circuit.
Parameter Symbol Limit Values Unit Remarks
min. max.
HV Voltage V
VCC Supply Voltage V
FB Voltage V
SoftS Voltage V
Gate Voltage V
CS Voltage V
Junction Temperature T
Storage Temperature T
Total Power Dissipation P
Thermal Resistance
Junction-Ambient
ESD Capability(incl. HV Pin) V
1)
According to EIA/JESD22-A114-B (discharging a 100pF capacitor through a 1.5kΩ series resistor)
HV
VCC
FB
SoftS
Gate
CS
j
S
totDSO8
P
totDIP8
R
thJADSO8
R
thJADIP8
ESD
- 500V V
-0.3 22 V
-0.3 6.5 V
-0.3 6.5 V
-0.3 22 V Internally clamped at 11.5V
-0.3 6.5 V
-40 150 °C
-55 150 °C
- 0.45 W P-DSO-8-8, T
- 0.90 W PG-DIP-8-6, T
amb
amb
< 50°C
< 50°C
- 185 K/W P-DSO-8-8
- 90 K/W PG-DIP-8-6
- 3 kV Human body model
1)
7
4.2 Operating Range
Note: Within the operating range the IC operates as described in the functional description.
Parameter Symbol Limit Values Unit Remarks
min. max.
VCC Supply Voltage V
Junction Temperature of
Controller
VCC
T
jCon
Version 1.1 16 21 May 2004
V
-25 130 °C Max value limited due to thermal
VCCoff
20 V
shut down of controller
F3
ICE3AS02 / ICE3AS02G / ICE3BS02 / ICE3BS02G
Electrical Characteristics
4.3 Characteristics
4.3.1 Supply Section 1
Note: The electrical characteristics involve the spread of values within the specified supply voltage and junction
temperature range T
related to 25°C. If not otherwise stated, a supply voltage of V
Parameter Symbol Limit Values Unit Test Condition
Start Up Current I
VCC Charge Current I
Leakage Current of Start Up Cell I
Supply Current with
Inactive Gate
Supply Current in
Auto Restart Mode with
Inactive Gate
Supply Current in
Active Burst Mode
with Inactive Gate
VCC Turn-On Threshold
VCC Turn-Off Threshold
VCC Turn-On/Off Hysteresis
from – 25 ° C to 130 °C. Typical values represent the median values, which are
J
= 15 V is assumed.
CC
min. typ. max.
VCCstart
VCCcharge1
I
VCCcharge2
StartLeak
I
VCCsup1
I
VCCrestart
I
VCCburst1
I
VCCburst2
V
VCCon
V
VCCoff
V
VCChys
- 160 220 µA V
0.55 1.05 1.60 mA V
- 0.88 - mA V
- 0.2 20 µA V
- 5.5 7.0 mA
- 300 - µA IFB = 0
- 1.05 1.25 mA V
- 0.95 1.15 mA V
14.2
8.0
-
15.0
8.5
6.5
15.8
9.0
-
V
V
V
=14V
VCC
= 0V
VCC
=14V
VCC
=16V, V
VCC
I
= 0
Softs
=15V
VCC
VFB = 3.7V, V
= 9.5V
VCC
VFB = 3.7V, V
HV
SoftS
SoftS
= 450V
= 4.4V
= 4.4V
4.3.2 Supply Section 2
Parameter Symbol Limit Values Unit Test Condition
min. typ. max.
Supply Current
with Active Gate
ICE3AS02
ICE3AS02G
ICE3BS02
ICE3BS02G
I
VCCsup2
I
VCCsup2
- 7.0 8.5 mA V
- 6.5 8.0 mA
= 4.4V
SoftS
IFB = 0, C
Load
=1nF
4.3.3 Internal Voltage Reference
Parameter Symbol Limit Values Unit Test Condition
min. typ. max.
Trimmed Reference Voltage V
REF
6.37 6.50 6.63 V measured at pin FB
IFB = 0
Version 1.1 17 21 May 2004
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ICE3AS02 / ICE3AS02G / ICE3BS02 / ICE3BS02G
Electrical Characteristics
4.3.4 PWM Section
Parameter Symbol Limit Values Unit Test Condition
min. typ. max.
Fixed Oscillator
Frequency
Max. Duty Cycle D
Min. Duty Cycle D
PWM-OP Gain A
Voltage Ramp Max Level V
VFB Operating Range Min Level V
VFB Operating Range Max level V
FB Pull-Up Resistor R
SoftS Pull-Up Resistor R
1)
Design characteristic (not meant for production testing)
ICE3AS02
ICE3AS02G
ICE3BS02
ICE3BS02G
f
OSC1
f
OSC2
f
OSC1
f
OSC2
max
min
V
Max-Ramp
FBmin
FBmax
FB
SoftS
92 100 108 kHz
94 100 106 kHz Tj = 25°C
61 67 73 kHz
63 67 71 kHz Tj = 25°C
0.67 0.72 0.77
0 - - VFB < 0.3V
3.5 3.7 3.9
- 0.85 - V
0.3 0.7 - V
- - 4.75 V CS=1V, limited by
Comparator C4
16 20 27 kΩ
39 50 62 kΩ
1)
4.3.5 Control Unit
Parameter Symbol Limit Values Unit Test Condition
min. typ. max.
Deactivation Level for SoftS
Comparator C7 by C2
Clamped V
Normal Operating Mode
Voltage during
SoftS
Activation Limit of
Comparator C3
SoftS Startup Current I
Over Load & Open Loop Detection
Limit for Comparator C4
Active Burst Mode Level for
Comparator C5
Active Burst Mode Level for
Comparator C6a
V
SoftSC2
V
SoftSclmp
V
SoftSC3
SoftSstart
V
FBC4
V
FBC5
V
FBC6a
3.85 4.00 4.15 V VFB > 5V
4.23 4.40 4.57 V VFB = 4V
5.20 5.40 5.60 V VFB > 5V
- 1.3 - mA V
4.62 4.80 4.98 V V
1.23 1.30 1.37 V V
SoftS
SoftS
SoftS
= 0V
> 5.6V
> 5.6V
3.85 4.00 4.15 V After Active Burst
Mode is entered
Version 1.1 18 21 May 2004
F3
ICE3AS02 / ICE3AS02G / ICE3BS02 / ICE3BS02G
Electrical Characteristics
Parameter Symbol Limit Values Unit Test Condition
min. typ. max.
Active Burst Mode Level for
Comparator C6b
Overvoltage Detection Limit V
Thermal Shutdown
1)
Spike Blanking t
1)
The parameter is not subjec t to pr oduction test - verified by design/characterization
Note: The trend of all the voltage levels in the Control Unit is the same regarding the deviation except V
and V
VCCPD
V
FBC6b
VCCOVP
T
jSD
Spike
3.25 3.40 3.55 V After Active Burst
Mode is entered
16.1 17.1 18.1 V VFB > 5V
V
< 4.0V
SoftS
130 140 150 °C
- 8.0 - µs
4.3.6 Current Limiting
Parameter Symbol Limit Values Unit Test Condition
min. typ. max.
Peak Current Limitation
(incl. Propagation Delay Time of
external MOS)
Peak Current Limitation during
Active Burst Mode
Leading Edge Blanking t
CS Input Bias Current I
V
csth
V
CS2
LEB
CSbias
0.97 1.02 1.07 V dV
(see Figure 14)
0.232 0.257 0.282 V
- 220 - ns V
-1.0 -0.2 0 µA V
SoftS
CS
sense
= 4.4V
=0V
/ dt = 0.6V/µs
VCCOVP
Version 1.1 19 21 May 2004
ICE3AS02 / ICE3AS02G / ICE3BS02 / ICE3BS02G
4.3.7 Driver Section
Parameter Symbol Limit Values Unit Test Condition
min. typ. max.
GATE Low Voltage
GATE High Voltage
GATE Rise Time
(incl. Gate Rising Slope)
GATE Fall Time
GATE Current, Peak,
Rising Edge
GATE Current, Peak,
Falling Edge
1)
Transient reference value
2)
Design characteristic (not meant for production testing)
V
GATElow
V
GATEhigh
t
rise
t
fall
I
GATE
I
GATE
- - 1.2 V V
- - 1.5 V V
- 0.8 - V I
- 1.6 2.0 V I
-0.2 0.2 - V I
- 11.5 - V V
- 10.5 - V V
- 7.5 - V V
- 150 - ns V
- 55 - ns V
-0.5 - - A CL = 4.7nF
- - 0.7 A CL = 4.7nF
Electrical Characteristics
= 5 V
VCC
I
= 5 mA
Gate
= 5 V
VCC
I
= 20 mA
Gate
= 0 A
Gate
= 20 mA
Gate
= -20 mA
Gate
= 20V
VCC
CL = 4.7nF
= 11V
VCC
CL = 4.7nF
= V
VCC
VCCoff
CL = 4.7nF
= 2V ...9V
Gate
CL = 4.7nF
= 9V ...2V
Gate
CL = 4.7nF
2)
2)
F3
+ 0.2V
1)
1)
Version 1.1 20 21 May 2004
F3
ICE3AS02 / ICE3AS02G / ICE3BS02 / ICE3BS02G
Typical Performance Characteristics
5 Typical Performance Characteristics
Version 1.1 21 21 May 2004
F3
ICE3AS02 / ICE3AS02G / ICE3BS02 / ICE3BS02G
6 Outline Dimension
PG-DIP-8-6
(Leadfree Plastic Dual
In-Line Outline)
Figure 19 PG-DIP-8-6 (Leadfree Plastic Dual In-Line Outline)
P-DSO-8-8
(Plastic Dual Small Outline)
Outline Dimension
Figure 20 P-DSO-8-8 (Plastic Dual Small Outline)
Dimensions in mm
Version 1.1 22 21 May 2004
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Published by Infineon Technologies AG
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