Off-Line SMPS Current Mode
Controller with integrated 650V/
800V CoolMOS™
Power Management & Supply
Never stop thinking.
CoolSET™-F2
Revision History:2006-12-25Datasheet
Previous Version: 2.5.
PageSubjects (major changes since last revision)
4,17~22,
24~28, 30~31
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www.infineon.com.
CoolMOS™, CoolSET™ are trademarks of Infineon Technologies AG.
Add ICE2A380P2
Edition 2006-12-25
Published by Infineon Technologies AG,
St.-Martin-Strasse 53,
D-81541 München
The information herein is given to describe certain components and shall not be considered as warranted characteristics.
Terms of delivery and rights to technical change reserved.
We hereby disclaim any and all warranties, including but not limited to warranties of non-infringement, regarding
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Information
For further information on technology, delivery terms and conditions and prices please contact your nearest
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Warnings
Due to technical requirements components may contain dangerous substances. For information on the types in
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and/or protect human life. If they fail, it is reasonable to assume that the health of the user or other persons may
be endangered.
P-TO220-6-46
P-TO220-6-47
Off-Line SMPS Current Mode Controller
with integrated 650V/800V CoolMOS™
CoolSET™-F2
Product Highlights
• Best in class in DIP8, DIP7, TO220 and DSO16/12
packages
• No heat-sink required for DIP8, DIP7 and DSO16/12
• Increased creepage distance for TO220, DIP7 and
DSO16/12
• Isolated drain for TO220 packages
• Lowest standby power dissipation
• Enhanced protection functions with
Auto Restart Mode
• Pb-free lead plating for all packages; RoHS compliant
Features
•650V/800V avalanche rugged CoolMOS™
•Only few external components required
•Input Vcc Undervoltage Lockout
•67kHz/100kHz switching frequency
•Max duty cycle 72%
•Low Power Standby Mode to meet
European Commission Requirements
•Thermal Shut Down with Auto Restart
•Overload and Open Loop Protection
•Overvoltage Protection during Auto Restart
•Adjustable Peak Current Limitation via
external resistor
•Overall tolerance of Current Limiting < ±5%
•Internal Leading Edge Blanking
•User defined Soft Start
•Soft driving for low EMI
Description
The second generation CoolSET™-F2 provides several
special enhancements to satisfy the needs for low power
standby and protection features. In standby mode
frequency reduction is used to lower the power
consumption and support a stable output voltage in this
mode. The frequency reduction is limited to 20kHz/21.5
kHz to avoid audible noise. In case of failure modes like
open loop, overvoltage or overload due to short circuit the
device switches in Auto Restart Mode which is controlled by
the internal protection unit. By means of the internal precise
peak current limitation, the dimension of the transformer
and the secondary diode can be sized lower which leads to
more cost effective for the overall system.
PG-DIP-7-1
P-DIP-7-1
PG-DIP-8-6
P-DIP-8-4, -6
PG-TO220-6-47PG-TO220-6-46
PG-DSO-16/12
Typical Application
+
85 ... 270 VAC
SoftS
C
Soft Start
FB
Feedback
Low Power
StandBy
Soft-Start Control
PWM-Controller
CoolSET™-F2
VCC
Power
Management
Protect ion Unit
R
Start -up
C
VCC
PWM Controller
Current Mode
Precise Low Tolerance
Peak Current Li mitati on
Snubber
Dra in
CoolMOS™
Isense
GND
R
Feedback
Sense
Converter
DC Output
-
Version 2.6325 Dec 2006
Overview
CoolSET™-F2
TypePackageV
DS
F
OSC
R
DSon
1)
230VAC ±15%
2)
85-265 VAC
ICE2A0565PG-DIP-8-6650V100kHz4.7Ω23W13W
ICE2A165PG-DIP-8-6650V100kHz3.0Ω31W18W
ICE2A265PG-DIP-8-6650V100kHz0.9Ω52W32W
ICE2A365PG-DIP-8-6650V100kHz0.45Ω67W45W
ICE2B0565PG-DIP-8-6650V67kHz4.7Ω23W13W
ICE2B165PG-DIP-8-6650V67kHz3.0Ω31W18W
ICE2B265PG-DIP-8-6650V67kHz0.9Ω52W32W
ICE2B365PG-DIP-8-6650V67kHz0.45Ω67W45W
ICE2A0565ZPG-DIP-7-1650V100kHz4.7Ω23W13W
ICE2A180ZPG-DIP-7-1800V100kHz3.0Ω29W17W
ICE2A280ZPG-DIP-7-1800V100KHz0.8Ω50W31W
1)
typ @ T=25°C
2)
Maximum power rating at Ta=75°C, Tj=125°C and with copper area on PCB = 6cm²
TypePackageV
DS
F
OSC
R
DSon
1)
230VAC ±15%
2)
85-265 VAC
ICE2A0565GPG-DSO-16/12650V100kHz4.7Ω23W13W
1)
typ @ T=25°C
2)
Maximum power rating at Ta=75°C, Tj=125°C and with copper area on PCB = 6cm²
2)
2)
TypePackageV
DS
F
OSC
R
DSon
1)
230VAC ±15%
2)
85-265 VAC
2)
ICE2A765IPG-TO-220-6-46650V100kHz0.45Ω240W130W
ICE2B765IPG-TO-220-6-46650V67kHz0.45Ω240W130W
ICE2A765P2PG-TO-220-6-47650V100kHz0.45Ω240W130W
ICE2B765P2PG-TO-220-6-47650V67kHz0.45Ω240W130W
ICE2A380P2PG-TO-220-6-47800V100kHz1.89Ω111W60W
1)
typ @ T=25°C
2)
Maximum practical continuous power in an open frame design at Ta=75°C, Tj=125°C and R
This pin combines the function of Soft Start in case of
Start Up and Auto Restart Mode and the controlling of
the Auto Restart Mode in case of an error detection.
FB (Feedback)
The information about the regulation is provided by the
FB Pin to the internal Protection Unit and to the internal
PWM-Comparator to control the duty cycle.
Isense (Current Sense)
The Current Sense pin senses the voltage developed
on the series resistor inserted in the source of the
integrated CoolMOS™. When Isense reaches the
internal threshold of the Current Limit Comparator, the
Driver output is disabled. By this means the Over
Current Detection is realized.
Furthermore the current information is provided for the
PWM-Comparator to realize the Current Mode.
CoolSET™-F2
Pin Configuration and Functionality
Drain (Drain of integrated CoolMOS™)
Pin Drain is the connection to the Drain of the internal
CoolMOS
VCC (Power supply)
This pin is the positive supply of the IC. The operating
range is between 8.5V and 21V.
To provide overvoltage protection the driver gets
disabled when the voltage becomes higher than 16.5V
during Start Up Phase.
GND (Ground)
This pin is the ground of the primary side of the SMPS.
TM
.
Version 2.6825 Dec 2006
2Representative Blockdiagram
OUT
-
+
V
Converter
DC Output
CoolSET™-F2
Representative Blockdiagram
Sense
R
Isense
Optocoupler
PWM
R
Comparator
Error-Latch
0.3V
D1
10k
220ns
Blanking
Leading Edge
csth
V
67kHz
100kHz
f
norm
20kHz
21.5kHz
standby
f
ICE2Bxxxx
Propagation-Delay
Compensation
Current Limiting
Comparator
Current-Limit
ICE2Axxxx
C5
osc
f
x3.65
0.8V
FB
U
norm
standby
f
f
Standby Unit
Improved Current Mode
PWM OP
Snubber
Drain
CoolMOS™
Gate
Driver
Q
Q
S
Soft-Start
Soft Start
PWM-Latch
Comparator
R
SQ
Spike
G4
Q
s
5
Blanking
G3
G2
0.72
Duty Cycle Max
norm
-f
max
Clock
Duty Cycle
Voltage
4.8V
4.0V
Reference
standby
f
Reset
Power-Up
G1
Oscillator
6.5V
5.3V
Internal Bias
Power Management
13.5V
Reset
Lockout
Power-Down
Undervoltage
Line
VCC
C
C
8.5V
16.5V
4.0V
6.5V
C2
Soft-Start
R
SoftS
5.6V
C4
C3
4.8V
5.3V
FB
R
6.5V
T1
Soft-Start
C
FB
>140°C
j
T
Thermal Shutdown
Protection Unit
GND
CoolSET™-F2
Start-up
R
85 ... 270 VAC
C1
VCC
Figure 5Representative Blockdiagram
Version 2.6925 Dec 2006
CoolSET™-F2
Functional Description
3Functional Description
3.1Power Management
Main Line (100V-380V)
R
Start-Up
Primary Winding
C
VCC
VCC
Power Management
SoftS
C
Soft-Start
Undervoltage
Lockout
8.5V
Power-Down
Reset
Power-Up
Reset
R
T1
13.5V
6.5V
Soft-Start
Internal
Bias
Voltage
Reference
RSQ
Q
Error-Latch
Soft-Start Comparator
Error-Detection
6.5V
5.3V
4.8V
4.0V
PWM-Latch
3.2Improved Current Mode
Soft-Start Comparator
FB
PWM-Latch
RSQ
Driver
PWM Comparator
Q
0.8V
PWM OP
x3.65
Isense
Improved
Current Mode
Figure 7Current Mode
Current Mode means that the duty cycle is controlled
by the slope of the primary current. This is done by
comparison the FB signal with the amplified current
sense signal.
Amplified Current Signal
FB
Figure 6Power Management
The Undervoltage Lockout monitors the external
supply voltage V
. In case the IC is inactive the
VCC
current consumption is max. 55µA. When the SMPS is
plugged to the main line the current through R
charges the external Capacitor C
exceeds the on-threshold V
=13.5V the internal bias
CCon
. When V
VCC
Start-up
VCC
0.8V
Driver
t
circuit and the voltage reference are switched on. After
that the internal bandgap generates a reference
voltage V
=6.5V to supply the internal circuits. To
REF
T
on
avoid uncontrolled ringing at switch-on a hysteresis is
implemented which means that switch-off is only after
active mode when Vcc falls below 8.5V.
In case of switch-on a Power Up Reset is done by
resetting the internal error-latch in the protection unit.
When V
falls below the off-threshold V
VCC
=8.5V the
CCoff
internal reference is switched off and the Power Down
reset let T1 discharging the soft-start capacitor C
Soft-Start
at pin SoftS. Thus it is ensured that at every switch-on
the voltage ramp at pin SoftS starts at zero.
Figure 8Pulse Width Modulation
In case the amplified current sense signal exceeds the
FB signal the on-time T
of the driver is finished by
on
resetting the PWM-Latch (see Figure 8).
The primary current is sensed by the external series
resistor R
inserted in the source of the integrated
Sense
t
CoolMOS™. By means of Current Mode regulation, the
Version 2.61025 Dec 2006
secondary output voltage is insensitive on line
variations. Line variation changes the current
waveform slope which controls the duty cycle.
The external R
allows an individual adjustment of
Sense
the maximum source current of the integrated
CoolMOS™.
Soft-Start Comparator
V
CoolSET™-F2
Functional Description
OSC
max .
Dut y Cy cle
PWM Comparator
FB
PWM-Latch
Oscillator
0.3V
C5
V
OSC
Gate Driver
0.8V
10k
Ω
x3.65
T
2
C
1
R
1
20pF
V
1
PWM OP
Voltage Ramp
Figure 9Improved Current Mode
To improve the Current Mode during light load
conditions the amplified current ramp of the PWM-OP
is superimposed on a voltage ramp, which is built by
the switch T
low pass filter composed of R
Figure 10). Every time the oscillator shuts down for
max. duty cycle limitation the switch T2 is closed by
V
. When the oscillator triggers the Gate Driver T2 is
OSC
opened so that the voltage ramp can start.
In case of light load the amplified current ramp is to
small to ensure a stable regulation. In that case the
Voltage Ramp is a well defined signal for the
comparison with the FB-signal. The duty cycle is then
controlled by the slope of the Voltage Ramp.
By means of the Comparator C5, the Gate Driver is
switched-off until the voltage ramp exceeds 0.3V. It
allows the duty cycle to be reduced continuously till 0%
by decreasing V
, the voltage source V1 and the 1st order
2
below that threshold.
FB
and C1(see Figure 9,
1
Voltage Ramp
0.8V
FB
0.3V
Gate Driver
t
t
t
Figure 10 Light Load Conditions
3.2.1PWM-OP
The input of the PWM-OP is applied over the internal
leading edge blanking to the external sense resistor
R
connected to pin Isense. R
Sense
converts the
Sense
source current into a sense voltage. The sense voltage
is amplified with a gain of 3.65 by PWM OP. The output
of the PWM-OP is connected to the voltage source V1.
The voltage ramp with the superimposed amplified
current signal is fed into the positive inputs of the PWMComparator, C5 and the Soft-Start-Comparator.
3.2.2PWM-Comparator
The PWM-Comparator compares the sensed current
signal of the integrated CoolMOS
signal V
(see Figure 11). VFB is created by an
FB
external optocoupler or external transistor in
combination with the internal pull-up resistor R
provides the load information of the feedback circuitry.
When the amplified current signal of the integrated
CoolMOS™ exceeds the signal V
Comparator switches off the Gate Driver.
TM
with the feedback
FB
the PWM-
FB
and
Version 2.61125 Dec 2006
CoolSET™-F2
Functional Description
R
FB
FB
Optocoupler
6.5V
Soft-Start Comparator
PWM-Latch
PWM Comparator
0.8V
PWM OP
Isense
x3.65
Improved
Current Mode
pull-up resistor R
. The Soft-Start-Comparator
Soft-Start
compares the voltage at pin SoftS at the negative input
with the ramp signal of the PWM-OP at the positive
input. When Soft-Start voltage V
Feedback voltage V
the Soft-Start-Comparator limits
FB
is less than
SoftS
the pulse width by resetting the PWM-Latch (see
Figure 12). In addition to Start-Up, Soft-Start is also
activated at each restart attempt during Auto Restart.
By means of the above mentioned C
Soft-Start
the SoftStart can be defined by the user. The Soft-Start is
finished when V
exceeds 5.3V. At that time the
SoftS
Protection Unit is activated by Comparator C4 and
senses the FB by Comparator C3 wether the voltage is
below 4.8V which means that the voltage on the
secondary side of the SMPS is settled. The internal
Zener Diode at SoftS has a clamp voltage of 5.6V to
prevent the internal circuit from saturation (see Figure
13).
6.5V
5.6V
R
SoftS
Power-Up Reset
Soft-Start
Error-Latch
RSQ
Figure 11 PWM Controlling
3.3Soft-Start
V
SoftS
5.6V
5.3V
T
Soft-Start
Gate Driver
6.5V
5.3V
4.8V
R
FB
C4
C3
G2
Q
RSQ
Gate
Driver
FB
Clock
Q
PWM-Latch
Figure 13 Activation of Protection Unit
The Start-Up time T
voltage V
Start Phase T
is settled must be shorter than the Soft-
OUT
Soft-Start
T
C
t
Soft Start–
-------------------------------------=
R
Soft Start–
within the converter output
Start-Up
(see Figure 14).
Soft Start–
1.69×
By means of Soft-Start there is an effective
minimization of current and voltage stresses on the
integrated CoolMOS™, the clamp circuit and the output
overshoot and prevents saturation of the transformer
during Start-Up.
t
Figure 12Soft-Start Phase
The Soft-Start is realized by the internal pull-up resistor
R
Figure 5). The Soft-Start voltage V
charging the external capacitor C
and the external Capacitor C
Soft-Start
Soft-Start
is generated by
SoftS
by the internal
Soft-Start
(see
Version 2.61225 Dec 2006
CoolSET™-F2
Functional Description
V
SoftS
5.3V
T
Soft-Start
V
FB
t
4.8V
V
OUT
V
OUT
T
Start-Up
t
t
Figure 14 Start Up Phase
3.4Oscillator and Frequency
Reduction
3.4.1Oscillator
The oscillator generates a frequency f
100kHz. A resistor, a capacitor and a current source
and current sink which determine the frequency are
integrated. The charging and discharging current of the
implemented oscillator capacitor are internally
trimmed, in order to achieve a very accurate switching
frequency. The ratio of controlled charge to discharge
current is adjusted to reach a max. duty cycle limitation
of D
=0.72.
max
= 67kHz/
switch
kHz
100
65
OSC
f
21.5
1.0
1.1 1.2 1 .3 1. 4 1.5 1. 6 1.7 1.8 1. 9 2.0
f
norm
21.5kHz
f
standby
67kHz
20kHz
ICE2 Bxx x xICE2Axxxx
100kHz
V
FB
V
Figure 15 Frequency Dependence
3.5Current Limiting
There is a cycle by cycle current limiting realized by the
Current-Limit Comparator to provide an overcurrent
detection. The source current of the integrated
CoolMOS
R
Sense
transformed to a sense voltage V
voltage V
V
csth
TM
is sensed via an external sense resistor
. By means of R
exceeds the internal threshold voltage
Sense
the source current is
Sense
. When the
Sense
the Current-Limit-Comparator immediately turns
off the gate drive. To prevent the Current Limiting from
distortions caused by leading edge spikes a Leading
Edge Blanking is integrated at the Current Sense.
Furthermore a Propagation Delay Compensation is
added to support the immediate shut down of the
CoolMOS™ in case of overcurrent.
3.5.1Leading Edge Blanking
V
Sense
V
csth
t
= 220ns
LEB
3.4.2Frequency Reduction
The frequency of the oscillator is depending on the
voltage at pin FB. The dependence is shown in Figure
15. This feature allows a power supply to operate at
lower frequency at light loads thus lowering the
switching losses while maintaining good cross
regulation performance and low output ripple. In case
of low power the power consumption of the whole
SMPS can now be reduced very effective. The minimal
reachable frequency is limited to 20kHz/21.5 kHz to
avoid audible noise in any case.
Figure 16 Leading Edge Blanking
Each time when CoolMOS™ is switched on a leading
spike is generated due to the primary-side
capacitances and secondary-side rectifier reverse
recovery time. To avoid a premature termination of the
switching pulse this spike is blanked out with a time
constant of t
= 220ns. During that time the output of
LEB
t
Version 2.61325 Dec 2006
CoolSET™-F2
e
-
Functional Description
the Current-Limit Comparator cannot switch off the
gate drive.
3.5.2Propagation Delay Compensation
In case of overcurrent detection by I
of CoolMOS™ is delayed due to the propagation delay
of the circuit. This delay causes an overshoot of the
peak current I
which depends on the ratio of dI/dt of
peak
the peak current (see Figure 17).
.
the shut down
Limit
Signal2Signal1
I
peak2
I
peak1
I
Limit
I
Sense
I
Overshoot2
t
Propagation Del ay
I
Overshoot1
t
Figure 17 Current Limiting
The overshoot of Signal2 is bigger than of Signal1 due
to the steeper rising waveform.
A propagation delay compensation is integrated to
bound the overshoot dependent on dI/dt of the rising
primary current. That means the propagation delay
time between exceeding the current sense threshold
V
and the switch off of CoolMOS™ is compensated
csth
over temperature within a range of at least.
dI
peak
Sense
------------×
dt
max. Duty Cycle
R
≤≤
V
OSC
dV
Sens
--------------
dt
The propagation delay compensation is done by
means of a dynamic threshold voltage V
(see Figure
csth
18). In case of a steeper slope the switch off of the
driver is earlier to compensate the delay.
E.g. I
= 0.5A with R
peak
= 2. Without propagation
Sense
delay compensation the current sense threshold is set
to a static voltage level V
dI/dt = 0.4A/µs, that means dV
propagation delay time of i.e. t
leads then to a I
overshoot of 14.4%. By means of
peak
=1V. A current ramp of
csth
/dt = 0.8V/µs, and a
Sense
Propagation Delay
=180ns
propagation delay compensation the overshoot is only
about 2% (see Figure 19).
dV
Sense
without compensation
V/u s
with compensation
V
1.3
1.25
1.2
1.15
1.1
Sense
V
1.05
1
0.95
0.9
00. 2 0.4 0.6 0.811.2 1.4 1.6 1.82
dt
Figure 19 Overcurrent Shutdown
3.6PWM-Latch
The oscillator clock output applies a set pulse to the
PWM-Latch when initiating CoolMOS™ conduction.
After setting the PWM-Latch can be reset by the PWMOP, the Soft-Start-Comparator, the Current-LimitComparator, Comparator C3 or the Error-Latch of the
Protection Unit. In case of resetting the driver is shut
down immediately.
3.7Driver
off ti me
V
Sense
V
csth
Propagation Delay
Signal1Signal2
Figure 18 Dynamic Voltage Threshold V
csth
The driver-stage drives the gate of the CoolMOS™ and
is optimized to minimize EMI and to provide high circuit
t
efficiency. This is done by reducing the switch on slope
when reaching the CoolMOS™ threshold. This is
achieved by a slope control of the rising edge at the
driver’s output (see Figure 20) to the CoolMOS™ gate.
Thus the leading switch on spike is minimized. When
CoolMOS™ is switched off, the falling shape of the
driver is slowed down when reaching 2V to prevent an
t
overshoot below ground. Furthermore the driver circuit
is designed to eliminate cross conduction of the output
stage. At voltages below the undervoltage lockout
threshold V
the gate drive is active low.
VCCoff
Version 2.61425 Dec 2006
CoolSET™-F2
Functional Description
ca. t = 130ns
5V
V
Gate
t
Figure 20Internal Gate Rising Slope
3.8Protection Unit (Auto Restart Mode)
An overload, open loop and overvoltage detection is
integrated within the Protection Unit. These three
failure modes are latched by an Error-Latch. Additional
thermal shutdown is latched by the Error-Latch. In case
of those failure modes the Error-Latch is set after a
blanking time of 5µs and the CoolMOS™ is shut down.
That blanking prevents the Error-Latch from distortions
caused by spikes during operation mode.
3.8.1Overload / Open Loop with Normal
Load
Figure 21 shows the Auto Restart Mode in case of
overload or open loop with normal load. The detection
of open loop or overload is provided by the Comparator
C3, C4 and the AND-gate G2 (see Figure 22). The
detection is activated by C4 when the voltage at pin
SoftS exceeds 5.3V. Till this time the IC operates in the
Soft-Start Phase. After this phase the comparator C3
can set the Error-Latch in case of open loop or overload
which leads the feedback voltage V
threshold of 4.8V. After latching VCC decreases till
8.5V and inactivates the IC. At this time the external
Soft-Start capacitor is discharged by the internal
transistor T1 due to Power Down Reset. When the IC
is inactive V
the Capacitor C
R
. Then the Error-Latch is reset by Power Up
Start-Up
increases till V
VCC
by means of the Start-Up Resistor
VCC
CCon
Reset and the external Soft-Start capacitor C
charged by the internal pull-up resistor R
the Soft-Start Phase which ends when the voltage at
pin SoftS exceeds 5.3V the detection of overload and
open loop by C3 and G2 is inactive. In this way the Start
Up Phase is not detected as an overload.
to exceed the
FB
= 13.5V by charging
is
Soft-Start
. During
Soft-Start
Overload / Open Loop with Normal Load
5µs Blanking
FB
4.8V
Failure
Det ect i on
Soft S
5.3V
Soft-Start Phase
T
Dri ve r
VCC
13.5V
8.5V
Burst 1
Figure 21 Auto Restart Mode
SoftS
FB
C
Soft-Start
6.5V
R
T1
Power Up Reset
Soft-Start
C4
5.3V
4.8V
C3
T
Resta rt
G2
t
t
t
t
Error-Latch
R
FB
6.5V
Figure 22FB-Detection
Version 2.61525 Dec 2006
CoolSET™-F2
Functional Description
But the Soft-Start Phase must be finished within the
Start Up Phase to force the voltage at pin FB below the
failure detection threshold of 4.8V.
3.8.2Overvoltage due to Open Loop with
No Load
Open loop & no load condition
5µs Blanking
FB
4.8V
Failure
Detection
SoftS
5.3V
4.0V
Driver
Soft-Start Phase
Overvoltage
Detection Phase
T
Burst2
T
Restart
t
t
normal operation mode is prevented from overvoltage
detection due to varying of VCC concerning the
regulation of the converter output. When the voltage
V
is above 4.0V the overvoltage detection by C1 is
SoftS
deactivated.
VCC
6.5V
C1
16.5V
R
Soft-Start
4.0V
SoftS
C
Soft-Start
T1
C2
Power Up Reset
Figure 24Overvoltage Detection
3.8.3Thermal Shut Down
Error Latch
G1
t
t
VCC
16.5V
13.5V
8.5V
Overvoltage Detection
Figure 23 Auto Restart Mode
Figure 23 shows the Auto Restart Mode for open loop
and no load condition. In case of this failure mode the
converter output voltage increases and also VCC. An
additional protection by the comparators C1, C2 and
the AND-gate G1 is implemented to consider this
failure mode (see Figure 24).The overvoltage detection
is provided by Comparator C1 only in the first time
during the Soft-Start Phase till the Soft-Start voltage
exceeds the threshold of the Comparator C2 at 4.0V
and the voltage at pin FB is above 4.8V. When VCC
exceeds 16.5V during the overvoltage detection phase
C1 can set the Error-Latch and the Burst Phase during
Auto Restart Mode is finished earlier. In that case
T
is shorter than T
Burst2
. By means of C2 the
Soft-Start
Thermal Shut Down is latched by the Error-Latch when
junction temperature T
of the pwm controller is
j
exceeding an internal threshold of 140°C. In that case
the IC switches in Auto Restart Mode.
Note:All the values which are mentioned in the
functional description are typical. Please refer
to Electrical Characteristics for min/max limit
values.
Version 2.61625 Dec 2006
CoolSET™-F2
Electrical Characteristics
4Electrical Characteristics
4.1Absolute Maximum Ratings
Note:Absolute maximum ratings are defined as ratings, which when being exceeded may lead to destruction
of the integrated circuit. For the same reason make sure, that any capacitor that will be connected to pin 6
(VCC) is discharged before assembling the application circuit.
ParameterSymbolLimit ValuesUnitRemarks
min.max.
Drain Source Voltage
ICE2A0565/165/265/365/765I/765P2
ICE2B0565/165/265/365/765I/765P2
ICE2A0565G
ICE2A0565Z
Drain Source Voltage
ICE2A180Z/280Z/380P2
Pulsed drain current,
t
limited by T
p
jmax
ICE2A0565/
ICE2B056/
ICE2A0565G/
ICE2A0565Z
ICE2A165/
ICE2B165
ICE2A265/
ICE2B265
ICE2A365/
ICE2B365
ICE2A180ZI
ICE2A280ZI
ICE2A765P2/
ICE2B765P2/
ICE2A765I/
ICE2B765I
V
DS
V
DS
I
D_Puls1
I
D_Puls2
I
D_Puls3
I
D_Puls4
D_Puls5
D_Puls6
I
D_Puls7
-650VTj = 110°C
-800VTj = 25°C
2.0A
3.8A
9.8A
23.3A
4.1A
14.8A
19.0A
ICE2A380P2/I
D_Puls8
5.7A
Version 2.61725 Dec 2006
CoolSET™-F2
Electrical Characteristics
ParameterSymbolLimit ValuesUnitRemarks
min.max.
Avalanche energy,
repetitive t
max. T
1)
Repetitive avalanche causes additional power losses that can be calculated as PAV=EAR* f
limited by
AR
=150°C
j
1)
ICE2A0565E
ICE2A165E
ICE2A265E
ICE2A365E
ICE2B0565E
ICE2B165E
ICE2B265E
ICE2B365E
ICE2A0565GE
ICE2A0565ZE
ICE2A180ZE
ICE2A280ZE
ICE2A765IE
ICE2B765IE
ICE2A765P2E
ICE2B765P2E
ICE2A380P2E
AR1
AR2
AR3
AR4
AR5
AR6
AR7
AR8
AR9
AR10
AR11
AR12
AR13
AR14
AR15
AR16
AR17
-0.01mJ
-0.07mJ
-0.40mJ
-0.50mJ
-0.01mJ
-0.07mJ
-0.40mJ
-0.50mJ
-0.01mJ
-0.01mJ
-0.07mJ
-0.40mJ
-0.50mJ
-0.50mJ
-0.50mJ
-0.50mJ
-0.06mJ
Version 2.61825 Dec 2006
CoolSET™-F2
Electrical Characteristics
ParameterSymbolLimit ValuesUnitRemarks
min.max.
Avalanche current,
repetitive tAR limited by
max. T
V
=150°C
j
Supply VoltageV
CC
FB VoltageV
SoftS VoltageV
I
Sense
Junction TemperatureT
Storage TemperatureT
Thermal Resistance
Junction-Ambient
ESD Robustness
1)
Equivalent to discharging a 100pF capacitor through a 1.5 kΩ series resistor
1)
ICE2A0565I
ICE2A165I
ICE2A265I
ICE2A365I
ICE2B0565I
ICE2B165I
ICE2B265I
ICE2B365I
ICE2A0565G I
ICE2A0565Z I
ICE2A180ZI
ICE2A280ZI
ICE2A765II
ICE2B765II
ICE2A765P2 I
ICE2B765P2 I
ICE2A380P2 I
AR1
AR2
AR3
AR4
AR5
AR6
AR7
AR8
AR9
AR10
AR11
AR12
AR13
AR14
AR15
AR16
AR17
CC
FB
SoftS
I
Sense
j
S
R
thJA1
R
thJA2
R
thJA3
V
ESD
-0.5A
-1A
-2A
-3A
-0.5A
-1A
-2A
-3A
-0.5A
-0.5A
-1A
-2A
-7A
-7A
-7A
-7A
-2.4A
-0.322V
-0.36.5V
-0.36.5V
-0.33V
-40150°CController & CoolMOS™
-50150°C
-90K/WPG-DIP-8-6
-96K/WPG-DIP-7-1
-110K/WP-DSO-16/12
-22)kVHuman Body Model
2)
1kV at pin drain of ICE2x0565, ICE2A0565Z and ICE2A0565G
Version 2.61925 Dec 2006
CoolSET™-F2
Electrical Characteristics
4.2Thermal Impedance (ICE2X765I and ICE2X765P2)
ParameterSymbolLimit ValuesUnitRemarks
min.max.
Thermal Resistance
Junction-Ambient
ICE2A765I
ICE2B765I
R
thJA4
-74K/WFree standing with no
heat-sink
ICE2A765P2
ICE2B765P2
ICE2A380P2 R
Junction-CaseICE2A765I
R
thJA5
thJC1
-82K/W
-2.5K/W
ICE2B765I
ICE2A765P2
ICE2B765P2
ICE2A380P2 R
thJC2
-2.86K/W
4.3Operating Range
Note:Within the operating range the IC operates as described in the functional description.
ParameterSymbolLimit ValuesUnitRemarks
min.max.
V
Supply VoltageV
CC
Junction Temperature of
Controller
T
CC
JCon
V
CCoff
21V
-25130°CLimited due to thermal shut down
of controller
Junction Temperature of
T
JCoolMOS
-25150°C
CoolMOS™
Version 2.62025 Dec 2006
CoolSET™-F2
Electrical Characteristics
4.4Characteristics
Note:The electrical characteristics involve the spread of values given within the specified supply voltage and
junction temperature range T
are related to 25°C. If not otherwise stated, a supply voltage of V
4.4.1Supply Section
ParameterSymbolLimit ValuesUnitTest Condition
from – 25 °C to 125 °C.Typical values represent the median values, which
1) Shear and punch direction no burrs this surfac
Back side, heatsink contour
All metal surfaces tin plated, except area of cu
PG-TO220-6-47
Isodrain Package
±0.3
±0.3
13
15.6
0...0.15
1.274 x
9.5
7.5
6.6
7.62
±0.2
±0.2
A
±0.2
2.8
±0.3
8.6
6 x 0.6
4.4
+0.1
1.3
-0.02
B
-0.15
3.7
0.25AMB
0.05
1)
±0.2
9.2
0.5
±0.1
2.4
±0.1
5.3
±0.3
8.4
±0.3
1) Shear and punch direction no burrs this surfac
Back side, heatsink contour
All metal surfaces tin plated, except area of cu
Figure 61 PG-TO220-6-47 (Isodrain Package)
Dimensions in mm
Version 2.63425 Dec 2006
PG-DSO-16/12
(Plastic Dual Small
Outline Package)
CoolSET™-F2
Outline Dimension
Figure 62 PG-DSO-16/12 (Plastic Dual Small Outline Package)
Dimensions in mm
Version 2.63525 Dec 2006
Total Quality Management
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Bedeutung. Wir wollen allen Ihren
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