INFINEON HYS72T32000GR, HYS72T64001GR, HYS72T64020GR User Manual
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HYS72T32000GR (2 56 MByte)
HYS72T64001GR (5 12 MByte)
HYS72T64020GR (5 12 MByte)
Data Sheet, V0.22,Feb. 2004
DDR2 Registered DIMM Modules
Memory Products
Never stop thinking.
HYS72T32000GR, HYS72T64001GR
HYS72T64020GR
Preliminary Datasheet Rev. 0.22 (2.04)
Low Profile 240-pin Registered DDR2 SDRAM Modules Datasheet
256 MByte & 512 MByte Modules
PC2-3200R /-4200R /-5300R
• 240-pin Registered 8-Byte ECC Dual-In-Line
DDR2 SDRAM Module for PC, Workstation
and Server main memory applications
• One rank 32Mb x 72, 64Mb x 72 and
two ranks 64Mb × 72 organizations
• JEDEC standard Double Data Rate 2
Synchronous DRAMs (DDR2 SDRAMs) with
+1.8V (± 0.1 V) power supply
• Modules built with 256 Mb DDR2 SDRAMs in
60-ball FBGA chipsize packages
• Programmable CAS
Burst Length (4 & 8) and Burst Type.
• Auto Refresh and Self Refresh
• All inputs and outputs SSTL_1.8 compatible
• Performance:
Speed Grade Indicator -5 -3.7 -3 Unit
Component Speed Grade on Module DDR2-400 DDR2-533 DDR2-667
Module Speed Grade PC2-3200 PC2-4200 PC2-5300
Max. Clock Frequency @ CL = 3 200 200 200 MHz
Max. Clock Frequency@ CL = 4 & 5 200 266 333 MHz
1.0 Description
The INFINEON HYS72T32000GR, HYS72T64020GR and HYS72T64001 are low profile
Registered DIMM modules with 30,00 mm height based on DDR2 technology. DIMMs are available
in 32M x 72 (256 MByte), 2 x 32M x 72 (512 MByte) and 64M x 72 (512 MByte) organisation and
density, intended for mounting into 240 pin connector sockets.
The memory array is designed with 256Mbit Double Data Rate (DDR2) Synchronous DRAMs for
ECC applications. All control and address signals are re-driven on the DIMM using register devices
and a PLL for the clock distribution. This reduces capacitive loading to the system bus, but adds one
cycle to the SDRAM timing. Decoupling capacitors are mounted on the PCB board, which pr ovide
a proper voltage supply impedance over the whole frequency range of operations as number and
values are accordant to the JEDEC specification. The DIMMs feature serial presence detect based
on a serial E
configuration data and the second 128 bytes are available to the customer.
2
PROM device using the 2-pin I2C protocol. The first 128 bytes are programmed with
Latencies (3, 4 & 5),
• Re-drive for all input signals using register
and PLL devices.
• OCD (Off-Chip Driver Impedance
Adjustment) and ODT (On-Die Termination)
• Serial Presence Detect with E
• Low Profile Modules form factor:
133.35 mm x 30,00 mm (MO-237)
• Based on JEDEC standard reference card
designs Raw Card “A”, “B” and “C”.
2
PROM
INFINEON Technologies
Rainer.Weidlich@Infineon.com 22.04
HYS72Txx0xxGR
Registered DDR2 SDRAM-Modules
1.1 Ordering Information
Type & Partnumber Compliance Code Description SDRAM
PC2-3200 (DDR2-400):
HYS72T32000GR-5-A PC2-3200R-33310-A one rank 256 MB Reg. DIMM 256 Mbit (x8)
HYS72T64020GR-5-A PC2-3200R-33310-B two ranks 512 MB Reg. DIMM 256 Mbit (x8)
HYS72T64001GR-5-A PC2-3200R-33310-C one ranks 512 MB Reg.DIMM 256 Mbit (x4)
PC2-4200 (DDR2-533):
HYS72T32000GR-3.7-A PC2-4200R-44410-A one rank 256 MB Reg. DIMM 256 Mbit (x8)
HYS72T64020GR-3.7-A PC2-4200R-44410-B two ranks 512 MB Reg. DIMM 256 Mbit (x8)
HYS72T64001GR-3.7-A PC2-4200R-44410-C one ranks 512 MB Reg.DIMM 256 Mbit (x4)
PC2-5300 (DDR2-667):
HYS72T32000GR-3-A PC2-5300R-44410-A one rank 256 MB Reg. DIMM 256 Mbit (x8)
HYS72T64020GR-3-A PC2-5300R-44410-B two ranks 512 MB Reg. DIMM 256 Mbit (x8)
HYS72T64001GR-3-A PC2-5300R-44410-C one ranks 512 MB Reg.DIMM 256 Mbit (x4)
Notes:
1. All part numbers end with a place code, designating the silicon die revision. Example: HYS72T32000GR-5-A, indicating
Rev. A dies are used for DDR2 SDRAM components. For all INFINEON DDR2 module and component nomenclature see
section 8 of this datasheet.
2. The Compliance Code is printed on the module label and describes the speed grade, f.e. “PC2-4200R-44410-C”, where
4200R means Registered DIMM modules with 4.26 GB/sec Module Bandwidth and “44410” means CAS latency = 4, trcd
latency = 4 and trp latency = 4 using the latest JEDEC SPD Revision 1.0 and produced on the Raw Card “C”.
Technology
1.2 Address Format
Part Number DIMM
Density
HYS72T32000GR 256 MB 32Mb × 72 1 (256Mb)
HYS72T64020GR 512 MB 2 x 32Mb × 72 2 (256Mb)
HYS72T64001GR- 512 MB 64Mb x 72 1 (256Mb)
Organization Memory
Ranks
DDR2-
SDRAMs
32Mb × 8
32Mb × 8
64Mb × 4
# of
SDRAMs
# of row/bank/
column bits
9 13/2/10
18 13/2/10
18 13/2/11
INFINEON Technologies 3 2.04
1.3 Components on Modules and RawCard
HYS72Txx0xxGR
Registered DDR2 SDRAM-Modules
DIMM
Density
DRAM components
reference datasheet
PLL Register Raw Card
256 MB HYB18T256800AC 1:10, 1.8V, CU877 1:1 25-bit 1.8V SSTU32864 A
512 MB HYB18T256800AC 1:10, 1.8V, CU877 1:2 14-bit 1.8V SSTU32864 B
512 MB HYB18T256400AC 1:10, 1.8V, CU877 1:2 14-bit 1.8V SSTU32864 C
For a detailed description of all functionalities of the DRAM components on these modules see the referenced component
datasheet
1.4 Pin Definition a nd Function
Pin Name Description Pin Name Description
A[12:0] Row Address Inputs CB[7:0] DIMM ECC Check Bits
A11, A[9:0] Column Address Inputs
A10/AP Column Address Input for Auto-
Precharge
BA[1:0] SDRAM Bank Selects DQS
CK0 Clock input
CK0
RAS
CAS
WE
CS
[1:0] Chip Selects
CKE[1:0] Clock Enable
(positive line of differential pair)
Clock input
(negative line of differential pair)
Row Address Strobe SA[2:0] slave address select
Column Address Strobe V
Read/Write Input V
3)
3)
ODT[1:0] Active termina ti on cont rol lin es
DQ[63:0] Data Input/Output NC No connection
1) Active termination only applies to DQ, DQS, DQS and DM signals
2) When low, all register outputs will be driven low and the PLL clocks to the DRAM and registers will be set to low levels (the
PLL will remain synchronized with the input clock
3) CS1, ODT1 and CKE1 are used on dual rank modules only
4) Column address A11 is used on modules based on x4 organised 256Mb DDR2 components only.
4)
DQS[8:0] SDRAM low data strobes
DM[8:0] /
DQS[17:9]
SDRAM low data mask/
high data strobes
[17:0] SDRAM differential data strobes
SCL Serial bus clock
SDA Serial bus data line
DD
REF
V
SS
V
DDSPD
1) 3)
RESET Register and PLL control pin
Power (+ 1.8 V)
I/O reference supply
Ground
EEPROM power supply
2)
INFINEON Technologies 4 2.04
HYS72Txx0xxGR
Registered DDR2 SDRAM-Modules
1.5 Pin Configurat ion
Symbol PIN# Symbol PIN# Symbol PIN# Symbol
PIN#
1 VREF 121 VSS 61 A4 181 VDDQ
2 VSS 122 DQ4 62 VDDQ 182 A3
3 DQ0 123 DQ5 63 A2 183 A1
4 DQ1 124 VSS 64 VDD 184 VDD
5 VSS 125 DM0, DQS9
6DQS0
7 DQS0 127 VSS 66 VSS 186 CK0
8 VSS 128 DQ6 67 VDD 187 VDD
9 DQ2 129 DQ7 68 NC 188 A0
10 DQ3 130 VSS 69 VDD 189 VDD
11 VSS 131 DQ12 70 A10/AP 190 BA1
12 DQ8 132 DQ13 71 BA0 191 VDDQ
13 DQ9 133 VSS 72 VDDQ 192 RAS
14 VSS 134 DM1, DQS10 73 WE 193 CS0
15 DQS1 135 DQS10 74 CAS 194 VDDQ
16 DQS1 136 VSS 75 VDDQ 195 ODT0
17 VSS 137 NC 76 CS1
18 RESET
19 NC 139 VSS
20 VSS 140 DQ14 79 VSS 199 DQ36
21 DQ10 141 DQ15 80 DQ32 200 DQ37
22 DQ11 142 VSS 81 DQ33 201 VSS
23 VSS 143 DQ20 82 VSS 202 DM4, DQS13
24 DQ16 144 DQ21 83 DQS4
25 DQ17 145 VSS 84 DQS4 204 VSS
26 VSS 146 DM2, DQS11 85 VSS 205 DQ38
27 DQS2
28 DQS2 148 VSS 87 DQ35 207 VSS
29 VSS 149 DQ22 88 VSS 208 DQ44
30 DQ18 150 DQ23 89 DQ40 209 DQ45
31 DQ19 151 VSS 90 DQ41 210 VSS
32 VSS 152 DQ28 91 VSS 211 DM5, DQS14
33 DQ24 153 DQ29 92 DQS5
34 DQ25 154 VSS 93 DQS5 213 VSS
35 VSS 155 DM3, DQS12 94 VSS 214 DQ46
36 DQS3
37 DQS3 157 VSS 96 DQ43 216 VSS
38 VSS 158 DQ30 97 VSS 217 DQ52
39 DQ26 159 DQ31 98 DQ48 218 DQ53
40 DQ27 160 VSS 99 DQ49 219 VSS
126 DQS9 65 VSS 185 CK0
138 NC 77 ODT1 197 VDD
78 VDDQ 198 VSS
147 DQS11 86 DQ34 206 DQ39
156 DQS12 95 DQ42 215 DQ47
KEY KEY
196 NC
203 DQS13
212 DQS14
INFINEON Technologies 5 2.04
HYS72Txx0xxGR
Registered DDR2 SDRAM-Modules
Pin Configuration (cont’d)
Symbol PIN# Symbol PIN# Symbol PIN# Symbol
PIN#
41 VSS 161 CB4 100 VSS 220 NC
42 CB0 162 CB5 101 SA2 221 NC
43 CB1 163 VSS 102 NC 222 VSS
44 VSS 164 DM8, DQS17 103 VSS 223 DM6, DQS15
45 DQS8
46 DQS8 166 VSS 105 DQS6 225 VSS
47 VSS 167 CB6 106 VSS 226 DQ54
48 CB2 168 CB7 107 DQ50 227 DQ55
49 CB3 169 VSS 108 DQ51 228 VSS
50 VSS 170 VDDQ 109 VSS 229 DQ60
51 VDDQ 171 NC, CKE1 110 DQ56 230 DQ61
52 CKE0 172 VDD 111 DQ57 231 VSS
53 VDD 173 NC 112 VSS 232 DM7, DQS16
54 NC 174 NC 113 DQS7
55 NC 175 VDDQ 114 DQS7 234 VSS
56 VDDQ 176 A12 115 VSS 235 DQ62
57 A11 177 A9 116 DQ58 236 DQ63
58 A7 178 VDD 117 DQ59 237 VSS
59 VDD 179 A8 118 VSS 238 VDDSPD
60 A5 180 A6 119 SDA 239 SA0
165 DQS17 104 DQS6 224 DQS15
233 DQS16
120 SCL 240 SA1
1.6 Pin Locations
Front
pin 1
pin 121
64
184
Backside
65
185
120
240
240 pin Modules (MO-237)
INFINEON Technologies 6 2.04
Registered DDR2 SDRAM-Modules
1.7 Registered DIMM Input/Output Functional Description
Symbol
CK0, CK
CKE[1:0]
CS[1:0]
ODT[1:0]
RAS, CAS,
DM[8:0]
BA[1:0]
A[12:0]
DQ[63:0],
CB[7:0]
DQS[17:0],
DQS
SA[2:0]
SDA
SCL
RESET
V
DD, VSS
V
V
DDSPD
Note: CS1, ODT1 and CKE1 are used on dual rank modules only.
Type Polarity Function
The system clock inputs. All address and command lines are sampled on the cross point of
0
Input Cross point
Active High
Input
Active Low
Input
Active High On-Die Termination control signals
Input
Active Low
WE
Input
Active High Masks write data when high, issued concurrently with input data.
Input
Input
Input
I/O - Data and Check Bit Input /Output pins.
I/O
[17:0]
REF
Cross point
Input
I/O -
Input
Input
Supply - Power and ground for the DDR SDRAM input buffers and core logic.
Supply - Reference voltage for the SSTL-18 inputs.
Supply -
the rising edge of CK and the falling edge of CK. An on-board DLL circuit is driven from the
clock inputs and output timing for read operations is synchronized to the input clock.
CKE high activates and CKE low deactivates internal clock signals and device input buffers
and output drivers of the SDRAMs. Taking CKE low provides Precharge Power-Down and
Self-Refresh operation (all banks idle), or Active Power-Down (row Active in any bank).
Enables the associated SDRAM command decoder when low and disables decoder when
high. When decoder is disabled, new commands are ignored and previous operations continue. The input signals also disable all outputs (except CKE and ODT) of the register(s) on
the DIMM when both inputs are high. When both CS[1:0] are high, all register outputs (except
CK, ODT and Chip select) remain in the previous state.
When sampled at the positive edge of the clock, RAS, CAS and WE define the operation to
be executed by the SDRAM.
- Selects which internal SDRAM memory bank is activated
During Bank Activate command cycle, Address defines the row address. During a Read or
Write command cycle, Address defines the column address. In addition to the column
address, A10(=AP) is used to invoke Auto-Precharge operation at the end of the burst read
or write cycle. If AP is high, Auto Precharge is selected and BA[1:0] defines the bank to be
precharged. If AP is low, Auto-Precharge is disabled. During a Precharge command cycle,
AP is used in conjunction with BA[1:0] to control which bank(s) to precharge. If AP is high, all
banks will be precharged regardless of the state of BA[1:0]. If AP is low, BA[1:0] are used to
define which bank to precharge.
The data strobes, associated with one data byte, source with data transfer. In Write mode,
the data strobe is sourced by the controller and is centered in the data window. In Read
mode the data strobe is sources by the DDR2 SDRAM and is sent at the leading edge of the
data window. DQS signals are complements, and timing is relative to the crosspoint of
respective DQS and DQS. If the module is to be operated in single ended strobe mode, all
DQS signals must be tied on the system board to VSS and DDR2 SDRAM mode registers
programmed appropriately.
These signals are tied at the system planar to either VSS or VDDSPD to configure the serial
SPD EEPROM address range
This bidirectional pin is used to transfer data into and out of the SPD EEPROM. A resistor
maybe connected from the SDA bus line to VDDSPD on the system planar to act as a pullup.
This signal is used to clock data into the SPD EEPROM. A resistor maybe connected from
the SCL bus line to VDDSPD on the system planar to act as a pull-up.
The RESET
-
When low, all register outputs will be driven low and the PLL clocks to the DRAMs and the
register(s) will be set to low level. The PLL will remain synchronized with the input clock.
Serial EEPROM positive power supply, wired to a separated power pin at the connector
which supports from 1.7 Volt to 3.6 Volt.
pin is connected to the RST pin on the register and to the OE pin on the PLL.
HYS72Txx0xxGR
INFINEON Technologies 7 2.04
HYS72Txx0xxGR
Registered DDR2 SDRAM-Modules
2.0 Block Diagrams (cont’d)
2.1 One Rank 32M x 72 (256 MByte) DDR2 SDRAM DIMM Module (x8 components)
HYS72T32000GR on Raw Card A
RS0
DQS0
DQS0
CS0 *
BA0-BA1
A0 -A12
RAS
CAS
WE
CKE0
ODT0
RESET
PCK7
PCK 7
DM0/DQS9
DQS9
DQS1
DQS1
DM1/DQS10
DQS10
DQS2
DQS0
DM2/DQS11
DQS11
DQS3
DQS3
DM3/DQS12
DQS12
DQS8
DQS8
DM8/DQS17
DQS17
CB0
CB1
CB2
CB3
CB4
CB5
CB6
CB7
RST
DQ0
DQ1
DQ2
DQ3
DQ4
DQ5
DQ6
DQ7
DQ8
DQ9
DQ10
DQ11
DQ12
DQ13
DQ14
DQ15
DQ16
DQ17
DQ18
DQ19
DQ20
DQ21
DQ22
DQ23
DQ24
DQ25
DQ26
DQ27
DQ28
DQ29
DQ30
DQ31
1:1
R
E
G
I
S
T
E
R
DM/
NU/
CS DQS
RDQS
RDQS
I/O 0
I/O 1
D0
I/O 2
I/O 3
I/O 4
I/O 5
I/O 6
I/O 7
DM/
NU/
CS DQS
RDQS
RDQS
I/O 0
I/O 1
D1
I/O 2
I/O 3
I/O 4
I/O 5
I/O 6
I/O 7
DM/
NU/
DQS
CS
RDQS
RDQS
I/O 0
I/O 1
D2
I/O 2
I/O 3
I/O 4
I/O 5
I/O 6
I/O 7
NU/
DM/
CS DQS
RDQS
RDQS
I/O 0
I/O 1
D3
I/O 2
I/O 3
I/O 4
I/O 5
I/O 6
I/O 7
DM/
NU/
CS DQS DQS
RDQS
RDQS
I/O 0
I/O 1
D8
I/O 2
I/O 3
I/O 4
I/O 5
I/O 6
I/O 7
0 -> CS : SDRAMs D0-D8
RS
RBA0-RBA1
RA0 -RA12-> A0 -A 12: SDRA Ms D0-D 8
RRA S -> RAS : SDR AMs D0- D8
RCAS -> C A S: SD RAMs D0-D8
RW E -> WE : SDRAMs D0-D8
RCKE0 -> CKE : SDRA D0-D8
RODT0 - > ODT 0: SDRAMs D0-D8
A0-BA1: SDRAMs D0-D8
-> B
*) CS0 connects to DCS and VDD connects to CSR on the Reg isters
DQS4
DQS4
DM4/DQS13
DQS
DQS
DQS
DQS
DQS13
DQS5
DQS5
DM5/DQS14
DQS14
DQS6
DQS6
DM6/DQS15
DQS15
DQS7
DQS7
DM7/DQS16
DQS16
DQ32
DQ33
DQ34
DQ35
DQ36
DQ37
DQ38
DQ39
DQ40
DQ41
DQ42
DQ43
DQ44
DQ45
DQ46
DQ47
DQ48
DQ49
DQ50
DQ51
DQ52
DQ53
DQ54
DQ55
DQ56
DQ57
DQ58
DQ59
DQ60
DQ61
DQ62
DQ63
Serial PD
SCL
A0
WP
A1 A2
SA0 SA1
SA2
CK0
CK 0
RESET
DM/
NU/
CS DQS DQS
RDQS
RDQS
I/O 0
I/O 1
D4
I/O 2
I/O 3
I/O 4
I/O 5
I/O 6
I/O 7
DM/
NU/
RDQS
I/O 0
I/O 1
I/O 2
I/O 3
I/O 4
I/O 5
I/O 6
I/O 7
NU/
RDQS
I/O 0
I/O 1
I/O 2
I/O 3
I/O 4
I/O 5
I/O 6
I/O 7
NU/
RDQS
I/O 0
I/O 1
I/O 2
I/O 3
I/O 4
I/O 5
I/O 6
I/O 7
SDA
PCK0-PCK6,PCK 8,PCK9
P
PCK0-PCK6,
L
L
PCK7
OE
PCK7
Notes:
1. DQ-to-I/O wiring may be changed within a byte
2. Unless otherwise noted, resistor values are 22 Ohms
CS DQS
RDQS
D5
DM/
DQS
CS
RDQS
D6
DM/
CS DQS
RDQS
D7
V
VREF
-> CK : Register
> CK : Register
DQS
DQS
DQS
DDSPD
V
V
DD,
DDQ
V
SS
PCK8,PCK9
CK : SDRAMs D0-D8
CK : SDRAMs D0-D8
Serial PD
D0 - D8
D0 - D8
D0 - D8
INFINEON Technologies 8 2.04
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