INFINEON HYS72D32300GBR–5–C, HYS72D64300GBR–5–C, HYS72D64320GBR–5–C, HYS72D32300GBR–6–C, HYS72D64300GBR–6–C User Manual

查询HYS72D128320GBR-6-C供应商

Data Sheet, Rev. 1.0, Mar. 2004

HYS72D32300GBR–[5/6]–C
HYS72D64300GBR–[5/6]–C
HYS72D64320GBR–[5/6]–C
HYS72D128320GBR–6–C

184-Pin Registered Double Data Rate SDRAM Module

Reg DIMM
DDR SDRAM

Memory Products

Never stop thinking.

Edition 2004-03
Published by Infineon Technologies AG,

St.-Martin-Strasse 53,
81669 München, Germany

© Infineon Technologies AG 2004.

All Rights Reserved.

Attention please!

The information herein is given to describe certain components and shall not be considered as a guarantee of
characteristics.

Terms of delivery and rights to technical change reserved.
We hereby disclaim any and all warranties, including but not limited to warranties of non-infringement, regarding

circuits, descriptions and charts stated herein.

Information

For further information on technology, delivery terms and conditions and prices please contact your nearest
Infineon Technologies Office (www.infineon.com).

Warnings

Due to technical requirements components may contain dangerous substances. For information on the types in
question please contact your nearest Infineon Technologies Office.

Infineon Technologies Components may only be used in life-support devices or systems with the express written
approval of Infineon Technologies, if a failure of such components can reasonably be expected to cause the failure
of that life-support device or system, or to affect the safety or effectiveness of that device or system. Life support
devices or systems are intended to be implanted in the human body, or to support and/or maintain and sustain
and/or protect human life. If they fail, it is reasonable to assume that the health of the user or other persons may
be endangered.

Data Sheet, Rev. 1.0, Mar. 2004

HYS72D32300GBR–[5/6]–C
HYS72D64300GBR–[5/6]–C
HYS72D64320GBR–[5/6]–C
HYS72D128320GBR–6–C

184-Pin Registered Double Data Rate SDRAM Module

Reg DIMM
DDR SDRAM

Memory Products

Never stop thinking.

HYS72D32300GBR–[5/6]–C HYS72D64300GBR–[5/6]–C HYS72D64320GBR–[5/6]–C HYS72D128320GBR–
6–CHYS72D64300GBR–[5/6]–C HYS72D64320GBR–[5/6]–C

Revision History: Rev. 1.0 2004-03

Previous Version: Rev. 0.5
Page Subjects (major changes since last revision)

20,21

I

values updated

dd

8,22 editorial changes
24,27 Changed SPD Code Byte 99 - 127 to FF

We Listen to Your Comments

Any information within this document that you feel is wrong, unclear or missing at all?
Your feedback will help us to continuously improve the quality of this document.
Please send your proposal (including a reference to this document) to:

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Template: mp_a4_v2.2_2003-10-07.fm

HYS72D[128/64/32][300/320]GBR–[5/6]–C

Registered Double Data Rate SDRAM

Table of Contents

1 Overview . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6

1.1 Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6

1.2 Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6

2 Pin Configuration . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8

3 Electrical Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17

3.1 Operating Conditions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17

4 Current Specification and Conditions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19

4.1 AC Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22

5 SPD Contents . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24

6 Package Outlines . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 30

7 Application Note . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 34

Data Sheet 5 Rev. 1.0, 2004-03

HYS72D[128/64/32][300/320]GBR–[5/6]–C

Registered Double Data Rate SDRAM

Overview

1Overview

1.1 Features

• 184-Pin Registered 8-Byte Dual-In-Line
DDR SDRAM Module for “1U” PC, Workstation and Server main memory applications

• One rank 32 M × 72 and 64M × 72 and two ranks 64 M ×72 and 128 M ×72 organization

• JEDEC standard Double Data Rate Synchronous DRAMs (DDR SDRAM) with a single + 2.5 V (± 0.2 V) power
supply and + 2.6 V (± 0.1 V) power supply for DDR400

• Built with 256-Mbit DDR SDRAMs in P-TFBGA-60-1 packages

• Programmable CAS

• Auto Refresh (CBR) and Self Refresh

• All inputs and outputs SSTL_2 compatible

• Re-drive for all input signals using register and PLL devices.

• Serial Presence Detect with E

• Low Profile Modules form factor:

133.35 mm × 28.58 mm × 4.00 mm / 2.64 mm and for 1GB 133.35 mm × 30.48 mm (1.2”)× 4.00 mm

• JEDEC standard reference layout for one rank 256 MB, 512 MB and two ranks 512 MB, 1 GB:
PC2700 and PC3200 Registered DIMM Raw Cards A,B,C,D

• Gold plated contacts

Table 1 Performance

Latency, Burst Length, and Wrap Sequence (Sequential & Interleave)

2

PROM

Part Number Speed Code –5 –6Unit
Speed Grade Component DDR400B DDR333B —

Module PC3200–3033 PC2700–2533 —

max. Clock Frequency @CL3

@CL2.5
@CL2

f

CK3

f

CK2.5

f

CK2

200 166 MHz
166 166 MHz
133 133 MHz

1.2 Description

The HYS72D[128/64/32][300/320]GBR–[5/6]–C and HYS72D64320GBR–5–C are low profile versions of the
standard Registered DIMM modules suitable for 1U Server Applications. The Low Profile DIMM versions are
available as 32 M ×72 (256 MB), 64 M ×72 (512 MB) and 128 M ×72 (1 GB)

The memory array is designed with Double Data Rate Synchronous DRAMs for ECC applications. All control and
address signals are re-driven on the DIMM using register devices and a PLL for the clock distribution. This reduces
capacitive loading to the system bus, but adds one cycle to the SDRAM timing. A variety of decoupling capacitors
are mounted on the PC board. The DIMMs feature serial presence detect based on a serial E
the 2-pin I
available to the customer.

2

C protocol. The first 128 bytes are programmed with configuration data and the second 128 bytes are

2

PROM device using

Data Sheet 6 Rev. 1.0, 2004-03
07302003-2MI6-FOP1

HYS72D[128/64/32][300/320]GBR–[5/6]–C

Registered Double Data Rate SDRAM

Table 2 Ordering Information
Type Compliance Code Description SDRAM

PC3200 (CL = 3.0)

HYS72D32300GBR–5–C PC3200R–30330–A0 1 Rank 256 MB Registered DIMM ECC 256 Mbit (×8)
HYS72D64300GBR–5–C PC3200R–30330–C0 1 Rank 512 MB Registered DIMM ECC 256 Mbit (×4)
HYS72D64320GBR–5–C PC3200R–30330–B0 2 Ranks 512 MB Registered DIMM ECC 256 Mbit (×8)

PC2700 (CL = 2.5,

HYS72D32300GBR–6–C PC2700R–25330–A0 1 Rank 256 MB Registered DIMM ECC 256 Mbit (×8)
HYS72D64300GBR–6–C PC2700R–25330–C0 1 Rank 512 MB Registered DIMM ECC 256 Mbit (×4)
HYS72D64320GBR–6–C PC2700R–25330–B0 2 Ranks 512 MB Registered DIMM ECC 256 Mbit (×8)
HYS72D128320GBR–6–C PC2700R–25330–D0 2 Ranks 1 GB Registered DIMM ECC 256 Mbit (×4)

t

= t

RP

= 3 at tCK = 6ns)

RCD

Overview

Technology

Data Sheet 7 Rev. 1.0, 2004-03
07302003-2MI6-FOP1

HYS72D[128/64/32][300/320]GBR–[5/6]–C

Registered Double Data Rate SDRAM

2 Pin Configuration

The pin configuration of the Registered DDR SDRAM
DIMM is listed by function in Table 3 (184 pins). The
abbreviations used in columns Pin and Buffer Type are
explained in Table 4 and Table 5 respectively. The pin
numbering is depicted in Figure 1.

Table 3 Pin Configuration of RDIMM
Pin# Name Pin

Type

Clock Signals

137 CK0 I SSTL Clock Signal
138 CK0
21 CKE0 I SSTL Clock Enable Rank 0
111 CKE1 I SSTL Clock Enable Rank 1

NC NC SSTL Note:1-rank module

Control Signals

157 S0
158 S1

NC NC – Note: 1-rank module
154 RAS
65 CAS

63 WE
10 RESET

Address Signals

59 BA0 I SSTL Bank Address Bus
52 BA1 I SSTL
48 A0 I SSTL Address Bus 11:0
43 A1 I SSTL
41 A2 I SSTL
130 A3 I SSTL
37 A4 I SSTL
32 A5 I SSTL Address Bus 11:0

I SSTL Complement Clock

I SSTL Chip Select of Rank 0
I SSTL Chip Select of Rank 1

I SSTL Row Address Strobe
I SSTL Column Address

I SSTL Write Enable
ILV-

Buffer
Type

CMOS

Function

Note: 2-rank module

Note: 2-ranks module

Strobe

Register Reset

Forces registered
inputs low

Note: For detailed

description of the
Power Up and
Power
Management see
the Application
Note at the end of
data sheet

1:0

Pin Configuration

Table 3 Pin Configuration of RDIMM (cont’d)
Pin# Name Pin

Type

125 A6 I SSTL Address Bus 11:0
29 A7 I SSTL
122 A8 I SSTL
27 A9 I SSTL
141 A10 I SSTL

AP I SSTL

118 A11 I SSTL
115 A12 I SSTL Address Signal 12

NC NC – Note: 128 Mbit based

167 A13 I SSTL Address Signal 13

NC NC – Note: Module based on

Buffer
Type

Function

Note: Module based on

256 Mbit or larger
dies

module

Note:1 Gbit based

module

512 Mbit or
smaller dies

Data Sheet 8 Rev. 1.0, 2004-03

HYS72D[128/64/32][300/320]GBR–[5/6]–C

Registered Double Data Rate SDRAM

Table 3 Pin Configuration of RDIMM (cont’d)
Pin# Name Pin

Type

Data Signals

2 DQ0 I/O SSTL Data Bus 63:0
4 DQ1 I/O SSTL
6 DQ2 I/O SSTL
8 DQ3 I/O SSTL
94 DQ4 I/O SSTL
95 DQ5 I/O SSTL
98 DQ6 I/O SSTL
99 DQ7 I/O SSTL
12 DQ8 I/O SSTL
13 DQ9 I/O SSTL
19 DQ10 I/O SSTL
20 DQ11 I/O SSTL
105 DQ12 I/O SSTL
106 DQ13 I/O SSTL
109 DQ14 I/O SSTL
110 DQ15 I/O SSTL
23 DQ16 I/O SSTL
24 DQ17 I/O SSTL
28 DQ18 I/O SSTL
31 DQ19 I/O SSTL
114 DQ20 I/O SSTL
117 DQ21 I/O SSTL
121 DQ22 I/O SSTL
123 DQ23 I/O SSTL
33 DQ24 I/O SSTL
35 DQ25 I/O SSTL
39 DQ26 I/O SSTL
40 DQ27 I/O SSTL
126 DQ28 I/O SSTL
127 DQ29 I/O SSTL
131 DQ30 I/O SSTL
133 DQ31 I/O SSTL
53 DQ32 I/O SSTL
55 DQ33 I/O SSTL
57 DQ34 I/O SSTL
60 DQ35 I/O SSTL
146 DQ36 I/O SSTL
147 DQ37 I/O SSTL

Buffer
Type

Function

Pin Configuration

Table 3 Pin Configuration of RDIMM (cont’d)
Pin# Name Pin

Type

150 DQ38 I/O SSTL Data Bus 63:0
151 DQ39 I/O SSTL
61 DQ40 I/O SSTL
64 DQ41 I/O SSTL
68 DQ42 I/O SSTL
69 DQ43 I/O SSTL
153 DQ44 I/O SSTL
155 DQ45 I/O SSTL
161 DQ46 I/O SSTL
162 DQ47 I/O SSTL
72 DQ48 I/O SSTL
73 DQ49 I/O SSTL
79 DQ50 I/O SSTL
80 DQ51 I/O SSTL
165 DQ52 I/O SSTL
166 DQ53 I/O SSTL
170 DQ54 I/O SSTL
171 DQ55 I/O SSTL
83 DQ56 I/O SSTL
84 DQ57 I/O SSTL
87 DQ58 I/O SSTL
88 DQ59 I/O SSTL
174 DQ60 I/O SSTL
175 DQ61 I/O SSTL
178 DQ62 I/O SSTL
179 DQ63 I/O SSTL
44 CB0 I/O SSTL Check Bits 7:0
45 CB1 I/O SSTL
49 CB2 I/O SSTL
51 CB3 I/O SSTL
134 CB4 I/O SSTL
135 CB5 I/O SSTL
142 CB6 I/O SSTL
144 CB7 I/O SSTL
5 DQS0 I/O SSTL Data Strobes 8:0
14 DQS1 I/O SSTL
25 DQS2 I/O SSTL
36 DQS3 I/O SSTL
56 DQS4 I/O SSTL
67 DQS5 I/O SSTL

Buffer
Type

Function

Note: See block

diagram for
corresponding
DQ signals

Data Sheet 9 Rev. 1.0, 2004-03

HYS72D[128/64/32][300/320]GBR–[5/6]–C

Registered Double Data Rate SDRAM

Table 3 Pin Configuration of RDIMM (cont’d)
Pin# Name Pin

Type

78 DQS6 I/O SSTL Data Strobes 8:0
86 DQS7 I/O SSTL
47 DQS8 I/O SSTL
97 DM0 I SSTL Data Mask 0

DQS9 I/O SSTL Data Strobe 9

107 DM1 I SSTL Data Mask 1

DQS10 I/O SSTL Data Strobe 10

119 DM2 I SSTL Data Mask 2

DQS11 I/O SSTL Data Strobe 11

129 DM3 I SSTL Data Mask 3

DQS12 I/O SSTL Data Strobe 12

149 DM4 I SSTL Data Mask 4

DQS13 I/O SSTL Data Strobe 13

159 DM5 I SSTL Data Mask 5

DQS14 I/O SSTL Data Strobe 14

169 DM6 I SSTL Data Mask 6

DQS15 I/O SSTL Data Strobe 15

177 DM7 I SSTL Data Mask 7

DQS16 I/O SSTL Data Strobe 16

140 DM8 I SSTL Data Mask 8

DQS17 I/O SSTL Data Strobe 17

Buffer
Type

Function

Note:

×

8 based module

Note:

×

4 based module

Note:

×

8 based module

Note:

×

4 based module

Note:

×

8 based module

×

Note:

Note:

Note:

Note:

Note:

Note:

Note:

Note:

Note:

Note:

Note:

Note:

Note:

4 based module

×

8 based module

×

4 based module

×

8 based module

×

4 based module

×

8 based module

×

4 based module

×

8 based module

×

4 based module

×

8 based module

×

4 based module

×

8 based module

×

4 based module

Pin Configuration

Table 3 Pin Configuration of RDIMM (cont’d)
Pin# Name Pin

Type

EEPROM

92 SCL I CMOS Serial Bus Clock
91 SDA I/O OD Serial Bus Data
181 SA0 I CMOS Slave Address Select
182 SA1 I CMOS
183 SA2 I CMOS

Power Supplies

1
184

15,
22,
30,
54,
62,
77,
96,
104,
112,
128,
136,
143,
156,
164,
172,
180

7,
38,
46,
70,
85,
108,
120,
148,
168

V

REF

V

DDSPD

V

DDQ

V

DD

AI – I/O Reference Voltage
PWR – EEPROM Power

PWR – I/O Driver Power

PWR – Power Supply

Buffer
Type

Function

Bus 2:0

Supply

Supply

Data Sheet 10 Rev. 1.0, 2004-03

HYS72D[128/64/32][300/320]GBR–[5/6]–C

Registered Double Data Rate SDRAM

Table 3 Pin Configuration of RDIMM (cont’d)
Pin# Name Pin

Type

V

3,
11,
18,
26,
34,
42,
50,
58,
66,
74,
81,
89,
93,
100,
116,
124,
132,
139,
145,
152,
160,
176

Other Pins

82

9,
16,
17,
71,
75,
76,
90,
101,
102,
103,
113,
163,
173

SS

V

DDID

NC NC – Not connected

GND – Ground Plane

OODVDD Identification

Buffer
Type

Function

Note: Pin in tristate,

indicating V
and V
connected on
PCB

Pins not connected on
Infineon RDIMM’s

DDQ

DD

nets

Pin Configuration

Table 4 Abbreviations for Pin Type
Abbreviation Description

I Standard input-only pin. Digital levels.
O Output. Digital levels.
I/O I/O is a bidirectional input/output signal.
AI Input. Analog levels.
PWR Power
GND Ground
NU Not Usable (JEDEC Standard)
NC Not Connected (JEDEC Standard)

Table 5 Abbreviations for Buffer Type
Abbreviation Description

SSTL Serial Stub Terminalted Logic (SSTL2)
LV-CMOS Low Voltage CMOS

CMOS

OD Open Drain. The corresponding pin has 2

CMOS Levels

operational states, active low and tristate,
and allows multiple devices to share as a
wire-OR.

Data Sheet 11 Rev. 1.0, 2004-03

HYS72D[128/64/32][300/320]GBR–[5/6]–C

Registered Double Data Rate SDRAM

V

REF

DQS0

NC

DQ09

NC

CKE0

DQS2

A7

DQ24

A4

A2
CB01
CB02

DQ32
DQ34
DQ40

CAS
DQ43
DQ49

V

DDQ

V
V

V
V

DM00/DQS9

NC
DQ12
DQ14

NC
DQ21
DQ22

A6

DM3/DQS12

DQ31

CK0

A10/AP

V

DM4/DQS13

DQ44

S0
DQ46
DQ52

DM6/DQS15

NC

DM7/DQS16

SA0

SS

DD

SS

SS

SS

Pin 001

­Pin 005

­Pin 009

­Pin 013

­Pin 017

­Pin 021

­Pin 025

­Pin 029

­Pin 033

­Pin 037

-

-

Pin 041

-

Pin 045

-

Pin 049

-

Pin 053

-

Pin 057

-

Pin 061

-

Pin 065

-

Pin 069

-

Pin 073

-

Pin 077

-

Pin 081

-

Pin 085

-

Pin 089

-

Pin 093

-

Pin 097

-

Pin 101

-

Pin 105

-

Pin 109

-

Pin 113

-

Pin 117

-

Pin 121

-

Pin 125

-

Pin 129

-

Pin 133

-

Pin 137

-

Pin 141

-

Pin 145

-

Pin 149

-

Pin 153

-

Pin 157

-

Pin 161

-

Pin 165

-

Pin 169

-

Pin 173

-

Pin 177

-

Pin 181

V
V
V

V

DDQ

DQ10
DQ16

A9
DQ19
DQ25
DQ26

A1

DQS8

CB03

DQ33

BA0

WE

DQS5

NC

NC
DQ50
DQ56
DQ58

SDA
DQ05
DQ07

NC

DM1/DQS10

CKE1/NC

A12/NC

DM2/DQS11

DQ23
DQ29
DQ30

CB5

V

V

DDQ

DQ37
DQ39
DQ45

DM5/DQS14

NC

A13/NC

DQ55
DQ61
DQ63

SA2

SS

DD

SS

SS

Pin 003

­Pin 007

­Pin 011

­Pin 015

­Pin 019

­Pin 023

­Pin 027

­Pin 031

­Pin 035

­Pin 039

-

Pin 043

­Pin 047

­Pin 051

­Pin 055

­Pin 059

­Pin 063

­Pin 067

­Pin 071

­Pin 075

­Pin 079

­Pin 083

­Pin 087

­Pin 091

­Pin 095

­Pin 099

­Pin 103

­Pin 107

­Pin 111

­Pin 115

­Pin 119

­Pin 123

­Pin 127

­Pin 131

­Pin 135

­Pin 139

­Pin 143

­Pin 147

­Pin 151

­Pin 155

­Pin 159

­Pin 163

­Pin 167

­Pin 171

­Pin 175

­Pin 179

­Pin 183

-

Pin Configuration

Pin 002

-

Pin 004
Pin 008
Pin 012
Pin 016
Pin 020
Pin 024
Pin 028
Pin 032
Pin 036
Pin 040

Pin 044
Pin 048
Pin 052
Pin 056

FRONTSIDE

BACKSIDE

Pin 060
Pin 064
Pin 068
Pin 072
Pin 076
Pin 080
Pin 084
Pin 088
Pin 092
Pin 096
Pin 100
Pin 104
Pin 108
Pin 112
Pin 116
Pin 120
Pin 124
Pin 128
Pin 132
Pin 136
Pin 140
Pin 144
Pin 148
Pin 152
Pin 156
Pin 160
Pin 164
Pin 168
Pin 172
Pin 176
Pin 180
Pin 184

DQ01

­DQ03

­DQ08

­NC

­DQ11

­DQ17

­DQ18

­A5

­DQS3

­DQ27

-

-

CB00

-

A0

-

BA1

-

DQS4

-

DQ35

-

DQ41

-

DQ42

-

DQ48

-

NC

-

DQ51

-

DQ57

-

DQ59

-

SCL
V

-

DDQ

V

-

SS

V

-

DDQ

V

-

DD

V

-

DDQ

V

-

SS

V

-

DD

V

-

SS

V

-

DDQ

V

-

SS

V

-

DDQ

-

DM8/DQS17

-

CB07
V

-

DD

V

-

SS

V

-

DDQ

V

-

SS

V

-

DDQ

V

-

DD

V

-

DDQ

V

-

SS

V

-

DDQ

-

V

DDSPD

Pin 006
Pin 010
Pin 014
Pin 018
Pin 022
Pin 026
Pin 030
Pin 034
Pin 038

Pin 042
Pin 046
Pin 050
Pin 054
Pin 058
Pin 062
Pin 066
Pin 070
Pin 074
Pin 078
Pin 082
Pin 086
Pin 090
Pin 094
Pin 098
Pin 102
Pin 106
Pin 110
Pin 114
Pin 118
Pin 122
Pin 126
Pin 130
Pin 134
Pin 138
Pin 142
Pin 146
Pin 150
Pin 154
Pin 158
Pin 162
Pin 166
Pin 170
Pin 174
Pin 178
Pin 182

DQ00

-

DQ02

-

RESET

-

DQS1

-

V
V

-

-

V
V

­V

­V

-

V

­V

-

-

V

-

V
V

­V

-

-

V
V

-

-

V
DQS6

-

V

­DQS7

­NC

­DQ04

­DQ06

­NC

­DQ13

­DQ15

­DQ20

­A11

­A8

­DQ28

­A3

­DQ04

­CK0

­CB06

­DQ36

­DQ38

­RAS

­S1 /NC

­DQ47

­DQ53

­DQ54

­DQ60

­DQ62

­SA1

-

SS

DDQ

SS

DDQ

SS

DD

SS

DD

SS

DDQ

SS

DDQ

SS

DD

SS

DDID

MPPD0020

Figure 1 Pin Configuration 184 Pins, Reg

Table 6 Address Table
Density Organization Memory

Ranks

SDRAMs # of SDRAMs # of row/rank/

columns bits

Refresh Period Interval

256 MB 32 M ×72 1 32 M ×8 9 13 / 2 / 10 8K 64ms 7.8 µs
512 MB 64 M ×72 1 64 M ×4 18 13 / 2 / 11 8K 64ms 7.8 µs

Data Sheet 12 Rev. 1.0, 2004-03