INFINEON HYS64D32020GDL–5–C, HYS64D16000GDL–6–C, HYS64D32020GDL–6–C, HYS64D32020HDL–5–C, HYS64D16000HDL–6–C User Manual
...
Data Sheet, Rev. 1.0, Mar. 2004
HYS64D32020[H/G]DL–5–C
HYS64D[32020/16000][H/G]DL–6–C
200-Pin Small Outline Dual-In-Line Memory Modules
SO-DIMM
DDR SDRAM
Memory Products
Never stop thinking.
Edition 2004-03
Published by Infineon Technologies AG,
St.-Martin-Strasse 53,
81669 München, Germany
© Infineon Technologies AG 2004.
All Rights Reserved.
Attention please!
The information herein is given to describe certain components and shall not be considered as a guarantee of
characteristics.
Terms of delivery and rights to technical change reserved.
We hereby disclaim any and all warranties, including but not limited to warranties of non-infringement, regarding
circuits, descriptions and charts stated herein.
Information
For further information on technology, delivery terms and conditions and prices please contact your nearest
Infineon Technologies Office (www.infineon.com).
Warnings
Due to technical requirements components may contain dangerous substances. For information on the types in
question please contact your nearest Infineon Technologies Office.
Infineon Technologies Components may only be used in life-support devices or systems with the express written
approval of Infineon Technologies, if a failure of such components can reasonably be expected to cause the failure
of that life-support device or system, or to affect the safety or effectiveness of that device or system. Life support
devices or systems are intended to be implanted in the human body, or to support and/or maintain and sustain
and/or protect human life. If they fail, it is reasonable to assume that the health of the user or other persons may
be endangered.
Data Sheet, Rev. 1.0, Mar. 2004
HYS64D32020[H/G]DL–5–C
HYS64D[32020/16000][H/G]DL–6–C
200-Pin Small Outline Dual-In-Line Memory Modules
SO-DIMM
DDR SDRAM
Memory Products
Never stop thinking.
HYS64D32020[H/G]DL–5–C,HYS64D[32020/16000][H/G]DL–6–C
Revision History: Rev. 1.0 2004-03
Previous Version: Rev. 0.5 2003-11
Page Subjects (major changes since last revision)
6,7 Added DDR400
18 Updated
I
Currents and added DDR400 Idd Currents
dd
24 Updated SPD Code Bytes 99 - 127 to FF and added SPD Codes for DDR400
13,14 editorial changes
We Listen to Your Comments
Any information within this document that you feel is wrong, unclear or missing at all?
Your feedback will help us to continuously improve the quality of this document.
Please send your proposal (including a reference to this document) to:
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Template: mp_a4_v2.0_2003-06-06.fm
HYS64D[32020/16000][H/G]DL–[5/6]–C
Small Outline DDR SDRAM Modules
Table of Contents
1 Overview . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6
1.1 Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6
2 Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6
3 Pin Configuration . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8
4 Electrical Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15
4.1 Operating Conditions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15
4.2 Current Specification and Conditions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17
4.3 AC Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19
5 SPD Contents . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22
6 Package Outlines . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 28
Data Sheet 5 Rev. 1.0, 2004-03
200-Pin Small Outline Dual-In-Line Memory Modules
SO-DIMM
HYS64D[32020/16000][H/G]DL–6–C
HYS64D32020[H/G]DL–5–C
1Overview
1.1 Features
• Non-parity 200-Pin Small Outline Dual-In-Line Memory Modules
• One rank 16M ×64 and two ranks 32M ×64 organization
• JEDEC standard Double Data Rate Synchronous DRAMs (DDR SDRAM)
•Single +2.5V (± 0.2 V) power supply
• Built with 256 Mbit DDR SDRAMs organised as ×16 in P–TSOPII–66–1 packages
• Programmable CAS Latency, Burst Length, and Wrap Sequence (Sequential & Interleave)
• Auto Refresh (CBR) and Self Refresh
• All inputs and outputs SSTL_2 compatible
• Serial Presence Detect with E
• Jedec standard form factor: 67.60 mm × 31.75 mm × 2.4 / 3.80 mm
• Jedec standard reference layout Raw Cards A and C
• Gold plated contacts
Table 1 Performance
2
PROM
Part Number Speed Code –5 –6Unit
Speed Grade Component DDR400B DDR333B —
Module PC3200–3033 PC2700–2533 —
max. Clock Frequency @CL3
@CL2.5
@CL2
f
CK3
f
CK2.5
f
CK2
200 166 MHz
166 166 MHz
133 133 MHz
2 Description
The HYS64D32020[H/G]DL–5–C and HYS64D[32020/16000][H/G]DL–6–C are industry standard 200-Pin Small
Outline Dual-In-Line Memory Modules (SO-DIMMs) organized as 32M × 64 and 16M × 64. The memory array is
designed with Double Data Rate Synchronous DRAMs (DDR SDRAM). A variety of decoupling capacitors are
mounted on the PC board. The DIMMs feature serial presence detect based on a serial E
2
2-pin I
available to the customer.
C protocol. The first 128 bytes are programmed with configuration data and the second 128 bytes are
2
PROM device using the
Data Sheet 6 Rev. 1.0, 2004-03
HYS64D[32020/16000][H/G]DL–[5/6]–C
Small Outline DDR SDRAM Modules
Table 2 Ordering Information
Type Compliance Code Description SDRAM
PC3200 (CL=3.0)
HYS64D32020GDL–5–C PC3200S–3033–1–A1 two ranks 256 MB SO-DIMM 256 MBit (×16)
PC2700 (CL=2.5)
HYS64D16000GDL–6–C PC2700S–2533–0–C1 one rank 128 MB SO-DIMM 256 MBit (×16)
HYS64D32020GDL–6–C PC2700S–2533–0–A1 two ranks 256 MB SO-DIMM 256 MBit (×16)
PC3200 (CL=3.0)
HYS64D32020HDL–5–C PC3200S–3033–1–A1 two ranks 256 MB SO-DIMM 256 MBit (×16)
PC2700 (CL=2.5)
HYS64D16000HDL–6–C PC2700S–2533–0–C1 one rank 128 MB SO-DIMM 256 MBit (×16)
HYS64D32020HDL–6–C PC2700S–2533–0–A1 two ranks 256 MB SO-DIMM 256 MBit (×16)
Notes
1. All part numbers end with a place code designating the silicon-die revision. Reference information available on
request. Example: HYS64D32020GDL-6-B, indicating rev. B dies are used for SDRAM components.
2. The Compliance Code is printed on the module labels describing the speed sort (for example “PC2700”), the
latencies and SPD code definition (for example “2033–0” means CAS latency of 2.0 clocks, RCD
3 clocks, Row Precharge latency of 3 clocks, and JEDEC SPD code definiton version 0), and the Raw Card
used for this module.
Description
Technology
1)
latency of
1) RCD: Row-Column-Delay
Data Sheet 7 Rev. 1.0, 2004-03
HYS64D[32020/16000][H/G]DL–[5/6]–C
Small Outline DDR SDRAM Modules
3 Pin Configuration
The pin configuration of the Unbuffered Small Outline
DDR SDRAM DIMM is listed by function in Table 3
(184 pins). The abbreviations used in columns Pin and
Buffer Type are explained in Table 4 and Table 5
respectively. The pin numbering is depicted in
Figure 1.
Table 3 Pin Configuration of SO-DIMM
Pin# Name Pin
Type
Clock Signals
35 CK0 I SSTL Clock Signal
160 CK1 I SSTL Clock Signal
89 CK2 I SSTL Clock Signal
NC NC – Note: non-ECC type
37 CK0
158 CK1
91 CK2
NC NC – Note: non-ECC type
96 CKE0 I SSTL Clock Enable Rank 0
95 CKE1 I SSTL Clock Enable Rank 1
NC NC – Note: 1-rank module
Control Signals
121 S0
122 S1
NC NC – Note: 1-rank module
118 RAS
120 CAS
119 WE
Address Signals
117 BA0 I SSTL Bank Address Bus
116 BA1 I SSTL
ISSTLComplement Clock
ISSTLComplement Clock
ISSTLComplement Clock
ISSTLChip Select Rank 0
ISSTLChip Select Rank 1
ISSTLRow Address
ISSTLColumn Address
ISSTLWrite Enable
Buffer
Type
Function
Note: ECC type
module
module
Note: ECC type
module
module
Note: 2-rank module
Note: 2-ranks module
Strobe
Strobe
1:0
Pin Configuration
Table 3 Pin Configuration of SO-DIMM (cont’d)
Pin# Name Pin
Type
112 A0 I SSTL Address Bus 11:0
111 A1 I SSTL
110 A2 I SSTL
109 A3 I SSTL
108 A4 I SSTL
107 A5 I SSTL
106 A6 I SSTL
105 A7 I SSTL
102 A8 I SSTL
101 A9 I SSTL
115 A10 I SSTL
AP I SSTL
100 A11 I SSTL
99 A12 I SSTL Address Signal 12
NC NC – Note: 128 Mbit based
123 A13 I SSTL Address Signal 13
NC NC – Note: Module based
Data Signals
5DQ0I/OSSTLData Bus 63:0
7DQ1I/OSSTL
13 DQ2 I/O SSTL
17 DQ3 I/O SSTL
6DQ4I/OSSTL
8DQ5I/OSSTL
14 DQ6 I/O SSTL
18 DQ7 I/O SSTL
19 DQ8 I/O SSTL
23 DQ9 I/O SSTL
29 DQ10 I/O SSTL
31 DQ11 I/O SSTL
20 DQ12 I/O SSTL
24 DQ13 I/O SSTL
Buffer
Type
Function
Note: Module based
on 256 Mbit or
larger dies
module
Note: 1 Gbit based
module
on 512 Mbit or
smaller dies
Data Sheet 8 Rev. 1.0, 2004-03
HYS64D[32020/16000][H/G]DL–[5/6]–C
Small Outline DDR SDRAM Modules
Table 3 Pin Configuration of SO-DIMM (cont’d)
Pin# Name Pin
Type
30 DQ14 I/O SSTL Data Bus 63:0
32 DQ15 I/O SSTL
41 DQ16 I/O SSTL
43 DQ17 I/O SSTL
49 DQ18 I/O SSTL
53 DQ19 I/O SSTL
42 DQ20 I/O SSTL
44 DQ21 I/O SSTL
50 DQ22 I/O SSTL
54 DQ23 I/O SSTL
55 DQ24 I/O SSTL
59 DQ25 I/O SSTL
65 DQ26 I/O SSTL
67 DQ27 I/O SSTL
56 DQ28 I/O SSTL
60 DQ29 I/O SSTL
66 DQ30 I/O SSTL
68 DQ31 I/O SSTL
127 DQ32 I/O SSTL
129 DQ33 I/O SSTL
135 DQ34 I/O SSTL
139 DQ35 I/O SSTL
128 DQ36 I/O SSTL
130 DQ37 I/O SSTL
136 DQ38 I/O SSTL
140 DQ39 I/O SSTL
141 DQ40 I/O SSTL
145 DQ41 I/O SSTL
151 DQ42 I/O SSTL
153 DQ43 I/O SSTL
142 DQ44 I/O SSTL
146 DQ45 I/O SSTL
152 DQ46 I/O SSTL
154 DQ47 I/O SSTL
163 DQ48 I/O SSTL
165 DQ49 I/O SSTL
171 DQ50 I/O SSTL
175 DQ51 I/O SSTL
164 DQ52 I/O SSTL
166 DQ53 I/O SSTL
Buffer
Type
Function
Pin Configuration
Table 3 Pin Configuration of SO-DIMM (cont’d)
Pin# Name Pin
Type
172 DQ54 I/O SSTL Data Bus 63:0
176 DQ55 I/O SSTL
177 DQ56 I/O SSTL
181 DQ57 I/O SSTL
187 DQ58 I/O SSTL
189 DQ59 I/O SSTL
178 DQ60 I/O SSTL
182 DQ61 I/O SSTL
188 DQ62 I/O SSTL
190 DQ63 I/O SSTL
71 CB0 I/O SSTL Check Bit 0
NC NC – Note: Non-ECC
73 CB1 I/O SSTL Check Bit 1
79 CB2 I/O SSTL Check Bit 2
83 CB3 I/O SSTL Check Bit 3
72 CB4 I/O SSTL Check Bit 4
74 CB5 I/O SSTL Check Bit 5
NC NC – Note: Non-ECC
NC NC – Note: Non-ECC
NC NC – Note: Non-ECC
NC NC – Note: Non-ECC
NC NC – Note: Non-ECC
Buffer
Type
Function
Note: ECC type
module
module
Note: ECC type
module
module
Note: ECC type
module
module
Note: ECC type
module
module
Note: ECC type
module
module
Note: ECC type
module
module
Data Sheet 9 Rev. 1.0, 2004-03
HYS64D[32020/16000][H/G]DL–[5/6]–C
Small Outline DDR SDRAM Modules
Table 3 Pin Configuration of SO-DIMM (cont’d)
Pin# Name Pin
Type
80 CB6 I/O SSTL Check Bit 6
NC NC – Note: Non-ECC
84 CB7 I/O SSTL Check Bit 7
NC NC – Note: Non-ECC
11 DQS0 I/O SSTL Data Strobes 7:0
25 DQS1 I/O SSTL
47 DQS2 I/O SSTL
61 DQS3 I/O SSTL
133 DQS4 I/O SSTL
147 DQS5 I/O SSTL
169 DQS6 I/O SSTL
183 DQS7 I/O SSTL
77 DQS8 I/O SSTL Data Strobe 8
NC NC – Note: Non-ECC
12 DM0 I SSTL Data Mask 7:0
26 DM1 I SSTL
48 DM2 I SSTL
62 DM3 I SSTL
134 DM4 I SSTL
148 DM5 I SSTL
170 DM6 I SSTL
184 DM7 I SSTL
78 DM8 I SSTL Data Mask 8
NC NC – Note: Non-ECC
EEPROM
195 SCL I CMOS Serial Bus Clock
193 SDA I/O OD Serial Bus Data
194 SA0 I CMOS Slave Address
196 SA1 I CMOS
198 SA2 I CMOS
Buffer
Type
Function
Note: ECC type
module
module
Note: ECC type
module
module
Note: See block
diagram for
corresponding
DQ signals
Note: ECC type
module
module
Note: ECC type
module
module
Select Bus 2:0
Pin Configuration
Table 3 Pin Configuration of SO-DIMM (cont’d)
Pin# Name Pin
Type
Power Supplies
1,2
197
9,10,
21,
22,
33,
34,
36,
45,
46,
57,
58,
69,
70,
81,
82,
92,
93,
94,
113,
114,
131,
132,
143,
144,
155,
156,
157,
167,
168,
179,
180,
191,
192
V
REF
V
DDSPD
V
DD
AI – I/O Reference
PWR – EEPROM Power
PWR – Power Supply
Buffer
Type
Function
Voltage
Supply
Data Sheet 10 Rev. 1.0, 2004-03
HYS64D[32020/16000][H/G]DL–[5/6]–C
Small Outline DDR SDRAM Modules
Table 3 Pin Configuration of SO-DIMM (cont’d)
Pin# Name Pin
Type
3,4,
15,
16,
27,
28,
38,
39,
40,
51,
52,
63,
64,
75,
76,
87,
88,
90,
103,
104,
125,
126,
137,
138,
149,
150,
159,
161,
162,
173,
174,
185,
186
Other Pins
199
V
V
SS
DDID
GND – Ground Plane
OODVDD Identification
Buffer
Type
Function
Note: Pin in tristate,
indicating V
and V
connected on
PCB
DDQ
DD
nets
Pin Configuration
Table 3 Pin Configuration of SO-DIMM (cont’d)
Pin# Name Pin
Type
85,
86,
97,
98,
124,
200
Table 4 Abbreviations for Pin Type
Abbreviation Description
I Standard input-only pin. Digital levels.
O Output. Digital levels.
I/O I/O is a bidirectional input/output signal.
AI Input. Analog levels.
PWR Power
GND Ground
NC Not Connected (JEDEC Standard)
Table 5 Abbreviations for Buffer Type
Abbreviation Description
SSTL Serial Stub Terminalted Logic (SSTL2)
LV-CMOS Low Voltage CMOS
CMOS
OD Open Drain. The corresponding pin has 2
NC NC – Not connected
CMOS Levels
operational states, active low and tristate,
and allows multiple devices to share as a
wire-OR.
Buffer
Type
Function
Note: Pins not
connected on
Infineon SO
DIMMs
Data Sheet 11 Rev. 1.0, 2004-03
HYS64D[32020/16000][H/G]DL–[5/6]–C
Small Outline DDR SDRAM Modules
Pin 001
-
V
REF
DQ0
V
DQ2
DQ3
V
DQS1
DQ10
V
CK0
DQ16
V
DQ18
DQ19
V
DQS3
DQ26
V
CB1/NC
DQS8/NC
V
NC
CK2/NC
V
NC
A9
A7
A3
V
BA0
S0
V
DQ33
DQS4
V
DQ40
DQ41
V
DQ43
V
V
DQ49
DQS6
V
DQ56
DQ57
V
DQ59
SDA
V
DDSPD
DD
DD
DD
DD
DD
DD
DD
DD
DD
SS
SS
SS
DD
SS
SS
SS
Pin 005
Pin 009
Pin 013
Pin 017
Pin 021
Pin 025
Pin 029
Pin 033
Pin 037
-
-
Pin 041
-
Pin 045
-
Pin 049
-
Pin 053
-
Pin 057
-
Pin 061
-
Pin 065
-
Pin 069
-
Pin 073
-
Pin 077
-
Pin 081
-
Pin 085
-
Pin 089
-
Pin 093
-
Pin 097
-
Pin 101
-
Pin 105
-
Pin 109
-
Pin 113
-
Pin 117
-
Pin 121
-
Pin 125
-
Pin 129
-
Pin 133
-
Pin 137
-
Pin 141
-
Pin 145
-
Pin 149
-
Pin 153
-
Pin 157
-
Pin 161
-
Pin 165
-
Pin 169
-
Pin 173
-
Pin 177
-
Pin 181
-
Pin 185
-
Pin 189
-
Pin 193
-
Pin 197
V
DQ1
DQS0
V
DQ8
DQ09
V
DQ11
CK0
V
DQ17
DQS2
V
DQ33
DQ25
V
DQ27
CB0/NC
V
CB2/NC
CB3/NC
V
CK2/NC
CKE1/NC
A12/NC
V
A5
A1
A10/AP
WE
A13/NC
DQ32
V
DD
DQ34
DQ35
V
DQS5
DQ42
V
V
DQ48
V
DQ50
DQ51
V
DQS7
DQ58
V
SCL
V
DDID
SS
SS
SS
SS
SS
SS
SS
SS
SS
DD
DD
SS
DD
DD
DD
Pin 003
Pin 007
Pin 011
Pin 015
Pin 019
Pin 023
Pin 027
Pin 031
Pin 035
Pin 039
-
Pin 043
Pin 047
Pin 051
Pin 055
Pin 059
Pin 063
Pin 067
Pin 071
Pin 075
Pin 079
Pin 083
Pin 087
Pin 091
Pin 095
Pin 099
Pin 103
Pin 107
Pin 111
Pin 115
Pin 119
Pin 123
Pin 127
Pin 131
Pin 135
Pin 139
Pin 143
Pin 147
Pin 151
Pin 155
Pin 159
Pin 163
Pin 167
Pin 171
Pin 175
Pin 179
Pin 183
Pin 187
Pin 191
Pin 195
Pin 199
-
FRONTSIDE
Figure 1 Pin Configuration Diagram 200-Pin SO-DIMM
Pin Configuration
Pin 002
-
V
Pin 004
Pin 008
Pin 012
Pin 016
Pin 020
Pin 024
Pin 028
Pin 032
Pin 036
Pin 040
Pin 044
Pin 048
Pin 052
Pin 056
Pin 060
BACKSIDE
Pin 064
Pin 068
Pin 072
Pin 076
Pin 080
Pin 084
Pin 088
Pin 092
Pin 096
Pin 100
Pin 104
Pin 108
Pin 112
Pin 116
Pin 120
Pin 124
Pin 128
Pin 132
Pin 136
Pin 140
Pin 144
Pin 148
Pin 152
Pin 156
Pin 160
Pin 164
Pin 168
Pin 172
Pin 176
Pin 180
Pin 184
Pin 188
Pin 192
Pin 196
Pin 200
V
-
SS
DQ6
DM0
V
-
SS
DQ12
DQ13
V
-
SS
DQ15
V
-
DD
V
-
SS
DQ21
DM2
V
-
SS
DQ28
DQ29
V
-
SS
DQ31
CB4/NC
V
-
SS
CB6/NC
CB7/NC
V
-
SS
V
-
DD
CKE0
A11
V
-
SS
A4
A0
BA1
CAS
NC
DQ36
-
V
-
DD
DQ38
DQ39
V
-
DD
DM5
DQ46
V
-
DD
CK1
DQ52
V
-
DD
DQ54
DQ55
V
-
DD
DM7
DQ62
V
-
DD
SA1
NC
-
Pin 006
Pin 010
Pin 014
Pin 018
Pin 022
Pin 026
Pin 030
Pin 034
Pin 038
Pin 042
Pin 046
Pin 050
Pin 054
Pin 058
Pin 062
Pin 066
Pin 070
Pin 074
Pin 078
Pin 082
Pin 086
Pin 090
Pin 094
Pin 098
Pin 102
Pin 106
Pin 110
Pin 114
Pin 118
Pin 122
Pin 126
Pin 130
Pin 134
Pin 138
Pin 142
Pin 146
Pin 150
Pin 154
Pin 158
Pin 162
Pin 166
Pin 170
Pin 174
Pin 178
Pin 182
Pin 186
Pin 190
Pin 194
Pin 198
REF
-
DQ4
-
V
DD
-
DQ6
-
DQ7
-
V
DD
-
DM1
-
DQ14
-
V
DD
V
-
SS
-
DQ20
V
-
DD
-
DQ22
-
DQ23
-
V
DD
-
DM3
-
DQ30
V
-
DD
-
CB5/NC
-
DM8/NC
-
V
DD
-
NC
-
V
SS
V
-
DD
-
NC
-
A8
-
A6
-
A2
-
V
DD
RAS
S1/NC
V
-
SS
DQ37
DM4
V
-
SS
DQ44
DQ45
V
-
SS
DQ47
CK1
V
-
SS
DQ53
DM6
V
-
SS
DQ60
DQ61
V
-
SS
DQ63
SA0
SA2
-
MPPD0040
Table 6
Density Organization Memory
Ranks
SDRAMs # of
SDRAMs
# of row/bank/
columns bits
Refresh Period Interval
128MB 16M ×64 1 16M ×16 4 13/2/9 8K 64 ms 7.8 µs
256MB 32M ×64 2 16M ×16 8 13/2/9 8K 64 ms 7.8 µs
Data Sheet 12 Rev. 1.0, 2004-03
HYS64D[32020/16000][H/G]DL–[5/6]–C
Small Outline DDR SDRAM Modules
BA0 - BA1
A0 - An
RAS
CAS
WE
CKE0
S0
DM1
DQS1
DQ8
DQ9
DQ10
DQ11
DQ12
DQ13
DQ14
DQ15
DM0
DQS0
DQ0
DQ1
DQ2
DQ3
DQ4
DQ5
DQ6
DQ7
BA0 - BA1: SDRAMs D0 - D3
A0 - An: SDRAMs D0 - D3
RAS: SDRAMs D0 - D3
CAS: SDRAMs D0 - D3
WE: SDRAMs D0 - D3
CKE: SDRAMs D0 - D3
LDM CS
LDQS
I/O 0
I/O 1
I/O 2
I/O 3
I/O 4
I/O 5
I/O 6
I/O 7
UDM
UDQS
I/O8
I/O9
I/O10
I/O11
I/O12
I/O13
I/O14
I/O15
D0
DQS3
DQ24
DQ25
DQ26
DQ27
DQ28
DQ29
DQ30
DQ31
DQS2
DQ16
DQ17
DQ18
DQ19
DQ20
DQ21
DQ22
DQ23
DM3
DM2
SCL
SAD
SA0
SA1
SA2
V
SS
VDD/V
LDM CS
LDQS
I/O 0
I/O 1
I/O 2
I/O 3
I/O 4
I/O 5
I/O 6
I/O 7
UDM
UDQS
I/O8
I/O9
I/O10
I/O11
I/O12
I/O13
I/O14
I/O15
SCL
SAD
A0
A1
A2
WP
V
DDSPD
V
V
DDID
DDQ
REF
V
SS
Strap: see Note 1
D1
E0
Pin Configuration
VDD: SPD EEPROM E0
V
V
V
DM5
DQS5
DQ40
DQ41
DQ42
DQ43
DQ44
DQ45
DQ46
DQ47
DM4
DQS4
DQ32
DQ33
DQ34
DQ35
DQ36
DQ37
DQ38
DQ39
DM7
DQS7
DQ56
DQ57
DQ58
DQ59
DQ60
DQ61
DQ62
DQ63
DM6
DQS6
DQ48
DQ49
DQ50
DQ51
DQ52
DQ53
DQ54
DQ55
DD/VDDQ
REF
SS
: SDRAMs D0 - D3
: SDRAMs D0 - D3
: SDRAMs D0 - D3
LDM CS
LDQS
I/O 0
I/O 1
I/O 2
I/O 3
I/O 4
I/O 5
I/O 6
I/O 7
UDM
UDQS
I/O8
I/O9
I/O10
I/O11
I/O12
I/O13
I/O14
I/O15
LDM CS
LDQS
I/O 0
I/O 1
I/O 2
I/O 3
I/O 4
I/O 5
I/O 6
I/O 7
UDM
UDQS
I/O8
I/O9
I/O10
I/O11
I/O12
I/O13
I/O14
I/O15
D2
D3
MPBD1051
Figure 2 Block Diagram Raw Card C ×64 1 Rank ×16
Notes
1.
V
= V
DD
2. DQ, DQS, DM resistors are 22
3. BAn, An, RAS
, therefore V
DDQ
strap open
DDID
Ω±
5%
, CAS, WE resistors are 7.5Ω±5%
Table 7 Clock Signal Loads
Clock Input Number of SDRAMs Note
CK0, CK0
CK1, CK1
CK2, CK2
NC —
2 SDRAMs —
2 SDRAMs —
Data Sheet 13 Rev. 1.0, 2004-03
HYS64D[32020/16000][H/G]DL–[5/6]–C
Small Outline DDR SDRAM Modules
BA0 - BA1
A0 - An
RAS
CAS
WE
CKE0
CKE1
CK0
CK0
CK1
CK1
CK2
CK2
S0
S1
DM0
DQS0
DQ0
DQ1
DQ2
DQ3
DQ4
DQ5
DQ6
DQ7
DM1
DQS1
DQ8
DQ9
DQ10
DQ11
DQ12
DQ13
DQ14
DQ15
DM2
DQS2
DQ16
DQ17
DQ18
DQ19
DQ20
DQ21
DQ22
DQ23
DM3
DQS3
DQ24
DQ25
DQ26
DQ27
DQ28
DQ29
DQ30
DQ31
BA0 - BA1: SDRAMs D0 - D3
A0 - An: SDRAMs D0 - D3
RAS: SDRAMs D0 - D3
CAS: SDRAMs D0 - D3
WE: SDRAMs D0 - D3
CKE: SDRAMs D0 - D3
CKE: SDRAMs D4 - D7
4 loads
4 loads
0 loads
CS
LDM
LDQS
I/O 0
I/O 1
I/O 2
I/O 3
I/O 4
I/O 5
I/O 6
I/O 7
UDM
UDQS
I/O8
I/O9
I/O10
I/O11
I/O12
I/O13
I/O14
I/O15
CS
LDM
LDQS
I/O 0
I/O 1
I/O 2
I/O 3
I/O 4
I/O 5
I/O 6
I/O 7
UDM
UDQS
I/O8
I/O9
I/O10
I/O11
I/O12
I/O13
I/O14
I/O15
D0
CS
LDM
LDQS
I/O 0
I/O 1
I/O 2
I/O 3
I/O 4
I/O 5
I/O 6
I/O 7
UDM
UDQS
I/O8
I/O9
I/O10
I/O11
I/O12
I/O13
I/O14
I/O15
D1 D5
CS
LDM
LDQS
I/O 0
I/O 1
I/O 2
I/O 3
I/O 4
I/O 5
I/O 6
I/O 7
UDM
UDQS
I/O8
I/O9
I/O10
I/O11
I/O12
I/O13
I/O14
I/O15
D4
V
DD,SPD
VDD/V
V
V
DDQ
REF
V
SS
DDID
Strap: see Note 1
DM4
DQS4
DQ32
DQ33
DQ34
DQ35
DQ36
DQ37
DQ38
DQ39
DM5
DQS5
DQ40
DQ41
DQ42
DQ43
DQ44
DQ45
DQ46
DQ47
DM6
DQS6
DQ48
DQ49
DQ50
DQ51
DQ52
DQ53
DQ54
DQ55
DM7
DQS7
DQ56
DQ57
DQ58
DQ59
DQ60
DQ61
DQ62
DQ63
Pin Configuration
VDD: SPD EEPROM E0
V
DD/VDDQ
V
REF
V
SS
SCL
SAD
SA0
SA1
SA2
V
SS
CS
LDM
LDQS
I/O 0
I/O 1
I/O 2
I/O 3
I/O 4
I/O 5
I/O 6
I/O 7
UDM
UDQS
I/O8
I/O9
I/O10
I/O11
I/O12
I/O13
I/O14
I/O15
CS
LDM
LDQS
I/O 0
I/O 1
I/O 2
I/O 3
I/O 4
I/O 5
I/O 6
I/O 7
UDM
UDQS
I/O8
I/O9
I/O10
I/O11
I/O12
I/O13
I/O14
I/O15
: SDRAMs D0 - D7
: SDRAMs D0 - D7
: SDRAMs D0 - D7
SCL
SAD
A0
A1
A2
WP
D2
CS
LDM
LDQS
I/O 0
I/O 1
I/O 2
I/O 3
I/O 4
I/O 5
I/O 6
I/O 7
UDM
UDQS
I/O8
I/O9
I/O10
I/O11
I/O12
I/O13
I/O14
I/O15
D3
CS
LDM
LDQS
I/O 0
I/O 1
I/O 2
I/O 3
I/O 4
I/O 5
I/O 6
I/O 7
UDM
UDQS
I/O8
I/O9
I/O10
I/O11
I/O12
I/O13
I/O14
I/O15
E0
D6
D7
MPBD1091
Figure 3 Block Diagram Raw Card A ×64 2 Ranks ×8
Notes
1.
V
DD
= V
, therefore V
DDQ
strap open
DDID
3. BAn, An, RAS
5%
, CAS, WE resistors are 22 ohms +/-
2. DQ, DQS, DM resistors are 18 ohms +/-5%
Data Sheet 14 Rev. 1.0, 2004-03
HYS64D[32020/16000][H/G]DL–[5/6]–C
Small Outline DDR SDRAM Modules
Electrical Characteristics
4 Electrical Characteristics
4.1 Operating Conditions
Table 8 Absolute Maximum Ratings
Parameter Symbol Values Unit Note/ Test Condition
min. typ. max.
Voltage on I/O pins relative to
Voltage on inputs relative to
Voltage on
Voltage on
V
supply relative to V
DD
V
supply relative to V
DDQ
Operating temperature (ambient)
Storage temperature (plastic)
Power dissipation (per SDRAM component)
Short circuit output current
Attention: Permanent damage to the device may occur if “Absolute Maximum Ratings” are exceeded. This
is a stress rating only, and functional operation should be restricted to recommended operation
conditions. Exposure to absolute maximum rating conditions for extended periods of time may
affect device reliability and exceeding only one of the values may cause irreversible damage to
the integrated circuit.
V
SS
V
SS
SS
SS
V
V
V
V
T
T
P
I
OUT
, V
IN
IN
DD
DDQ
A
STG
D
OUT
–0.5 – V
+0.5 V –
DDQ
–1 – +3.6 V –
–1 – +3.6 V –
–1 – +3.6 V –
0–+70 °C–
-55 – +150 °C–
–1– W–
–50– mA–
Table 9 Electrical Characteristics and DC Operating Conditions
Parameter Symbol Values Unit Note/Test Condition
Min. Typ. Max.
Device Supply Voltage
Device Supply Voltage
Output Supply Voltage V
Output Supply Voltage
EEPROM supply voltage V
Supply Voltage, I/O Supply
Voltage
Input Reference Voltage
I/O Termination Voltage
V
DD
V
DD
DDQ
V
DDQ
DDSPD
V
SS
V
SSQ
V
REF
V
TT
2.3 2.5 2.7 V
f
≤ 166 MHz
CK
2.5 2.6 2.7 V fCK>166MHz
2.3 2.5 2.7 V
f
≤ 166 MHz
CK
2.5 2.6 2.7 V fCK>166MHz
2.3 2.5 3.6 V —
,
00V—
0.49 ×
V
DDQ
V
– 0.04 V
REF
0.5 ×
V
DDQ
0.51 ×
V
DDQ
+ 0.04 V
REF
3)
V
4)
(System)
Input High (Logic1) Voltage V
Input Low (Logic0) Voltage V
Input Voltage Level,
CK and CK
Inputs
Input Differential Voltage,
CK and CK
Inputs
VI-Matching Pull-up
IH(DC)VREF
IL(DC)
V
IN(DC)
V
ID(DC)
VI
Ratio
–0.3 V
–0.3 V
0.36 V
0.71 1.4 —
+ 0.15 V
+ 0.3 V
DDQ
– 0.15 V
REF
+ 0.3 V
DDQ
+ 0.6 V
DDQ
7)
7)
7)
7)5)
6)
Current to Pull-down
Current
1)
2)
2)
Data Sheet 15 Rev. 1.0, 2004-03
HYS64D[32020/16000][H/G]DL–[5/6]–C
Small Outline DDR SDRAM Modules
Electrical Characteristics
Table 9 Electrical Characteristics and DC Operating Conditions (cont’d)
Parameter Symbol Values Unit Note/Test Condition
1)
Min. Typ. Max.
Input Leakage Current
Output Leakage Current I
Output High Current,
I
I
I
OZ
OH
–2 2 µA Any input 0 V ≤ VIN≤ VDD;
All other pins not under test
7)8)
=0V
–5 5 µA DQs are disabled;
DDQ
7)
7)
— –16.2 mA V
0V ≤
OUT
V
≤ V
OUT
= 1.95 V
Normal Strength Driver
Output Low
I
OL
16.2 — mA V
= 0.35 V
OUT
7)
Current, Normal Strength
Driver
1) 0 °C ≤ TA ≤ 70 °C
2) DDR400 conditions apply for all clock frequencies above 166 MHz
V
3) Peak to peak AC noise on
V
4)
5)
6) The ratio of the pull-up current to the pull-down current is specified for the same temperature and voltage, over the entire
7) Inputs are not recognized as valid until
8) Values are shown per DDR SDRAM component
is not applied directly to the device. VTT is a system supply for signal termination resistors, is expected to be set equal
TT
to V
V
temperature and voltage range, for device drain to source voltage from 0.25 to 1.0 V. For a given output, it represents the
maximum difference between pull-up and pull-down drivers due to process variation.
, and must track variations in the DC level of V
REF
is the magnitude of the difference between the input level on CK and the input level on CK.
ID
may not exceed ± 2% V
REF
V
stabilizes.
REF
REF (DC)
REF
. V
is also expected to track noise variations in V
REF
.
DDQ
.
Data Sheet 16 Rev. 1.0, 2004-03
HYS64D[32020/16000][H/G]DL–[5/6]–C
Small Outline DDR SDRAM Modules
Electrical Characteristics
4.2 Current Specification and Conditions
Table 10 IDD Conditions
Parameter Symbol
Operating Current 0
one bank; active/ precharge; DQ, DM, and DQS inputs changing once per clock cycle;
address and control inputs changing once every two clock cycles.
Operating Current 1
one bank; active/read/precharge; Burst Length = 4; see component data sheet.
Precharge Power-Down Standby Current
all banks idle; power-down mode; CKE ≤
Precharge Floating Standby Current
CS
≥ V
address and other control inputs changing once per clock cycle;
Precharge Quiet Standby Current
CS
≥ V
address and other control inputs stable at ≥
Active Power-Down Standby Current
one bank active; power-down mode; CKE ≤
Active Standby Current
one bank active; CS
DQ, DM and DQS inputs changing twice per clock cycle;
address and control inputs changing once per clock cycle.
Operating Current Read
one bank active; Burst Length = 2; reads; continuous burst;
address and control inputs changing once per clock cycle;
50% of data outputs changing on every clock edge;
CL = 2 for DDR266(A), CL = 3 for DDR333 and DDR400B;
Operating Current Write
one bank active; Burst Length = 2; writes; continuous burst;
address and control inputs changing once per clock cycle;
50% of data outputs changing on every clock edge;
CL = 2 for DDR266(A), CL = 3 for DDR333 and DDR400B
Auto-Refresh Current
t
= t
RC
RFCMIN
Self-Refresh Current
CKE ≤ 0.2 V; external clock on
Operating Current 7
four bank interleaving with Burst Length = 4; see component data sheet.
, all banks idle; CKE ≥ V
IH,,MIN
, all banks idle; CKE ≥ V
IHMIN
≥ V
IH,MIN
, burst refresh
; CKE ≥ V
IH,MIN
IH,MIN
IH,MIN
V
IL,MAX
;
; VIN = V
V
IH,MIN
V
ILMAX
; tRC= t
V
= V
IN
for DQ, DQS and DM;
REF
or ≤ V
; VIN = V
RAS,MAX
.
IL,MAX
for DQ, DQS and DM.
REF
;
I
=0mA
OUT
for DQ, DQS and DM.
REF
I
DD0
I
DD1
I
DD2P
I
DD2F
I
DD2Q
I
DD3P
I
DD3N
I
DD4R
I
DD4W
I
DD5
I
DD6
I
DD7
Data Sheet 17 Rev. 1.0, 2004-03
HYS64D[32020/16000][H/G]DL–[5/6]–C
Small Outline DDR SDRAM Modules
Table 11
I
Specification for HYS64D[32020/16000][H/G]DL–[5/6]–C
DD
HYS64D16000HDL–5–C
HYS64D16000GDL–5–C
HYS64D32020HDL–5–C
HYS64D32020GDL–5–C
HYS64D16000HDL–6–C
HYS64D16000GDL–6–C
HYS64D32020HDL–6–C
HYS64D32020GDL–6–C
Electrical Characteristics
Unit Note
1)2)
128MB 256MB 128MB 256MB
×64 ×64 ×64 ×64
1 Ranks 2 Ranks 1 Ranks 2 Ranks
Part Number & Organization
–5 –5 –6 –6
Symbol Typ. Max. Typ. Max. Typ. Max. Typ. Max.
[component]
DDx
3)
3)4)
5)
5)
5)
5)
5)
3)4)
3)
3)
5)
3)4)
I
DD0
I
DD1
I
DD2P
I
DD2F
I
DD2Q
I
DD3P
I
DD3N
I
DD4R
I
DD4W
I
DD5
I
DD6
I
DD7
1) Module IDD values are calculated on the basis of component IDD and can be measured differently according to DQ loading
capacity.
2) Test condition for maximum values:
3) The module I
m ×
modules
4) DQ I/O (I
5) The module I
300 360 472 576 260 300 404 480 mA
380 440 552 656 320 380 464 560 mA
16 20 32 40 16 20 32 40 mA
120 144 240 288 100 120 200 240 mA
80 112 160 224 68 96 136 192 mA
52 72 104 144 44 60 88 120 mA
172 216 344 432 144 180 288 360 mA
400 480 572 696 340 400 484 580 mA
400 520 572 736 360 440 504 620 mA
560 760 732 976 480 640 624 820 mA
5.6 11.2 11.2 22.4 6 11 11 22 mA
840 1000 1012 1216 720 860 864 1040 mA
V
=2.7V, TA=10°C
DD
values are calculated from the I
I
DDx
DDx
[component] + n × I
) currents are not included in the calculations (see note 1)
DDQ
values are calculated from the corrponent I
DDx
[component] with m and n number of components of rank 1 and 2; n=0 for 1 rank
DD3N
values of the component data sheet as follows:
DDx
data sheet values as: (m + n) × I
DDx
Data Sheet 18 Rev. 1.0, 2004-03
HYS64D[32020/16000][H/G]DL–[5/6]–C
Small Outline DDR SDRAM Modules
Electrical Characteristics
4.3 AC Characteristics
Table 12 AC Timing - Absolute Specifications for DDR400B and DDR333
Parameter Symbol –5 –6 Unit Note/ Test
Condition
2)3)4)5)
2)3)4)5)
2)3)4)5)
2)3)4)5)
2)3)4)5)
2)3)4)5)
2)3)4)5)
2)3)4)5)6)
2)3)4)5)6)
2)3)4)5)7)
2)3)4)5)7)
2)3)4)5)
2)3)4)5)
2)3)4)5)
2)3)4)5)
2)3)4)5)
2)3)4)5)
2)3)4)5)
2)3)4)5)
2)3)4)5)8)
2)3)4)5)9)
2)3)4)5)
3)4)5)6)10)
3)4)5)6)10)
DQ output access time from CK/
CK
DQS output access time from
CK/CK
CK high-level width t
CK low-level width t
Clock Half Period t
Clock cycle time t
DQ and DM input hold time t
DQ and DM input setup time t
Control and Addr. input pulse
width (each input)
DQ and DM input pulse width
(each input)
Data-out high-impedance time
from CK/CK
Data-out low-impedance time
from CK/CK
Write command to 1st DQS
latching transition
DQS-DQ skew (DQS and
associated DQ signals)
Data hold skew factor t
DQ/DQS output hold time t
DQS input low (high) pulse width
(write cycle)
DQS falling edge to CK setup
time (write cycle)
DQS falling edge hold time from
CK (write cycle)
Mode register set command
cycle time
Write preamble setup time t
Write postamble t
Write preamble t
Address and control input setup
time
t
AC
t
DQSCK
CH
CL
HP
CK
DH
DS
t
IPW
t
DIPW
t
HZ
t
LZ
t
DQSS
t
DQSQ
QHS
QH
t
DQSL,H
t
DSS
t
DSH
t
MRD
WPRES
WPST
WPRE
t
IS
DDR400B DDR333
Min. Max. Min. Max.
–0.5 +0.5 –0.7 +0.7 ns
–0.6 +0.6 –0.6 +0.6 ns
0.45 0.55 0.45 0.55 t
0.45 0.55 0.45 0.55 t
CK
CK
min. (tCL, tCH)min. (tCL, tCH)ns
5 8 6 12 ns CL = 3.0
6 12 6 12 ns CL = 2.5
7.5 12 7.5 12 ns CL = 2.0
0.4 — 0.45 — ns
0.4 — 0.45 — ns
2.2 — 2.2 — ns
1.75 — 1.75 — ns
— +0.7 –0.7 +0.7 ns
–0.7 +0.7 –0.7 +0.7 ns
0.75 1.25 0.75 1.25 t
— +0.40 — +0.45 ns TSOPII
— +0.50 — +0.55 ns TSOPII
t
HP
– t
QHS
t
HP
– t
QHS
0.35 — 0.35 — t
0.2 — 0.2 — t
0.2 — 0.2 — t
2— 2— t
0— 0— ns
0.40 0.60 0.40 0.60 t
0.25 — 0.25 — t
0.6 — 0.75 — ns fast slew rate
0.7 — 0.8 — ns slow slew rate
CK
ns
CK
CK
CK
CK
CK
CK
1)
2)3)4)5)
2)3)4)5)
2)3)4)5)
Data Sheet 19 Rev. 1.0, 2004-03
HYS64D[32020/16000][H/G]DL–[5/6]–C
Small Outline DDR SDRAM Modules
Electrical Characteristics
Table 12 AC Timing - Absolute Specifications for DDR400B and DDR333 (cont’d)
Parameter Symbol –5 –6 Unit Note/ Test
DDR400B DDR333
Condition
Min. Max. Min. Max.
Address and control input hold
time
Read preamble t
Read postamble t
Active to Precharge command t
Active to Active/Auto-refresh
t
IH
RPRE
RPST
RAS
t
RC
0.6 — 0.75 — ns fast slew rate
3)4)5)6)10)
0.7 — 0.8 — ns slow slew rate
0.9 1.1 0.9 1.1 t
0.40 0.60 0.40 0.60 t
CK
CK
40 70E+3 42 70E+3 ns
55 — 60 — ns
3)4)5)6)10)
2)3)4)5)
2)3)4)5)
2)3)4)5)
2)3)4)5)
command period
Auto-refresh to Active/Auto-
t
RFC
65 — 72 — ns
2)3)4)5)
refresh command period
Active to Read or Write delay t
Precharge command period t
Active to Autoprecharge delay t
RCD
RP
RAP
15 — 18 — ns
15 — 18 — ns
t
RCD
or t
RASmintRCD
or t
RASmin
ns
2)3)4)5)
2)3)4)5)
2)3)4)5)
1)
Active bank A to Active bank B
t
RRD
10 — 12 — ns
2)3)4)5)
command
Write recovery time t
Auto precharge write recovery +
precharge time
Internal write to read command
WR
t
DAL
t
WTR
15 — 15 — ns
——— —
t
2— 1— t
CK
CK
2)3)4)5)
2)3)4)5)11)
2)3)4)5)
delay
Exit self-refresh to non-read
t
XSNR
75 — 75 — ns
2)3)4)5)
command
Exit self-refresh to read
t
XSRD
200 — 200 — t
CK
2)3)4)5)
command
Average Periodic Refresh
t
REFI
— 7.8 — 7.8 µs
2)3)4)5)12)
Interval
1) 0 °C ≤ TA ≤ 70 °C; V
(DDR400)
2) Input slew rate ≥ 1 V/ns for DDR400, DDR333
3) The CK/CK
level for signals other than CK/CK
4) Inputs are not recognized as valid until
5) The Output timing reference level, as measured at the timing reference point indicated in AC Characteristics (note 3) is
6) These parameters guarantee device timing, but they are not necessarily tested on each device.
t
and tLZ transitions occur in the same access time windows as valid data transitions. These parameters are not referred
7)
HZ
to a specific voltage level, but specify when the device is no longer driving (HZ), or begins driving (LZ).
8) The specific requirement is that DQS be valid (HIGH, LOW, or some point on a valid transition) on or before this CK edge.
A valid transition is defined as monotonic and meeting the input slew rate specifications of the device. When no writes were
previously in progress on the bus, DQS will be transitioning from Hi-Z to logic LOW. If a previous write was in progress,
DQS could be HIGH, LOW, or transitioning from HIGH to LOW at this time, depending on
9) The maximum limit for this parameter is not a device limit. The device operates with a greater value for this parameter, but
system performance (bus turnaround) degrades accordingly.
input reference level (for timing reference to CK/CK) is the point at which CK and CK cross: the input reference
= 2.5 V ± 0.2 V, VDD = +2.5 V ± 0.2 V (DDR333); V
DDQ
, is V
. CK/CK slew rate are ≥ 1.0 V/ns.
REF
V
stabilizes.
REF
= 2.6 V ± 0.1 V, VDD = +2.6 V ± 0.1 V
DDQ
t
.
DQSS
V
TT
.
Data Sheet 20 Rev. 1.0, 2004-03
HYS64D[32020/16000][H/G]DL–[5/6]–C
Small Outline DDR SDRAM Modules
10) Fast slew rate ≥ 1.0 V/ns , slow slew rate ≥ 0.5 V/ns and < 1 V/ns for command/address and CK & CK slew rate > 1.0 V/
ns, measured between V
11) For each of the terms, if not already an integer, round to the next highest integer.
cycle time.
12) A maximum of eight Autorefresh commands can be posted to any given DDR SDRAM device.
OH(ac)
and V
OL(ac)
.
t
CK
Electrical Characteristics
is equal to the actual system clock
Data Sheet 21 Rev. 1.0, 2004-03
HYS64D[32020/16000][H/G]DL–[5/6]–C
Small Outline DDR SDRAM Modules
SPD Contents
5SPD Contents
Table 13 SPD Codes for HYS64D32020[H/G]DL–5–C
Product Type & Organization HYS64D32020GDL–5–C HYS64D32020HDL–5–C
256 MB 256 MB
×64 ×64
2 Ranks 2 Ranks
Label Code PC3200S–3033–1 PC3200S–3033–1
Jedec SPD Revision Rev 1.0 Rev 1.0
Byte# Description HEX HEX
0 Programmed SPD Bytes in E2PROM 80 80
1 Total number of Bytes in E2PROM 08 08
2 Memory Type (DDR = 07h) 07 07
3 Number of Row Addresses 0D 0D
4 Number of Column Addresses 09 09
5 Number of DIMM Ranks 02 02
6 Data Width (LSB) 40 40
7 Data Width (MSB) 00 00
8 Interface Voltage Levels 04 04
9 tCK @ CLmax (Byte 18) [ns] 50 50
10 tAC SDRAM @ CLmax (Byte 18) [ns] 50 50
11 Error Correction Support 00 00
12 Refresh Rate 82 82
13 Primary SDRAM Width 10 10
14 Error Checking SDRAM Width 00 00
15 tCCD [cycles] 01 01
16 Burst Length Supported 0E 0E
17 Number of Banks on SDRAM Device 04 04
18 CAS Latency 1C 1C
19 CS Latency 01 01
20 Write Latency 02 02
21 DIMM Attributes 20 20
22 Component Attributes C1 C1
23 tCK @ CLmax -0.5 (Byte 18) [ns] 60 60
24 tAC SDRAM @ CLmax -0.5 [ns] 50 50
25 tCK @ CLmax -1 (Byte 18) [ns] 75 75
26 tAC SDRAM @ CLmax -1 [ns] 50 50
27 tRPmin [ns] 3C 3C
28 tRRDmin [ns] 28 28
29 tRCDmin [ns] 3C 3C
30 tRASmin [ns] 28 28
31 Module Density per Rank 20 20
32 tAS, tCS [ns] 60 60
Data Sheet 22 Rev. 1.0, 2004-03
HYS64D[32020/16000][H/G]DL–[5/6]–C
Small Outline DDR SDRAM Modules
Table 13 SPD Codes for HYS64D32020[H/G]DL–5–C
Product Type & Organization HYS64D32020GDL–5–C HYS64D32020HDL–5–C
256 MB 256 MB
×64 ×64
2 Ranks 2 Ranks
Label Code PC3200S–3033–1 PC3200S–3033–1
Jedec SPD Revision Rev 1.0 Rev 1.0
Byte# Description HEX HEX
33 tAH, TCH [ns] 60 60
34 tDS [ns] 40 40
35 tDH [ns] 40 40
36 - 40 not used 00 00
41 tRCmin [ns] 37 37
42 tRFCmin [ns] 41 41
43 tCKmax [ns] 28 28
44 tDQSQmax [ns] 28 28
45 tQHSmax [ns] 50 50
46 not used 00 00
47 DIMM PCB Height 01 01
48 - 61 not used 00 00
62 SPD Revision 10 10
63 Checksum of Byte 0-62 F6 F6
64 JEDEC ID Code of Infineon (1) C1 C1
65 - 71 JEDEC ID Code of Infineon (2 - 8) 00 00
72 Module Manufacturer Location xx xx
73 Part Number, Char 1 36 36
74 Part Number, Char 2 34 34
75 Part Number, Char 3 44 44
76 Part Number, Char 4 33 33
77 Part Number, Char 5 32 32
78 Part Number, Char 6 30 30
79 Part Number, Char 7 32 32
80 Part Number, Char 8 30 30
81 Part Number, Char 9 47 48
82 Part Number, Char 10 44 44
83 Part Number, Char 11 4C 4C
84 Part Number, Char 12 35 35
85 Part Number, Char 13 43 43
86 Part Number, Char 14 20 20
87 Part Number, Char 15 20 20
88 Part Number, Char 16 20 20
89 Part Number, Char 17 20 20
90 Part Number, Char 18 20 20
SPD Contents
Data Sheet 23 Rev. 1.0, 2004-03
HYS64D[32020/16000][H/G]DL–[5/6]–C
Small Outline DDR SDRAM Modules
Table 13 SPD Codes for HYS64D32020[H/G]DL–5–C
Product Type & Organization HYS64D32020GDL–5–C HYS64D32020HDL–5–C
256 MB 256 MB
×64 ×64
2 Ranks 2 Ranks
Label Code PC3200S–3033–1 PC3200S–3033–1
Jedec SPD Revision Rev 1.0 Rev 1.0
Byte# Description HEX HEX
91 Module Revision Code 0x 0x
92 Test Program Revision Code xx xx
93 Module Manufacturing Date Year xx xx
94 Module Manufacturing Date Week xx xx
95 - 98 Module Serial Number (1 - 4) xx xx
99 - 127 Blank FF FF
Table 14 SPD Codes for HYS64D[32020/16000][H/G]DL–6–C
Part Number & Organization
SPD Contents
HYS64D16000GDL–6–C
128MB 128MB 256MB 256MB
×64 ×64 ×64 ×64
1 Rank 1 Rank 2 Ranks 2 Ranks
–6 –6 –6 –6
Label Code PC2700S–
2533–0
Jedec SPD Revision Rev 0.0 Rev 0.0 Rev 0.0 Rev 0.0
Byte# Description HEX HEX HEX HEX
0 Programmed SPD Bytes in E2PROM 80 80 80 80
1 Total number of Bytes in E2PROM 08 08 08 08
2 Memory Type DDR = 07h 07 07 07 07
3 # of Row Addresses 0D 0D 0D 0D
4 # Number of Column Addresses 09 09 09 09
5 # of DIMM Ranks 01 01 02 02
6 Data Width (LSB) 40 40 40 40
7 Data Width (MSB) 00 00 00 00
8 Interface Voltage Levels 04 04 04 04
9 tCK @ CLmax (Byte 18) [ns] 60 60 60 60
10 tAC SDRAM @ CLmax (Byte 18) [ns] 70 70 70 70
HYS64D16000HDL–6–C
PC2700S–
2533–0
HYS64D32020GDL–6–C
PC2700S–
2533–0
HYS64D32020HDL–6–C
PC2700S–
2533–0
Data Sheet 24 Rev. 1.0, 2004-03
HYS64D[32020/16000][H/G]DL–[5/6]–C
Small Outline DDR SDRAM Modules
Table 14 SPD Codes for HYS64D[32020/16000][H/G]DL–6–C
Part Number & Organization
HYS64D16000GDL–6–C
128MB 128MB 256MB 256MB
×64 ×64 ×64 ×64
1 Rank 1 Rank 2 Ranks 2 Ranks
–6 –6 –6 –6
Label Code PC2700S–
2533–0
Jedec SPD Revision Rev 0.0 Rev 0.0 Rev 0.0 Rev 0.0
Byte# Description HEX HEX HEX HEX
11 DIMM Configuration Type (non- / ECC) 00 00 00 00
12 Refresh Rate 82 82 82 82
13 Primary SDRAM width 10 10 10 10
14 Error Checking SDRAM width 00 00 00 00
15 tCCD [cycles] 01 01 01 01
16 Burst Length Supported 0E 0E 0E 0E
17 Number of Banks on SDRAM 04 04 04 04
18 CAS Latency 0C 0C 0C 0C
19 CS Latency 01 01 01 01
20 WE (Write) Latency 02 02 02 02
21 DIMM Attributes 20 20 20 20
22 Component Attributes C1 C1 C1 C1
23 tCK @ CLmax -0.5 (Byte 18) [ns] 75 75 75 75
24 tAC SDRAM @ CLmax -0.5 [ns] 70 70 70 70
25 tCK @ CLmax -1 (Byte 18) [ns] 00 00 00 00
26 tAC SDRAM @ CLmax -1 [ns] 00 00 00 00
27 tRPmin (ns) 48 48 48 48
28 tRRDmin [ns] 30 30 30 30
29 tRCDmin [ns] 48 48 48 48
30 tRASmin [ns] 2A 2A 2A 2A
31 Module Density per Rank 20 20 20 20
32 tAS, tCS [ns] 75 75 75 75
33 tAH, TCH [ns] 75 75 75 75
34 tDS [ns] 45 45 45 45
35 tDH [ns] 45 45 45 45
36 - 40 not used 00 00 00 00
HYS64D16000HDL–6–C
PC2700S–
2533–0
HYS64D32020GDL–6–C
PC2700S–
2533–0
SPD Contents
HYS64D32020HDL–6–C
PC2700S–
2533–0
Data Sheet 25 Rev. 1.0, 2004-03
HYS64D[32020/16000][H/G]DL–[5/6]–C
Small Outline DDR SDRAM Modules
Table 14 SPD Codes for HYS64D[32020/16000][H/G]DL–6–C
Part Number & Organization
HYS64D16000GDL–6–C
128MB 128MB 256MB 256MB
×64 ×64 ×64 ×64
1 Rank 1 Rank 2 Ranks 2 Ranks
–6 –6 –6 –6
Label Code PC2700S–
2533–0
Jedec SPD Revision Rev 0.0 Rev 0.0 Rev 0.0 Rev 0.0
Byte# Description HEX HEX HEX HEX
41 tRCmin [ns] 3C 3C 3C 3C
42 tRFCmin [ns] 48 48 48 48
43 tCKmax [ns] 30 30 30 30
44 tDQSQmax [ns] 2D 2D 2D 2D
45 tQHSmax [ns] 55 55 55 55
46 - 61 not used 00 00 00 00
62 SPD Revision 00 00 00 00
63 Checksum of Byte 0-62 (LSB only) E8 E8 E9 E9
64 JEDEC ID Code for Infineon(1) C1 C1 C1 C1
65 - 71 JEDEC ID Code for Infineon(2 -8) 00 00 00 00
72 Module Manufacturer Location xx xx xx xx
73 Part Number, Char 1 36 36 36 36
74 Part Number, Char 2 34 34 34 34
75 Part Number, Char 3 44 44 44 44
76 Part Number, Char 4 31 31 33 33
77 Part Number, Char 5 36 36 32 32
78 Part Number, Char 6 30 30 30 30
79 Part Number, Char 7 30 30 32 32
80 Part Number, Char 8 30 30 30 30
81 Part Number, Char 9 47 48 47 48
82 Part Number, Char 10 44 44 44 44
83 Part Number, Char 11 4C 4C 4C 4C
84 Part Number, Char 12 36 36 36 36
85 Part Number, Char 13 43 43 43 43
86 Part Number, Char 14 20 20 20 20
87 Part Number, Char 15 20 20 20 20
HYS64D16000HDL–6–C
PC2700S–
2533–0
HYS64D32020GDL–6–C
PC2700S–
2533–0
SPD Contents
HYS64D32020HDL–6–C
PC2700S–
2533–0
Data Sheet 26 Rev. 1.0, 2004-03
HYS64D[32020/16000][H/G]DL–[5/6]–C
Small Outline DDR SDRAM Modules
Table 14 SPD Codes for HYS64D[32020/16000][H/G]DL–6–C
Part Number & Organization
HYS64D16000GDL–6–C
128MB 128MB 256MB 256MB
×64 ×64 ×64 ×64
1 Rank 1 Rank 2 Ranks 2 Ranks
–6 –6 –6 –6
Label Code PC2700S–
2533–0
Jedec SPD Revision Rev 0.0 Rev 0.0 Rev 0.0 Rev 0.0
Byte# Description HEX HEX HEX HEX
88 Part Number, Char 16 20 20 20 20
89 Part Number, Char 17 20 20 20 20
90 Part Number, Char 18 20 20 20 20
91 Module Revision Code xx xx xx xx
92 Test Program Revision Code xx xx xx xx
93 Module Manufacturing Date Year xx xx xx xx
94 Module Manufacturing Date Week xx xx xx xx
95 - 98 Module Serial Number (1 - 4) xx xx xx xx
99 -127 not used FF FF FF FF
HYS64D16000HDL–6–C
PC2700S–
2533–0
HYS64D32020GDL–6–C
PC2700S–
2533–0
SPD Contents
HYS64D32020HDL–6–C
PC2700S–
2533–0
Data Sheet 27 Rev. 1.0, 2004-03
HYS64D[32020/16000][H/G]DL–[5/6]–C
Small Outline DDR SDRAM Modules
6 Package Outlines
±0.05
±0.1
4
1.8
1
11.4
±0.1
18.45
1.8
(2.4)
±0.1
±0.1
67.6
63.6
47.4
±0.1
Package Outlines
2.4 MAX.
31.75
(2.45)(2.15)
100
1
±0.1
0.15
(2.45)
±0.1
4
-0.18
0.25
0.6
1.5
±0.1
1
101
2 MIN.
Detail of contacts
±0.1
(2.7)
±0.1
0.45
±0.03
2.55
(2.15)
200
6
20
Burnished, no burr allowed
L-DIM-200-011
Figure 4 Package Outlines – Raw Card C DDR-SDRAM SO-DIMM HYS64D16000[G/H]DL–6–C
Data Sheet 28 Rev. 1.0, 2004-03
HYS64D[32020/16000][H/G]DL–[5/6]–C
Small Outline DDR SDRAM Modules
Package Outlines
67.6
3.8 MAX.
±0.1
1
0.15
±0.05
1.8
(2.15)
±0.1
4
±0.1
63.6
31.75
±0.1
±0.1
(2.45)
100
1
18.45
1.8
(2.4)
±0.1
11.4
47.4
±0.1
(2.7)
(2.45)
±0.1
4
1
101
±0.1
1.5
±0.1
(2.15)
200
±0.1
6
±0.1
20
2 MIN.
Detail of contacts
-0.18
2.55
0.25
±0.03
0.45
±0.1
0.6
Burnished, no burr allowed
L-DIM-200-006
Figure 5 Package Outlines – Raw Card A DDR SDRAM SO-DIMM HYS64D32020[G/H]DL–5/6]–C
Data Sheet 29 Rev. 1.0, 2004-03
www.infineon.com
Published by Infineon Technologies AG
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