INFINEON HYS64D32020GDL–5–C, HYS64D16000GDL–6–C, HYS64D32020GDL–6–C, HYS64D32020HDL–5–C, HYS64D16000HDL–6–C User Manual
...
Data Sheet, Rev. 1.0, Mar. 2004
HYS64D32020[H/G]DL–5–C
HYS64D[32020/16000][H/G]DL–6–C
200-Pin Small Outline Dual-In-Line Memory Modules
SO-DIMM
DDR SDRAM
Memory Products
Never stop thinking.
Edition 2004-03
Published by Infineon Technologies AG,
St.-Martin-Strasse 53,
81669 München, Germany
© Infineon Technologies AG 2004.
All Rights Reserved.
Attention please!
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Data Sheet, Rev. 1.0, Mar. 2004
HYS64D32020[H/G]DL–5–C
HYS64D[32020/16000][H/G]DL–6–C
200-Pin Small Outline Dual-In-Line Memory Modules
SO-DIMM
DDR SDRAM
Memory Products
Never stop thinking.
HYS64D32020[H/G]DL–5–C,HYS64D[32020/16000][H/G]DL–6–C
Revision History: Rev. 1.0 2004-03
Previous Version: Rev. 0.5 2003-11
Page Subjects (major changes since last revision)
6,7 Added DDR400
18 Updated
I
Currents and added DDR400 Idd Currents
dd
24 Updated SPD Code Bytes 99 - 127 to FF and added SPD Codes for DDR400
13,14 editorial changes
We Listen to Your Comments
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Template: mp_a4_v2.0_2003-06-06.fm
HYS64D[32020/16000][H/G]DL–[5/6]–C
Small Outline DDR SDRAM Modules
Table of Contents
1 Overview . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6
1.1 Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6
2 Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6
3 Pin Configuration . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8
4 Electrical Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15
4.1 Operating Conditions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15
4.2 Current Specification and Conditions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17
4.3 AC Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19
5 SPD Contents . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22
6 Package Outlines . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 28
Data Sheet 5 Rev. 1.0, 2004-03
200-Pin Small Outline Dual-In-Line Memory Modules
SO-DIMM
HYS64D[32020/16000][H/G]DL–6–C
HYS64D32020[H/G]DL–5–C
1Overview
1.1 Features
• Non-parity 200-Pin Small Outline Dual-In-Line Memory Modules
• One rank 16M ×64 and two ranks 32M ×64 organization
• JEDEC standard Double Data Rate Synchronous DRAMs (DDR SDRAM)
•Single +2.5V (± 0.2 V) power supply
• Built with 256 Mbit DDR SDRAMs organised as ×16 in P–TSOPII–66–1 packages
• Programmable CAS Latency, Burst Length, and Wrap Sequence (Sequential & Interleave)
• Auto Refresh (CBR) and Self Refresh
• All inputs and outputs SSTL_2 compatible
• Serial Presence Detect with E
• Jedec standard form factor: 67.60 mm × 31.75 mm × 2.4 / 3.80 mm
• Jedec standard reference layout Raw Cards A and C
• Gold plated contacts
Table 1 Performance
2
PROM
Part Number Speed Code –5 –6Unit
Speed Grade Component DDR400B DDR333B —
Module PC3200–3033 PC2700–2533 —
max. Clock Frequency @CL3
@CL2.5
@CL2
f
CK3
f
CK2.5
f
CK2
200 166 MHz
166 166 MHz
133 133 MHz
2 Description
The HYS64D32020[H/G]DL–5–C and HYS64D[32020/16000][H/G]DL–6–C are industry standard 200-Pin Small
Outline Dual-In-Line Memory Modules (SO-DIMMs) organized as 32M × 64 and 16M × 64. The memory array is
designed with Double Data Rate Synchronous DRAMs (DDR SDRAM). A variety of decoupling capacitors are
mounted on the PC board. The DIMMs feature serial presence detect based on a serial E
2
2-pin I
available to the customer.
C protocol. The first 128 bytes are programmed with configuration data and the second 128 bytes are
2
PROM device using the
Data Sheet 6 Rev. 1.0, 2004-03
HYS64D[32020/16000][H/G]DL–[5/6]–C
Small Outline DDR SDRAM Modules
Table 2 Ordering Information
Type Compliance Code Description SDRAM
PC3200 (CL=3.0)
HYS64D32020GDL–5–C PC3200S–3033–1–A1 two ranks 256 MB SO-DIMM 256 MBit (×16)
PC2700 (CL=2.5)
HYS64D16000GDL–6–C PC2700S–2533–0–C1 one rank 128 MB SO-DIMM 256 MBit (×16)
HYS64D32020GDL–6–C PC2700S–2533–0–A1 two ranks 256 MB SO-DIMM 256 MBit (×16)
PC3200 (CL=3.0)
HYS64D32020HDL–5–C PC3200S–3033–1–A1 two ranks 256 MB SO-DIMM 256 MBit (×16)
PC2700 (CL=2.5)
HYS64D16000HDL–6–C PC2700S–2533–0–C1 one rank 128 MB SO-DIMM 256 MBit (×16)
HYS64D32020HDL–6–C PC2700S–2533–0–A1 two ranks 256 MB SO-DIMM 256 MBit (×16)
Notes
1. All part numbers end with a place code designating the silicon-die revision. Reference information available on
request. Example: HYS64D32020GDL-6-B, indicating rev. B dies are used for SDRAM components.
2. The Compliance Code is printed on the module labels describing the speed sort (for example “PC2700”), the
latencies and SPD code definition (for example “2033–0” means CAS latency of 2.0 clocks, RCD
3 clocks, Row Precharge latency of 3 clocks, and JEDEC SPD code definiton version 0), and the Raw Card
used for this module.
Description
Technology
1)
latency of
1) RCD: Row-Column-Delay
Data Sheet 7 Rev. 1.0, 2004-03
HYS64D[32020/16000][H/G]DL–[5/6]–C
Small Outline DDR SDRAM Modules
3 Pin Configuration
The pin configuration of the Unbuffered Small Outline
DDR SDRAM DIMM is listed by function in Table 3
(184 pins). The abbreviations used in columns Pin and
Buffer Type are explained in Table 4 and Table 5
respectively. The pin numbering is depicted in
Figure 1.
Table 3 Pin Configuration of SO-DIMM
Pin# Name Pin
Type
Clock Signals
35 CK0 I SSTL Clock Signal
160 CK1 I SSTL Clock Signal
89 CK2 I SSTL Clock Signal
NC NC – Note: non-ECC type
37 CK0
158 CK1
91 CK2
NC NC – Note: non-ECC type
96 CKE0 I SSTL Clock Enable Rank 0
95 CKE1 I SSTL Clock Enable Rank 1
NC NC – Note: 1-rank module
Control Signals
121 S0
122 S1
NC NC – Note: 1-rank module
118 RAS
120 CAS
119 WE
Address Signals
117 BA0 I SSTL Bank Address Bus
116 BA1 I SSTL
ISSTLComplement Clock
ISSTLComplement Clock
ISSTLComplement Clock
ISSTLChip Select Rank 0
ISSTLChip Select Rank 1
ISSTLRow Address
ISSTLColumn Address
ISSTLWrite Enable
Buffer
Type
Function
Note: ECC type
module
module
Note: ECC type
module
module
Note: 2-rank module
Note: 2-ranks module
Strobe
Strobe
1:0
Pin Configuration
Table 3 Pin Configuration of SO-DIMM (cont’d)
Pin# Name Pin
Type
112 A0 I SSTL Address Bus 11:0
111 A1 I SSTL
110 A2 I SSTL
109 A3 I SSTL
108 A4 I SSTL
107 A5 I SSTL
106 A6 I SSTL
105 A7 I SSTL
102 A8 I SSTL
101 A9 I SSTL
115 A10 I SSTL
AP I SSTL
100 A11 I SSTL
99 A12 I SSTL Address Signal 12
NC NC – Note: 128 Mbit based
123 A13 I SSTL Address Signal 13
NC NC – Note: Module based
Data Signals
5DQ0I/OSSTLData Bus 63:0
7DQ1I/OSSTL
13 DQ2 I/O SSTL
17 DQ3 I/O SSTL
6DQ4I/OSSTL
8DQ5I/OSSTL
14 DQ6 I/O SSTL
18 DQ7 I/O SSTL
19 DQ8 I/O SSTL
23 DQ9 I/O SSTL
29 DQ10 I/O SSTL
31 DQ11 I/O SSTL
20 DQ12 I/O SSTL
24 DQ13 I/O SSTL
Buffer
Type
Function
Note: Module based
on 256 Mbit or
larger dies
module
Note: 1 Gbit based
module
on 512 Mbit or
smaller dies
Data Sheet 8 Rev. 1.0, 2004-03
HYS64D[32020/16000][H/G]DL–[5/6]–C
Small Outline DDR SDRAM Modules
Table 3 Pin Configuration of SO-DIMM (cont’d)
Pin# Name Pin
Type
30 DQ14 I/O SSTL Data Bus 63:0
32 DQ15 I/O SSTL
41 DQ16 I/O SSTL
43 DQ17 I/O SSTL
49 DQ18 I/O SSTL
53 DQ19 I/O SSTL
42 DQ20 I/O SSTL
44 DQ21 I/O SSTL
50 DQ22 I/O SSTL
54 DQ23 I/O SSTL
55 DQ24 I/O SSTL
59 DQ25 I/O SSTL
65 DQ26 I/O SSTL
67 DQ27 I/O SSTL
56 DQ28 I/O SSTL
60 DQ29 I/O SSTL
66 DQ30 I/O SSTL
68 DQ31 I/O SSTL
127 DQ32 I/O SSTL
129 DQ33 I/O SSTL
135 DQ34 I/O SSTL
139 DQ35 I/O SSTL
128 DQ36 I/O SSTL
130 DQ37 I/O SSTL
136 DQ38 I/O SSTL
140 DQ39 I/O SSTL
141 DQ40 I/O SSTL
145 DQ41 I/O SSTL
151 DQ42 I/O SSTL
153 DQ43 I/O SSTL
142 DQ44 I/O SSTL
146 DQ45 I/O SSTL
152 DQ46 I/O SSTL
154 DQ47 I/O SSTL
163 DQ48 I/O SSTL
165 DQ49 I/O SSTL
171 DQ50 I/O SSTL
175 DQ51 I/O SSTL
164 DQ52 I/O SSTL
166 DQ53 I/O SSTL
Buffer
Type
Function
Pin Configuration
Table 3 Pin Configuration of SO-DIMM (cont’d)
Pin# Name Pin
Type
172 DQ54 I/O SSTL Data Bus 63:0
176 DQ55 I/O SSTL
177 DQ56 I/O SSTL
181 DQ57 I/O SSTL
187 DQ58 I/O SSTL
189 DQ59 I/O SSTL
178 DQ60 I/O SSTL
182 DQ61 I/O SSTL
188 DQ62 I/O SSTL
190 DQ63 I/O SSTL
71 CB0 I/O SSTL Check Bit 0
NC NC – Note: Non-ECC
73 CB1 I/O SSTL Check Bit 1
79 CB2 I/O SSTL Check Bit 2
83 CB3 I/O SSTL Check Bit 3
72 CB4 I/O SSTL Check Bit 4
74 CB5 I/O SSTL Check Bit 5
NC NC – Note: Non-ECC
NC NC – Note: Non-ECC
NC NC – Note: Non-ECC
NC NC – Note: Non-ECC
NC NC – Note: Non-ECC
Buffer
Type
Function
Note: ECC type
module
module
Note: ECC type
module
module
Note: ECC type
module
module
Note: ECC type
module
module
Note: ECC type
module
module
Note: ECC type
module
module
Data Sheet 9 Rev. 1.0, 2004-03
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