infineon CYTVII-B-H-8M-320-CPU User Manual

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CYTVII-B-H-8M-320-CPU Evaluation Board

CYTVII-B-H-8M-320-CPU

User Guide

Evaluation Board User Guide

Document Number: 002-26716 Rev. *A

Cypress Semiconductor

198 Champion Court

San Jose, CA 95134-1709

www.cypress.com

Copyrights

© Cypress Semiconductor Corporation, 2019-2020. This document is the property of Cypress Semiconductor Corporation and its subsidiaries (“Cypress”). This document, including any software or firmware included or referenced in this document (“Software”), is owned by Cypress under the intellectual property laws and treaties of the United States and other countries worldwide. Cypress reserves all rights under such laws and treaties and does not, except as specifically stated in this paragraph, grant any license under its patents, copyrights, trademarks, or other intellectual property rights. If the Software is not accompanied by a license agreement and you do not otherwise have a written agreement with Cypress governing the use of the Software, then Cypress hereby grants you a personal, non-exclusive, nontransferable license (without the right to sublicense) (1) under its copyright rights in the Software (a) for Software provided in source code form, to modify and reproduce the Software solely for use with Cypress hardware products, only internally within your organization, and (b) to distribute the Software in binary code form externally to end users (either directly or indirectly through resellers and distributors), solely for use on Cypress hardware product units, and (2) under those claims of Cypress's patents that are infringed by the Software (as provided by Cypress, unmodified) to make, use, distribute, and import the Software solely for use with Cypress hardware products. Any other use, reproduction, modification, translation, or compilation of the Software is prohibited.

TO THE EXTENT PERMITTED BY APPLICABLE LAW, CYPRESS MAKES NO WARRANTY OF ANY KIND, EXPRESS OR IMPLIED, WITH REGARD TO THIS DOCUMENT OR ANY SOFTWARE OR ACCOMPANYING HARDWARE, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE. No computing device can be absolutely secure. Therefore, despite security measures implemented in Cypress hardware or software products, Cypress shall have no liability arising out of any security breach, such as unauthorized access to or use of a Cypress product. CYPRESS DOES NOT REPRESENT, WARRANT, OR GUARANTEE THAT CYPRESS PRODUCTS, OR SYSTEMS CREATED USING CYPRESS PRODUCTS, WILL BE FREE FROM CORRUPTION, ATTACK, VIRUSES, INTERFERENCE, HACKING, DATA LOSS OR THEFT, OR OTHER SECURITY INTRUSION (collectively, “Security Breach”). Cypress disclaims any liability relating to any Security Breach, and you shall and hereby do release Cypress from any claim, damage, or other liability arising from any Security Breach. In addition, the products described in these materials may contain design defects or errors known as errata which may cause the product to deviate from published specifications. To the extent permitted by applicable law, Cypress reserves the right to make changes to this document without further notice. Cypress does not assume any liability arising out of the application or use of any product or circuit described in this document. Any information provided in this document, including any sample design information or programming code, is provided only for reference purposes. It is the responsibility of the user of this document to properly design, program, and test the functionality and safety of any application made of this information and any resulting product. “High-Risk Device” means any device or system whose failure could cause personal injury, death, or property damage. Examples of High-Risk Devices are weapons, nuclear installations, surgical implants, and other medical devices. “Critical Component” means any component of a High-Risk Device whose failure to perform can be reasonably expected to cause, directly or indirectly, the failure of the High-Risk Device, or to affect its safety or effectiveness. Cypress is not liable, in whole or in part, and you shall and hereby do release Cypress from any claim, damage, or other liability arising from any use of a Cypress product as a Critical Component in a High-Risk Device. You shall indemnify and hold Cypress, its directors, officers, employees, agents, affiliates, distributors, and assigns harmle arising out of any claim, including claims for product liability, personal injury or death, or property damage arising from any use of a Cypress product as a Critical Component in a High-Risk Device. Cypress products are not intended or authorized for use as a Critical Component in any High-Risk Device except to the limited extent that (i) Cypress's published data sheet for the product explicitly states Cypress has qualified the product for use in a specific High-Risk Device, or (ii) Cypress has given you advance written authorization to use the product as a Critical Component in the specific High-Risk Device and you have signed a separate indemnification agreement.

Cypress, the Cypress logo, Spansion, the Spansion logo, and combinations thereof, WICED, PSoC, CapSense, EZ-USB, FRAM, and Traveo are trademarks or registered trademarks of Cypress in the United States and other countries. For a more complete list of Cypress trademarks, visit cypress.com. Other names and brands may be claimed as property of their respective owners.

ss from and against all claims, costs, damages, and expenses,

Disclaimer of Schematics and Layouts: This material constitutes a reference design. CYPRESS MAKES NO WARRANTY OF ANY KIND, EXPRESS OR IMPLIED, WITH REGARD TO THIS MATERIAL, INCLUDING, BUT NOT LIMITED TO. THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE. Cypress reserves the right to make changes without further notice to the materials described herein. Cypress does not assume any liability arising out of the application or use of any product or circuit described herein. Cypress does not authorize its products for use as critical components in life-support systems where a malfunction or failure may reasonably be expected to result in significant injury to the user. The inclusion of Cypress products in a life-support systems application implies that the manufacturer assumes all risk of such use and in doing so indemnifies Cypress against all changes.

CYTVII-B-H-8M-320-CPU Evaluation Board User Guide, Document Number: 002-26716 Rev. *A 2

Safety Information

Regulatory Compliance

This Evaluation Board is intended for use as a development platform for hardware in a laboratory environment. The board is an open system design, which does not include a shielded enclosure. This may cause interference to other electrical or electronic devices in close proximity.

In a domestic environment, this product may cause radio interference. The user may then be required to take adequate prevention measures. Also, the board should not be used near any medical equipment or RF devices.

Attaching additional wiring to this product or modifying the product operation from the factory default may affect its performance and cause interference with other apparatus in the immediate vicinity. If such interference is detected, suitable mitigating measures should be taken.

This Evaluation Board contains electrostatic discharge (ESD) sensitive devices. Electrostatic charges readily accumulate on the human body and any equipment, and can discharge without detection. Permanent damage may occur on devices subjected to high-energy discharges. Proper ESD precautions are recommended to avoid performance degradation or loss of functionality. Store unused this board in the protective shipping package.

General Safety Instructions

ESD Protection

ESD can damage boards and associated components. Cypress recommends that you perform procedures only at an ESD workstation. If an ESD workstation is not available, use appropriate ESD protection by wearing an antistatic wrist strap attached to chassis ground (any unpainted metal surface) on your board when handling parts.

Handling Boards

This board is sensitive to ESD. Hold the board only by its edges. After removing the board from its box, place it on a grounded, static-free surface. Use a conductive foam pad if available. Do not slide board over any surface.

CYTVII-B-H-8M-320-CPU Evaluation Board User Guide, Document Number: 002-26716 Rev. *A 4

1. Introduction

This user guide provides instructions to handle the CYTVII-B-H-8M-320-CPU and CYTVII-B-H-320-SO evaluation boards, collectively referred to as 'CPU board' in this document. This is an evaluation platform for the CYT4BFCC Traveo™ II device. The board can be used as a standalone board for basic validation or in combination with the CYTVII-B-E-BB Traveo II base board (available separately from Cypress). This document assumes that you will work with the combination (CPU board + base board), and provides guidance on how to use the features of the evaluation platform.

1.1 Precautions and Warnings

The board is a delicate PCB; make sure that the evaluation board is handled by qualified personnel who are aware of the capabilities of the board. Handle the board carefully and make sure it is not bent or subjected to stress. Ensure your own safety arising from electrical hazards and other sources.

The CPU board is shipped with a 12 V DC power adapter. This adapter can be plugged into the AC mains supply anywhere in the world and is designed to receive 100-240 V AC V @ 50/60 Hz. While powering the board, you must connect only the power adapter supplied with the evaluation board and not any other part.

CYTVII-B-H-8M-320-CPU Evaluation Board User Guide, Document Number: 002-26716 Rev. *A 5

2. Overview

Figure 2-1 shows the CYTVII-B-H-320-SO board. Insert a Traveo II device into the IC socket (high-

lighted in red) while the evaluation board is powered OFF.

Figure 2-1. CYTVII-B-H-320-SO Board

A variant of the CPU board (CYTVII-B-H-8M-320-CPU) is also available, where the Traveo II device is soldered directly onto the PCB. Functionally, the CYTVII-B-H-8M-320-CPU and CYTVII-B-H-320SO boards are identical, except that the device can be easily replaced in the latter.

The CPU board is meant to be used along with a Traveo II base board (CYTVII-B-E-BB). The base board brings out all important interface connections such as CAN, LIN, SPI EEPROM, CXPI, and FlexRay, and can be used in conjunction with several CPU boards of the Traveo II family. Figure 2-2 shows the base board.

CYTVII-B-H-8M-320-CPU Evaluation Board User Guide, Document Number: 002-26716 Rev. *A 6

Figure 2-2. Traveo II Base Board (CYTVII-B-E-BB)

Overview

Two Samtec connectors on the CPU board and corresponding mating connectors on the base board are used to connect signals across the two boards. When put together, the boards appear as shown in Figure 2-3.

Figure 2-3. Combination of CPU Board and Traveo II Base Board

CYTVII-B-H-8M-320-CPU Evaluation Board User Guide, Document Number: 002-26716 Rev. *A 7

2.1 Functional Overview

The CPU board has the following components:

1. One Traveo II device, either soldered or mounted on a socket (U6).

2. PMIC to generate the 5-V, 3.3-V, and 1.1-V outputs, which power the CPU board and the base board (if connected).

3. Programming interface (Arm ETM Mictor) to connect several programming tools such as IAR I-jet, Green Hills MULTI, also Cypress MiniProg.

4. USB-UART interface for terminal logging (J28).

5. One user switch (SW1) and one user LED (LD1) for standalone operation without the base board.

6. Reset controller with manual reset switch (SW3) and voltage supervision.

7. Measurement of device current on VCCD using jumper J14, VDDD using jumper J17, VDDIO_1 using jumper J16, VDDIO_2 using jumper J18, VDDIO_3 using jumper J21, VDDIO_4 using jumper J20, and VDDA using jumper J19 respectively.

8. Samtec connector interface (J35 and J36) for connecting to the base board CYTVII-B-E-BB.

9. Gigabit Ethernet Interface (J24).

10. Automotive Ethernet(J25)

2

11. I

S Audio Codec (J34)

12. SD Card Connector (U10)

13. HyperFlash and HyperRAM (U15, U14)

14. Dual Quad SPI Flash (U13, U12)

15. 0.10-inch Through-Hole Test Points

Overview

®

Standard JTAG, Cortex® Debug, Cortex Debug + ETM and Arm

The Traveo II base board has the following components:

1. Six CAN-FD transceivers based on TJA1057GT (Dual connectors P6, P7, P8).

2. Four CAN-FD transceivers based on TJA1145T, with SPI-based transceiver configuration (Dual connectors P9, P10).

3. Six LIN transceivers based on TJA1021T (Dual connectors P3, P4, P5).

4. Two FlexRay transceivers based on TJA1081TS (Dual connector P2).

5. One CXPI transceiver based on S6BT112A01 (Connector P1).

6. One SPI EEPROM 25LC320A (U9).

7. Five user switches (SW1 through SW5), 10 user LEDs (USER_LED0 through USER_LED9), and one potentiometer (POT1) for analog input.

8. Pin headers to access all I/Os of the Traveo II device (when a CPU board is connected to the base board).

9. Samtec connector interface (J38 and J84) for connecting to a CPU board.

CYTVII-B-H-8M-320-CPU Evaluation Board User Guide, Document Number: 002-26716 Rev. *A 8

2.1.1 Block Diagram

S6BP501A,

S6BP502A

(PMIC)

Pass Transistor

USB-UA RT

Traveo II

CYT4BF Seri es

320-Pin MCU

eMMC

Connector

SMIF

Connector

Debug

Interfaces

I2S Audio

Interface

3.5mm

Audio Jack

HyperF lash

&

HyperR AM

Dual Qu ad

SPI Flash

Reset

Contro ller

Automotive

Ethernet

D-sub

9 Pin

180 Pin QSH

Connector (Samtec)

J36

180 Pin QSH

Connector (Samtec)

J35

180 Pin QTH

Connector (Samtec)

J84

180 Pin QTH

Connector (Samtec)

J38

CYTVII-B-H-8M-320pin CPU Board

Traveo II

Base Board

0.100" Through Hole Test Points

Gigabit

Ethernet

RJ45

The block diagram is shown in Figure 2-4.

Figure 2-4. Block Diagram

Overview

CYTVII-B-H-8M-320-CPU Evaluation Board User Guide, Document Number: 002-26716 Rev. *A 9

2.1.2 Through-Hole Test Points

The location of the Through-Hole Test Points is shown in Figure 2-5.

Figure 2-5. Through-Hole Test Points

Overview

CYTVII-B-H-8M-320-CPU Evaluation Board User Guide, Document Number: 002-26716 Rev. *A 10

2.1.3 USB Connector

The location of the USB connector is shown in Figure 2-6.

Figure 2-6. USB Connector

Overview

CYTVII-B-H-8M-320-CPU Evaluation Board User Guide, Document Number: 002-26716 Rev. *A 11

2.1.4 Ethernet Connector (Automotive Ethernet)

The location of the Ethernet connector (Automotive Ethernet) is shown in Figure 2-7.

Figure 2-7. Ethernet Connector (Automotive Ethernet)

Overview

CYTVII-B-H-8M-320-CPU Evaluation Board User Guide, Document Number: 002-26716 Rev. *A 12

2.1.5 Ethernet Connector (Gigabit Ethernet)

The location of the Ethernet connector (Gigabit Ethernet) is shown in Figure 2-8.

Figure 2-8. Ethernet Connector (Gigabit Ethernet)

Overview

CYTVII-B-H-8M-320-CPU Evaluation Board User Guide, Document Number: 002-26716 Rev. *A 13

2.1.6 On-board SMIF Devices

The location of the onboard SMIF devices in shown in Figure 2-9.

Figure 2-9. SMIF Connector

Overview

CYTVII-B-H-8M-320-CPU Evaluation Board User Guide, Document Number: 002-26716 Rev. *A 14

2.1.7 SD Card Connector

The location of the SD Card connector is shown in Figure 2-10.

Figure 2-10. eMMC Connector

Overview

CYTVII-B-H-8M-320-CPU Evaluation Board User Guide, Document Number: 002-26716 Rev. *A 15

2.1.8 Audio Connector

The location of the audio connector is shown in Figure 2-11.

Figure 2-11. Audio Connector

Overview

CYTVII-B-H-8M-320-CPU Evaluation Board User Guide, Document Number: 002-26716 Rev. *A 16

3. Operation

This section describes the operation of the CPU board and the base board. It is assumed that you have connected the CPU board to the base board using the Samtec interface and inserted a Traveo II device into the IC socket (applicable to CYTVII-B-H-320-SO boards only). Follow these steps to operate the CPU board and the base board:

1. For the socketed CPU board, ensure that the device is inserted into the socket. Remove the four screws on the socket using the screwdriver provided in the box and open the socket cover. If the device is not present, place one carefully using a vacuum picker or a pair of tweezers.

2. Ensure that pin 1 of the device is near the pin 1 marking on the PCB, as shown in Figure 3-1. Also ensure that the device is placed in an angle such that the pins on all four sides of the FBGA package match well with the socket pins. Align the device slightly, if required.

Figure 3-1. Orientation of Device when Inserted in Socket

3. Replace the socket cover and fix the four screws so that the socket cover tightly sits on the socket base.

4. A 12 V wall adapter board is supplied along with the CPU board. Connect the 12 V wall adapter to the barrel connector marked “12V DC” on the CPU board. Connect its plug to a mains socket using one of the four plug adapters provided in the white box (depending on the geographical location and the socket type available).

5. Ensure that jumpers J16, J17, J18, J19 (position “1-2”), J14, J20, J21 (current measurement jumpers) are inserted on the CPU board.

6. Turn on the mains supply to the wall adapter. Turn on the switch SW2 on the CPU board. The LED labeled PWR should light up.

CYTVII-B-H-8M-320-CPU Evaluation Board User Guide, Document Number: 002-26716 Rev. *A 17

Operation

7. Connect an appropriate programming tool to one of the programming interfaces (J13, J4, J12, J5). Programming tool options are:

❐ Arm ETM MICTOR on J13

❐ Cortex DEBUG on J4

❐ Arm Standard JTAG on J12

❐ Cortex DEBUG and ETM on J5

8. Install the appropriate programming integrated development environment (IDE) on a PC. The programming IDE (GHS MULTI, IAR Embedded Workbench, Cypress Programmer, etc.) should be able to detect a device (read the device ID) and to load a firmware HEX file (.srec) into the device flash successfully. As part of the release package, various firmware examples compiled in .srec programming IDEs are available. Some examples use specific transceivers on the base board.

9. To start with, use the LED blink example provided with the release package to test the functioning of the board.

10. Connect a USB-mini cable to J28 and the other end to a PC. Open Tera Term or your preferred terminal logging application and set the appropriate port and baud rate (typically 115,200 baud, 8, N, 1). Ensure that jumpers J30 and J31 are inserted on the CPU board. Some firmware examples provide data logs from the device or ask for user inputs over the terminal.

CYTVII-B-H-8M-320-CPU Evaluation Board User Guide, Document Number: 002-26716 Rev. *A 18

4. Connections and Settings

4.1 Evaluation Board Connections

4.1.1 Base Board Connections

Make sure that the following jumpers are inserted on the base board, so that each transceiver on the base board can be used with the respective firmware example that activate each functionality of the device:

■ CAN1.4 from the device uses the CAN0 transceiver on the base board (connect jumpers J70,

J71, J72).

■ CAN1.3 from the device uses the CAN1 transceiver on the base board (connect jumpers J66,

J67, J68).

■ CAN0.2 from the device uses the CAN2 transceiver on the base board (connect jumpers J81,

J82, J83).

■ CAN1.0 from the device uses the CAN3 transceiver on the base board (connect jumpers J76,

J77, J78).

■ CAN1.2 from the device uses the CAN4 transceiver on the base board (connect jumpers J91,

J92, J93).

■ CAN1.1 from the device uses the CAN6 transceiver on the base board (connect jumpers J86,

J87, J88).

■ LIN0 from the device uses the LIN0 transceiver on the base board (connect jumpers J58, J59,

J60, J63).

■ LIN6 from the device uses the LIN1 transceiver on the base board (connect jumpers J51, J52,

J53, J56).

■ LIN8 from the device uses the LIN2 transceiver on the base board (connect jumpers J37, J39,

J40, J43).

■ LIN7 from the device uses the LIN3 transceiver on the base board (connect jumpers J30, J31,

J32, J35).

■ LIN10 from the device uses the LIN4 transceiver on the base board (connect jumpers J22, J23,

J24, J27).

■ LIN5 from the device uses the LIN5 transceiver on the base board (connect jumpers J10, J16,

J17, J20).

■ EEPROM on the base board is enabled by connecting jumpers J47, J48, J49.

■ The user switch functionality is enabled by connecting jumper J102.

■ The potentiometer functionality is enabled by connecting jumper J89.

CYTVII-B-H-8M-320-CPU Evaluation Board User Guide, Document Number: 002-26716 Rev. *A 19

4.1.2 CPU Board Connections

■ Gigabit Ethernet on the CPU board is enabled for GMII and RGMII mode by shorting the jumpers

R127 and R149. R316 should be open. For MII mode, by shorting the jumper R316. R127 and R149 should be open.

■ Automotive Ethernet on the CPU Board is enabled for RMII mode by shorting jumper R107. For

MII mode, R107 should be open.

■ SMIF - Dual Quad SPI on the CPU Board is enabled by shorting jumpers R190 and R191.

■ SMIF - HyperFlash and HyperRAM on the CPU Board is enabled by shorting jumpers R189 and

R193.

■ SD Card Connector on the CPU board is always enabled.

■ I2S Audio Codec on the CPU board is always enabled.

In addition, power is supplied to the base board by connecting jumper J80 to the 3 V or 5 V select jumper pin in the ‘5 V’ position. Make sure that jumper J80 is always connected. Once a specific functionality is chosen by connecting the jumpers listed above, ensure that the appropriate firmware is loaded onto the device. Incorrect firmware can result in port pins being configured incorrectly leading to bus contention and damage to hardware. For example, if you connect jumpers related to CAN0.0, you must ensure that firmware configures the related ports as CAN pins. Contact Cypress technical support for firmware examples.

Connections and Settings

Apart from these interface transceivers that can be used for specific functions, all pins of the device are also accessible on the base board using pin headers JP1 through JP12.

The device port pins are connected to pin headers on the CPU board as listed in Ta ble 4 -1 .

CYTVII-B-H-8M-320-CPU Evaluation Board User Guide, Document Number: 002-26716 Rev. *A 20

Connections and Settings

Table 4-1. Device Port Pin Connections on CPU Board

Pin Order Pad Pin Text Test Point Connection 1 Connection 2 Connection 3

1 J20 DRV_VOUT R34.1 DRV_VOUT

2A18

3B18

4B17

5C17

6A17

7A16

8B16

9C16

10 C15

11 E15 P1_5/LIN8_TX/SCB8_TX/SCB8_SDA/SCB8_MOSI P1.6 GPIO_P1_5

12 F14 P1_6/LIN8_EN/SCB8_RTS/SCB8_SCL/SCB8_CLK P1.10 GPIO_P1_6

13 A15

14 B15

15 A14

16 B14

17 C14

18 E14

19 C13 P2_6/PWM1_72/PWM1_71_N/TC1_72_TR0/TC1_71_TR1/SCB8_CTS/SCB8_SEL0 P6.6 BB_LIN2_WAKE

20 E13 P2_7/PWM1_73/PWM1_72_N/TC1_73_TR0/TC1_72_TR1/SCB8_SEL1/LIN11_RX P5.12 BB_USER_LED9

21 A13

P0_0/PWM1_18/PWM1_22_N/TC1_18_TR0/TC1_22_TR1/PWM0_H_0/SCB0_RX/ SCB7_SDA/SCB0_MISO/LIN1_RX

P0_1/PWM1_17/PWM1_18_N/TC1_17_TR0/TC1_18_TR1/PWM0_H_0_N/ SCB0_TX/SCB7_SCL/SCB0_MOSI/LIN1_TX

P0_2/PWM1_14/PWM1_17_N/TC1_14_TR0/TC1_17_TR1/TC0_H_0_TR0/ SCB0_RTS/SCB0_SCL/SCB0_CLK/SCB4_MISO/LIN1_EN/CAN0_1_TX

P0_3/PWM1_13/PWM1_14_N/TC1_13_TR0/TC1_14_TR1/TC0_H_0_TR1/ SCB0_CTS/SCB0_SDA/SCB0_SEL0/SCB4_MOSI/CAN0_1_RX

P1_0/PWM1_12/PWM1_13_N/TC1_12_TR0/TC1_13_TR1/PWM1_H_4/SCB0_SCL/ SCB0_MISO/SCB4_CLK

P1_1/PWM1_11/PWM1_12_N/TC1_11_TR0/TC1_12_TR1/PWM1_H_5/SCB0_SDA/ SCB0_MOSI/SCB4_SEL0

P1_2/PWM1_10/PWM1_11_N/TC1_10_TR0/TC1_11_TR1/PWM1_H_6/SCB0_CLK/ LIN0_RX/TRIG_IN[0]

P1_3/PWM1_8/PWM1_10_N/TC1_8_TR0/TC1_10_TR1/PWM1_H_7/SCB0_SEL0/ LIN0_TX/TRIG_IN[1]

P1_4/PWM1_71/PWM1_70_N/TC1_71_TR0/TC1_70_TR1/LIN8_RX/SCB8_RX/ SCB8_MISO

P2_0/PWM1_7/PWM1_8_N/TC1_7_TR0/TC1_8_TR1/TC1_H_4_TR0/SCB7_RX/ SCB0_SEL1/SCB7_MISO/LIN0_RX/CAN0_0_TX/SWJ_TRSTN/TRIG_IN[2]

P2_1/PWM1_6/PWM1_7_N/TC1_6_TR0/TC1_7_TR1/TC1_H_5_TR0/SCB7_TX/ SCB7_SDA/SCB0_SEL2/SCB7_MOSI/LIN0_TX/CAN0_0_RX/TRIG_IN[3]

P2_2/PWM1_5/PWM1_6_N/TC1_5_TR0/TC1_6_TR1/ETH0_RX_ER/ TC1_H_6_TR0/SCB7_RTS/SCB7_SCL/SCB0_SEL3/SCB7_CLK/LIN0_EN/ TRIG_IN[4]

P2_3/PWM1_4/PWM1_5_N/TC1_4_TR0/TC1_5_TR1/ETH0_ETH_TSU_TIMER_CMP_VAL/TC1_H_7_TR0/SCB7_CTS/SCB7_SEL0/LIN5_RX/TRIG_IN[5]

P2_4/PWM1_3/PWM1_4_N/TC1_3_TR0/TC1_4_TR1/PWM1_H_4_N/SCB7_SEL1/ LIN5_TX/TRIG_IN[6]

P2_5/PWM1_2/PWM1_3_N/TC1_2_TR0/TC1_3_TR1/PWM1_H_5_N/SCB7_SEL2/ LIN5_EN/TRIG_IN[7]

P3_0/PWM1_1/PWM1_2_N/TC1_1_TR0/TC1_2_TR1/ETH0_MDIO/PWM1_H_6_N/ SCB6_RX/SCB6_MISO/CAN0_3_TX/TRIG_DBG[0]

J52.2 GPIO_P0_0

P14.2 GPIO_P0_1

P14.7 GPIO_P0_2

P14.4 GPIO_P0_3

P13.7 BB_CAN5_S

P13.9 BB_CAN4_S

P6.9 BB_LIN0_RXD

P6.10 BB_LIN5_WAKE

P6.8 BB_LIN4_WAKE

J13.21 TRSTN_PRM

P14.9 GPIO_P2_1

P10.13 AUTO_ETH_RXER_R

P14.12 GPIO_P2_3

P6.7 BB_LIN3_WAKE

P1.11 GPIO_P2_5

P10.15 AUTO_ETH_MDIO_R

CYTVII-B-H-8M-320-CPU Evaluation Board User Guide, Document Number: 002-26716 Rev. *A 21

Connections and Settings

Table 4-1. Device Port Pin Connections on CPU Board (continued)

Pin Order Pad Pin Text Test Point Connection 1 Connection 2 Connection 3

22 B13

23 A12

24 B12

25 C12

26 E12

27 C11

28 E11 P3_7/PWM1_75/PWM1_74_N/TC1_75_TR0/TC1_74_TR1/LIN11_EN/CAN1_2_RX P5.10 BB_USER_LED7

29 A9

30 A8

31 B8

32 C8

33 E8

34 A7 P4_5/SCB9_RX/SCB9_MISO/TRIG_IN[32] P8.2 BB_CAN0_S

35 B7 P4_6/SCB9_TX/SCB9_SDA/SCB9_MOSI/TRIG_IN[33] P8.13 BB_CXPI_CLK

36 A5

37 B5

38 C5

39 A4

40 B4

41 C4

42 A3

P3_1/PWM1_0/PWM1_1_N/TC1_0_TR0/TC1_1_TR1/ETH0_MDC/PWM1_H_7_N/ SCB6_TX/SCB6_SDA/SCB6_MOSI/CAN0_3_RX/TRIG_DBG[1]

P3_2/PWM1_M_3/PWM1_0_N/TC1_M_3_TR0/TC1_0_TR1/TC1_H_4_TR1/ SCB6_RTS/SCB6_SCL/SCB6_CLK

P3_3/PWM1_M_2/PWM1_M_3_N/TC1_M_2_TR0/TC1_M_3_TR1/TC1_H_5_TR1/ SCB6_CTS/SCB6_SEL0

P3_4/PWM1_M_1/PWM1_M_2_N/TC1_M_1_TR0/TC1_M_2_TR1/TC1_H_6_TR1/ SCB6_SEL1/LIN1_RX

P3_5/PWM1_M_0/PWM1_M_1_N/TC1_M_0_TR0/TC1_M_1_TR1/TC1_H_7_TR1/ SCB6_SEL2/LIN1_TX

P3_6/PWM1_74/PWM1_73_N/TC1_74_TR0/TC1_73_TR1/SCB8_SEL2/LIN11_TX/ CAN1_2_TX

P4_0/PWM1_4/PWM1_M_0_N/TC1_4_TR0/TC1_M_0_TR1/EXT_MUX[0]_0/ SCB5_RX/SCB5_MISO/LIN1_RX/TRIG_IN[10]

P4_1/PWM1_5/PWM1_4_N/TC1_5_TR0/TC1_4_TR1/EXT_MUX[0]_1/SCB5_TX/ SCB5_SDA/SCB5_MOSI/LIN1_TX/TRIG_IN[11]

P4_2/PWM1_6/PWM1_5_N/TC1_6_TR0/TC1_5_TR1/EXT_MUX[0]_2/SCB5_RTS/ SCB5_SCL/SCB5_CLK/LIN1_EN/TRIG_IN[12]

P4_3/PWM1_7/PWM1_6_N/TC1_7_TR0/TC1_6_TR1/EXT_MUX[0]_EN/SCB5_CTS/ SCB5_SEL0/CAN0_1_TX/TRIG_IN[13]

P4_4/PWM1_8/PWM1_7_N/TC1_8_TR0/TC1_7_TR1/LIN15_RX/SCB5_SEL1/ CAN0_1_RX

P5_0/PWM1_9/PWM1_8_N/TC1_9_TR0/TC1_8_TR1/PWM0_M_0/PWM1_H_10/ LIN15_TX/SCB5_SEL2/LIN7_RX/TRIG_IN[38]

P5_1/PWM1_10/PWM1_9_N/TC1_10_TR0/TC1_9_TR1/PWM0_M_0_N/ PWM1_H_10_N/SCB9_SEL3/LIN7_TX/TRIG_IN[39]

P5_2/PWM1_11/PWM1_10_N/TC1_11_TR0/TC1_10_TR1/TC0_M_0_TR0/ TC1_H_10_TR0/LIN10_RX/LIN7_EN

P5_3/PWM1_12/PWM1_11_N/TC1_12_TR0/TC1_11_TR1/TC0_M_0_TR1/ TC1_H_10_TR1/LIN10_TX/LIN2_RX

P5_4/PWM1_13/PWM1_12_N/TC1_13_TR0/TC1_12_TR1/LIN9_RX/PWM1_H_11/ LIN2_TX

P5_5/PWM1_14/PWM1_13_N/TC1_14_TR0/TC1_13_TR1/LIN9_TX/ PWM1_H_11_N/LIN2_EN

P6_0/PWM1_M_0/PWM1_14_N/TC1_M_0_TR0/TC1_14_TR1/PWM0_0/LIN9_EN/ TC1_H_11_TR0/SCB4_RX/SCB4_MISO/LIN3_RX/ADC[0]_0

P10.16 AUTO_ETH_MDC_R

P13.13 BB_CAN3_S

P5.16 BB_CXPI_TXD

P5.13 BB_LIN1_WAKE

P5.11 BB_USER_LED8

P5.15 BB_LIN0_WAKE

P15.9 BB_SPI0_MISO

P15.12 BB_SPI0_MOSI

P14.1 BB_SPI0_CLK

P14.11 BB_SPI0_SS0

P15.11 AUDIO_SPI0_SS1

P15.4 GPIO_P5_0

P15.3 GPIO_P5_1

P15.2 GPIO_P5_2

P15.6 GPIO_P5_3

P14.13 BB_CAN8_WAKE

P8.12 BB_FRB_ERRN

P15.5 GPIO_P6_0

CYTVII-B-H-8M-320-CPU Evaluation Board User Guide, Document Number: 002-26716 Rev. *A 22

Connections and Settings

Table 4-1. Device Port Pin Connections on CPU Board (continued)

Pin Order Pad Pin Text Test Point Connection 1 Connection 2 Connection 3

43 B3

44 A2

45 B1

46 B2

47 C1

48 C2

49 D1 P6_7/PWM1_3/PWM1_M_3_N/TC1_3_TR0/TC1_M_3_TR1/TRIG_IN[9]/ADC[0]_7 P3.14

50 F1

51 F2

52 G1

53 G2

54 G3

55 G5

56 G6

57 H5

58 H1

59 H2

60 H3

P6_1/PWM1_0/PWM1_M_0_N/TC1_0_TR0/TC1_M_0_TR1/TC1_H_11_TR1/ SCB4_TX/SCB4_SDA/SCB4_MOSI/LIN3_TX/ADC[0]_1

P6_2/PWM1_M_1/PWM1_0_N/TC1_M_1_TR0/TC1_0_TR1/PWM0_0_N/SDHC_CARD_MECH_WRITE_PROT/PWM1_H_12/SCB4_RTS/SCB4_SCL/SCB4_CLK/ LIN3_EN/CAN0_2_TX/ADC[0]_2

P6_3/PWM1_1/PWM1_M_1_N/TC1_1_TR0/TC1_M_1_TR1/SPIHB_CLK/SDHC_CARD_CMD/PWM1_H_12_N/SCB4_CTS/SCB4_SEL0/LIN4_RX/CAN0_2_RX/ CAL_SUP_NZ/ADC[0]_3

P6_4/PWM1_M_2/PWM1_1_N/TC1_M_2_TR0/TC1_1_TR1/TC0_0_TR0/SPIHB_RWDS/SDHC_CLK_CARD/TC1_H_12_TR0/SCB4_SEL1/LIN4_TX/ADC[0]_4

P6_5/PWM1_2/PWM1_M_2_N/TC1_2_TR0/TC1_M_2_TR1/TC0_0_TR1/SPIHB_SEL0/SDHC_CARD_DETECT_N/TC1_H_12_TR1/SCB4_SEL2/LIN4_EN/ADC[0]_5

P6_6/PWM1_M_3/PWM1_2_N/TC1_M_3_TR0/TC1_2_TR1/SCB4_SEL3/ TRIG_IN[8]/ADC[0]_6

P7_0/PWM1_M_4/PWM1_3_N/TC1_M_4_TR0/TC1_3_TR1/PWM0_1/SPIHB_SEL1/ SDHC_CARD_IF_PWR_EN/SCB5_RX/SCB5_MISO/LIN4_RX/ADC[0]_16

P7_1/PWM1_15/PWM1_M_4_N/TC1_15_TR0/TC1_M_4_TR1/SPIHB_DATA0/SDHC_CARD_DAT_3TO0_0/SCB5_TX/SCB5_SDA/SCB5_MOSI/LIN4_TX/ADC[0]_17

P7_2/PWM1_M_5/PWM1_15_N/TC1_M_5_TR0/TC1_15_TR1/PWM0_1_N/SPIHB_DATA1/SDHC_CARD_DAT_3TO0_1/SCB5_RTS/SCB5_SCL/SCB5_CLK/LIN4_EN/ ADC[0]_18

P7_3/PWM1_16/PWM1_M_5_N/TC1_16_TR0/TC1_M_5_TR1/TC0_1_TR0/SPIHB_DATA2/SDHC_CARD_DAT_3TO0_2/SCB5_CTS/SCB5_SEL0/CAN0_4_TX/ ADC[0]_19

P7_4/PWM1_M_6/PWM1_16_N/TC1_M_6_TR0/TC1_16_TR1/TC0_1_TR1/SPIHB_DATA3/SDHC_CARD_DAT_3TO0_3/SCB5_SEL1/CAN0_4_RX/ADC[0]_20

P7_5/PWM1_17/PWM1_M_6_N/TC1_17_TR0/TC1_M_6_TR1/PWM0_H_2/SPIHB_DATA4/SDHC_CARD_DAT_7TO4_0/LIN10_RX/SCB5_SEL2/ADC[0]_21

P7_6/PWM1_M_7/PWM1_17_N/TC1_M_7_TR0/TC1_17_TR1/LIN10_TX/ TRIG_IN[16]/ADC[0]_22

P7_7/PWM1_18/PWM1_M_7_N/TC1_18_TR0/TC1_M_7_TR1/LIN10_EN/ TRIG_IN[17]/ADC[0]_23

P8_0/PWM1_19/PWM1_18_N/TC1_19_TR0/TC1_18_TR1/PWM0_H_2_N/SPIHB_DATA5/SDHC_CARD_DAT_7TO4_1/PWM1_H_8/LIN2_RX/CAN0_0_TX

P8_1/PWM1_20/PWM1_19_N/TC1_20_TR0/TC1_19_TR1/TC0_H_2_TR0/SPIHB_DATA6/SDHC_CARD_DAT_7TO4_2/PWM1_H_8_N/LIN2_TX/CAN0_0_RX/ TRIG_IN[14]/ADC[0]_24

P8_2/PWM1_21/PWM1_20_N/TC1_21_TR0/TC1_20_TR1/TC0_H_2_TR1/SPIHB_DATA7/SDHC_CARD_DAT_7TO4_3/TC1_H_8_TR0/LIN2_EN/TRIG_IN[15]/ ADC[0]_25

P15.8 GPIO_P6_1

P16.2 EMMC_WP

P16.3 GPIO_P6_3 EMMC_CMD BB_CAN2_RXD

P16.4 GPIO_P6_4 EMMC_CLK BB_CAN7_WAKE

P16.1 EMMC_CD

P8.10 BB_FRA_WAKE

BB_USER_BUTTON_1

P16.15 GPIO_P7_0

P16.6 EMMC_DATA0

P16.5 EMMC_DATA1

P16.8 EMMC_DATA2

P16.7 EMMC_DATA3

P16.10 GPIO_P7_5

P5.3 BB_LIN4_TXD

P5.2 BB_LIN4_SLP

P15.1 GPIO_P8_0

P16.14 GPIO_P8_1

P17.2 GPIO_P8_2

CYTVII-B-H-8M-320-CPU Evaluation Board User Guide, Document Number: 002-26716 Rev. *A 23

Connections and Settings

Table 4-1. Device Port Pin Connections on CPU Board (continued)

Pin Order Pad Pin Text Test Point Connection 1 Connection 2 Connection 3

61 J1

62 J2

63 K1

64 K2

65 J3

66 J5

67 K5

68 L5

69 M5

70 N5

71 R1

72 R2

73 R3

74 T1

75 P5

76 P6

77 R5

78 T2

79 T3

P8_3/PWM1_22/PWM1_21_N/TC1_22_TR0/TC1_21_TR1/TC1_H_8_TR1/ LIN16_RX/TRIG_DBG[0]/ADC[0]_26

P8_4/PWM1_23/PWM1_22_N/TC1_23_TR0/TC1_22_TR1/LIN16_TX/TRIG_DBG[1]/ ADC[0]_27

P9_0/PWM1_24/PWM1_23_N/TC1_24_TR0/TC1_23_TR1/PWM1_H_9/LIN16_EN/ ADC[0]_28

P9_1/PWM1_25/PWM1_24_N/TC1_25_TR0/TC1_24_TR1/PWM1_H_9_N/ LIN12_RX/ADC[0]_29

P9_2/PWM1_26/PWM1_25_N/TC1_26_TR0/TC1_25_TR1/TC1_H_9_TR0/ LIN12_TX/ADC[0]_30

P9_3/PWM1_27/PWM1_26_N/TC1_27_TR0/TC1_26_TR1/TC1_H_9_TR1/ LIN12_EN/ADC[0]_31

P10_0/PWM1_28/PWM1_27_N/TC1_28_TR0/TC1_27_TR1/PWM1_H_10/ SCB4_RX/SCB4_MISO/LIN7_RX/TRIG_IN[18]

P10_1/PWM1_29/PWM1_28_N/TC1_29_TR0/TC1_28_TR1/PWM1_H_10_N/ SCB4_TX/SCB4_SDA/SCB4_MOSI/LIN7_TX/TRIG_IN[19]

P10_2/PWM1_30/PWM1_29_N/TC1_30_TR0/TC1_29_TR1/LIN8_RX/ TC1_H_10_TR0/SCB4_RTS/SCB4_SCL/SCB4_CLK/FLEXRAY_RXDA

P10_3/PWM1_31/PWM1_30_N/TC1_31_TR0/TC1_30_TR1/LIN8_TX/ TC1_H_10_TR1/SCB4_CTS/SCB4_SEL0/FLEXRAY_TXDA

P10_4/PWM1_32/PWM1_31_N/TC1_32_TR0/TC1_31_TR1/LIN8_EN/PWM1_H_11/ SCB4_SEL1/FLEXRAY_TXENA_N/ADC[1]_0

P10_5/PWM1_33/PWM1_32_N/TC1_33_TR0/TC1_32_TR1/PWM1_H_11_N/ SCB4_SEL2/LIN13_RX/FLEXRAY_RXDB/ADC[1]_1

P10_6/PWM1_33_N/TC1_33_TR1/PWM1_34/TC1_H_11_TR0/TC1_34_TR0/ LIN13_TX/FLEXRAY_TXDB/ADC[1]_2

P10_7/PWM1_35/PWM1_34_N/TC1_35_TR0/TC1_34_TR1/TC1_H_11_TR1/ LIN13_EN/FLEXRAY_TXENB_N/ADC[1]_3

P11_0/PWM1_61/PWM1_62_N/TC1_61_TR0/TC1_62_TR1/AUDIOSS0_MCLK/ ADC[0]_M

P11_1/PWM1_60/PWM1_61_N/TC1_60_TR0/TC1_61_TR1/AUDIOSS0_TX_SCK/ ADC[1]_M

P11_2/PWM1_59/PWM1_60_N/TC1_59_TR0/TC1_60_TR1/AUDIOSS0_TX_WS/ ADC[2]_M

P12_0/PWM1_36/TC1_36_TR0/PWM0_H_1/PWM1_35_N/AUDIOSS0_TX_SDO/ SCB8_RX/TC1_35_TR1/SCB8_MISO/CAN0_2_TX/TRIG_IN[20]/ADC[1]_4

P12_1/PWM1_37/PWM1_36_N/TC1_37_TR0/TC1_36_TR1/PWM0_H_1_N/ AUDIOSS0_CLK_I2S_IF/SCB8_TX/SCB8_SDA/SCB8_MOSI/LIN6_EN/ CAN0_2_RX/TRIG_IN[21]/ADC[1]_5

P15.16 GPIO_P8_3

P15.13 GPIO_P8_4

P16.11 GPIO_P9_0

P15.15 GPIO_P9_1

P17.6 GPIO_P9_2

P16.16 GPIO_P9_3

P1.14 GPIO_P10_0

P16.13 GPIO_P10_1

P13.4 BB_FRA_RXD

P13.2 BB_FRA_TXD

P4.12 BB_FRA_TXEN

P4.11 BB_FRB_RXD

P3.3 BB_FRB_TXD

P4.14 BB_FRB_TXEN

AUDIO_0_I2S_MCLK

AUDIO_0_I2S_TX_SCK

AUDIO_0_I2S_TX_WS

P14.8 GPIO_P12_0

P4.10 GPIO_P12_1

AUDIO_0_I2S_TX_SDO

AUDIO_0_CLK_I2S_IF

BB_CAN2_TXD

BB_LIN1_SLP

CYTVII-B-H-8M-320-CPU Evaluation Board User Guide, Document Number: 002-26716 Rev. *A 24

Connections and Settings

Table 4-1. Device Port Pin Connections on CPU Board (continued)

Pin Order Pad Pin Text Test Point Connection 1 Connection 2 Connection 3

80 U1

81 U2

82 U3

83 V1

84 V2 P12_6/PWM1_42/PWM1_41_N/TC1_42_TR0/TC1_41_TR1/ADC[1]_10 P8.7 BB_ADC_POT

85 W1 P12_7/PWM1_43/PWM1_42_N/TC1_43_TR0/TC1_42_TR1/ADC[1]_11 P16.12 GPIO_P12_7_R

86 Y2

87 W2

88 Y3

89 W3

90 Y4

91 W4

92 Y5

93 W5

94 V5

95 T5

96 Y6

97 W6

98 V6

P12_2/PWM1_38/PWM1_37_N/TC1_38_TR0/TC1_37_TR1/TC0_H_1_TR0/ AUDIOSS0_RX_SCK/EXT_MUX[1]_EN/SCB8_RTS/SCB8_SCL/SCB8_CLK/ LIN6_RX/ADC[1]_6

P12_3/PWM1_39/PWM1_38_N/TC1_39_TR0/TC1_38_TR1/TC0_H_1_TR1/ AUDIOSS0_RX_WS/EXT_MUX[1]_0/SCB8_CTS/SCB8_SEL0/LIN6_TX/ADC[1]_7

P12_4/PWM1_40/PWM1_39_N/TC1_40_TR0/TC1_39_TR1/TC0_2_TR1/ AUDIOSS0_RX_SDI/EXT_MUX[1]_1/SCB8_SEL1/CAN1_1_TX/ADC[1]_8

P12_5/PWM1_41/PWM1_40_N/TC1_41_TR0/TC1_40_TR1/EXT_MUX[1]_2/ CAN1_1_RX/ADC[1]_9

P13_0/PWM1_M_8/PWM1_43_N/TC1_M_8_TR0/TC1_43_TR1/TC0_2_TR0/ AUDIOSS1_MCLK/EXT_MUX[2]_0/SCB3_RX/LIN3_RX/SCB3_MISO/ADC[1]_12

P13_1/PWM1_44/PWM1_M_8_N/TC1_44_TR0/TC1_M_8_TR1/PWM0_2_N/ AUDIOSS1_TX_SCK/EXT_MUX[2]_1/SCB3_TX/SCB3_SDA/LIN3_TX/SCB3_MOSI/ ADC[1]_13

P13_2/PWM1_M_9/PWM1_44_N/TC1_M_9_TR0/TC1_44_TR1/PWM0_2/ AUDIOSS1_TX_WS/EXT_MUX[2]_2/SCB3_RTS/SCB3_SCL/LIN3_EN/SCB3_CLK/ ADC[1]_14

P13_3/PWM1_45/PWM1_M_9_N/TC1_45_TR0/TC1_M_9_TR1/AUDIOSS1_TX_SDO/EXT_MUX[2]_EN/SCB3_CTS/LIN2_RX/SCB3_SEL0/ADC[1]_15

P13_4/PWM1_M_10/PWM1_45_N/TC1_M_10_TR0/TC1_45_TR1/LIN8_RX/ AUDIOSS1_CLK_I2S_IF/PWM1_H_4/LIN2_TX/SCB3_SEL1/ADC[1]_16

P13_5/PWM1_46/PWM1_M_10_N/TC1_46_TR0/TC1_M_10_TR1/LIN8_TX/ AUDIOSS1_RX_SCK/PWM1_H_4_N/SCB3_SEL2/ADC[1]_17

P13_6/PWM1_M_11/PWM1_46_N/TC1_M_11_TR0/TC1_46_TR1/LIN8_EN/ AUDIOSS1_RX_WS/PWM1_H_5/SCB3_SEL3/TRIG_IN[22]/ADC[1]_18

P13_7/PWM1_47/PWM1_M_11_N/TC1_47_TR0/TC1_M_11_TR1/AUDIOSS1_RX_SDI/PWM1_H_5_N/TRIG_IN[23]/ADC[1]_19

P14_0/PWM1_48/PWM1_47_N/TC1_48_TR0/TC1_47_TR1/PWM0_M_1/ AUDIOSS2_MCLK/PWM1_H_6/SCB2_MISO/SCB2_RX/CAN1_0_TX/ADC[1]_20

P14_1/PWM1_49/PWM1_48_N/TC1_49_TR0/TC1_48_TR1/PWM0_M_1_N/ AUDIOSS2_TX_SCK/PWM1_H_6_N/SCB2_MOSI/SCB2_SDA/SCB2_TX/ CAN1_0_RX/ADC[1]_21

P14_2/PWM1_50/PWM1_49_N/TC1_50_TR0/TC1_49_TR1/TC0_M_1_TR0/ PWM1_H_7/SCB2_CLK/SCB2_SCL/SCB2_RTS/LIN6_RX/ADC[1]_22

P14_3/PWM1_51/PWM1_50_N/TC1_51_TR0/TC1_50_TR1/TC0_M_1_TR1/ PWM1_H_7_N/SCB2_SEL0/SCB2_CTS/LIN6_TX/ADC[1]_23

P14_4/PWM1_52/PWM1_51_N/TC1_52_TR0/TC1_51_TR1/AUDIOSS2_TX_WS/ TC1_H_4_TR0/SCB2_SEL1/LIN6_EN/ADC[1]_24

P4.5 GPIO_P12_2

P3.2 GPIO_P12_3

AUDIO_0_I2S_RX_SDI

P16.9 GPIO_P12_5_R

P15.7 GPIO_P13_0 AUDIO_1_I2S_MCLK UART_RX

J47.2 GPIO_P13_1

P8.9 GPIO_P13_2

P15.14 GPIO_P13_3

P8.1 GPIO_P13_4

P8.3 GPIO_P13_5

P8.5 GPIO_P13_6

AUDIO_1_I2S_RX_SDI

P11.15 GPIO_P14_0

P4.4 BB_I2C1_SDA

P4.13 BB_I2C1_SCL

P11.14 GPIO_P14_3

P11.16 GPIO_P14_4

AUDIO_0_I2S_RX_SCK

AUDIO_0_I2S_RX_WS

AUDIO_1_I2S_TX_SCK

AUDIO_1_I2S_TX_WS

AUDIO_1_I2S_TX_SDO

AUDIO_1_CLK_I2S_IF

AUDIO_1_I2S_RX_SCK

AUDIO_1_I2S_RX_WS

BB_LIN1_RXD

BB_LIN1_TXD

UART_TX

BB_UART0_RTS

BB_UART0_CTS

BB_LIN2_RXD

BB_LIN2_TXD

BB_LIN2_SLP

CYTVII-B-H-8M-320-CPU Evaluation Board User Guide, Document Number: 002-26716 Rev. *A 25

Connections and Settings

Table 4-1. Device Port Pin Connections on CPU Board (continued)

Pin Order Pad Pin Text Test Point Connection 1 Connection 2 Connection 3

99 T6

100 R7

101 T7

102 Y7

103 W7

104 V7

105 T8

106 T9

107 T10

108 T11

109 T12

110 T13 P16_4/PWM1_68/PWM1_69_N/TC1_68_TR0/TC1_69_TR1/ADC[2]_4 P2.16 GPIO_P16_4

111 Y12 P16_5/PWM1_67/PWM1_68_N/TC1_67_TR0/TC1_68_TR1/ADC[2]_5 P12.5 GPIO_P16_5

112 Y13 P16_6/PWM1_66/PWM1_67_N/TC1_66_TR0/TC1_67_TR1/ADC[2]_6 P12.4 GPIO_P16_6

113 Y14 P16_7/PWM1_65/PWM1_66_N/TC1_65_TR0/TC1_66_TR1/ADC[2]_7 P12.3 GPIO_P16_7

114 W1 4

115 V1 4

116 T1 4

117 R1 4

118 Y1 5

119 W1 5

120 Y16

P14_5/PWM1_53/PWM1_52_N/TC1_53_TR0/TC1_52_TR1/AUDIOSS2_TX_SDO/ TC1_H_4_TR1/SCB2_SEL2/LIN14_RX/ADC[1]_25

P14_6/PWM1_54/PWM1_53_N/TC1_54_TR0/TC1_53_TR1/TC1_H_5_TR0/ LIN14_TX/TRIG_IN[24]/ADC[1]_26

P14_7/PWM1_55/PWM1_54_N/TC1_55_TR0/TC1_54_TR1/TC1_H_5_TR1/ LIN14_EN/TRIG_IN[25]/ADC[1]_27

P15_0/PWM1_56/PWM1_55_N/TC1_56_TR0/TC1_55_TR1/AUDIOSS2_CLK_I2S_IF/TC1_H_6_TR0/SCB9_RX/SCB9_MISO/CAN1_3_TX/ADC[1]_28

P15_1/PWM1_57/PWM1_56_N/TC1_57_TR0/TC1_56_TR1/AUDIOSS2_RX_SCK/ TC1_H_6_TR1/SCB9_TX/SCB9_SDA/SCB9_MOSI/CAN1_3_RX/ADC[1]_29

P15_2/PWM1_58/PWM1_57_N/TC1_58_TR0/TC1_57_TR1/AUDIOSS2_RX_WS/ TC1_H_7_TR0/SCB9_RTS/SCB9_SCL/SCB9_CLK/ADC[1]_30

P15_3/PWM1_59/PWM1_58_N/TC1_59_TR0/TC1_58_TR1/AUDIOSS2_RX_SDI/ TC1_H_7_TR1/SCB9_CTS/SCB9_SEL0/ADC[1]_31

P16_0/PWM1_60/PWM1_59_N/TC1_60_TR0/TC1_59_TR1/PWM1_H_0/SCB9_SEL1/LIN11_RX/ADC[2]_0

P16_1/PWM1_61/PWM1_60_N/TC1_61_TR0/TC1_60_TR1/PWM1_H_0_N/SCB9_SEL2/LIN11_TX/ADC[2]_1

P16_2/PWM1_62/PWM1_61_N/TC1_62_TR0/TC1_61_TR1/PWM1_H_1/SCB9_SEL3/LIN11_EN/ADC[2]_2

P16_3/PWM1_62/PWM1_62_N/TC1_62_TR0/TC1_62_TR1/PWM1_H_1_N/ ADC[2]_3

P17_0/PWM1_61/PWM1_62_N/TC1_61_TR0/TC1_62_TR1/LIN11_RX/CAN1_1_TX/ ADC[2]_8

P17_1/PWM1_60/PWM1_61_N/TC1_60_TR0/TC1_61_TR1/SCB3_RX/LIN11_TX/ CAN1_1_RX/ADC[2]_9

P17_2/PWM1_59/PWM1_60_N/TC1_59_TR0/TC1_60_TR1/SCB3_TX/SCB3_SDA/ LIN11_EN/ADC[2]_10

P17_3/PWM1_58/PWM1_59_N/TC1_58_TR0/TC1_59_TR1/PWM1_H_3/ SCB3_RTS/SCB3_SCL/SCB3_CLK/TRIG_IN[26]/ADC[2]_11

P17_4/PWM1_57/PWM1_58_N/TC1_57_TR0/TC1_58_TR1/PWM1_H_3_N/ SCB3_CTS/SCB3_SEL0/TRIG_IN[27]/ADC[2]_12

P17_5/PWM1_56/PWM1_57_N/TC1_56_TR0/TC1_57_TR1/PWM1_H_2/LIN15_RX/ SCB3_SEL1/ADC[2]_13

P17_6/PWM1_M_4/PWM1_56_N/TC1_M_4_TR0/TC1_56_TR1/PWM1_H_2_N/ LIN15_TX/SCB3_SEL2/ADC[2]_14

P12.12 GPIO_P14_5

P12.16 GPIO_P14_6

P17.8 GPIO_P14_7

P3.6 BB_CAN1_TXD

P4.6 BB_CAN1_RXD

P12.14 GPIO_P15_2

P12.10 GPIO_P15_3

P12.15 GPIO_P16_0

P12.9 GPIO_P16_1

P11.13 GPIO_P16_2

P2.6 GPIO_P16_3

P14.15 BB_CAN6_TXD

P14.16 BB_CAN6_RXD

P2.15 GPIO_P17_2

P1.13 GPIO_P17_3

P12.2 GPIO_P17_4

P12.6 GPIO_P17_5

P12.7 GPIO_P17_6

CYTVII-B-H-8M-320-CPU Evaluation Board User Guide, Document Number: 002-26716 Rev. *A 26

Connections and Settings

Table 4-1. Device Port Pin Connections on CPU Board (continued)

Pin Order Pad Pin Text Test Point Connection 1 Connection 2 Connection 3

121 W16

122 V16

123 Y17

124 W17

125 Y18

126 Y19

127 T15

128 T16

129 R16

130 P19

131 P18

132 P16

133 P15

134 N16

135 N18

136 M18

137 M16

138 L19

139 L18

P17_7/PWM1_M_5/PWM1_M_4_N/TC1_M_5_TR0/TC1_M_4_TR1/LIN15_EN/ LIN12_RX/ADC[2]_15

P18_0/PWM1_M_6/PWM1_M_5_N/TC1_M_6_TR0/TC1_M_5_TR1/ETH0_REF_CLK/PWM1_H_0/SCB1_RX/SCB1_MISO/LIN12_TX/FAULT_OUT_0/ADC[2]_16

P18_1/PWM1_M_7/PWM1_M_6_N/TC1_M_7_TR0/TC1_M_6_TR1/ETH0_TX_CTL/ PWM1_H_0_N/SCB1_TX/SCB1_SDA/SCB1_MOSI/SCB3_MISO/FAULT_OUT_1/ ADC[2]_17

P18_2/PWM1_55/PWM1_M_7_N/TC1_55_TR0/TC1_M_7_TR1/ETH0_TX_ER/ PWM1_H_1/SCB1_RTS/SCB1_SCL/SCB1_CLK/SCB3_MOSI/ADC[2]_18

P18_3/PWM1_54/PWM1_55_N/TC1_54_TR0/TC1_55_TR1/ETH0_TX_CLK/ PWM1_H_1_N/SCB1_CTS/SCB1_SEL0/SCB3_CLK/TRACE_CLOCK/ADC[2]_19

P18_4/PWM1_53/PWM1_54_N/TC1_53_TR0/TC1_54_TR1/PWM0_M_2/ETH0_TXD_0/PWM1_H_2/SCB1_SEL1/SCB3_SEL0/TRACE_DATA_0/ADC[2]_20

P18_5/PWM1_52/PWM1_53_N/TC1_52_TR0/TC1_53_TR1/PWM0_M_2_N/ ETH0_TXD_1/PWM1_H_2_N/SCB1_SEL2/TRACE_DATA_1/ADC[2]_21

P18_6/PWM1_51/PWM1_52_N/TC1_51_TR0/TC1_52_TR1/TC0_M_2_TR0/ ETH0_TXD_2/PWM1_H_3/SCB1_SEL3/CAN1_2_TX/TRACE_DATA_2/ADC[2]_22

P18_7/PWM1_50/PWM1_51_N/TC1_50_TR0/TC1_51_TR1/TC0_M_2_TR1/ ETH0_TXD_3/PWM1_H_3_N/CAN1_2_RX/TRACE_DATA_3/ADC[2]_23

P19_0/PWM1_M_3/PWM1_50_N/TC1_M_3_TR0/TC1_50_TR1/ETH0_RXD_0/ TC1_H_0_TR0/SCB2_MISO/SCB2_RX/CAN1_3_TX/FAULT_OUT_2/ADC[2]_24

P19_1/PWM1_26/PWM1_M_3_N/TC1_26_TR0/TC1_M_3_TR1/ETH0_RXD_1/ TC1_H_0_TR1/SCB2_MOSI/SCB2_SDA/SCB2_TX/CAN1_3_RX/FAULT_OUT_3/ ADC[2]_25

P19_2/PWM1_27/PWM1_26_N/TC1_27_TR0/TC1_26_TR1/ETH0_RXD_2/ TC1_H_1_TR0/SCB2_CLK/SCB2_SCL/SCB2_RTS/TRIG_IN[28]/ADC[2]_26

P19_3/PWM1_28/PWM1_27_N/TC1_28_TR0/TC1_27_TR1/ETH0_RXD_3/ TC1_H_1_TR1/SCB2_SEL0/SCB2_CTS/TRIG_IN[29]/ADC[2]_27

P19_4/PWM1_29/PWM1_28_N/TC1_29_TR0/TC1_28_TR1/TC1_H_2_TR0/SCB2_SEL1/ADC[2]_28

P20_0/PWM1_30/PWM1_29_N/TC1_30_TR0/TC1_29_TR1/TC1_H_2_TR1/SCB2_SEL2/LIN5_RX/ADC[2]_29

P20_1/PWM1_49/PWM1_30_N/TC1_49_TR0/TC1_30_TR1/TC1_H_3_TR0/ LIN5_TX/ADC[2]_30

P20_2/PWM1_48/PWM1_49_N/TC1_48_TR0/TC1_49_TR1/TC1_H_3_TR1/ LIN5_EN/ADC[2]_31

P20_3/PWM1_47/PWM1_48_N/TC1_47_TR0/TC1_48_TR1/SCB1_RX/SCB1_MISO/ CAN1_2_TX

P20_4/PWM1_46/PWM1_47_N/TC1_46_TR0/TC1_47_TR1/SCB1_TX/SCB1_SDA/ SCB1_MOSI/CAN1_2_RX

P12.8 GPIO_P17_7

P7.5 GPIO_P18_0

P7.16 GPIO_P18_1 AUTO_ETH_TXEN_R BB_CAN_SPI1_MOSI

P7.6 GPIO_P18_2 AUTO_ETH_TXER_R BB_CAN_SPI1_SCK

P7.14 GPIO_P18_3 AUTO_ETH_TXC_R TRACE_CLOCK_0

P15.10 GPIO_P18_4 AUTO_ETH_TXD0_R TRACE_DATA_0_0

P7.8 GPIO_P18_5 AUTO_ETH_TXD1_R TRACE_DATA_1_0

P7.3 GPIO_P18_6 AUTO_ETH_TXD2_R TRACE_DATA_2_0

P7.4 GPIO_P18_7 AUTO_ETH_TXD3_R TRACE_DATA_3_0

P7.12 GPIO_P19_0 AUTO_ETH_RXD0_R TRSTN_SEC

P7.9 GPIO_P19_1 AUTO_ETH_RXD1_R SWO_TDO_SEC

P7.1 GPIO_P19_2 AUTO_ETH_RXD2_R SWDOE_TDI_SEC

P7.15 GPIO_P19_3 AUTO_ETH_RXD3_R SWDIO_TMS_SEC

P7.2 SWCLK_TCLK_SEC

P3.5 BB_LIN5_RXD

P3.8 BB_LIN5_TXD

P3.7 BB_LIN5_SLP

P13.8 BB_CAN4_TXD

P13.6 BB_CAN4_RXD

AUTO_ETH_REF_CLK_R

BB_CAN_SPI1_MISO

CYTVII-B-H-8M-320-CPU Evaluation Board User Guide, Document Number: 002-26716 Rev. *A 27

Connections and Settings

Table 4-1. Device Port Pin Connections on CPU Board (continued)

Pin Order Pad Pin Text Test Point Connection 1 Connection 2 Connection 3

140 L16

141 K16

142 J16

143 N19 P21_0/PWM1_42/PWM1_43_N/TC1_42_TR0/TC1_43_TR1/SCB1_SEL2/WCO_IN CPU_WCO_IN

144 N20 P21_1/PWM1_41/PWM1_42_N/TC1_41_TR0/TC1_42_TR1/WCO_OUT TP19 CPU_WCO_OUT

145 M19

P20_5/PWM1_45/PWM1_46_N/TC1_45_TR0/TC1_46_TR1/SCB1_RTS/SCB1_SCL/ SCB1_CLK

P20_6/PWM1_44/PWM1_45_N/TC1_44_TR0/TC1_45_TR1/SCB1_CTS/SCB1_SEL0/CAN1_4_TX

P20_7/PWM1_43/PWM1_44_N/TC1_43_TR0/TC1_44_TR1/SCB1_SEL1/ CAN1_4_RX

P21_2/PWM1_40/PWM1_41_N/TC1_40_TR0/TC1_41_TR1/EXT_CLK/ TRIG_DBG[1]/ECO_IN CPU_ECO_IN

P1.15 GPIO_P20_5

P13.10 BB_CAN_SPI1_SS0

P13.12 BB_CAN_SPI1_SS1

146 M20

147 K19

148 J19

149 H19 P21_6/PWM1_36/PWM1_37_N/TC1_36_TR0/TC1_37_TR1/LIN0_TX/LIN13_RX P6.14 BB_LIN0_TXD

150 H18

151 H20

152 G20

153 F20

154 G19

155 G18

156 H16

157 G16

158 F19

159 F18

P21_3/PWM1_39/PWM1_40_N/TC1_39_TR0/TC1_40_TR1/ECO_OUT

P21_4/PWM1_38/PWM1_39_N/TC1_38_TR0/TC1_39_TR1/HIBERNATE_WAKEUP[0]

P21_5/PWM1_37/PWM1_38_N/TC1_37_TR0/TC1_38_TR1/PWM1_34/ PWM1_35_N/ETH0_RX_CTL/TC1_35_TR1/TC1_34_TR0/LIN0_RX/CAN1_1_TX/ TRACE_DATA_0

P21_7/PWM1_35/PWM1_36_N/TC1_35_TR0/TC1_36_TR1/SCB6_RX/SCB6_MISO/ LIN0_EN/LIN13_TX/CAL_SUP_NZ/RTC_CAL

P22_1/PWM1_33/PWM1_34_N/TC1_33_TR0/TC1_34_TR1/SCB6_TX/SCB6_SDA/ SCB6_MOSI/CAN1_1_RX/TRACE_DATA_1/EXT_PS_CTL0

P22_2/PWM1_32/PWM1_33_N/TC1_32_TR0/TC1_33_TR1/SCB6_RTS/SCB6_SCL/ SCB6_CLK/TRACE_DATA_2/EXT_PS_CTL1

P22_3/PWM1_31/PWM1_32_N/TC1_31_TR0/TC1_32_TR1/SCB6_CTS/SCB6_SEL0/TRACE_DATA_3/EXT_PS_CTL2

P22_4/PWM1_30/PWM1_31_N/TC1_30_TR0/TC1_31_TR1/SCB6_SEL1/TRACE_CLOCK

P22_5/PWM1_29/PWM1_30_N/TC1_29_TR0/TC1_30_TR1/PWM1_H_8/SCB6_SEL2/LIN7_RX

P22_6/PWM1_28/PWM1_29_N/TC1_28_TR0/TC1_29_TR1/PWM1_H_8_N/ LIN7_TX

P22_7/PWM1_27/PWM1_28_N/TC1_27_TR0/TC1_28_TR1/TC1_H_8_TR0/ LIN14_RX/LIN7_EN

P23_0/PWM1_M_8/PWM1_27_N/TC1_M_8_TR0/TC1_27_TR1/TC1_H_8_TR1/ SCB7_RX/LIN14_TX/SCB7_MISO/CAN1_0_TX/FAULT_OUT_0

P23_1/PWM1_M_9/PWM1_M_8_N/TC1_M_9_TR0/TC1_M_8_TR1/SCB7_TX/ SCB7_SDA/SCB7_MOSI/CAN1_0_RX/FAULT_OUT_1

CPU_ECO_OUT

J2.1 CB_BUTTON_P21_4

P10.10 GPIO_P21_5

P6.15 BB_LIN0_SLP

P1.9 GPIO_P22_1 TRACE_DATA_1_1 EXT_PS_CTL0

P1.7 GPIO_P22_2 TRACE_DATA_2_1 EXT_PS_CTL1

P1.3 GPIO_P22_3 TRACE_DATA_3_1 EXT_PS_CTL2

P1.5 TRACE_CLOCK_1

P6.12 BB_LIN3_RXD

P3.10 BB_LIN3_TXD

P6.16 BB_LIN3_SLP

P6.11 BB_CAN3_TXD

P6.13 BB_CAN3_RXD

AUTO_ETH_RXDV_R

TRACE_DATA_0_1

CYTVII-B-H-8M-320-CPU Evaluation Board User Guide, Document Number: 002-26716 Rev. *A 28

Connections and Settings

Table 4-1. Device Port Pin Connections on CPU Board (continued)

Pin Order Pad Pin Text Test Point Connection 1 Connection 2 Connection 3

160 E20

161 E19

162 E18

163 D20

164 F16

165 G15

166 K3 P24_0/EXT_CLK/SDHC_CARD_DETECT_N/LIN16_RX P17.4 GPIO_P24_0

167 L1 P24_1/SPIHB_CLK/SDHC_CARD_MECH_WRITE_PROT P17.13 GM_CK_R

168 L2 P24_2/SPIHB_RWDS/SDHC_CLK_CARD P17.15 GM_RWDS_R

169 L3 P24_3/SPIHB_SEL0/SDHC_CARD_CMD/LIN16_TX P17.11 GM_CS#0_R

170 M1 P24_4/SPIHB_SEL1/SDHC_CARD_IF_PWR_EN/LIN16_EN P17.9 GM_CS#1_R

171 M2 P25_0/SPIHB_DATA0/SDHC_CARD_DAT_3TO0_0 P17.7 GM_DQ0_R

172 M3 P25_1/SPIHB_DATA1/SDHC_CARD_DAT_3TO0_1 P17.16 GM_DQ1_R

173 N1 P25_2/SPIHB_DATA2/SDHC_CARD_DAT_3TO0_2 P17.5 GM_DQ2_R

174 N2 P25_3/SPIHB_DATA3/SDHC_CARD_DAT_3TO0_3 P17.3 GM_DQ3_R

175 N3 P25_4/SPIHB_DATA4/SDHC_CARD_DAT_7TO4_0 P17.14 GM_DQ4_R

176 P1 P25_5/SPIHB_DATA5/SDHC_CARD_DAT_7TO4_1 P17.1 GM_DQ5_R

177 P2 P25_6/SPIHB_DATA6/SDHC_CARD_DAT_7TO4_2 P17.10 GM_DQ6_R

178 P3 P25_7/SPIHB_DATA7/SDHC_CARD_DAT_7TO4_3 P17.12 GM_DQ7_R

179 Y8 P26_0/ETH1_REF_CLK R144.2

180 W8 P26_1/ETH1_TX_CTL P11.5

181 V8 P26_2/ETH1_TX_CLK P11.4 GIG_ETH_TX_CLK_R

182 Y9 P26_3/ETH1_TXD_0 P11.10 GIG_ETH_TX_D0_R

183 W9 P26_4/ETH1_TXD_1 P11.11 GIG_ETH_TX_D1_R

184 V9 P26_5/ETH1_TXD_2 P11.2 GIG_ETH_TX_D2_R

185 Y10 P26_6/ETH1_TXD_3 P11.8 GIG_ETH_TX_D3_R

186 W10 P26_7/ETH1_RXD_0 P11.9 GIG_ETH_RX_D0_R

P23_2/PWM1_M_10/PWM1_M_9_N/TC1_M_10_TR0/TC1_M_9_TR1/SCB7_RTS/ SCB7_SCL/SCB7_CLK/LIN6_RX/FAULT_OUT_2

P23_3/PWM1_M_11/PWM1_M_10_N/TC1_M_11_TR0/TC1_M_10_TR1/ETH0_RX_CLK/SCB7_CTS/SCB7_SEL0/LIN6_TX/FAULT_OUT_3/TRIG_IN[30]

P23_4/PWM1_25/PWM1_M_11_N/TC1_25_TR0/TC1_M_11_TR1/PWM1_H_9/ SCB2_MISO/SCB7_SEL1/TRIG_DBG[0]/SWJ_SWO_TDO/TRIG_IN[31]

P23_5/PWM1_24/PWM1_25_N/TC1_24_TR0/TC1_25_TR1/LIN9_RX/ PWM1_H_9_N/SCB2_MOSI/SCB7_SEL2/SWJ_SWCLK_TCLK

P23_6/PWM1_23/PWM1_24_N/TC1_23_TR0/TC1_24_TR1/LIN9_TX/ TC1_H_9_TR0/SCB2_CLK/SWJ_SWDIO_TMS

P23_7/PWM1_22/PWM1_23_N/TC1_22_TR0/TC1_23_TR1/EXT_CLK/LIN9_EN/ TC1_H_9_TR1/SCB2_SEL0/CAL_SUP_NZ/SWJ_SWDOE_TDI/HIBERNATE_WAKEUP[1]

J3.2 CB_LED_P23_2

P10.14 AUTO_ETH_RXC_R

P2.3 SWO_TDO_PRM

P2.5 SWCLK_TCLK_PRM

P2.9 SWDIO_TMS_PRM

P2.7 SWDOE_TDI_PRM

GIG_ETH_REF_CLK_R

GIG_ETH_TX_EN_CTRL_R

CYTVII-B-H-8M-320-CPU Evaluation Board User Guide, Document Number: 002-26716 Rev. *A 29

Connections and Settings

Table 4-1. Device Port Pin Connections on CPU Board (continued)

Pin Order Pad Pin Text Test Point Connection 1 Connection 2 Connection 3

187 V10 P27_0/ETH1_RXD_1 P11.7 GIG_ETH_RX_D1_R

188 Y11 P27_1/ETH1_RXD_2 P11.6 GIG_ETH_RX_D2_R

189 W11 P27_2/ETH1_RXD_3 P11.3 GIG_ETH_RX_D3_R

190 V11 P27_3/ETH1_RX_CTL P11.1

191 W12 P27_4/ETH1_RX_CLK P9.15 GIG_ETH_RX_CLK_R

192 V12 P27_5/ETH1_MDIO P9.16 GIG_ETH_MDIO_R

193 W13 P27_6/ETH1_MDC P9.14 GIG_ETH_MDC_R

194 V13 P27_7/ETH1_ETH_TSU_TIMER_CMP_VAL P12.1 GPIO_P27_7

195 E16

196 D19

197 D18

198 C20

199 C19

200 B20

201 B19

202 A19 P28_7/PWM1_70/PWM1_69_N/TC1_70_TR0/TC1_69_TR1/LIN19_RX P13.11 BB_CAN6_WAKE

203 A11 P29_0/PWM1_76/PWM1_75_N/TC1_76_TR0/TC1_75_TR1/LIN19_TX P13.15 BB_CAN2_S

204 B11 P29_1/PWM1_77/PWM1_76_N/TC1_77_TR0/TC1_76_TR1/LIN19_EN P5.14 BB_CXPI_SELMS

205 A10 P29_2/PWM1_78/PWM1_77_N/TC1_78_TR0/TC1_77_TR1 P4.7 BB_CAN1_S

206 B10 P29_3/PWM1_79/PWM1_78_N/TC1_79_TR0/TC1_78_TR1 P4.3 BB_CXPI_RXD

207 E10 P29_4/PWM1_80/PWM1_79_N/TC1_80_TR0/TC1_79_TR1 P5.9 BB_USER_LED6

208 B9 P29_5/PWM1_81/PWM1_80_N/TC1_81_TR0/TC1_80_TR1 P4.8 BB_CXPI_NSLP

209 C9 P29_6/PWM1_82/PWM1_81_N/TC1_82_TR0/TC1_81_TR1 P8.6 BB_GPIO_56_RESET

210 E9 P29_7/PWM1_83/PWM1_82_N/TC1_83_TR0/TC1_82_TR1 P5.8 BB_USER_LED5

211 C7

212 A6

P28_0/PWM1_63/PWM1_65_N/TC1_63_TR0/TC1_65_TR1/PWM1_H_12/ SCB10_RX/SCB10_MISO

P28_1/PWM1_64/PWM1_63_N/TC1_64_TR0/TC1_63_TR1/PWM1_H_12_N/ SCB10_TX/SCB10_SDA/SCB10_MOSI/LIN17_RX

P28_2/PWM1_65/PWM1_64_N/TC1_65_TR0/TC1_64_TR1/TC1_H_12_TR0/ SCB10_RTS/SCB10_SCL/SCB10_CLK/LIN17_TX

P28_3/PWM1_66/PWM1_65_N/TC1_66_TR0/TC1_65_TR1/TC1_H_12_TR1/ SCB10_CTS/SCB10_SEL0/LIN17_EN

P28_4/PWM1_67/PWM1_66_N/TC1_67_TR0/TC1_66_TR1/SCB10_SEL1/ LIN18_RX

P28_5/PWM1_68/PWM1_67_N/TC1_68_TR0/TC1_67_TR1/SCB10_SEL2/ LIN18_TX

P28_6/PWM1_69/PWM1_68_N/TC1_69_TR0/TC1_68_TR1/SCB10_SEL3/ LIN18_EN

P30_0/PWM1_83/PWM1_83_N/TC1_83_TR0/TC1_83_TR1/SCB9_RTS/SCB9_SCL/ SCB9_CLK/TRIG_IN[34]

P30_1/PWM1_82/PWM1_83_N/TC1_82_TR0/TC1_83_TR1/SCB9_CTS/SCB9_SEL0/LIN16_RX/TRIG_IN[35]

P1.2 GPIO_P28_0

P6.5

P13.1

P6.4 BB_SPI0_WP

P6.3 BB_SPI0_HOLD

P6.2 BB_FRA_STBN

P6.1 BB_FRA_ERRN

P5.6 BB_FRB_WAKE

P1.8 GPIO_P30_1

GIG_ETH_RX_DV_CTRL_R

BB_USER_BUTTON_5

BB_USER_BUTTON_4

CYTVII-B-H-8M-320-CPU Evaluation Board User Guide, Document Number: 002-26716 Rev. *A 30

Connections and Settings

Table 4-1. Device Port Pin Connections on CPU Board (continued)

Pin Order Pad Pin Text Test Point Connection 1 Connection 2 Connection 3

213 B6

214 C6

215 E7 P31_0/PWM1_79/PWM1_80_N/TC1_79_TR0/TC1_80_TR1/LIN17_RX P5.7 BB_USER_LED4

216 F7 P31_1/PWM1_78/PWM1_79_N/TC1_78_TR0/TC1_79_TR1/LIN17_TX P1.12 GPIO_P31_1

217 E6 P31_2/PWM1_77/PWM1_78_N/TC1_77_TR0/TC1_78_TR1/LIN17_EN P5.5 BB_USER_LED3

218 D2

219 D3

220 E5

221 E1

222 E2

223 E3

224 F3

225 F5

226 W18 P33_0/ETH0_REF_CLK P2.12 GPIO_P33_0

227 V17 P33_1/ETH0_TX_CTL/ETH1_TX_ER P9.13 GIG_ETH_TX_ER_R

228 W19 P33_2/ETH0_TX_CLK P2.10 GPIO_P33_2

229 V18 P33_3/ETH0_TXD_0/ETH1_TXD_4 P9.1 GPIO_P33_3 AUTO_ETH_TXD0_R GIG_ETH_TX_D4_R

230 W20 P33_4/ETH0_TXD_1/ETH1_TXD_5 P9.11 GIG_ETH_TX_D5_R

231 V20 P33_5/ETH0_TXD_2/ETH1_TXD_6 P9.9 GIG_ETH_TX_D6_R

232 V19 P33_6/ETH0_TXD_3/ETH1_TXD_7 P9.10 GIG_ETH_TX_D7_R

233 U20 P33_7/ETH0_RXD_0/ETH1_RXD_4 P9.7 GIG_ETH_RX_D4_R

234 U19 P34_0/ETH0_RXD_1/ETH1_RXD_5 P9.8 GIG_ETH_RX_D5_R

235 U18 P34_1/ETH0_RXD_2/ETH1_RXD_6 P9.12 GIG_ETH_RX_D6_R

236 T20 P34_2/ETH0_RXD_3/ETH1_RXD_7 P9.5 GIG_ETH_RX_D7_R

237 T19 P34_3/ETH0_RX_CTL/ETH1_RX_ER P9.6 GIG_ETH_RX_ER_R

238 T18 P34_4/ETH0_RX_CLK P2.8 GPIO_P34_4

P30_2/PWM1_81/PWM1_82_N/TC1_81_TR0/TC1_82_TR1/SCB9_SEL1/LIN16_TX/ CAN1_3_TX/TRIG_IN[36]

P30_3/PWM1_80/PWM1_81_N/TC1_80_TR0/TC1_81_TR1/SCB9_SEL2/LIN16_EN/ CAN1_3_RX/TRIG_IN[37]

P32_0/PWM1_76/PWM1_77_N/TC1_76_TR0/TC1_77_TR1/SCB10_RX/ SCB10_MISO/TRIG_IN[40]/ADC[0]_8

P32_1/PWM1_75/PWM1_76_N/TC1_75_TR0/TC1_76_TR1/SCB10_TX/ SCB10_SDA/SCB10_MOSI/TRIG_IN[41]/ADC[0]_9

P32_2/PWM1_74/PWM1_75_N/TC1_74_TR0/TC1_75_TR1/SCB10_RTS/ SCB10_SCL/SCB10_CLK/LIN18_RX/TRIG_IN[42]/ADC[0]_10

P32_3/PWM1_73/PWM1_74_N/TC1_73_TR0/TC1_74_TR1/SCB10_CTS/SCB10_SEL0/LIN18_TX/TRIG_IN[43]/ADC[0]_11

P32_4/PWM1_72/PWM1_73_N/TC1_72_TR0/TC1_73_TR1/LIN10_RX/SCB10_SEL1/LIN18_EN/TRIG_IN[44]/ADC[0]_12

P32_5/PWM1_71/PWM1_72_N/TC1_71_TR0/TC1_72_TR1/LIN10_TX/SCB10_SEL2/LIN19_RX/TRIG_IN[45]/ADC[0]_13

P32_6/PWM1_70/PWM1_71_N/TC1_70_TR0/TC1_71_TR1/LIN10_EN/SCB10_SEL3/LIN19_TX/CAN1_4_TX/TRIG_IN[46]/ADC[0]_14

P32_7/PWM1_69/PWM1_70_N/TC1_69_TR0/TC1_70_TR1/LIN19_EN/ CAN1_4_RX/TRIG_IN[47]/ADC[0]_15

P14.14 BB_CAN9_WAKE

P8.11 BB_FRB_STBN

P3.15

P3.13

P3.16 BB_USER_LED2

P14.5 BB_USER_LED0

P4.16 BB_LIN4_RXD

P5.1 BB_USER_LED1

P4.15 BB_CAN0_TXD

P5.4 BB_CAN0_RXD

BB_USER_BUTTON_2

BB_USER_BUTTON_3

CYTVII-B-H-8M-320-CPU Evaluation Board User Guide, Document Number: 002-26716 Rev. *A 31

Connections and Settings

Table 4-1. Device Port Pin Connections on CPU Board (continued)

Pin Order Pad Pin Text Test Point Connection 1 Connection 2 Connection 3

239 R20 P34_5/ETH0_MDIO P2.11 GPIO_P34_5

240 R19 P34_6/ETH0_MDC P2.4 GPIO_P34_6

241 R18 P34_7/ETH0_ETH_TSU_TIMER_CMP_VAL P2.2 GPIO_P34_7

242 F15 VCCD CPU_VCCD

243 R6 VCCD CPU_VCCD

244 R15 VCCD CPU_VCCD

245 F6 VCCD CPU_VCCD

246 N6 VDDA CPU_VDDA

247 F8 VDDD CPU_VDDD

248 F9 VDDD CPU_VDDD

249 H15 VDDD CPU_VDDD

250 J15 VDDD CPU_VDDD

251 K15 VDDD CPU_VDDD

252 M15 VDDD CPU_VDDD

253 L15 VDDD CPU_VDDD

254 N15 VDDD CPU_VDDD

255 R12 VDDD CPU_VDDD

256 R13 VDDD CPU_VDDD

257 F11 VDDIO_1 CPU_VDDIO1

258 F12 VDDIO_1 CPU_VDDIO1

259 F13 VDDIO_1 CPU_VDDIO1

260 F10 VDDIO_1 CPU_VDDIO1

261 R8 VDDIO_2 CPU_VDDIO2

262 N8 VSSA AGND

263 A1 VSSD DGND

264 A20 VSSD DGND

265 C3 VSSD DGND

266 C10 VSSD DGND

267 C18 VSSD DGND

268 H9 VSSD DGND

269 H10 VSSD DGND

270 H11 VSSD DGND

271 H12 VSSD DGND

CYTVII-B-H-8M-320-CPU Evaluation Board User Guide, Document Number: 002-26716 Rev. *A 32

Connections and Settings

Table 4-1. Device Port Pin Connections on CPU Board (continued)

Pin Order Pad Pin Text Test Point Connection 1 Connection 2 Connection 3

272 H13 VSSD DGND

273 J9 VSSD DGND

274 J10 VSSD DGND

275 J11 VSSD DGND

276 J12 VSSD DGND

277 J13 VSSD DGND

278 J18 VSSD DGND

279 K9 VSSD DGND

280 K10 VSSD DGND

281 K11 VSSD DGND

282 K12 VSSD DGND

283 K13 VSSD DGND

284 K18 VSSD DGND

285 L9 VSSD DGND

286 L10 VSSD DGND

287 L11 VSSD DGND

288 L12 VSSD DGND

289 L13 VSSD DGND

290 M9 VSSD DGND

291 Y20 VSSD DGND

292 Y1 VSSD DGND

293 V15 VSSD DGND

294 V4 VSSD DGND

295 V3 VSSD DGND

296 N12 VSSD DGND

297 M13 VSSD DGND

298 M12 VSSD DGND

299 M11 VSSD DGND

300 M10 VSSD DGND

301 N13 VSSD_1 DGND

302 L20 VSSD_2 DGND

303 H6 VDDIO_3 CPU_VDDIO3

304 J6 VDDIO_3 CPU_VDDIO3

CYTVII-B-H-8M-320-CPU Evaluation Board User Guide, Document Number: 002-26716 Rev. *A 33

Connections and Settings

Table 4-1. Device Port Pin Connections on CPU Board (continued)

Pin Order Pad Pin Text Test Point Connection 1 Connection 2 Connection 3

305 K6 VDDIO_3 CPU_VDDIO3

306 L6 VDDIO_3 CPU_VDDIO3

307 R9 VDDIO_4 CPU_VDDIO4

308 R10 VDDIO_4 CPU_VDDIO4

309 R11 VDDIO_4 CPU_VDDIO4

310 M6 VREFH CPU_VDDA_R

311 M8 VREFL AGND_R

312 P20 VSSD_2 DGND

313 J8 VSSIO_3 DGND

314 K8 VSSIO_3 DGND

315 L8 VSSIO_3 DGND

316 H8 VSSIO_3 DGND

317 N10 VSSIO_4 DGND

318 N11 VSSIO_4 DGND

319 N9 VSSIO_4 DGND

320 K20 XRES CPU_XRES

The first column in Ta bl e 4 -1 lists the pin number on the MCU, followed by pad information and then the port pin name.

For each pin, the connected peripheral or net on the CPU / Base board is depicted by the Connection-x column.

The Test Point column indicates the place where the signal can be probed on the CPU board. Refer to the schematics / component assembly below to locate them. The ones named in the format Pxx.y, refer to the pin-y on the '8 x 2' Pxx header.

If the Test Point column is empty for a pin, it indicates that the signal is unavailable on a test point. Refer to the schematics for more information.

For details on the alternate functionality of each MCU pin, see the device datasheet.

Note:

If there are pins with more than one connection, make sure that no two peripherals are driven at the same time. The unused peripheral jumpers must be disconnected before using the other connection.

CYTVII-B-H-8M-320-CPU Evaluation Board User Guide, Document Number: 002-26716 Rev. *A 34

4.1.3 Reset Switch

The correspondence between the Reset switch and port number is given in Table 4 -2.

Table 4-2. Reset Switch

Switch Part No. Port Name

Reset Switch SW3 XRES

4.1.4 User Switch

The correspondence between the User switch and port number is given in Table 4-3.

Table 4-3. User Switch

Switch Part No. Port Name

User Switch SW1 P21.4

4.1.5 User LED

The correspondence between the User LED and port number is given in Ta bl e 4 -4 .

Table 4-4. User LED

Connections and Settings

Switch Part No. Port Name

User LED LD1 P23.2

4.2 Power Supply Settings

Power supply settings are shown in Table 4-5 and Figure 4-1.

Table 4-5. Power Supply Jumpers Settings

Jumper Pin MCU Power Remarks

J17

J19

J16

J18

J21 1-2 (default) VDDIO_3 = +3.3 V

J20 1-2 (default) VDDIO_4 = +3.3 V

J14 1-2 (default) VCCD = +1.1 V

1-2 (default) VDDD = +5.0 V

2-3 VDDD = +3.3 V

1-2 (default) VDDA = +5.0 V

2-3 VDDA = +3.3 V

1-2 (default) VDDIO_1 = +5.0 V

2-3 VDDIO_1 = +3.3 V

1-2 (default) VDDIO_2 = +5.0 V

2-3 VDDIO_2 = +3.3 V

CYTVII-B-H-8M-320-CPU Evaluation Board User Guide, Document Number: 002-26716 Rev. *A 35

Figure 4-1. Power Supply Jumpers Settings

VCC_3V3

J21

VCC_5V

VCC_3V3

J17

CPU_VDDD

TP9

J19 CPU_VDDA

J16 CPU_VDDIO1

J18 CPU_VDDIO2

TP11

TP8

TP10

CPU_VDDIO3

TP15

J20

CPU_VDDIO4

TP14

VCC_3V3

J14

CPU_VCCD

TP13

VCC_1V1

Connections and Settings

4.3 External Power Supply Control Signals Settings

Jumper settings of the external power supply control signals from MCU are shown in Table 4-6.

Table 4-6. External Power Supply Control Signals Jumper Settings

Jumpers Name PASS Transistor S6BP501A Remarks

EXT_PS_CTL0 J11 J6

EXT_PS_CTL1 J8 J9

EXT_PS_CTL2 - R11 Connected a 0-ohm resistor (R11)

J11 open (default)

J6 closed (default)

J8 open (default)

J9 closed (default)

CYTVII-B-H-8M-320-CPU Evaluation Board User Guide, Document Number: 002-26716 Rev. *A 36

5. Power Management IC (PMIC)

CYTVII-PMIC8M with S6BP501A

HOT PG5V PG3V PG1V

EN5V EN1V

SYNC

EN3V

VIN

PGND

VOUT3V

PGND

1.10V / 0.02A – 0.75A

PGND

VOUT5V

SMPS

Buck

SMPS

Boost

SMPS

Buck

Logic /

Power

FB1V_IN

DC Power Supply

12V typ.

to FB1V_IN

PGND

VOUT1V

3.30V / 0A – 0.75A

5.00V / 0A – 0.75A

5.1 Power Management IC (PMIC) Module

5.1.1 PMIC Module - CYTVII-PMIC8M

CYTVII-PMIC8M is the PMIC module for the power block of an automotive application with CYT4B Series MCU. The PMIC module implements the Cypress PMIC S6BP501A and is optimized for power supply of CYT4B Series MCU. 1.1-V output of the supply to VCCD of CYT4B Series MCU needs external schottky barrier diode (SBD), output capacitor, and constant load current no less than 20 mA.

Figure 5-1. Evaluation Board Block Diagram

CYTVII-B-H-8M-320-CPU Evaluation Board User Guide, Document Number: 002-26716 Rev. *A 37

*SMPS: Switching Mode Power Supply

5.1.2 Input / Output Pin Descriptions

113

2614

Table 5-1. Input / Output Pin Descriptions

Connector Symbol I/O Function Description

1, 2 VOUT3V O 3.3 V power rail output terminal (0 A - 0.75 A)

3, 4 PGND O Ground terminal

5 SYNC I

6 PG1V O Power good terminal of 1.1 V power rail

7 PG3V O Power good terminal of 3.3 V power rail

8 PG5V O Power good terminal of 5 V power rail

9 FB1V_IN I Feed-back terminal for 1.1 V power rail

10, 11 PGND – Ground terminal

12, 13 VOUT1V O 1.1 V output terminal (0 A - 0.75 A)

14, 15 VOUT5V O 5 V output terminal (0 A - 0.75 A)

16, 17 PGND – Ground terminal

18 HOT O Thermal warning output terminal

19 EN5V I 5 V power rail output enable terminal

20 EN3V I 3.3 V power rail output enable terminal

21 EN1V I 1.1 V power rail output enable terminal

22 N.C. N.C. No connection

23, 24 PGND – Ground terminal

25, 26 VIN I DC power supply terminal (4.5 V-42 V, 12 V typ.)

Power Management IC (PMIC)

Mode setting or external clock input terminal

Refer to the S6BP501A datasheet

Figure 5-2. Pin Layout

CYTVII-B-H-8M-320-CPU Evaluation Board User Guide, Document Number: 002-26716 Rev. *A 38

A. Schematics of CPU Board

This appendix contains the schematics of CYTVII-B-H-8M-320-CPU board.

CYTVII-B-H-8M-320-CPU Evaluation Board User Guide, Document Number: 002-26716 Rev. *A 39

Figure A-1. Block Diagram

5

4

3

2

1

D

C

B B

A

0.100" THRUHOLE TEST POINTS

RJ45

GIGABIT ETHERNET

DSUB 9

AUTOMOTIVE ETHERNET

eMMC CONNECTOR

DUAL QUAD_SPI FLASH

SMIF INTERFACE

HYPER FLASH& SRAM

DEBUG INTERFACES

RESET CONTROLLER

I2S AUDIO INTERFACE

3.5MM AUDIO JACK

180 Pin QSH

Connector (Samtec)

J84

180 Pin QSH

Connector (Samtec)

J38

TVII-B-H-8M-CPU BOARD

180 Pin QTH

Connector (Samtec)

J84

180 Pin QTH

Connector (Samtec)

J38

TRAVEO II

MCU

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BLOCK DIAGRAM

VJYM SPPD

Schematics of CPU Board

CYTVII-B-H-8M-320-CPU Evaluation Board User Guide, Document Number: 002-26716 Rev. *A 40

Figure A-2. Power Architecture

5

Schematics of CPU Board

4

3

2

1

POWER ARCHITECTURE

D

12V

SMIF POWER JACK

C

PMIC MODULE

1V1

3V3

TRAVEO II MCU

2V5 LDO

GIGABIT ETHERNET

1V1 LDO

AUTOMOTIVE ETHERNET

D

C

5V

B

DEBUG INTERFACE

I2S AUDIO CODE

SDHC INTERFACE

CYPRESS SEMICONDUCTOR

CYPRESS SEMICONDUCTOR 198 CHAMPION COURT

198 CHAMPION COURT

198 CHAMPION COURT SAN JOSE, CA 95134

SAN JOSE, CA 95134

SAN JOSE, CA 95134 (408) 943-2600

(408) 943-2600

B

Rev

A

5

4

1V8 LDO

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Date: Sheet

TVII-B-H-8M 320-BGA CPU BOARD

POWER ARCHITECTURE

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CYTVII-B-H-8M-320-CPU Evaluation Board User Guide, Document Number: 002-26716 Rev. *A 41

Figure A-3. Power Input-1

POWER INPUT-1

12V POWER INPUT

PASS TRANSISTOR

MONITOR LED

5

4

3

2

1

D

C

B

A A

4A

DEFAULT OPEN

VCC12V_EXT_SW

FUSE_12V ZENER_12V

DRV_VOUT_R

EXT_PS_CTL0_R

1V1_LED_R_D

3V3_LED_R_D5V_LED_R_D

1V1_LED_D_T

1V1_LED_R_T

VCC12V_EXT

VCC_12V

VCC_5V

VCC_1V1_TR

VCC_5V

VCC_3V3VCC_5V

VCC_1V1

DRV_VOUT{5,8}

EXT_PS_CTL0

{5,16}

EXT_PS_CTL1{5,16}

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C9

0.1uF/25V

C96

0.1uF/25V

R220

0.1ohm 1%

TR2 ZXT849K

1

2 3

R34

0 Ohm/2 Pin Jumper

J11

HDR_1X2

1

2

J32

HDR_1X2

1

2

J10

CON_PWRJACK3_RAPC722

1

2

3

LED3

LTST-C150GKT

21

R6

220 OHM

R10

470 OHM

C5

10uF/16V

C4

47uF/25V

SW2

500SSP1S2M2QEA

1

2

3

R5

220 OHM

C6

1uF/25V

J7

HDR_1X2

1

2

TP56

5002

D1

B120-13

2 1

C7

0.1uF/25V

R232

10k ohm 5%

J8

HDR_1X2

1

2

LED1

LTST-C150GKT

21

LED2

LTST-C150GKT

21

TR1 2SC2712

1

32

+

C8

100uF/25V

J1

HDR_1X2

1

2

TP6

THRU HOLE

F1

1.6A

1

2

D2

SMAJ12CA

2 1

FL2

BLM21PG300SH1D

1 2

R7

220 OHM

Schematics of CPU Board

CYTVII-B-H-8M-320-CPU Evaluation Board User Guide, Document Number: 002-26716 Rev. *A 42

Schematics of CPU Board

Figure A-4. Power Input-2

5

4

3

2

1

POWER INPUT-2

D D

FL4 BLM21PG300SH1D

VCC_12V

FB1V_IN

DNI

0 Ohm

PMIC_EN3

DNI

PMIC_NC

HDR_1X2

J9

1

2

TP3

R224 0 Ohm

R225 0 Ohm

EN1

R19

R20 0 OhmDNI

R11 0 Ohm

DNI

4

C

{4,16}

EXT_PS_CTL1

B

A

5

TP5 THRU HOLE

EXT_PS_CTL2{16}

{5,14}

DRV_VOUT{4,8}

FB1V

THRU HOLE

U1

25

VIN-1

26

VIN-2

9

FB1V_IN

19

EN5

20

EN3

21

EN1

5

SYNC

22

NC

3

GND-1

4

GND-2

10

GND-3

11

GND-4

27

EP-1

28

EP-2

VOUT5-1

VOUT5-2

VOUT3-1

VOUT3-2

VOUT1-1

VOUT1-2

PG5

PG3

PG1

HOT

GND-5

GND-6

GND-7

GND-8

EP-3

EP-4

S6BP501A_MODULE

3

VCC_5V_OUT

14

15

VCC_3V3_OUT

1

2

12

13

8

7

6

18

16

17

23

24

29

30

VCC_1V1_OUT

PG1

1 2

BLM21PG300SH1D

FL1 BLM21PG300SH1D

1

BLM21PG300SH1D

FL3 BLM21PG300SH1D

1 2

BLM21PG300SH1D

DEFAULT CLOSE

2

HDR_1X2

J6

1

2

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VCC_5V

TP18 THRU HOLE

VCC_3V3

TP1 THRU HOLE

R58

100 ohm

D3

2 1

RB168MM100TR

DNI

TP2 THRU HOLE

R223 0 Ohm

Drawn By

VJYM SPPD

VCC_1V1_FL VCC_1V1_PMIC

FB1V{5,14}

TVII-B-H-8M 320-BGA CPU BOARD

POWER INPUT-2

630-60569-01 01

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VCC_1V1_TR

VCC_1V1

J15

1

2

3

3 Pin Jumper

DEFAULT 2-3 CLOSE

EXT_PS_CTL0 {4,16}

VCC_1V1_PMIC

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1

TP7

C

B

A

CYTVII-B-H-8M-320-CPU Evaluation Board User Guide, Document Number: 002-26716 Rev. *A 43

Figure A-5. Power Input-3

Schematics of CPU Board

5

4

3

2

1

LDO REGULATOR 2.5V - FOR GIGABIT ETHERNET

TP20

C15

0.1uF/25V

VCC_2V5

C16

10uF/16V

VCC_3V3

D D

VCC_5V

DNI

R59 0 Ohm

R57 0 Ohm

2V5_LDO_IN

10uF/16V

C10

C11

0.1uF/25V

3

U3

INPUT

NCP1117

OUTPUT

GND

1

2

LDO REGULATOR 1.1V - FOR GIGABIT ETHERNET

VCC_1V1_ADJ

TP12

R60

1K

R62

10K

VCC_1V1_LDO

C12

10uF/16V

C

B

VCC_3V3

VCC_5V

VCC_12V

DNI

R50 0 Ohm

R55 0 Ohm

R56 0 Ohm

DNI

1V1_LDO_VIN

10uF/16V

C13

VCC_1V1_VC

R61

0 ohm

C14

0.1uF/25V

5

6

7

8

U2

VC

NC1

NC2

VIN

NR301E

D4

B0520LW-7-F

NC3

GND GND

ADJ

4

3 9 2

1

VO

C

B

LDO REGULATOR 1.8V - FOR AUDIO INTERFACE

2

TP37

C76

0.1uF/25V

VCC_1V8

C75

10uF/16V

CYPRESS SEMICONDUCTOR

CYPRESS SEMICONDUCTOR 198 CHAMPION COURT

198 CHAMPION COURT

198 CHAMPION COURT SAN JOSE, CA 95134

SAN JOSE, CA 95134

SAN JOSE, CA 95134 (408) 943-2600

(408) 943-2600

SCH Title :

Page Title :

Size

A4

Date:

TVII-B-H-8M 320-BGA CPU BOARD

POWER INPUT-3

Document Number Re v

630-60569-01 01

Wednesday, Auguﬆ 21, 2019

2

Drawn By

VJYM SPPD

Sheet

Approved By

1

644

A

of

VCC_3V3

DNI

VCC_5V

A

5

R174 0 Ohm

R173 0 Ohm

1V8_LDO_IN

C74

10uF/16V

4

C73

0.1uF/25V

3

U9

INPUT

NCP1117

OUTPUT

GND

1

3

CYTVII-B-H-8M-320-CPU Evaluation Board User Guide, Document Number: 002-26716 Rev. *A 44

Figure A-6. MCU Power Rail-Supply Select

Schematics of CPU Board

5

4

3

2

1

JUMPERS FOR MCU POWER

D

VCC_3V3

C

B

VCC_3V3 VCC_5V

VCC_3V3

VCC_5V CPU_VDDD

J17

1

2

3

3 Pin Jumper

CPU_VDDA

J19

1

2

3

3 Pin Jumper

VCC_5V

CPU_VDDIO1

J16

1

2

3

3 Pin Jumper

TP9 THRU HOLE

TP11 THRU HOLE

TP8 THRU HOLE

J21 HDR_1X2

1

VCC_3V3 CPU_VDDIO3

VCC_3V3 CPU_VDDIO4

VCC_1V1 CPU_VCCD

2

J20 HDR_1X2

2

J14 HDR_1X2

1

2

TP15 THRU HOLE

TP14 THRU HOLE

TP13 THRU HOLE

D

C

B

VCC_3V3 VCC_5V

A A

5

4

CPU_VDDIO2

J18

1

2

3

3 Pin Jumper

TP10 THRU HOLE

CYPRESS SEMICONDUCTOR

CYPRESS SEMICONDUCTOR 198 CHAMPION COURT

198 CHAMPION COURT

198 CHAMPION COURT SAN JOSE, CA 95134

SAN JOSE, CA 95134

SAN JOSE, CA 95134 (408) 943-2600

(408) 943-2600

SCH Title :

Page Title :

Size

A4

Date: Sheet

3

Date: Sheet

TVII-B-H-8M 320-BGA CPU BOARD

MCU POWER RAIL-SUPPLY SELECT

Document Number Re v

630-60569-01 01

Wednesday, Auguﬆ 21, 2019

2

Drawn By

VJYM SPPD

Approved By

1

of

744

CYTVII-B-H-8M-320-CPU Evaluation Board User Guide, Document Number: 002-26716 Rev. *A 45

Figure A-7. TVII-B-H-8M-320-BGA

TVII_B_H_8M_320_BGA

5

4

3

2

1

D

C C

B B

A A

DRV_VOUT{4,5}

CB_LED_P0_0

{19,23}

GPIO_P0_1{20}

GPIO_P0_3{20}

GPIO_P2_1{20}

AUTO_ETH_RXER_R

{19,27}

GPIO_P2_3

{20} BB_LIN3_WAKE

{20,41}

GPIO_P2_5{19}

BB_LIN2_WAKE

{20,40}

BB_USER_LED9{20,40}

AUTO_ETH_MDIO_R

{19,27}

AUTO_ETH_MDC_R

{19,27}

BB_CAN3_S{20,42}

BB_CXPI_TXD{20,40}

BB_LIN1_WAKE{20,40} BB_USER_LED8{20,40}

BB_LIN0_WAKE

{20,40}

BB_USER_LED7

{20,41}

BB_SPI0_MISO

{19,35,41}

BB_SPI0_MOSI

{19,35,41}

BB_SPI0_CLK{20,35,42} BB_SPI0_SS0{20,42}

AUDIO_SPI0_SS1{19,35}

BB_CAN0_S

{20,40}

BB_CXPI_CLK

{20,41}

GPIO_P5_0{19} GPIO_P5_1{19} GPIO_P5_2{19} GPIO_P5_3{19}

BB_CAN8_WAKE

{20,43}

BB_CAN5_S{20,42} BB_CAN4_S

{20,42}

BB_LIN0_RXD{20,40}

BB_LIN5_WAKE{20,40}

BB_LIN4_WAKE{20,41}

GPIO_P1_5{19} GPIO_P1_6{19}

GPIO_P0_2{20}

TRSTN_PRM{25}

SCH Title :

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Page Title :

Drawn By

CYPRESS SEMICONDUCTOR 198 CHAMPION COURT SAN JOSE, CA 95134 (408) 943-2600

Approved By

630-60569-01 01

TVII-B-H-8M 320-BGA CPU BOARD

A4

844

Wednesday, Auguﬆ 21, 2019

TVII_B_H_8M_320_BGA_P1

VJYM SPPD

SCH Title :

Size

Document Number Re v

Date: Sheet

of

Page Title :

Drawn By

CYPRESS SEMICONDUCTOR 198 CHAMPION COURT SAN JOSE, CA 95134 (408) 943-2600

Approved By

630-60569-01 01

TVII-B-H-8M 320-BGA CPU BOARD

A4

844

Wednesday, Auguﬆ 21, 2019

TVII_B_H_8M_320_BGA_P1

VJYM SPPD

SCH Title :

Size

Document Number Re v

Date: Sheet

of

Page Title :

Drawn By

CYPRESS SEMICONDUCTOR 198 CHAMPION COURT SAN JOSE, CA 95134 (408) 943-2600

Approved By

630-60569-01 01

TVII-B-H-8M 320-BGA CPU BOARD

A4

844

Wednesday, Auguﬆ 21, 2019

TVII_B_H_8M_320_BGA_P1

VJYM SPPD

U6A

TVII_B_H_8M_320_BGA_18

P5_4/PWM1_13/PWM1_12_N/TC1_13_TR0/TC1_12_TR1/LIN9_R

X/PWM1_H_11/LIN2_TX

B4

P5_3/PWM1_12/PWM1_11_N/TC1_12_TR0/TC1_11_TR1/TC0_M_0_TR1/TC1_H_10_TR1/LIN10_TX/LIN2_RX

A4

P5_2/PWM1_11/PWM1_10_N/TC1_11_TR0/TC1_10_TR1/TC0_M_0_TR0/TC1_H_10_TR0/LIN10_RX/LIN7_EN

C5

P5_1/PWM1_10/PWM1_9_N/TC1_10_TR0/TC1_9_TR1/PW M0_M_0_N/PWM1_H_10_N/SCB9_SEL3/LIN7_TX/TRIG_IN[39]

B5

P5_0/PWM1_9/PWM1_8_N/TC1_9_TR0/TC1_8_TR1/PW M0_M_0/PWM1_H_10/LIN15_TX/SCB5_SEL2/LIN7_RX/TRIG_IN[38]

A5

P4_6/SCB9_TX/SCB9_SDA/SCB9_MOSI/TRIG_IN[33]

B7

P4_5/SCB9_RX/SCB9_MISO/TRIG_IN[32]

A7

P4_4/PWM1_8/PWM1_7_N/TC1_8_TR0/TC1_7_TR1/LIN15_RX/SCB5_SEL1/CAN0_1_RX

E8

P4_3/PWM1_7/PWM1_6_N/TC1_7_TR0/TC1_6_TR1/EXT_MUX[0]_EN/SCB5_CTS/SCB5_SEL0/CAN0_1_TX/TRIG_IN[13]

C8

P4_2/PWM1_6/PWM1_5_N/TC1_6_TR0/TC1_5_TR1/EXT_MUX[0]_2/SCB5_RTS/SCB5_SCL/SCB5_CLK/LIN1_EN/TRIG_IN[12]

B8

P4_1/PWM1_5/PWM1_4_N/TC1_5_TR0/TC1_4_TR1/EXT_MUX[0]

_1/SCB5_TX/SCB5_SDA/SCB5_MOSI/LIN1_TX/TRIG_IN[11]

A8

P4_0/PWM1_4/PWM1_M_0_N/TC1_4_TR0/TC1_M_0_TR1/EXT_MUX[0]_0/SCB5_RX/SCB5_MISO/LIN1_RX/TRIG_IN[10]

A9

P3_7/PWM1_75/PWM1_74_N/TC1_75_TR0/TC1_74_TR1/LIN11_EN/CAN1_2_RX

E11

P3_6/PWM1_74/PWM1_73_N/TC1_74_TR0/TC1_73_TR1/SCB8_SEL2/LIN11_TX/CAN1_2_TX

C11

P3_5/PWM1_M_0/PWM1_M_1_N/TC1_M_0_TR0/TC1_M_1_TR1/TC1_H_7_TR1/SCB6_SEL2/LIN1_TX

E12

P3_4/PWM1_M_1/PWM1_M_2_N/TC1_M_1_TR0/TC1_M_2_TR1/TC1_H_6_TR1/SCB6_SEL1/LIN1_RX

C12

P3_3/PWM1_M_2/PWM1_M_3_N/TC1_M_2_TR0/TC1_M_3_TR1/TC1_H_5_TR1/SCB6_CTS/SCB6_SEL0

B12

P3_2/PWM1_M_3/PWM1_0_N/TC1_M_3_TR0/TC1_0_TR1/TC1_H_

4_TR1/SCB6_RTS/SCB6_SCL/SCB6_CLK

A12

P3_1/PWM1_0/PWM1_1_N/TC1_0_TR0/TC1_1_TR1/ETH0_MDC/PWM1_H_7_N/SCB6_TX/SCB6_SDA/SCB6_MOSI/CAN0_3_RX/TRIG_DBG[1]

B13

P3_0/PWM1_1/PWM1_2_N/TC1_1_TR0/TC1_2_TR1/ETH0_MDIO/PWM1_H_6_N/SCB6_RX/SCB6_MISO/CAN0_3_TX/TRIG_DBG[0]

A13

P2_7/PWM1_73/PWM1_72_N/TC1_73_TR0/TC1_72_TR1/SCB8_S

EL1/LIN11_RX

E13

P2_6/PWM1_72/PWM1_71_N/TC1_72_TR0/TC1_71_TR1/SCB8_CTS/SCB8_SEL0

C13

P2_5/PWM1_2/PWM1_3_N/TC1_2_TR0/TC1_3_TR1/PW M1_H_5_N

/SCB7_SEL2/LIN5_EN/TRIG_IN[7]

E14

P2_4/PWM1_3/PWM1_4_N/TC1_3_TR0/TC1_4_TR1/PW M1_H_4_N/SCB7_SEL1/LIN5_TX/TRIG_IN[6]

C14

P2_3/PWM1_4/PWM1_5_N/TC1_4_TR0/TC1_5_TR1/ETH0_ETH_TSU_TIMER_CMP_VAL/TC1_H_7_TR0/SCB7_CTS/SCB7_SEL0/LIN5_RX/TRIG_IN[5]

B14

P2_2/PWM1_5/PWM1_6_N/TC1_5_TR0/TC1_6_TR1/ETH0_RX_ER

/TC1_H_6_TR0/SCB7_RTS/SCB7_SCL/SCB0_SEL3/SCB7_CLK/LIN0_EN/TRIG_IN[4]

A14

P2_1/PWM1_6/PWM1_7_N/TC1_6_TR0/TC1_7_TR1/TC1_H_5_TR0/SCB7_TX/SCB7_SDA/SCB0_SEL2/SCB7_MOSI/LIN0_TX/CAN0_0_RX/TRIG_IN[3]

B15

P2_0/PWM1_7/PWM1_8_N/TC1_7_TR0/TC1_8_TR1/TC1_H_4_TR

0/SCB7_RX/SCB0_SEL1/SCB7_MISO/LIN0_RX/CAN0_0_TX/SWJ

_TRSTN/TRIG_IN[2]

A15

P1_6/LIN8_EN/SCB8_RTS/SCB8_SCL/SCB8_CLK

F14

P1_5/LIN8_TX/SCB8_TX/SCB8_SDA/SCB8_MOSI

E15

P1_4/PWM1_71/PWM1_70_N/TC1_71_TR0/TC1_70_TR1/LIN8_RX/SCB8_RX/SCB8_MISO

C15

P1_3/PWM1_8/PWM1_10_N/TC1_8_TR0/TC1_10_TR1/PW M1_H_7/SCB0_SEL0/LIN0_TX/TRIG_IN[1]

C16

P1_2/PWM1_10/PWM1_11_N/TC1_10_TR0/TC1_11_TR1/PW M1_H_6/SCB0_CLK/LIN0_RX/TRIG_IN[0]

B16

P1_1/PWM1_11/PWM1_12_N/TC1_11_TR0/TC1_12_TR1/PW M1_H

_5/SCB0_SDA/SCB0_MOSI/SCB4_SEL0

A16

P1_0/PWM1_12/PWM1_13_N/TC1_12_TR0/TC1_13_TR1/PW M1_H_4/SCB0_SCL/SCB0_MISO/SCB4_CLK

A17

P0_3/PWM1_13/PWM1_14_N/TC1_13_TR0/TC1_14_TR1/TC0_H_0_TR1/SCB0_CTS/SCB0_SDA/SCB0_SEL0/SCB4_MOSI/CAN0_1_RX

C17

P0_2/PWM1_14/PWM1_17_N/TC1_14_TR0/TC1_17_TR1/TC0_H_0_TR0/SCB0_RTS/SCB0_SCL/SCB0_CLK/SCB4_MISO/LIN1_EN/CAN0_1_TX

B17

P0_1/PWM1_17/PWM1_18_N/TC1_17_TR0/TC1_18_TR1/PW M0_H

_0_N/SCB0_TX/SCB7_SCL/SCB0_MOSI/LIN1_TX

B18

P0_0/PWM1_18/PWM1_22_N/TC1_18_TR0/TC1_22_TR1/PW M0_H

_0/SCB0_RX/SCB7_SDA/SCB0_MISO/LIN1_RX

A18

DRV_VOUT

J20

Schematics of CPU Board

CYTVII-B-H-8M-320-CPU Evaluation Board User Guide, Document Number: 002-26716 Rev. *A 46

Figure A-8. TVII-B-H-8M-320-BGA

TVII_B_H_8M_320_BGA

5

4

3

2

1

D

C

B

A

BB_FRB_ERRN

{20,40}

GPIO_P6_0{19}

GPIO_P6_1

{19}

GPIO_P6_3{16}

EMMC_DATA2

{19,36}

EMMC_DATA3

{19,36}

GPIO_P7_5{19} BB_LIN4_TXD

{20,41}

BB_LIN4_SLP{20,41}

GPIO_P8_0{19} GPIO_P8_1{19}

GPIO_P8_2{19} GPIO_P8_3{19} GPIO_P8_4{19} GPIO_P9_0

{19}

GPIO_P9_1{19} GPIO_P9_2{19}

GPIO_P9_3{19} GPIO_P10_0{19} GPIO_P10_1{19}

BB_FRA_RXD

{20,40}

BB_FRA_TXD

{20,40}

BB_FRA_TXEN{20,40}

BB_FRB_RXD

{20,40}

BB_FRB_TXD

{20,40}

BB_FRB_TXEN{20,40} AUDIO_0_I2S_MCLK{34} AUDIO_0_I2S_TX_SCK{34} AUDIO_0_I2S_TX_WS{34}

GPIO_P12_0{16} GPIO_P12_1{16} GPIO_P12_2{16}

GPIO_P6_4

{16}

EMMC_CD{19,36}

BB_FRA_WAKE{20,40}

BB_USER_BUTTON_1{20,41}

GPIO_P7_0{19}

EMMC_DATA0

{19,36}

EMMC_DATA1{19,36}

EMMC_WP

{19,36}

SCH Title :

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Drawn By

CYPRESS SEMICONDUCTOR 198 CHAMPION COURT SAN JOSE, CA 95134 (408) 943-2600

Approved By

630-60569-01 01

TVII-B-H-8M 320-BGA CPU BOARD

A4

944

Wednesday, Auguﬆ 21, 2019

TVII_B_H_8M_320_BGA_P2

VJYM SPPD

SCH Title :

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Document Number Re v

Date: Sheet

of

Page Title :

Drawn By

CYPRESS SEMICONDUCTOR 198 CHAMPION COURT SAN JOSE, CA 95134 (408) 943-2600

Approved By

630-60569-01 01

TVII-B-H-8M 320-BGA CPU BOARD

A4

944

Wednesday, Auguﬆ 21, 2019

TVII_B_H_8M_320_BGA_P2

VJYM SPPD

SCH Title :

Size

Document Number Re v

Date: Sheet

of

Page Title :

Drawn By

CYPRESS SEMICONDUCTOR 198 CHAMPION COURT SAN JOSE, CA 95134 (408) 943-2600

Approved By

630-60569-01 01

TVII-B-H-8M 320-BGA CPU BOARD

A4

944

Wednesday, Auguﬆ 21, 2019

TVII_B_H_8M_320_BGA_P2

VJYM SPPD

U6B

TVII_B_H_8M_320_BGA_18

P12_2/PWM1_38/PWM1_37_N/TC1_38_TR0/TC1_37_TR1/TC0_H

_1_TR0/AUDIOSS0_RX_SCK/EXT_MUX[1]_EN/SCB8_RTS/SCB8_SCL/SCB8_CLK/LIN6_RX/ADC[1]_6

U1

P12_1/PWM1_37/PWM1_36_N/TC1_37_TR0/TC1_36_TR1/PW M0_

H_1_N/AUDIOSS0_CLK_I2S_IF/SCB8_TX/SCB8_SDA/SCB8_MOSI/LIN6_EN/CAN0_2_RX/TRIG_IN[21]/ADC[1]_5

T3

P12_0/PWM1_36/TC1_36_TR0/PWM0_H_1/PW M1_35_N/AUDIOSS0_TX_SDO/SCB8_RX/TC1_35_TR1/SCB8_MISO/CAN0_2_TX/TRI

G_IN[20]/ADC[1]_4

T2

P11_2/PWM1_59/PWM1_60_N/TC1_59_TR0/TC1_60_TR1/AUDIO

SS0_TX_WS/ADC[2]_M

R5

P11_1/PWM1_60/PWM1_61_N/TC1_60_TR0/TC1_61_TR1/AUDIOSS0_TX_SCK/ADC[1]_M

P6

P11_0/PWM1_61/PWM1_62_N/TC1_61_TR0/TC1_62_TR1/AUDIO

SS0_MCLK/ADC[0]_M

P5

P10_7/PWM1_35/PWM1_34_N/TC1_35_TR0/TC1_34_TR1/TC1_H_11_TR1/LIN13_EN/FLEXRAY_TXENB_N/ADC[1]_3

T1

P10_6/PWM1_33_N/TC1_33_TR1/PWM1_34/TC1_H_11_TR0/TC1_34_TR0/LIN13_TX/FLEXRAY_TXDB/ADC[1]_2

R3

P10_5/PWM1_33/PWM1_32_N/TC1_33_TR0/TC1_32_TR1/PW M1_

H_11_N/SCB4_SEL2/LIN13_RX/FLEXRAY_RXDB/ADC[1]_1

R2

P10_4/PWM1_32/PWM1_31_N/TC1_32_TR0/TC1_31_TR1/LIN8_

EN/PWM1_H_11/SCB4_SEL1/FLEXRAY_TXENA_N/ADC[1]_0

R1

P10_3/PWM1_31/PWM1_30_N/TC1_31_TR0/TC1_30_TR1/LIN8_

TX/TC1_H_10_TR1/SCB4_CTS/SCB4_SEL0/FLEXRAY_TXDA

N5

P10_2/PWM1_30/PWM1_29_N/TC1_30_TR0/TC1_29_TR1/LIN8_

RX/TC1_H_10_TR0/SCB4_RTS/SCB4_SCL/SCB4_CLK/FLEXRAY_RXDA

M5

P10_1/PWM1_29/PWM1_28_N/TC1_29_TR0/TC1_28_TR1/PW M1_H_10_N/SCB4_TX/SCB4_SDA/SCB4_MOSI/LIN7_TX/TRIG_IN[19]

L5

P10_0/PWM1_28/PWM1_27_N/TC1_28_TR0/TC1_27_TR1/PW M1_

H_10/SCB4_RX/SCB4_MISO/LIN7_RX/TRIG_IN[18]

K5

P9_3/PWM1_27/PWM1_26_N/TC1_27_TR0/TC1_26_TR1/TC1_H_9_TR1/LIN12_EN/ADC[0]_31

J5

P9_2/PWM1_26/PWM1_25_N/TC1_26_TR0/TC1_25_TR1/TC1_H_

9_TR0/LIN12_TX/ADC[0]_30

J3

P9_1/PWM1_25/PWM1_24_N/TC1_25_TR0/TC1_24_TR1/PW M1_H_9_N/LIN12_RX/ADC[0]_29

K2

P9_0/PWM1_24/PWM1_23_N/TC1_24_TR0/TC1_23_TR1/PW M1_H_9/LIN16_EN/ADC[0]_28

K1

P8_4/PWM1_23/PWM1_22_N/TC1_23_TR0/TC1_22_TR1/LIN16_

TX/TRIG_DBG[1]/ADC[0]_27

J2

P8_3/PWM1_22/PWM1_21_N/TC1_22_TR0/TC1_21_TR1/TC1_H_8_TR1/LIN16_RX/TRIG_DBG[0]/ADC[0]_26

J1

P8_2/PWM1_21/PWM1_20_N/TC1_21_TR0/TC1_20_TR1/TC0_H_

2_TR1/SPIHB_DATA7/SDHC_CARD_DAT_7TO4_3/TC1_H_8_TR0/LIN2_EN/TRIG_IN[15]/ADC[0]_25

H3

P8_1/PWM1_20/PWM1_19_N/TC1_20_TR0/TC1_19_TR1/TC0_H_2_TR0/SPIHB_DATA6/SDHC_CARD_DAT_7TO4_2/PWM1_H_8_N/L

IN2_TX/CAN0_0_RX/TRIG_IN[14]/ADC[0]_24

H2

P8_0/PWM1_19/PWM1_18_N/TC1_19_TR0/TC1_18_TR1/PW M0_H_2_N/SPIHB_DATA5/SDHC_CARD_DAT_7TO4_1/PWM1_H_8/LIN2_RX/CAN0_0_TX

H1

P7_7/PWM1_18/PWM1_M_7_N/TC1_18_TR0/TC1_M_7_TR1/LIN1

0_EN/TRIG_IN[17]/ADC[0]_23

H5

P7_6/PWM1_M_7/PWM1_17_N/TC1_M_7_TR0/TC1_17_TR1/LIN1

0_TX/TRIG_IN[16]/ADC[0]_22

G6

P7_5/PWM1_17/PWM1_M_6_N/TC1_17_TR0/TC1_M_6_TR1/PW M0

_H_2/SPIHB_DATA4/SDHC_CARD_DAT_7TO4_0/LIN10_RX/SCB5_SEL2/ADC[0]_21

G5

P7_4/PWM1_M_6/PWM1_16_N/TC1_M_6_TR0/TC1_16_TR1/TC0_

1_TR1/SPIHB_DATA3/SDHC_CARD_DAT_3TO0_3/SCB5_SEL1/CAN0_4_RX/ADC[0]_20

G3

P7_3/PWM1_16/PWM1_M_5_N/TC1_16_TR0/TC1_M_5_TR1/TC0_1_TR0/SPIHB_DATA2/SDHC_CARD_DAT_3TO0_2/SCB5_CTS/SCB5_SEL0/CAN0_4_TX/ADC[0]_19

G2

P7_2/PWM1_M_5/PWM1_15_N/TC1_M_5_TR0/TC1_15_TR1/PW M0

_1_N/SPIHB_DATA1/SDHC_CARD_DAT_3TO0_1/SCB5_RTS/SCB5_SCL/SCB5_CLK/LIN4_EN/ADC[0]_18

G1

P7_1/PWM1_15/PWM1_M_4_N/TC1_15_TR0/TC1_M_4_TR1/SPIHB_DATA0/SDHC_CARD_DAT_3TO0_0/SCB5_TX/SCB5_SDA/SCB5_

MOSI/LIN4_TX/ADC[0]_17

F2

P7_0/PWM1_M_4/PWM1_3_N/TC1_M_4_TR0/TC1_3_TR1/PW M0_1

/SPIHB_SEL1/SDHC_CARD_IF_PWR_EN/SCB5_RX/SCB5_MISO/LIN4_RX/ADC[0]_16

F1

P6_7/PWM1_3/PWM1_M_3_N/TC1_3_TR0/TC1_M_3_TR1/TRIG_I

N[9]/ADC[0]_7

D1

P6_6/PWM1_M_3/PWM1_2_N/TC1_M_3_TR0/TC1_2_TR1/SCB4_SEL3/TRIG_IN[8]/ADC[0]_6

C2

P6_5/PWM1_2/PWM1_M_2_N/TC1_2_TR0/TC1_M_2_TR1/TC0_0_

TR1/SPIHB_SEL0/SDHC_CARD_DETECT_N/TC1_H_12_TR1/SCB4_SEL2/LIN4_EN/ADC[0]_5

C1

P6_4/PWM1_M_2/PWM1_1_N/TC1_M_2_TR0/TC1_1_TR1/TC0_0_

TR0/SPIHB_RWDS/SDHC_CLK_CARD/TC1_H_12_TR0/SCB4_SEL1

/LIN4_TX/ADC[0]_4

B2

P6_3/PWM1_1/PWM1_M_1_N/TC1_1_TR0/TC1_M_1_TR1/SPIHB_CLK/SDHC_CARD_CMD/PWM1_H_12_N/SCB4_CTS/SCB4_SEL0/LIN4_RX/CAN0_2_RX/CAL_SUP_NZ/ADC[0]_3

B1

P6_2/PWM1_M_1/PWM1_0_N/TC1_M_1_TR0/TC1_0_TR1/PW M0_0_N/SDHC_CARD_MECH_WRITE_PROT/PWM1_H_12/SCB4_RTS/SCB4_SCL/SCB4_CLK/LIN3_EN/CAN0_2_TX/ADC[0]_2

A2

P6_1/PWM1_0/PWM1_M_0_N/TC1_0_TR0/TC1_M_0_TR1/TC1_H_11_TR1/SCB4_TX/SCB4_SDA/SCB4_MOSI/LIN3_TX/ADC[0]_1

B3

P6_0/PWM1_M_0/PWM1_14_N/TC1_M_0_TR0/TC1_14_TR1/PW M0

_0/LIN9_EN/TC1_H_11_TR0/SCB4_RX/SCB4_MISO/LIN3_RX/ADC[0]_0

A3

P5_5/PWM1_14/PWM1_13_N/TC1_14_TR0/TC1_13_TR1/LIN9_TX/PWM1_H_11_N/LIN2_EN

C4

Schematics of CPU Board

CYTVII-B-H-8M-320-CPU Evaluation Board User Guide, Document Number: 002-26716 Rev. *A 47

Figure A-9. TVII-B-H-8M-320-BGA

Schematics of CPU Board

5

4

3

2

1

TVII_B_H_8M_320_BGA

D

GPIO_P12_3

{16}

AUDIO_0_I2S_RX_SDI{34}

GPIO_P12_5_R{10}

BB_ADC_POT{20,41}

GPIO_P12_7_R{10}

GPIO_P13_0{18} GPIO_P13_1{18}

GPIO_P13_2{18}

GPIO_P13_3{18} GPIO_P13_4{18} GPIO_P13_5{18} GPIO_P13_6{18}

AUDIO_1_I2S_RX_SDI{34}

GPIO_P14_0{19}

BB_I2C1_SDA

{20,41}

BB_I2C1_SCL

{20,41}

GPIO_P14_3

C

B

{19}

GPIO_P14_4{19}

GPIO_P14_5{19} GPIO_P14_6{19,38}

GPIO_P14_7{19} BB_CAN1_TXD{20,40} BB_CAN1_RXD{20,40}

GPIO_P15_2{19}

GPIO_P15_3{19}

GPIO_P16_0{19,38}

GPIO_P16_1{19,39}

GPIO_P16_2{19}

GPIO_P16_3{19}

GPIO_P16_4{19}

GPIO_P16_5{19}

GPIO_P16_6{19}

GPIO_P16_7{19}

BB_CAN6_TXD{20,43} BB_CAN6_RXD{20,43}

GPIO_P17_2 GPIO_P17_3{19}

GPIO_P17_4 GPIO_P17_5{19} GPIO_P17_6{19}

U6C

U2

P12_3_PWM1_39/PWM1_38_N/TC1_39_TR0/TC1_38_TR1/TC0_H_1_TR1/EXT_MUX[1]_0/SCB8_CTS/SCB8_SEL0/LIN6_TX/ADC[1]_7

U3

P12_4_PWM1_40/PWM1_39_N/TC1_40_TR0/TC1_39_TR1/TC0_2_TR1/EXT_MUX[1]_1/SCB8_SEL1/CAN1_1_TX/ADC[1]_8

V1

P12_5_PWM1_41/PWM1_40_N/TC1_41_TR0/TC1_40_TR1/EXT_MUX[1]_2/CAN1_1_RX/ADC[1]_9

V2

P12_6_PWM1_42/PWM1_41_N/TC1_42_TR0/TC1_41_TR1/ADC[1]_10

W1

P12_7_PWM1_43/PWM1_42_N/TC1_43_TR0/TC1_42_TR1/ADC[1]_11

Y2

P13_0_PWM1_M_8/PWM1_43_N/TC1_M_8_TR0/TC1_43_TR1/TC0_2_TR0/AUDIOSS2_MCLK/EXT_MUX[2]_0/SCB3_RX/LIN3_RX/SCB3_MISO/ADC[1]_12

W2

P13_1/PWM1_44/PWM1_M_8_N/TC1_44_TR0/TC1_M_8_TR1/PW M0_2_N/AUDIOSS1_TX_SCK/EXT_MUX[2]_1/SCB3_TX/SCB3_SDA/LIN3_TX/SCB3_MOSI/ADC[1]_13

Y3

P13_2_PWM1_M_9/PWM1_44_N/TC1_M_9_TR0/TC1_44_TR1/PW M0_2/AUDIOSS2_TX_WS/EXT_MUX[2]_2/SCB3_RTS/SCB3_SCL/LIN3_EN/SCB3_CLK/ADC[1]_14

W3

P13_3_PWM1_45/PWM1_M_9_N/TC1_45_TR0/TC1_M_9_TR1/AUDIOSS2_TX_SDO/EXT_MUX[2]_EN/SCB3_CTS/LIN2_RX/SCB3_SEL0/ADC[1]_15

Y4

P13_4_PWM1_M_10/PWM1_45_N/TC1_M_10_TR0/TC1_45_TR1/LIN8_RX/AUDIOSS2_CLK_I2S_IF/PWM1_H_4/LIN2_TX/SCB3_SEL1/ADC[1]_16

W4

P13_5_PWM1_46/PWM1_M_10_N/TC1_46_TR0/TC1_M_10_TR1/LIN8_TX/AUDIOSS2_RX_SCK/PWM1_H_4_N/SCB3_SEL2/ADC[1]_17

Y5

P13_6_PWM1_M_11/PWM1_46_N/TC1_M_11_TR0/TC1_46_TR1/LIN8_EN/AUDIOSS2_RX_WS/PW M1_H_5/SCB3_SEL3/TRIG_IN[22

W5

P13_7_PWM1_47/PWM1_M_11_N/TC1_47_TR0/TC1_M_11_TR1/AUDIOSS2_RX_SDI/PWM1_H_5_N/TRIG_IN[23]/ADC[1]_19

V5

P14_0_PWM1_48/PWM1_47_N/TC1_48_TR0/TC1_47_TR1/PW M0_M_1/AUDIOSS1_MCLK/PWM1_H_6/SCB2_MISO/SCB2_RX/CAN1_0_TX/ADC[1]_20

T5

P14_1/PWM1_49/PWM1_48_N/TC1_49_TR0/TC1_48_TR1/PW M0_M_1_N/AUDIOSS2_TX_SCK/PWM1_H_6_N/SCB2_MOSI/SCB2_SDA/SCB2_TX/CAN1_0_RX/ADC[1]_21

Y6

P14_2_PWM1_50/PWM1_49_N/TC1_50_TR0/TC1_49_TR1/TC0_M_1_TR0/AUDIOSS1_TX_WS/PW M1_H_7/SCB2_CLK/SCB2_SCL/SCB2_RTS/LIN6_RX/ADC[1]_22

W6

P14_3_PWM1_51/PWM1_50_N/TC1_51_TR0/TC1_50_TR1/TC0_M_1_TR1/AUDIOSS1_TX_SDO/PWM1_H_7_N/SCB2_SEL0/SCB2_CTS/LIN6_TX/ADC[1]_23

V6

P14_4_PWM1_52/PWM1_51_N/TC1_52_TR0/TC1_51_TR1/TC1_H_4_TR0/SCB2_SEL1/LIN6_EN/ADC[1]_24

T6

P14_5_PWM1_53/PWM1_52_N/TC1_53_TR0/TC1_52_TR1/TC1_H_4_TR1/SCB2_SEL2/LIN14_RX/ADC[1]_25

R7

P14_6_PWM1_54/PWM1_53_N/TC1_54_TR0/TC1_53_TR1/TC1_H

T7

P14_7_PWM1_55/PWM1_54_N/TC1_55_TR0/TC1_54_TR1/TC1_H_5_TR1/LIN14_EN/TRIG_IN[25]/ADC[1]_27

Y7

P15_0_PWM1_56/PWM1_55_N/TC1_56_TR0/TC1_55_TR1/TC1_H_6_TR0/SCB9_RX/SCB9_MISO/CAN1_3_TX/ADC[1]_28

W7

P15_1_PWM1_57/PWM1_56_N/TC1_57_TR0/TC1_56_TR1/TC1_H_6_TR1/SCB9_TX/SCB9_SDA/SCB9_MOSI/CAN1_3_RX/ADC[1]_29

V7

P15_2_PWM1_58/PWM1_57_N/TC1_58_TR0/TC1_57_TR1/TC1_H_7_TR0/SCB9_RTS/SCB9_SCL/SCB9_CLK/ADC[1]_30

T8

P15_3_PWM1_59/PWM1_58_N/TC1_59_TR0/TC1_58_TR1/TC1_H

T9

P16_0_PWM1_60/PWM1_59_N/TC1_60_TR0/TC1_59_TR1/PW M1_H_0/SCB9_SEL1/LIN11_RX/ADC[2]_0

T10

P16_1_PWM1_61/PWM1_60_N/TC1_61_TR0/TC1_60_TR1/PW M1_H_0_N/SCB9_SEL2/LIN11_TX/ADC[2]_1

T11

P16_2_PWM1_62/PWM1_61_N/TC1_62_TR0/TC1_61_TR1/PW M1_H_1/SCB9_SEL3/LIN11_EN/ADC[2]_2

T12

P16_3_PWM1_62/PWM1_62_N/TC1_62_TR0/TC1_62_TR1/PW M1_H_1_N/ADC[2]_3

T13

P16_4_PWM1_68/PWM1_69_N/TC1_68_TR0/TC1_69_TR1/ADC[2

Y12

P16_5_PWM1_67/PWM1_68_N/TC1_67_TR0/TC1_68_TR1/ADC[2]_5

Y13

P16_6_PWM1_66/PWM1_67_N/TC1_66_TR0/TC1_67_TR1/ADC[2]_6

Y14

P16_7_PWM1_65/PWM1_66_N/TC1_65_TR0/TC1_66_TR1/ADC[2]_7

W14

P17_0_PWM1_61/PWM1_62_N/TC1_61_TR0/TC1_62_TR1/LIN11_RX/CAN1_1_TX/ADC[2]_8

V14

P17_1_PWM1_60/PWM1_61_N/TC1_60_TR0/TC1_61_TR1/SCB3_

T14

P17_2_PWM1_59/PWM1_60_N/TC1_59_TR0/TC1_60_TR1/SCB3_TX/SCB3_SDA/LIN11_EN/ADC[2]_10

R14

P17_3_PWM1_58/PWM1_59_N/TC1_58_TR0/TC1_59_TR1/PW M1_H_3/SCB3_RTS/SCB3_SCL/SCB3_CLK/TRIG_IN[26]/ADC[2]_11

Y15

P17_4_PWM1_57/PWM1_58_N/TC1_57_TR0/TC1_58_TR1/PW M1_H_3_N/SCB3_CTS/SCB3_SEL0/TRIG_IN[27]/ADC[2]_12

W15

P17_5_PWM1_56/PWM1_57_N/TC1_56_TR0/TC1_57_TR1/PW M1_H_2/LIN15_RX/SCB3_SEL1/ADC[2]_13

Y16

P17_6_PWM1_M_4/PWM1_56_N/TC1_M_4_TR0/TC1_56_TR1/PW M1_H_2_N/LIN15_TX/SCB3_SEL2/ADC[2]_14

TVII_B_H_8M_320_BGA_18

_5_TR0/LIN14_TX/TRIG_IN[24]/ADC[1]_26

_7_TR1/SCB9_CTS/SCB9_SEL0/ADC[1]_31

]_4

RX/LIN11_TX/CAN1_1_RX/ADC[2]_9

]/ADC[1]_18

D

C

B

GPIO_P12_7{19}

A

GPIO_P12_5{19}

C66

0.1uF/16V

C70

0.1uF/16V

5

R159 0 Ohm

DNI

R164 0 Ohm

DNI

C63

DNI

0.1uF/16V

C71

DNI

0.1uF/16V

GPIO_P12_7_R {10}

GPIO_P12_5_R {10}

4

CYPRESS SEMICONDUCTOR

CYPRESS SEMICONDUCTOR 198 CHAMPION COURT

198 CHAMPION COURT

198 CHAMPION COURT SAN JOSE, CA 95134

SAN JOSE, CA 95134

SAN JOSE, CA 95134 (408) 943-2600

(408) 943-2600

SCH Title :

Page Title :

Size

A4

Date: Sheet

3

Date: Sheet

TVII-B-H-8M 320-BGA CPU BOARD

TVII_B_H_8M_320_BGA_P3

Document Number Re v

630-60569-01 01

Wednesday, Auguﬆ 21, 2019

2

Drawn By

VJYM SPPD

Approved By

1

10 44

of

A

CYTVII-B-H-8M-320-CPU Evaluation Board User Guide, Document Number: 002-26716 Rev. *A 48

Schematics of CPU Board

Figure A-10. TVII-B-H-8M-320-BGA

5

4

3

2

1

TVII_B_H_8M_320_BGA

D

U6D

GPIO_P17_7{19} GPIO_P18_0

{17,20}

GPIO_P18_1{17,20} GPIO_P18_2{17,20} GPIO_P18_3{17,20} GPIO_P18_4

{17,19}

GPIO_P18_5{17,20} GPIO_P18_6

{17,20}

GPIO_P18_7{17,20} GPIO_P19_0

{18,20}

GPIO_P19_1{18,20} GPIO_P19_2{18,20} GPIO_P19_3{18,20}

SWCLK_TCLK_SEC

C C

GPIO_P22_1{16} GPIO_P22_2{16} GPIO_P22_3{16}

B B

{20,25}

{20,43} {20,43}

{19} BB_CAN_SPI1_SS0{20,42} BB_CAN_SPI1_SS1{20,42}

CPU_WCO_OUT

{21}

CB_BUTTON_P21_4{23}

GPIO_P21_5{17}

TRACE_CLOCK_1{19,25}

{20,41}

CB_LED_P23_2

{23}

BB_LIN5_RXD{20,40} BB_LIN5_TXD{20,40}

BB_LIN5_SLP{20,40} BB_CAN4_TXD BB_CAN4_RXD

GPIO_P20_5

CPU_WCO_IN{21}

CPU_ECO_IN{21}

CPU_ECO_OUT{21}

BB_LIN0_TXD{20,40}

BB_LIN0_SLP{20,40}

BB_LIN3_RXD{20,41}

BB_LIN3_TXD{20,41}

BB_LIN3_SLP BB_CAN3_TXD

BB_CAN3_RXD{20,41}

W16

P17_7_PWM1_M_5/PWM1_M_4_N/TC1_M_5_TR0/TC1_M_4_TR1/L

V16

P18_0_PWM1_M_6/PWM1_M_5_N/TC1_M_6_TR0/TC1_M_5_TR1/AUDIOSS1_CLK_I2S_IF/PWM1_H_0/SCB1_RX/SCB1_MISO/LIN12_TX/FAULT_OUT_0/ADC[2]_16

Y17

P18_1/PWM1_M_7/PWM1_M_6_N/TC1_M_7_TR0/TC1_M_6_TR1/ETH0_TX_CTL/PWM1_H_0_N/SCB1_TX/SCB1_SDA/SCB1_MOSI/SCB3_MISO/FAULT_OUT_1/ADC[2]_17

W17

P18_2_PWM1_55/PWM1_M_7_N/TC1_55_TR0/TC1_M_7_TR1/AUDIOSS1_RX_WS/PW M1_H_1/SCB1_RTS/SCB1_SCL/SCB1_CLK/SCB

Y18

P18_3_PWM1_54/PWM1_55_N/TC1_54_TR0/TC1_55_TR1/AUDIOSS1_RX_SDI/PWM1_H_1_N/SCB1_CTS/SCB1_SEL0/SCB3_CLK/TRACE_CLOCK/ADC[2]_19

Y19

P18_4_PWM1_53/PWM1_54_N/TC1_53_TR0/TC1_54_TR1/PW M0_M_2/AUDIOSS0_MCLK/PWM1_H_2/SCB1_SEL1/SCB3_SEL0/TRAC

T15

P18_5_PWM1_52/PWM1_53_N/TC1_52_TR0/TC1_53_TR1/PW M0_

T16

P18_6_PWM1_51/PWM1_52_N/TC1_51_TR0/TC1_52_TR1/TC0_M_2_TR0/AUDIOSS0_TX_WS/PW M1_H_3/SCB1_SEL3/CAN1_2_TX/TRACE_DATA_2/ADC[2]_22

R16

P18_7_PWM1_50/PWM1_51_N/TC1_50_TR0/TC1_51_TR1/TC0_M

P19

P19_0_PWM1_M_3/PWM1_50_N/TC1_M_3_TR0/TC1_50_TR1/AUDIOSS0_CLK_I2S_IF/TC1_H_0_TR0/SCB2_MISO/SCB2_RX/CAN1_3_TX/FAULT_OUT_2/ADC[2]_

P18

P19_1/PWM1_26/PWM1_M_3_N/TC1_26_TR0/TC1_M_3_TR1/ETH0_RXD_1/TC1_H_0_TR1/SCB2_MOSI/SCB2_SDA/SCB2_TX/CAN1

P16

P19_2_PWM1_27/PWM1_26_N/TC1_27_TR0/TC1_26_TR1/AUDIOSS0_RX_WS/TC1_H_1_TR0/SCB2_CLK/SCB2_SCL/SCB2_RTS/TR

P15

P19_3_PWM1_28/PWM1_27_N/TC1_28_TR0/TC1_27_TR1/AUDIOSS0_RX_SDI/TC1_H_1_TR1/SCB2_SEL0/SCB2_CTS/TRIG_IN[29]/ADC[2]_27

N16

P19_4_PWM1_29/PWM1_28_N/TC1_29_TR0/TC1_28_TR1/TC1_H_2_TR0/SCB2_SEL1/ADC[2]_28

N18

P20_0_PWM1_30/PWM1_29_N/TC1_30_TR0/TC1_29_TR1/TC1_H_2_TR1/SCB2_SEL2/LIN5_RX/ADC[2]_29

M18

P20_1_PWM1_49/PWM1_30_N/TC1_49_TR0/TC1_30_TR1/TC1_H_3_TR0/LIN5_TX/ADC[2]_30

M16

P20_2_PWM1_48/PWM1_49_N/TC1_48_TR0/TC1_49_TR1/TC1_H

L19

P20_3_PWM1_47/PWM1_48_N/TC1_47_TR0/TC1_48_TR1/SCB1_RX/SCB1_MISO/CAN1_2_TX

L18

P20_4_PWM1_46/PWM1_47_N/TC1_46_TR0/TC1_47_TR1/SCB1_TX/SCB1_SDA/SCB1_MOSI/CAN1_2_RX

L16

P20_5_PWM1_45/PWM1_46_N/TC1_45_TR0/TC1_46_TR1/SCB1_RTS/SCB1_SCL/SCB1_CLK

K16

P20_6_PWM1_44/PWM1_45_N/TC1_44_TR0/TC1_45_TR1/SCB1_CTS/SCB1_SEL0/CAN1_4_TX

J16

P20_7_PWM1_43/PWM1_44_N/TC1_43_TR0/TC1_44_TR1/SCB1_

N19

P21_0_PWM1_42/PWM1_43_N/TC1_42_TR0/TC1_43_TR1/SCB1_SEL2/WCO_IN

N20

P21_1_PWM1_41/PWM1_42_N/TC1_41_TR0/TC1_42_TR1/W CO_O

M19

P21_2/PWM1_40/PWM1_41_N/TC1_40_TR0/TC1_41_TR1/EXT_CLK/TRIG_DBG[1]/ECO_IN

M20

P21_3/PWM1_39/PWM1_40_N/TC1_39_TR0/TC1_40_TR1/ECO_OUT

K19

P21_4_PWM1_38/PWM1_39_N/TC1_38_TR0/TC1_39_TR1/HIBERNATE_WAKEUP[0]

J19

P21_5_PWM1_37/PWM1_38_N/TC1_37_TR0/TC1_38_TR1/PW M1_

H19

P21_6_PWM1_36/PWM1_37_N/TC1_36_TR0/TC1_37_TR1/LIN0_TX/LIN13_RX

H18

P21_7_PWM1_35/PWM1_36_N/TC1_35_TR0/TC1_36_TR1/SCB6_

H20

P22_1_PWM1_33/PWM1_34_N/TC1_33_TR0/TC1_34_TR1/SCB6_TX/SCB6_SDA/SCB6_MOSI/CAN1_1_RX/TRACE_DATA_1/EXT_PS_CTL0

G20

P22_2_PWM1_32/PWM1_33_N/TC1_32_TR0/TC1_33_TR1/SCB6_RTS/SCB6_SCL/SCB6_CLK/TRACE_DATA_2/EXT_PS_CTL1

F20

P22_3_PWM1_31/PWM1_32_N/TC1_31_TR0/TC1_32_TR1/SCB6_

G19

P22_4_PWM1_30/PWM1_31_N/TC1_30_TR0/TC1_31_TR1/SCB6_SEL1/TRACE_CLOCK

G18

P22_5_PWM1_29/PWM1_30_N/TC1_29_TR0/TC1_30_TR1/PW M1_

H16

P22_6_PWM1_28/PWM1_29_N/TC1_28_TR0/TC1_29_TR1/PW M1_H_8_N/LIN7_TX

G16

P22_7_PWM1_27/PWM1_28_N/TC1_27_TR0/TC1_28_TR1/TC1_H_8_TR0/LIN14_RX/LIN7_EN

F19

P23_0_PWM1_M_8/PWM1_27_N/TC1_M_8_TR0/TC1_27_TR1/TC1

F18

P23_1_PWM1_M_9/PWM1_M_8_N/TC1_M_9_TR0/TC1_M_8_TR1/SCB7_TX/SCB7_SDA/SCB7_MOSI/CAN1_0_RX/FAULT_OUT_1

E20

P23_2_PWM1_M_10/PWM1_M_9_N/TC1_M_10_TR0/TC1_M_9_TR1

TVII_B_H_8M_320_BGA_18

IN15_EN/LIN12_RX/ADC[2]_15

3_MOSI/ADC[2]_18

M_2_N/AUDIOSS0_TX_SCK/PWM1_H_2_N/SCB1_SEL2/TRACE_DATA_1/ADC[2]_21

_2_TR1/AUDIOSS0_TX_SDO/PWM1_H_3_N/CAN1_2_RX/TRACE_DATA_3/ADC[2]_23

_3_TR1/LIN5_EN/ADC[2]_31

SEL1/CAN1_4_RX

UT

34/PWM1_35_N/TC1_34_TR0/TC1_35_TR1/LIN0_RX/CAN1_1_TX/TRACE_DATA_0

RX/SCB6_MISO/LIN0_EN/LIN13_TX/CAL_SUP_NZ/RTC_CAL

CTS/SCB6_SEL0/TRACE_DATA_3/EXT_PS_CTL2

H_8/SCB6_SEL2/LIN7_RX

_H_8_TR1/SCB7_RX/LIN14_TX/SCB7_MISO/CAN1_0_TX/FAULT_OUT_0

/SCB7_RTS/SCB7_SCL/SCB7_CLK/LIN6_RX/FAULT_OUT_2

E_DATA_0/ADC[2]_20

_3_RX/FAULT_OUT_3/ADC[2]_25

IG_IN[28]/ADC[2]_26

D

CYPRESS SEMICONDUCTOR

CYPRESS SEMICONDUCTOR 198 CHAMPION COURT

198 CHAMPION COURT

198 CHAMPION COURT SAN JOSE, CA 95134

SAN JOSE, CA 95134

SAN JOSE, CA 95134 (408) 943-2600

(408) 943-2600

A

SCH Title :

Page Title :

Size

A4

Date: Sheet

5

4

3

Date: Sheet

TVII-B-H-8M 320-BGA CPU BOARD

TVII_B_H_8M_320_BGA_P4

Document Number Re v

630-60569-01 01

Wednesday, Auguﬆ 21, 2019

2

Drawn By

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Approved By

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of

11 44

A

CYTVII-B-H-8M-320-CPU Evaluation Board User Guide, Document Number: 002-26716 Rev. *A 49

Figure A-11. TVII-B-H-8M-320-BGA

TVII_B_H_8M_320_BGA

5

4

3

2

1

D

C

B

A

AUTO_ETH_RXC_R

{19,27}

SWO_TDO_PRM

{19,25}

SWCLK_TCLK_PRM

{19,25}

SWDOE_TDI_PRM{19,25}

GM_DQ2_R

{19,37}

GM_DQ3_R

{19,37}

GM_DQ4_R

{19,37}

GM_DQ5_R

{19,37}

GM_DQ6_R{19,37} GM_DQ7_R

{19,37}

GIG_ETH_REF_CLK_R{30}

GIG_ETH_TX_EN_CTRL_R

{19,30}

GIG_ETH_TX_CLK_R{19,30}

GIG_ETH_TX_D0_R{19,30} GIG_ETH_TX_D1_R{19,30} GIG_ETH_TX_D2_R

{19,30}

GIG_ETH_TX_D3_R

{19,30}

GIG_ETH_RX_D0_R

{19,30}

GIG_ETH_RX_D1_R{19,30} GIG_ETH_RX_D2_R

{19,30}

GIG_ETH_RX_D3_R{19,30}

GIG_ETH_RX_DV_CTRL_R

{19,30}

GIG_ETH_RX_CLK_R{19,30}

GIG_ETH_MDIO_R{19,30}

GIG_ETH_MDC_R

{19,30}

GPIO_P27_7{19}

GPIO_P28_0{19} BB_USER_BUTTON_5{20,41} BB_USER_BUTTON_4{20,42}

BB_SPI0_WP{20,40}

BB_SPI0_HOLD

{20,40}

BB_FRA_STBN{20,40}

GPIO_P24_0{19}

GM_CK_R{19,37}

GM_RWDS_R

{19,37}

GM_CS#0_R{19,37}

GM_DQ0_R

{19,37}

GM_DQ1_R{19,37}

SWDIO_TMS_PRM

{19,25}

GM_CS#1_R

{19,37}

SCH Title :

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Date: Sheet

of

Page Title :

Drawn By

CYPRESS SEMICONDUCTOR 198 CHAMPION COURT SAN JOSE, CA 95134 (408) 943-2600

Approved By

630-60569-01 01

TVII-B-H-8M 320-BGA CPU BOARD

A4

12 44

Wednesday, Auguﬆ 21, 2019

TVII_B_H_8M_320_BGA_P5

VJYM SPPD

SCH Title :

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Document Number Re v

Date: Sheet

of

Page Title :

Drawn By

CYPRESS SEMICONDUCTOR 198 CHAMPION COURT SAN JOSE, CA 95134 (408) 943-2600

Approved By

630-60569-01 01

TVII-B-H-8M 320-BGA CPU BOARD

A4

12 44

Wednesday, Auguﬆ 21, 2019

TVII_B_H_8M_320_BGA_P5

VJYM SPPD

SCH Title :

Size

Document Number Re v

Date: Sheet

of

Page Title :

Drawn By

CYPRESS SEMICONDUCTOR 198 CHAMPION COURT SAN JOSE, CA 95134 (408) 943-2600

Approved By

630-60569-01 01

TVII-B-H-8M 320-BGA CPU BOARD

A4

12 44

Wednesday, Auguﬆ 21, 2019

TVII_B_H_8M_320_BGA_P5

VJYM SPPD

U6E

TVII_B_H_8M_320_BGA_18

P28_5_PWM1_68/PWM1_67_N/TC1_68_TR0/TC1_67_TR1/SCB10

_SEL2/LIN18_TX

B20

P28_4_PWM1_67/PWM1_66_N/TC1_67_TR0/TC1_66_TR1/SCB10_SEL1/LIN18_RX

C19

P28_3_PWM1_66/PWM1_65_N/TC1_66_TR0/TC1_65_TR1/TC1_H_12_TR1/SCB10_CTS/SCB10_SEL0/LIN17_EN

C20

P28_2_PWM1_65/PWM1_64_N/TC1_65_TR0/TC1_64_TR1/TC1_H

_12_TR0/SCB10_RTS/SCB10_SCL/SCB10_CLK/LIN17_TX

D18

P28_1_PWM1_64/PWM1_63_N/TC1_64_TR0/TC1_63_TR1/PW M1_H_12_N/SCB10_TX/SCB10_SDA/SCB10_MOSI/LIN17_RX

D19

P28_0_PWM1_63/PWM1_65_N/TC1_63_TR0/TC1_65_TR1/PW M1_

H_12/SCB10_RX/SCB10_MISO

E16

P27_7_ETH1_ETH_TSU_TIMER_CMP_VAL

V13

P27_6_ETH1_MDC

W13

P27_5_PWM1_31/PWM1_32_N/TC1_31_TR0/TC1_32_TR1/ETH1_MDIO

V12

P27_4_PWM1_32/PWM1_33_N/TC1_32_TR0/TC1_33_TR1/ETH1_RX_CLK

W12

P27_3_PWM1_33/PWM1_34_N/TC1_33_TR0/TC1_34_TR1/ETH1_

RX_CTL

V11

P27_2_ETH1_RXD_3

W11

P27_1_ETH1_RXD_2

Y11

P27_0_ETH1_RXD_1

V10

P26_7_ETH1_RXD_0

W10

P26_6_ETH1_TXD_3

Y10

P26_5_ETH1_TXD_2

V9

P26_4_ETH1_TXD_1

W9

P26_3_ETH1_TXD_0

Y9

P26_2_ETH1_TX_CLK

V8

P26_1_ETH1_TX_CTL

W8

P26_0_ETH1_REF_CLK

Y8

P25_7_SPIHB_DATA7/SDHC_CARD_DAT_7TO4_3

P3

P25_6_SPIHB_DATA6/SDHC_CARD_DAT_7TO4_2

P2

P25_5_SPIHB_DATA5/SDHC_CARD_DAT_7TO4_1

P1

P25_4_SPIHB_DATA4/SDHC_CARD_DAT_7TO4_0

N3

P25_3_SPIHB_DATA3/SDHC_CARD_DAT_3TO0_3

N2

P25_2_SPIHB_DATA2/SDHC_CARD_DAT_3TO0_2

N1

P25_1_SPIHB_DATA1/SDHC_CARD_DAT_3TO0_1

M3

P25_0_EXT_CLK/SPIHB_DATA0/SDHC_CARD_DAT_3TO0_0

M2

P24_4_SPIHB_SEL1/SDHC_CARD_IF_PWR_EN

M1

P24_3_SPIHB_SEL0/SDHC_CARD_CMD

L3

P24_2_SPIHB_RWDS/SDHC_CLK_CARD/LIN16_EN

L2

P24_1_SPIHB_CLK/SDHC_CARD_MECH_WRITE_PROT/LIN16_TX

L1

P24_0_SDHC_CARD_DETECT_N/LIN16_RX

K3

P23_7/PWM1_22/PWM1_23_N/TC1_22_TR0/TC1_23_TR1/EXT_CLK/LIN9_EN/TC1_H_9_TR1/SCB2_SEL0/CAL_SUP_NZ/SWJ_SW DOE_TDI/HIBERNATE_WAKEUP[1]

G15

P23_6_PWM1_23/PWM1_24_N/TC1_23_TR0/TC1_24_TR1/LIN9_TX/TC1_H_9_TR0/SCB2_CLK/SWJ_SW DIO_TMS

F16

P23_5_PWM1_24/PWM1_25_N/TC1_24_TR0/TC1_25_TR1/LIN9_RX/PWM1_H_9_N/SCB2_MOSI/SCB7_SEL2/SW J_SWCLK_TCLK

D20

P23_4_PWM1_25/PWM1_M_11_N/TC1_25_TR0/TC1_M_11_TR1/PWM1_H_9/SCB2_MISO/SCB7_SEL1/TRIG_DBG[0]/SW J_SWO_TDO/TRIG_IN[31]

E18

P23_3_PWM1_M_11/PWM1_M_10_N/TC1_M_11_TR0/TC1_M_10_TR1/SCB7_CTS/SCB7_SEL0/LIN6_TX/FAULT_OUT_3/TRIG_IN[30]

E19

Schematics of CPU Board

CYTVII-B-H-8M-320-CPU Evaluation Board User Guide, Document Number: 002-26716 Rev. *A 50

Schematics of CPU Board

Figure A-12. TVII-B-H-8M-320-BGA

5

4

3

2

1

TVII_B_H_8M_320_BGA

D

U6F

BB_FRA_ERRN{20,40}

BB_CAN6_WAKE

{20,42}

BB_CAN2_S

{20,42}

{20,40}

BB_CXPI_SELMS

BB_CAN1_S{20,40}

BB_CXPI_RXD

{20,40}

BB_USER_LED6{20,41}

BB_CXPI_NSLP

{20,40}

BB_GPIO_56_RESET{20,40}

BB_USER_LED5{20,41}

BB_FRB_WAKE{20,40}

GPIO_P30_1{19}

BB_CAN9_WAKE

C

B B

{20,43}

{20,40}

BB_USER_BUTTON_2{20,41} BB_USER_BUTTON_3{20,41}

{20,40}

BB_FRB_STBN

BB_USER_LED4{20,41}

BB_USER_LED3{20,41}

BB_USER_LED2{20,41} BB_USER_LED0{20,42}

BB_LIN4_RXD{20,41}

BB_USER_LED1{20,41}

BB_CAN0_TXD BB_CAN0_RXD{20,40}

GIG_ETH_TX_ER_R{19,30}

{17,19}

GIG_ETH_TX_D5_R{19,30} GIG_ETH_TX_D6_R{19,30} GIG_ETH_TX_D7_R{19,30} GIG_ETH_RX_D4_R{19,30} GIG_ETH_RX_D5_R{19,30} GIG_ETH_RX_D6_R{19,30} GIG_ETH_RX_D7_R{19,30} GIG_ETH_RX_ER_R{19,30}

{19}

GPIO_P31_1{19}

GPIO_P33_0{19}

GPIO_P33_2{19} GPIO_P33_3

GPIO_P34_4{19} GPIO_P34_5 GPIO_P34_6{19} GPIO_P34_7{19}

B19

P28_6_PWM1_69/PWM1_68_N/TC1_69_TR0/TC1_68_TR1/SCB10

A19

P28_7_PWM1_70/PWM1_69_N/TC1_70_TR0/TC1_69_TR1/LIN19_RX

A11

P29_0_PWM1_76/PWM1_75_N/TC1_76_TR0/TC1_75_TR1/LIN19

B11

P29_1_PWM1_77/PWM1_76_N/TC1_77_TR0/TC1_76_TR1/LIN19_EN

A10

P29_2_PWM1_78/PWM1_77_N/TC1_78_TR0/TC1_77_TR1

B10

P29_3_PWM1_79/PWM1_78_N/TC1_79_TR0/TC1_78_TR1

E10

P29_4_PWM1_80/PWM1_79_N/TC1_80_TR0/TC1_79_TR1

B9

P29_5_PWM1_81/PWM1_80_N/TC1_81_TR0/TC1_80_TR1

C9

P29_6_PWM1_82/PWM1_81_N/TC1_82_TR0/TC1_81_TR1

E9

P29_7_PWM1_83/PWM1_82_N/TC1_83_TR0/TC1_82_TR1

C7

P30_0_PWM1_83/PWM1_83_N/TC1_83_TR0/TC1_83_TR1/SCB9_

A6

P30_1_PWM1_82/PWM1_83_N/TC1_82_TR0/TC1_83_TR1/SCB9_CTS/SCB9_SEL0/LIN16_RX/TRIG_IN[35]

B6

P30_2_PWM1_81/PWM1_82_N/TC1_81_TR0/TC1_82_TR1/SCB9_

C6

P30_3_PWM1_80/PWM1_81_N/TC1_80_TR0/TC1_81_TR1/SCB9_SEL2/LIN16_EN/CAN1_3_RX/TRIG_IN[37]

E7

P31_0_PWM1_79/PWM1_80_N/TC1_79_TR0/TC1_80_TR1/LIN17_RX

F7

P31_1_PWM1_78/PWM1_79_N/TC1_78_TR0/TC1_79_TR1/LIN17

E6

P31_2_PWM1_77/PWM1_78_N/TC1_77_TR0/TC1_78_TR1/LIN17_EN

D2

P32_0_PWM1_76/PWM1_77_N/TC1_76_TR0/TC1_77_TR1/SCB10

D3

P32_1_PWM1_75/PWM1_76_N/TC1_75_TR0/TC1_76_TR1/SCB10_TX/SCB10_SDA/SCB10_MOSI/TRIG_IN[41]/ADC[0]_9

E5

P32_2_PWM1_74/PWM1_75_N/TC1_74_TR0/TC1_75_TR1/SCB10_RTS/SCB10_SCL/SCB10_CLK/LIN18_RX/TRIG_IN[42]/ADC[0]_10

E1

P32_3_PWM1_73/PWM1_74_N/TC1_73_TR0/TC1_74_TR1/SCB10

E2

P32_4_PWM1_72/PWM1_73_N/TC1_72_TR0/TC1_73_TR1/LIN10_RX/SCB10_SEL1/LIN18_EN/TRIG_IN[44]/ADC[0]_12

E3

P32_5_PWM1_71/PWM1_72_N/TC1_71_TR0/TC1_72_TR1/LIN10

F3

P32_6_PWM1_70/PWM1_71_N/TC1_70_TR0/TC1_71_TR1/LIN10_EN/SCB10_SEL3/LIN19_TX/CAN1_4_TX/TRIG_IN[46]/ADC[0]_14

F5

P32_7_PWM1_69/PWM1_70_N/TC1_69_TR0/TC1_70_TR1/LIN19

W18

P33_0_ETH0_REF_CLK/LIN12_RX

V17

P33_1_ETH0_TX_CTL/LIN12_TX/ETH1_TX_ER

W19

P33_2_ETH0_TX_CLK/LIN12_EN

V18

P33_3_ETH0_TXD_0/LIN13_RX/ETH1_TXD_4

W20

P33_4_ETH0_TXD_1/LIN13_TX/ETH1_TXD_5

V20

P33_5_ETH0_TXD_2/LIN13_EN/ETH1_TXD_6

V19

P33_6_ETH0_TXD_3/ETH1_TXD_7

U20

P33_7_ETH0_RXD_0/LIN14_RX/ETH1_RXD_4

U19

P34_0_ETH0_RXD_1/LIN14_TX/ETH1_RXD_5

U18

P34_1_ETH0_RXD_2/LIN14_EN/ETH1_RXD_6

T20

P34_2_ETH0_RXD_3/LIN15_RX/ETH1_RXD_7

T19

P34_3_ETH0_RX_CTL/LIN15_TX/ETH1_RX_ER

T18

P34_4_ETH0_RX_CLK/LIN15_EN

R20

P34_5_ETH0_MDIO

R19

P34_6_ETH0_MDC

R18

P34_7_ETH0_ETH_TSU_TIMER_CMP_VAL

TVII_B_H_8M_320_BGA_18

_SEL3/LIN18_EN

_TX

RTS/SCB9_SCL/SCB9_CLK/TRIG_IN[34]

SEL1/LIN16_TX/CAN1_3_TX/TRIG_IN[36]

_TX

_RX/SCB10_MISO/TRIG_IN[40]/ADC[0]_8

_CTS/SCB10_SEL0/LIN18_TX/TRIG_IN[43]/ADC[0]_11

_TX/SCB10_SEL2/LIN19_RX/TRIG_IN[45]/ADC[0]_13

_EN/CAN1_4_RX/TRIG_IN[47]/ADC[0]_15

D

C

CYPRESS SEMICONDUCTOR

CYPRESS SEMICONDUCTOR 198 CHAMPION COURT

198 CHAMPION COURT

198 CHAMPION COURT SAN JOSE, CA 95134

SAN JOSE, CA 95134

SAN JOSE, CA 95134 (408) 943-2600

(408) 943-2600

A

5

4

3

SCH Title :

Page Title :

Size

A4

Date: Sheet

TVII-B-H-8M 320-BGA CPU BOARD

TVII_B_H_8M_320_BGA_P6

Document Number Re v

630-60569-01 01

Wednesday, Auguﬆ 21, 2019

2

Drawn By

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Approved By

1

13 44

of

A

CYTVII-B-H-8M-320-CPU Evaluation Board User Guide, Document Number: 002-26716 Rev. *A 51

Figure A-13. TVII-B-H-8M-320-BGA

TVII_B_H_8M_320_BGA

5

4

3

2

1

D D

C C

B B

A A

Place one 0.1uF capacitor near each of the Power pins

4.7uF capacitor needs to be placed near to the corresponding pins

On each VCCD/VSSD pin pair a 0.1uF is required

DGND

AGND

DGND

DNGADNGD

On each VDDD/VSSD pin pair a 0.1uF is required

On each VDDA/VSSD pin pair a 0.1uF is required

DGND

AGND

DGND

CPU_VDDD

CPU_VDDA

CPU_VDDIO1

CPU_VCCD

CPU_VDDIO2

FB1V{5}

SCH Title :

Size

Document Number Re v

Date: Sheet

of

Page Title :

Drawn By

CYPRESS SEMICONDUCTOR 198 CHAMPION COURT SAN JOSE, CA 95134 (408) 943-2600

Approved By

630-60569-01

01

TVII-B-H-8M 320-BGA CPU BOARD

A4

14 44

Wednesday, Auguﬆ 21, 2019

TVII_B_H_8M_320_BGA_P7

VJYM SPPD

SCH Title :

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Document Number Re v

Date: Sheet

of

Page Title :

Drawn By

CYPRESS SEMICONDUCTOR 198 CHAMPION COURT SAN JOSE, CA 95134 (408) 943-2600

Approved By

630-60569-01

01

TVII-B-H-8M 320-BGA CPU BOARD

A4

14 44

Wednesday, Auguﬆ 21, 2019

TVII_B_H_8M_320_BGA_P7

VJYM SPPD

SCH Title :

Size

Document Number Re v

Date: Sheet

of

Page Title :

Drawn By

CYPRESS SEMICONDUCTOR 198 CHAMPION COURT SAN JOSE, CA 95134 (408) 943-2600

Approved By

630-60569-01

01

TVII-B-H-8M 320-BGA CPU BOARD

A4

14 44

Wednesday, Auguﬆ 21, 2019

TVII_B_H_8M_320_BGA_P7

VJYM SPPD

C131

0.1uF/16V

C118

0.1uF/16V

C133

0.1uF/16V

C107

0.1uF/16V

C115

0.1uF/16V

C106

0.1uF/16V

C97

10uF/16V

C108

0.1uF/16V

C110

0.1uF/16V

C113

0.1uF/16V

C121

0.1uF/16V

C105

0.1uF/16V

R222 0 Ohm

DNI

R146

2 Pin Jumper

C98

10uF/16V

C111

0.1uF/16V

C124

0.1uF/16V

U6G

TVII_B_H_8M_320_BGA_18

VSSD

H12

VSSD

H11

VSSD

H10

VSSD

H9

VSSD

C18

VSSD

C10

VSSD

C3

VSSD

A20

VSSD

A1

VSSA

N8

VDDIO_2

R8

VDDIO_1

F13

VDDIO_1

F12

VDDIO_1

F11

VDDIO_1

F10

VDDD

R13

VDDD

R12

VDDD

N15

VDDD

L15

VDDD

M15

VDDD

K15

VDDD

J15

VDDD

H15

VDDD

F9

VDDD

F8

VDDA

N6

VCCD

R15

VCCD

R6

VCCD

F15

VCCD

F6

VSSD

H13

VSSD

J9

VSSD

J10

VSSD

J11

VSSD

J12

VSSD

J13

VSSD

J18

VSSD

K9

VSSD

K10

VSSD

K11

VSSD

K12

VSSD

K13

VSSD

K18

VSSD

L9

VSSD

L10

VSSD

L11

VSSD

L12

VSSD

L13

VSSD

M9

VSSD

Y20

VSSD

Y1

VSSD

V15

VSSD

V4

VSSD

V3

VSSD

N12

VSSD

M13

VSSD

M12

VSSD

M11

VSSD

M10

VSSD_1

N13

VSSD_2

L20

C112

0.1uF/16V

C125

0.1uF/16V

C116

2.2uF/16V

C127

4.7uF/16V

C114

0.1uF/16V

C126

0.1uF/16V

C117

0.1uF/16V

C109

2.2uF/16V

C128

0.1uF/16V

Schematics of CPU Board

CYTVII-B-H-8M-320-CPU Evaluation Board User Guide, Document Number: 002-26716 Rev. *A 52

Figure A-14. TVII-B-H-8M-320-BGA

Schematics of CPU Board

TP35 THRU HOLE

AGND_R

3

U6H

M8

VREFL

M6

VREFH

L6

VDDIO_3

K6

VDDIO_3

J6

VDDIO_3

H6

VDDIO_3

R11

VDDIO_4

R10

VDDIO_4

R9

VDDIO_4

TVII_B_H_8M_320_BGA_18

3

XRES

VSSD_2

VSSIO_3

VSSIO_4

K20

P20

L8

K8

J8

H8

N11

N10

N9

2

CPU_XRES {22,25,26,28,31,35,39}

DGND

SCH Title :

Page Title :

Size

A4

Date: Sheet

TVII-B-H-8M 320-BGA CPU BOARD

TVII_B_H_8M_320_BGA_P8

Document Number

630-60569-01

Wednesday, Auguﬆ 21, 2019

2

CYPRESS SEMICONDUCTOR

CYPRESS SEMICONDUCTOR 198 CHAMPION COURT

198 CHAMPION COURT

198 CHAMPION COURT SAN JOSE, CA 95134

SAN JOSE, CA 95134

SAN JOSE, CA 95134 (408) 943-2600

(408) 943-2600

Drawn By

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5

D D

C

B

A

5

CPU_VDDA

CPU_VDDIO3

CPU_VDDIO4

4

R119 0 Ohm

2.2uF/16V

C137

2.2uF/16V

C104

2.2uF/16V

4

TVII_B_H_8M_320_BGA

R142 0 Ohm

AGND

TP36 THRU HOLE

CPU_VDDA_R

C134

0.1uF/16V

C132

DGND

C123

0.1uF/16V

DGND

C130

C129

0.1uF/16V

C122

0.01uF/25V

1

Approved By

15 44

1

Rev

01

of

C

B

A

CYTVII-B-H-8M-320-CPU Evaluation Board User Guide, Document Number: 002-26716 Rev. *A 53

Figure A-15. MCU Port Pin Mux Options

A

5 4 3 2 1

D

Schematics of CPU Board

MCU PORT PIN - MUX OPTIONS

0 OHM

J22

1

2

3

3 Pin Jumper

J37

1

2

3

3 Pin Jumper

R317

R318

R319

R320

{9}

GPIO_P6_3

{9}

GPIO_P6_4

C

GPIO_P22_1{11}

GPIO_P22_2{11}

EMMC_CMD {19,36}

BB_CAN2_RXD {20,42}

EMMC_CLK {19,36}

BB_CAN7_WAKE {20,42}

TRACE_DATA_1_1 {19,25}

EXT_PS_CTL0 {4,5}

TRACE_DATA_2_1 {19,25}

EXT_PS_CTL1 {4,5}

GPIO_P12_0{9}

GPIO_P12_1

{9}

GPIO_P12_2

{9}

GPIO_P12_3{10}

B

J38

GPIO_P22_3{11}

1

2

3

3 Pin Jumper

TRACE_DATA_3_1 {19,25}

EXT_PS_CTL2 {5}

A

0 OHM

R340

R339

0 OHM

R341

R342

0 OHM

R348

R347

0 OHM

R350

R349

0 OHM

SCH Title :

TVII-B-H-8M 320-BGA CPU BOARD

MCU PORT PIN - MUX OPTIONS

Page Title :

Size

Document Number Re v

A4

630-60569-01 01

Wednesday, Auguﬆ 21, 2019

Date:

AUDIO_0_I2S_TX_SDO {34}

BB_CAN2_TXD {20,42}

AUDIO_0_CLK_I2S_IF {34}

BB_LIN1_SLP {20,40}

AUDIO_0_I2S_RX_SCK {34}

BB_LIN1_RXD {20,40}

AUDIO_0_I2S_RX_WS {34}

BB_LIN1_TXD {20,40}

CYPRESS SEMICONDUCTOR

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198 CHAMPION COURT

198 CHAMPION COURT SAN JOSE, CA 95134

SAN JOSE, CA 95134

SAN JOSE, CA 95134 (408) 943-2600

(408) 943-2600

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CYTVII-B-H-8M-320-CPU Evaluation Board User Guide, Document Number: 002-26716 Rev. *A 54

Figure A-16. MCU Port Pin Mux Options

A

5 4 3 2 1

Schematics of CPU Board

MCU PORT PIN - MUX OPTIONS

D

GPIO_P18_0{11,20}

{11,20}

GPIO_P18_1

C

{11,20}

GPIO_P18_2

{11,20}

GPIO_P18_3

B

{11,19}

GPIO_P18_4

{11,20}

GPIO_P18_5

0 OHM

J39

1

2

3

3 Pin Jumper

J40

1

2

3

3 Pin Jumper

J41

1

2

3

3 Pin Jumper

R352

R351

R371

R372

R362

R361

AUTO_ETH_REF_CLK_R {19,27}

BB_CAN_SPI1_MISO {40}

AUTO_ETH_TXEN_R {19,27}

BB_CAN_SPI1_MOSI {40}

AUTO_ETH_TXER_R {19,27}

BB_CAN_SPI1_SCK {40}

AUTO_ETH_TXC_R {19,27}

TRACE_CLOCK_0 {25}

AUTO_ETH_TXD0_R {17,27}

TRACE_DATA_0_0 {25}

AUTO_ETH_TXD1_R {19,27}

TRACE_DATA_1_0 {25}

{11}

GPIO_P18_6{11,20}

GPIO_P18_7{11,20}

GPIO_P33_3{13,19}

GPIO_P21_5

A

J42

1

2

3

3 Pin Jumper

J43

1

2

3

3 Pin Jumper

J44

1

2

3

3 Pin Jumper

J45

1

2

3

3 Pin Jumper

SCH Title :

Page Title :

Size

Document Number

A4

630-60569-01 01

Wednesday, Auguﬆ 21, 2019

Date:

AUTO_ETH_TXD2_R {19,27}

TRACE_DATA_2_0 {25}

AUTO_ETH_TXD3_R {19,27}

TRACE_DATA_3_0 {25}

AUTO_ETH_TXD0_R {17,27}

GIG_ETH_TX_D4_R {30}

AUTO_ETH_RXDV_R {19,27}

TRACE_DATA_0_1 {19,25}

CYPRESS SEMICONDUCTOR

CYPRESS SEMICONDUCTOR 198 CHAMPION COURT

198 CHAMPION COURT

198 CHAMPION COURT SAN JOSE, CA 95134

SAN JOSE, CA 95134

SAN JOSE, CA 95134 (408) 943-2600

(408) 943-2600

TVII-B-H-8M 320-BGA CPU BOARD

MCU PORT PIN - MUX OPTIONS

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CYTVII-B-H-8M-320-CPU Evaluation Board User Guide, Document Number: 002-26716 Rev. *A 55

Figure A-17. MCU Port Pin Mux Options

MCU PORT PIN - MUX OPTIONS

5 4

3

2 1

D

C

B

A

GPIO_P19_0{11,20}

AUTO_ETH_RXD0_R {19,27}

TRSTN_SEC {25}

GPIO_P19_1{11,20}

AUTO_ETH_RXD1_R {19,27}

SWO_TDO_SEC {25}

GPIO_P19_2{11,20}

AUTO_ETH_RXD2_R {19,27}

SWDOE_TDI_SEC {25}

GPIO_P19_3{11,20}

AUTO_ETH_RXD3_R {19,27}

SWDIO_TMS_SEC {25}

GPIO_P13_1{10}

AUDIO_1_I2S_TX_SCK {34}

UART_TX {24,41}

GPIO_P13_3{10}

AUDIO_1_I2S_TX_SDO {19,34}

BB_UART0_CTS {20,41}

GPIO_P13_5

{10}

AUDIO_1_I2S_RX_SCK {34}

BB_LIN2_TXD {20,40}

GPIO_P13_0{10}

AUDIO_1_I2S_MCLK {19,34}

UART_RX {24,41}

GPIO_P13_2{10}

AUDIO_1_I2S_TX_WS {34}

BB_UART0_RTS {20,41}

GPIO_P13_4

{10}

AUDIO_1_CLK_I2S_IF {34}

BB_LIN2_RXD {20,40}

GPIO_P13_6

{10}

AUDIO_1_I2S_RX_WS {34}

BB_LIN2_SLP {20,41}

SCH Title :

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Approved By

630-60569-01 01

TVII-B-H-8M 320-BGA CPU BOARD

A4

Wednesday, Auguﬆ 21, 2019

MCU PORT PIN - MUX OPTIONS

VJYM SPPD

SCH Title :

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630-60569-01 01

TVII-B-H-8M 320-BGA CPU BOARD

A4

Wednesday, Auguﬆ 21, 2019

MCU PORT PIN - MUX OPTIONS

VJYM SPPD

SCH Title :

Size

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Approved By

630-60569-01 01

TVII-B-H-8M 320-BGA CPU BOARD

A4

Wednesday, Auguﬆ 21, 2019

MCU PORT PIN - MUX OPTIONS

VJYM SPPD

R360

0 OHM

R369

0 OHM

R367

0 OHM

J51

3 Pin Jumper

1

2

3

R370

0 OHM

R368

0 OHM

J49

3 Pin Jumper

1

2

3

J47

3 Pin Jumper

1

2

3

R357

0 OHM

R358

0 OHM

R365

0 OHM

J50

3 Pin Jumper

1

2

3

J48

3 Pin Jumper

1

2

3

R366

0 OHM

R359

0 OHM

J46

3 Pin Jumper

1

2

3

Schematics of CPU Board

CYTVII-B-H-8M-320-CPU Evaluation Board User Guide, Document Number: 002-26716 Rev. *A 56

18 44

Figure A-18. Test Points-1

Schematics of CPU Board

5

4

3

2

1

TEST POINTS-1

P10

AUTO_ETH_TXC_R{17,27} AUTO_ETH_TXEN_R {17,27}

D D

C C

B B

A A

AUTO_ETH_REF_CLK_R{17,27}

AUTO_ETH_TXD1_R{17,27}

{17,27}

AUTO_ETH_TXD3_R

{18,27}

AUTO_ETH_RXD1_R

{18,27}

AUTO_ETH_RXD2_R

AUTO_ETH_RXER_R{8,27}

AUTO_ETH_MDIO_R{8,27}

GIG_ETH_RX_DV_CTRL_R{12,30}

GIG_ETH_TX_EN_CTRL_R{12,30}

{13,30} {13,30}

{13,30}

GIG_ETH_RX_CLK_R

{12,30}

{12,37}

{16,25}

GIG_ETH_RX_D3_R{12,30}

GIG_ETH_RX_D1_R{12,30} GIG_ETH_RX_D0_R{12,30}

GIG_ETH_TX_D1_R{12,30}

GPIO_P16_2{10} GPIO_P14_0{10}

GPIO_P33_3{13,17}

GIG_ETH_RX_D7_R GIG_ETH_RX_D4_R

GIG_ETH_TX_D6_R{13,30} GIG_ETH_TX_D5_R GIG_ETH_TX_ER_R{13,30}

GM_DQ5_R{12,37} GM_DQ3_R{12,37} GM_DQ2_R{12,37} GM_DQ0_R

{12,37}

GM_CS#1_R{12,37} GM_CS#0_R

GM_CK_R{12,37}

GM_RWDS_R

TRACE_DATA_0_1{17,25} TRACE_DATA_3_1{16,25} TRACE_CLOCK_1{11,25} TRACE_DATA_2_1 TRACE_DATA_1_1{16,25}

GPIO_P2_5{8} GPIO_P17_3{10} GPIO_P20_5{11}

5

1 3 5 7

9 11 13 15

HEADER_8X2

1

3

5

7

9 11 13 15

1

3

5

7

9 11 13 15

1

3

5

7

9 11 13 15

1

3

5

7

9 11 13 15

1

2

3

4

5

6

7

8

9

10

11

12

13

14

15

16

P11

1

2

3

4

5

6

7

8

9

10

11

12

13

14

15

16

HEADER_8X2

P9

1

2

3

4

5

6 8

7 9

10

11

12

13

14

15

16

HEADER_8X2

P17

1

2

3

4

5

6 8

7 9

10

11

12

13

14

15

16

HEADER_8X2

P1

1

2

3

4

5

6 8

7 9

10

11

12

13

14

15

16

HEADER_8X2

2 4 6 8 10 12 14 16

AUTO_ETH_TXER_R {17,27} AUTO_ETH_TXD2_R {17,27} AUTO_ETH_RXD0_R {18,27} AUTO_ETH_RXDV_R {17,27} AUTO_ETH_RXD3_R {18,27} AUTO_ETH_RXC_R {12,27} AUTO_ETH_MDC_R {8,27}

GIG_ETH_TX_D2_R {12,30} GIG_ETH_TX_CLK_R {12,30} GIG_ETH_RX_D2_R {12,30} GIG_ETH_TX_D3_R {12,30} GIG_ETH_TX_D0_R {12,30}

GPIO_P14_3 {10} GPIO_P14_4 {10}

GIG_ETH_RX_ER_R {13,30} GIG_ETH_RX_D5_R {13,30} GIG_ETH_TX_D7_R {13,30} GIG_ETH_RX_D6_R {13,30} GIG_ETH_MDC_R {12,30} GIG_ETH_MDIO_R {12,30}

GPIO_P8_2 {9} GPIO_P24_0 {12} GPIO_P9_2 {9} GPIO_P14_7 {10} GM_DQ6_R {12,37} GM_DQ7_R {12,37} GM_DQ4_R {12,37} GM_DQ1_R {12,37}

GPIO_P28_0 {12} CB_LED_P0_0 {8,23} GPIO_P1_5 {8} GPIO_P30_1 {13} GPIO_P1_6 {8} GPIO_P31_1 {13} GPIO_P10_0 {9}

4

SWO_TDO_PRM{12,25}

SWCLK_TCLK_PRM{12,25}

SWDOE_TDI_PRM

{12,25}

SWDIO_TMS_PRM{12,25}

GPIO_P34_5{13}

GPIO_P17_2{10}

{9,36}

EMMC_CD

EMMC_CMD{16,36} EMMC_DATA1{9,36} EMMC_DATA3

{9,36}

{10}

GPIO_P12_5

GPIO_P9_0

{9}

GPIO_P10_1{9} GPIO_P7_0{9}

GPIO_P8_0{9}

{8}

GPIO_P5_1

GPIO_P6_0{9}

AUDIO_1_I2S_MCLK{18,34}

BB_SPI0_MISO{8,35,41}

{8,35}

AUDIO_SPI0_SS1

GPIO_P8_4{9} GPIO_P9_1{9}

GPIO_P27_7{12} GPIO_P16_7{10} GPIO_P16_5{10} GPIO_P17_6{10} GPIO_P16_1{10,39}

GPIO_P16_0{10,38}

3

P2

1 3 5 7

9 11 13 15

1

3

5

7

9 11 13 15

1

3

5

7

9 11 13 15

1

3

5

7

9 11 13 15

SCH Title :

Page Title :

Size

A4

Date: Sheet

2

1

2

4

3

6

5

6

8

7

8

10

9

12

11

14

13

16

15

16

HEADER_8X2

P16

2

1

2

4

3

4

6

5

8

7

8

10

9

10

12

11

14

13

16

15

HEADER_8X2

P15

2

1

2

4

3

6

5

8

7

8

10

9

12

11

14

13

16

15

HEADER_8X2

P12

2

1

2

4

3

4

6

5

8

7

8

10

9

10

12

11

14

13

16

15

HEADER_8X2

TVII-B-H-8M 320-BGA CPU BOARD

TEST POINTS-1

Document Number Re v

630-60569-01

Wednesday, Auguﬆ 21, 2019

GPIO_P34_7 {13} GPIO_P34_6 {13} GPIO_P16_3 {10} GPIO_P34_4 {13} GPIO_P33_2 {13} GPIO_P33_0 {13}

GPIO_P16_4 {10}

EMMC_WP {9,36} EMMC_CLK {16,36} EMMC_DATA0 {9,36} EMMC_DATA2 {9,36} GPIO_P7_5 {9} GPIO_P12_7 {10} GPIO_P8_1 {9} GPIO_P9_3 {9}

GPIO_P5_2 {8} GPIO_P5_0 {8} GPIO_P5_3 {8} GPIO_P6_1 {9} GPIO_P18_4 {11,17} BB_SPI0_MOSI {8,35,41} AUDIO_1_I2S_TX_SDO {18,34} GPIO_P8_3 {9}

GPIO_P17_4 {10} GPIO_P16_6 {10} GPIO_P17_5 {10} GPIO_P17_7 {11} GPIO_P15_3 {10} GPIO_P14_5 {10} GPIO_P15_2 {10} GPIO_P14_6 {10,38}

CYPRESS SEMICONDUCTOR

CYPRESS SEMICONDUCTOR 198 CHAMPION COURT

198 CHAMPION COURT

198 CHAMPION COURT SAN JOSE, CA 95134

SAN JOSE, CA 95134

SAN JOSE, CA 95134 (408) 943-2600

(408) 943-2600

Drawn By

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CYTVII-B-H-8M-320-CPU Evaluation Board User Guide, Document Number: 002-26716 Rev. *A 57

Figure A-19. Test Points-2

Schematics of CPU Board

5

4

3

2

1

TEST POINTS-2

P14

{8,35,42}

D

C

B B

{13,42}

{8,43}

{10,43}

{18,40}

{8,40}

{12,40}

BB_USER_BUTTON_5{12,41}

{11,41}

{8,42}

{8,41}

{9,41}

BB_SPI0_CLK BB_CAN7_WAKE{16,42} BB_USER_LED0

GPIO_P0_2{8} GPIO_P2_1{8} BB_SPI0_SS0

BB_CAN8_WAKE

BB_CAN6_TXD

BB_LIN2_RXD BB_LIN2_TXD{18,40} BB_LIN2_SLP{18,41}

BB_ADC_POT{10,41} BB_UART0_RTS{18,41} BB_FRB_STBN{13,40}

BB_CXPI_CLK BB_UART0_CTS{18,41}

BB_USER_LED1{13,41}

BB_LIN4_TXD BB_USER_LED3{13,41} BB_USER_LED4{13,41} BB_USER_LED6{13,41} BB_USER_LED8 BB_LIN1_WAKE{8,40} BB_LIN0_WAKE{8,40}

BB_FRA_ERRN{13,40} BB_SPI0_HOLD

BB_LIN3_WAKE{8,41}

BB_LIN0_RXD{8,40} BB_CAN3_TXD{11,41} BB_CAN3_RXD

BB_LIN0_SLP{11,40}

1 3 5

7

9 11 13 15

1

3

5

7

9 11 13 15

1

3

5 7 9

11 13 15

1 3

5 7 9

11 13 15

1

2

3

4

5

6

7

8

9

10

11

12

13

14

15

16

HEADER_8X2

P8

1

2

3

4

5

6

7

8

9

10

11

12

13

14

15

16

HEADER_8X2

P5

1

2

3

4

5

6

7

8

9

10

11

12

13

14

15

16

HEADER_8X2

P6

1

2

3

4

5

6

7

8

9

10

11

12

13

14

15

16

HEADER_8X2

2 4 6 8 10 12 14 16

GPIO_P0_1 {8} GPIO_P0_3 {8} BB_CAN2_RXD {16,42} BB_CAN2_TXD {16,42}

GPIO_P2_3 {8} BB_CAN9_WAKE {13,43} BB_CAN6_RXD {10,43}

BB_CAN0_S {8,40}

BB_GPIO_56_RESET {13,40}

BB_FRA_WAKE {9,40} BB_FRB_ERRN {9,40}

BB_LIN4_SLP {9,41} BB_CAN0_RXD {13,40} BB_FRB_WAKE {13,40} BB_USER_LED5 {13,41} BB_USER_LED7 {8,41} BB_USER_LED9 {8,40} BB_CXPI_SELMS {13,40} BB_CXPI_TXD {8,40}

BB_FRA_STBN {12,40} BB_SPI0_WP {12,40} BB_LIN2_WAKE {8,40} BB_LIN4_WAKE {8,41} BB_LIN5_WAKE {8,40} BB_LIN3_RXD {11,41} BB_LIN0_TXD {11,40} BB_LIN3_SLP {11,41}

{13,40}

{10,41}

{13,40}

{9,40}

BB_USER_BUTTON_3{13,41} BB_USER_BUTTON_2{13,41}

{12,42}

BB_USER_BUTTON_4

{13,42}

BB_CXPI_RXD BB_LIN1_RXD{16,40} BB_CAN1_S{13,40}

BB_FRB_RXD{9,40} BB_I2C1_SCL

BB_CAN0_TXD

BB_FRB_TXD BB_LIN5_RXD{11,40} BB_LIN5_SLP{11,40}

BB_CAN5_S{8,42} BB_CAN4_S

{8,42}

BB_CAN6_WAKE

BB_CAN3_S

{8,42}

BB_CAN2_S{13,42}

{11,18} {11,17} {11,17}

{11,18}

GPIO_P19_2 GPIO_P18_6 GPIO_P18_0

GPIO_P19_1

GPIO_P19_3

1

3

5

7

9

11

13

15

HEADER_8X2

1

3

5

7

9

11

13

15

HEADER_8X2

1

3

5

7

9

11

13

15

HEADER_8X2

1

3

5

7

9

11

13

15

HEADER_8X2

P4

P3

P13

P7

2

4

4 6

8 10 12 14 16

2

4

6

8 10 12 14 16

2

4

6

8 10 12 14 16

2

4

6

8 10 12 14 16

BB_I2C1_SDA {10,41}

6

BB_CAN1_RXD {10,40}

8

BB_CXPI_NSLP {13,40}

10

BB_LIN1_SLP {16,40}

12

BB_FRA_TXEN {9,40}

14

BB_FRB_TXEN {9,40}

16

BB_LIN4_RXD {13,41}

2

BB_LIN1_TXD {16,40}

4 6

BB_CAN1_TXD {10,40}

8

BB_LIN5_TXD {11,40}

10

BB_LIN3_TXD {11,41}

12 14

BB_USER_BUTTON_1 {9,41}

16

BB_USER_LED2 {13,41}

2

BB_FRA_TXD {9,40}

4

BB_FRA_RXD {9,40}

6

BB_CAN4_RXD {11,43}

8

BB_CAN4_TXD {11,43}

10

BB_CAN_SPI1_SS0 {11,42}

12

BB_CAN_SPI1_SS1 {11,42}

14 16

2

SWCLK_TCLK_SEC {11,25}

4

GPIO_P18_7 {11,17}

6

GPIO_P18_2 {11,17}

8

GPIO_P18_5 {11,17}

10 12

GPIO_P19_0 {11,18}

14

GPIO_P18_3 {11,17}

16

GPIO_P18_1 {11,17}

CYPRESS SEMICONDUCTOR

CYPRESS SEMICONDUCTOR 198 CHAMPION COURT

198 CHAMPION COURT

198 CHAMPION COURT SAN JOSE, CA 95134

SAN JOSE, CA 95134

SAN JOSE, CA 95134 (408) 943-2600

(408) 943-2600

D

C

A A

Size

A4

5

4

3

SCH Title :

TVII-B-H-8M 320-BGA CPU BOARD

TEST POINTS-2

Page Title :

Document Number

630-60569-01

Wednesday, Auguﬆ 21, 2019

Date: Sheet

2

Drawn By

VJYM SPPD

Approved By

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1

Rev

01

of

CYTVII-B-H-8M-320-CPU Evaluation Board User Guide, Document Number: 002-26716 Rev. *A 58

Figure A-20. Clock

5

4

3

2

1

D

C

B

A

Damping resistor, need to be tuned

ECI/BTB_R

ECO/BTB_R

WCO/BTB_R

CPU_WCO_IN {11} CPU_WCO_OUT {11} CPU_ECO_IN {11} CPU_ECO_OUT {11}

ECI/BTB

{21}

WCI/BTB{21}

WCO/BTB

{21}

ECI/BTB{21} ECO/BTB{21}

WCI/BTB

{21}

ECI/BTB {21}

ECO/BTB {21}

WCO/BTB

{21}

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CLOCK

VJYM SPPD

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CLOCK

VJYM SPPD

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CLOCK

VJYM SPPD

C18

12pF/50V

J23

CON_MCXJACK5_F

DNI

2

1

3 4 5

R65 0 OhmC17

12pF/50V

R64 0 Ohm

R66 0 Ohm

C102

10pF/25V

TP19

R280 0 Ohm

Y8

ABM10-16.000MHZ-D30-T3

1

4 2

3

C101

10pF/25V

R277

0 Ohm

R279 0 Ohm

TP21

Y1

32.768KHz

1 4

2 3

R278

0 Ohm

DNI

CLOCK

ECO & WCO

Schematics of CPU Board

CYTVII-B-H-8M-320-CPU Evaluation Board User Guide, Document Number: 002-26716 Rev. *A 59

Figure A-21. Reset Controller

5

4

3

2

1

D

C

B

A

DEFAULT CLOSE

RESET_LED

RST_SW RST_MR

RST_MR

CT

RESET_CON_OUT

RESET_SNS

RST_OUT

RST_MR

RESET_CON_SENSE

CPU_VDDD

VCC_1V1

CPU_XRES {15,22,25,26,28,31,35,39}

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RESET CONTROLLER

VJYM SPPD

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A4

22 44

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RESET CONTROLLER

VJYM SPPD

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A4

22 44

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RESET CONTROLLER

VJYM SPPD

R148

10K

R158

1K

LED7

LTST-C150GKT

2 1

R152

1K / 2 Pin Jumper

DNI

SW3

PTS810 SJG 250 SMTR LFS

1

3

2

4

R156 1K

R155

0 Ohm

C64

0.1uF/25V

R160

10K

R157 0 Ohm

DNI

J27 HDR_1X2

1

2

C61

0.1uF/16V

DNI

R154 1K

R161 220 OHM

D6

SD05C-01FTG

12

R153 22K

R145 100 ohm_1% U7

TPS3808G01QDBVRQ1

RESET

1

GND

2

MR

3

CT

4

SENSE

5

VDD

6

C60

0.1uF/16V

C62

1000pF/16V

RESET CONTROLLER

Schematics of CPU Board

CYTVII-B-H-8M-320-CPU Evaluation Board User Guide, Document Number: 002-26716 Rev. *A 60

Figure A-22. GPIO - Button & Led

5

4

3

2

1

D

C

B

A A

DEFAULT CLOSE Footprint of J5 Should be compatible with a 0E resistor

DEFAULT CLOSE

CB_LED_P23_2_RCB_LED_P23_2_LED

CB_BUTTON_P21_4_R CB_BUTTON_P21_4_SW

CB_LED_P0_0_LED

CB_LED_P0_0_R

CPU_VDDIO2

CB_LED_P23_2{11}

CB_BUTTON_P21_4 {11}

CB_LED_P0_0

{8,19}

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GPIO - BUTTON & LED

VJYM SPPD

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GPIO - BUTTON & LED

VJYM SPPD

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23 44

Wednesday, Auguﬆ 21, 2019

GPIO - BUTTON & LED

VJYM SPPD

R373 1K

LD2

LTST-C150GKT

2 1

R218 20 ohm

R219

10K

C94

0.1uF/16V

LD1

LTST-C150GKT

2 1

J2

HDR_1X2

1

2

R8 1K

J3

HDR_1X2

1

2

J52

HDR_1X2

1

2

SW1

PTS810 SJG 250 SMTR LFS

1

3

2

4

GPIO - BUTTON & LED

PUSH BUTTON

USER LED USER LED

Schematics of CPU Board

CYTVII-B-H-8M-320-CPU Evaluation Board User Guide, Document Number: 002-26716 Rev. *A 61

Figure A-23. UART - USB Transceiver

5

4

3

2

1

D

C

B

A A

DEFAULT CLOSE

OVERLAP THE VCCIO_USB_5V PADS OF R57 & R48

DEFAULT CLOSE

USBDM_CONN USBDP_CONN

CTS RTS

DTR DSR

DCD

RI

RST_UART

USB_GPIO4

TXLED RXLED

USB_TX_R

USB_RX_R

VCCD

USB_DNU

USB_NC2

TXD RXD

USB_RXR

USBDM

USBDP

USBDP USBDM

USB_SHIELD

VCCIO_USB

USB_VIN

VCCIO_USB

VCC_USB

CPU_VDDIO2

UART_RX

{18,41}

UART_TX{18,41}

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A4

24

44

Wednesday, Auguﬆ 21, 2019

USB-UART TRANCEIVER

VJYM SPPD

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A4

24

44

Wednesday, Auguﬆ 21, 2019

USB-UART TRANCEIVER

VJYM SPPD

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A4

24

44

Wednesday, Auguﬆ 21, 2019

USB-UART TRANCEIVER

VJYM SPPD

L4

90 OHM

1

3

2

4

LED5 LTST-C150GKT

21

R176

0 Ohm

DNI

C68

0.1uF/25V

FL6

BLM18HE601SN1D

12

R172 0 Ohm

DNI

LED6 LTST-C150GKT

21

R167

1K

C65

4.7uF/16V

R288 220 OHM

R171 0 Ohm

DNI

R165

4.7K

DNI

R175 0 Ohm

U8

CY7C65213-28PVXI

TXD

1

RTS#

3

VCCIO

4

RXD

5

GND

7

GPIO5

8

DCD#

10

CTS#

11

GPIO4

12

GPIO2

13

GPIO3

14

VCCD

17

GND

18

RESET#

19

GND

21

GPIO1

22

GPIO0

23

NC1

24

NC2

25

DNU

26

GPIO6

27

GPIO7

28

VCC

20

USBDP

15

USBDM

16

RI#

6

DTR#

2

DSR#

9

R289 220 OHM

TP38

THRU HOLE

R166

10K

DNI

C138

4.7uF/16V

C77

0.1uF/25V

J28 CON_MUSB-B_5_F

VBUS

1

D+

3

D-

2

ID

4

SH1

SH2

GND

5

R162

0 Ohm

DNI

C67

1uF/25V

R170 0 Ohm

C72

0.01uF/25V

J31

HDR_1X2

1

2

R163 0 Ohm

DNI

FL5 BLM18HE601SN1D

1 2

J30

HDR_1X2

1

2

R169

0 Ohm

UART TO USB TRANSCEIVER

Schematics of CPU Board

CYTVII-B-H-8M-320-CPU Evaluation Board User Guide, Document Number: 002-26716 Rev. *A 62

Figure A-24. Debug Interface-1

5

4

3

2

1

D

C

B

A A

ARM_JTAG_R1

ARM_JTAG_NC1 ARM_JTAG_NC2

TCLK_R

ARM_JTAG_R2

CORTEX_DEBUG_R

CPU_VDDD

CPU_VDDD CPU_VDDD

TRSTN{25,26} SWDOE_TDI{25,26} SWDIO_TMS{25,26}

SWCLK_TCLK{25,26}

SWO_TDO{25,26}

SRST_IDC20{25}

SWDIO_TMS {25,26} SWCLK_TCLK {25,26} SWO_TDO {25,26} SWDOE_TDI {25,26} NRST_CORTEX20 {25} TRACE_CLOCK {25,26} TRACE_DATA_0 {25,26} TRACE_DATA_1 {25,26} TRACE_DATA_2 {25,26} TRACE_DATA_3 {25,26}

SWO_TDO {25,26}

SWCLK_TCLK {25,26}

SWDIO_TMS {25,26}

SWDOE_TDI {25,26}

TRSTN {25,26}

TRSTN_SEC

{18}

SWDOE_TDI_SEC{18}

SWDIO_TMS_SEC{18}

SWCLK_TCLK_SEC

{11,20}

SWO_TDO_SEC

{18}

SWO_TDO_PRM{12,19}

SWCLK_TCLK_PRM{12,19}

SWDIO_TMS_PRM{12,19}

SWDOE_TDI_PRM{12,19}

TRSTN_PRM

{8}

TRACE_DATA_0_1{17,19}

TRACE_DATA_1_1{16,19}

TRACE_DATA_2_1{16,19}

TRACE_DATA_3_1{16,19}

TRACE_CLOCK_1

{11,19}

TRACE_DATA_0_0{17}

TRACE_DATA_1_0{17}

TRACE_DATA_2_0{17}

TRACE_DATA_3_0{17}

TRACE_CLOCK_0{17}

TRACE_DATA_0 {25,26}

TRACE_DATA_1 {25,26}

TRACE_DATA_2 {25,26}

TRACE_DATA_3 {25,26}

TRACE_CLOCK {25,26}

SRST_IDC20{25}

TRSTN {25,26}

NRST_CORTEX20

{25}

TRSTN {25,26}

CPU_XRES {15,22,25,26,28,31,35,39}

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DEBUG INTERFACE_1

VJYM SPPD

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DEBUG INTERFACE_1

VJYM SPPD

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25 44

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DEBUG INTERFACE_1

VJYM SPPD

R22

0 OhmDNI

R237 0 Ohm

J5

FTSH-110-01-L-DV-K

VTref1SWDIO/TMS

2

GND

5

SWDCLK/TCK

4

GND

3

SW0/TDO

6

KEY

7

TDI

8

GND DETECT9nRESET

10

GND

11

TRACECLK

12

GND13TRACEDATA[0]

14

GND

15

TRACEDATA[1]

16

GND

17

TRACEDATA[2]

18

GND

19

TRACEDATA[3]

20

R230

10K

R31

0 Ohm

C95

0.1uF/25V

J12

CON_BOX_2X10_M_TH

VCC

1

VCC

2

TRST

3

GND

4

NC/TDI

5

GND

6

SWDIO/TMS

7

GND

8

SWDCLK/TCLK

9

GND

10

RTCK

11

GND

12

SWO/TDO13GND

14

RESET

15

GND

16

N/C1

17

GND

18

N/C2

19

GND

20

R21

0 OhmDNI

R229

10K

R24

0 OhmDNI

R33

0 Ohm

R236 0 Ohm

DNI

R25

0 Ohm

R235 0 Ohm

R1 0 Ohm

R234 0 Ohm

DNI

R29

0 OhmDNI

R253 0 Ohm

R32

0 Ohm

R256 0 Ohm

R252 0 Ohm

DNI

R2 0 Ohm

DNI

R257 0 Ohm

DNI

R13

0 Ohm

DNI

R26

0 OhmDNI

R247 0 Ohm

R228

0 Ohm

R226

20 ohm

R231 0 Ohm

R221

0 Ohm

R28

0 Ohm

C2

0.1uF/25V

R246 0 Ohm

DNI

R227 0 Ohm

DNI

R12

0 Ohm

DNI

DEBUG INTERFACE - 1

ARM STANDARD JTAG

CORTEX DEBUG + ETM

Schematics of CPU Board

CYTVII-B-H-8M-320-CPU Evaluation Board User Guide, Document Number: 002-26716 Rev. *A 63

Figure A-25. Debug Interface-2

5

4

3

2

1

D D

C C

B B

A A

MICTOR_TRACE_CTL

TRACE_TCK

TRACE_RTCK

MICTOR_TRACE_DBGACK

MICTOR_TRACE_DBGRO

MICTOR_TRACE_CLOCK_R

MICTOR_TRACE_VTREF MICTOR_TRACE_VSUPPLY

MICTOR_TRACE_LOGIC1

TRSTN_LED

CPU_VDDD

SRST_MICTOR

{26}

SWO_TDO{25,26}

SWCLK_TCLK{25,26}

SWDIO_TMS{25,26} SWDOE_TDI

{25,26}

TRSTN{25,26}

SWDIO_TMS {25,26} SWCLK_TCLK {25,26} SWO_TDO {25,26} SWDOE_TDI {25,26} NRST_CORTEX10 {26}

SRST_MICTOR{26}

CPU_XRES {15,22,25,26,28,31,35,39}

TRSTN {25,26}

TRACE_CLOCK {25}

TRACE_DATA_3 {25} TRACE_DATA_2 {25} TRACE_DATA_1 {25}

TRACE_DATA_0 {25}

TRSTN {25,26}

TRSTN{25,26}

NRST_CORTEX10{26}

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DEBUG INTERFACE-2

VJYM SPPD

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DEBUG INTERFACE-2

VJYM SPPD

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Wednesday, Auguﬆ 21, 2019

DEBUG INTERFACE-2

VJYM SPPD

C3

0.1uF/25V

R4 0 OhmDNI

R49

10K

R17 10K

R14

10K

J4

FTSH-105-01-L-DV-K

VCC1SDWIO/TMS

2

GND3SWDCLK/TCLK

4

GND5SWO/TDO

6

KEY

7

NC/TDI

8

GND Detect

9

nRESET

10

R45 0 OhmDNI R37 20 ohm

R40 0 Ohm

TP4

THRU HOLE

R44

10K

DNI

R38

10K

R51

10K

DNI

R53

10K

DNI

R41

10K

DNI

R39 0 OhmDNI

R42

10K

DNI

R46

10K

DNI

R43

10K

DNI

R18 20 ohm

LED4

LTST-C150GKT

21

R52

10K

DNI

R15 0 Ohm

R54

10K

R9 1K

J13

MICTOR38

NC1

1

NC2

2

NC3

3

NC4

4

GND

5

TRCCLK

6

DBGRO7DBGACK

8

nSRST9EXTTRIG

10

TDO

11

VTREF

12

RTCK13VSUPPLY

14

TCK

15

TRCDAT7

16

TMS17TRCDAT6

18

TDI

19

TRCDAT5

20

nTRST21TRCDAT4

22

TRCDAT1523TRCDAT3

24

TRCDAT1425TRCDAT2

26

TRCDAT1327TRCDAT1

28

TRCDAT1229Logic01

30

TRCDAT1131Logic02

32

TRCDAT1033Logic1

34

TRCDAT935TRCCTL

36

TRCDAT837TRCDAT0

38

GND39GND40GND41GND42GND

43

R48

10K

DNI

R3 0 Ohm

R16 0 Ohm

R47

10K

C1

0.1uF/25V

DEBUG INTERFACE - 2

ARM ETM MICTOR

CORTEX DEBUG

Schematics of CPU Board

CYTVII-B-H-8M-320-CPU Evaluation Board User Guide, Document Number: 002-26716 Rev. *A 64

Figure A-26. Automotive Ethernet-1

5

4

3

2

1

D

C

B

A

AUTO_ETH_TXC {28}

AUTO_ETH_REF_CLK_R{17,19}

AUTO_ETH_TXEN {28}

AUTO_ETH_TXD3 {28}

AUTO_ETH_TXD2 {28}

AUTO_ETH_REF_CLK {28}

AUTO_ETH_TXD1 {28}

AUTO_ETH_TXD0 {28}

AUTO_ETH_TXER {28}

AUTO_ETH_MDIO {28}

AUTO_ETH_MDC {28}

AUTO_ETH_RXER {28}

AUTO_ETH_RXDV {28}

AUTO_ETH_RXD3 {28}

AUTO_ETH_RXD2 {28}

AUTO_ETH_RXD1 {28}

AUTO_ETH_RXD0 {28}

AUTO_ETH_RXC {28}

AUTO_ETH_MDIO_R{8,19}

AUTO_ETH_RXD3_R

{18,19}

AUTO_ETH_RXD2_R

{18,19}

AUTO_ETH_RXD1_R{18,19}

AUTO_ETH_RXD0_R

{18,19}

AUTO_ETH_RXC_R

{12,19}

AUTO_ETH_TXD3_R

{17,19}

AUTO_ETH_TXD2_R

{17,19}

AUTO_ETH_TXD1_R

{17,19}

AUTO_ETH_TXD0_R{17}

AUTO_ETH_TXER_R{17,19}

AUTO_ETH_TXC_R{17,19}

AUTO_ETH_TXEN_R

{17,19}

AUTO_ETH_MDC_R

{8,19}

AUTO_ETH_RXER_R

{8,19}

AUTO_ETH_RXDV_R{17,19}

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A4

27 44

Wednesday, Auguﬆ 21, 2019

AUTOMOTIVE ETHERNET-1

VJYM SPPD

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A4

27 44

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AUTOMOTIVE ETHERNET-1

VJYM SPPD

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A4

27 44

Wednesday, Auguﬆ 21, 2019

AUTOMOTIVE ETHERNET-1

VJYM SPPD

R117 0 Ohm

R113 0 Ohm

R109 0 Ohm

R136 0 Ohm

R88 0 Ohm

R93 0 Ohm

R282 0 Ohm

R101 0 Ohm

R105 0 Ohm

R121 0 Ohm

R133 0 Ohm

R84 0 Ohm

R98 0 Ohm

R120 0 Ohm

R128

0 Ohm/2 Pin Jumper

R81 0 Ohm

R79 0 Ohm

AUTOMOTIVE ETHERNET - 1

Schematics of CPU Board

CYTVII-B-H-8M-320-CPU Evaluation Board User Guide, Document Number: 002-26716 Rev. *A 65

Figure A-27. Automotive Ethernet-2

Schematics of CPU Board

5

AUTOMOTIVE ETHERNET - 2

D

AUTO_ETH_TXC{27} AUTO_ETH_TXEN{27} AUTO_ETH_TXD3{27} AUTO_ETH_TXD2{27} AUTO_ETH_TXD1{27}

{27}

AUTO_ETH_TXD0

C

AUTO_ETH_TXER{27}

AUTO_ETH_MDIO{27}

AUTO_ETH_MDC

{27}

AUTO_ETH_RXER{27} AUTO_ETH_RXDV{27}

AUTO_ETH_RXD3{27} AUTO_ETH_RXD2{27} AUTO_ETH_RXD1{27} AUTO_ETH_RXD0{27}

AUTO_ETH_RXC{27}

B B

C55

0.1uF/25V

A

AUTO_PHY_REF_CLK{28}

Y4

1

INH

2

GND

KC3225A50.0000C30E00

5

VCC_3V3VCC_3V3

DNI

R106 0 Ohm

DNI

R110 0 Ohm

DNI

R99 0 Ohm

DNI

R102 0 Ohm

VCC

Output

DNI

R90 0 Ohm

R95 0 Ohm

DNI

R83 0 Ohm

DNI

R85 0 Ohm

4

OSC_50M_OUT

3

R129 0 Ohm

DNI

R123 0 Ohm

DNI

R124 0 Ohm

R138 0 Ohm

DNI

R130 0 Ohm

R135 0 Ohm

VCC_3V3

DNI

FOR RMII MODE

R107

0 Ohm/2 Pin Jumper

DNI

AUTO_ETH_REF_CLK {27}

DNI

R131 0 Ohm

R111 20ohm 1%

DNI

R115

R125 0 Ohm

0 Ohm/2 Pin Jumper

4

ETH_TRX_P_CMC

ETH_TRX_M_CMC

4

VCC_3V3

10K ohm 1%

R75

TJA_INT_N

U4A

2

28

TXC

29 30 31 32 33 34

36 1

17 18 21 22 23 24 25

INT_N

TXEN TXD3

TXD2 TXD1 TXD0 TXER

MDIO MDC

RXER/CONFIG3 RXDV/CONFIG2/CRSDV RXD3/CONFIG1 RXD2/CONFIG0 RXD1/PHYAD1

RXD0/PHYAD0 RXC/REF_CLK

TJA1100

AUTO_PHY_REF_CLK {28}

0.1uF/10V

C33

0.1uF/10V

C35

10K ohm 1%

R77

TJA_EN

35

EN

8

10

INH

WAKE_LED

ETH_TRX_P_RC

3

RST_N

WAKE_LED

R871K ohm 1%

C32

4.7nF/50V

3

VCC_3V3

5

XO

6

XI

TJA_TRX_M

13

TRX_M

TJA_TRX_P

12

TRX_P

AUTO_ETH_TRX_P

AUTO_ETH_TRX_M

R971K ohm 1%

ETH_TRX_M_RC

C41

4.7nF/50V

AUTO_PHY_RST{28}

R71 10K

AUTO_PHY_RST {28}

0 Ohm/2 Pin Jumper

TJA_X0

R73

TJA_X1

R72

0 Ohm/2 Pin Jumper

R94 82 ohm 1%

R89 82 ohm 1%

TP23

DB9 MALE _ CONN

1 6 2 7 3 8 4 9 5

J25

2

TP22

DNI

R69 0 Ohm

TJA_XO_SMA

R63 0 Ohm

TJA_X0_RC

ABM8-25.000MHZ-B2-T

TJA_X1_RC

1 2

10

11

C20

18pF/50V

1 3

ETH_TRX_M_R_CMC

ETH_TRX_P_R_CMC

D5 RCLAMP0582BQ

3

SCH Title :

Page Title :

Size

A4

Date: Sheet

TVII-B-H-8M 320-BGA CPU BOARD

AUTOMOTIVE ETHERNET-2

Document Number Re v

630-60569-01 01

Wednesday, Auguﬆ 21, 2019

2

C19

18pF/50V

Y2

2

4

1

CPU_XRES {15,22,25,26,31,35,39}

5

L3

3

4

ACT45L-201-2P-TL000

Drawn By

VJYM SPPD

CN1 733910060

DNI

234

1

ETH_TRX_M_CMC

2

ETH_TRX_P_CMC

1

CYPRESS SEMICONDUCTOR

CYPRESS SEMICONDUCTOR 198 CHAMPION COURT

198 CHAMPION COURT

198 CHAMPION COURT SAN JOSE, CA 95134

SAN JOSE, CA 95134

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(408) 943-2600

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D

C

A

CYTVII-B-H-8M-320-CPU Evaluation Board User Guide, Document Number: 002-26716 Rev. *A 66

Figure A-28. Automotive Ethernet-3

Schematics of CPU Board

5

4

3

2

1

AUTOMOTIVE ETHERNET - 3

D

VCC_3V3

L5

MPZ2012S101ATD25

C

L2

MPZ2012S101ATD25

L1

B B

MPZ2012S101ATD25

TJA_VDDIO

0.1uF/25V

TJA_VDDA

0.1uF/25V

TJA_VDDA_3V3

C120

C42

0.47uF/25V

C119

0.1uF/25V

C31

0.1uF/25V

C21

U4B

19

VDD(IO)

27

VDD(IO)4

11

VDDA(TX)1

14

VDDA(TX)

VDDA(3V3)7VDDD(1V8)

TJA1100

C103

0.1uF/25V

VBat

GND GND2 GND3

TPAD

VDDA(1V8)

0.01uF/25V

C44

9

15 20 26 37

4 16

TJA_VDDD_1V8

0.47uF/25V

C46

C28

0.1uF/25V

TJA_VDDA_1V8

C27

0.47uF/25V

12

C26

1000pF/25V

D

C

CYPRESS SEMICONDUCTOR

CYPRESS SEMICONDUCTOR 198 CHAMPION COURT

198 CHAMPION COURT

198 CHAMPION COURT SAN JOSE, CA 95134

SAN JOSE, CA 95134

SAN JOSE, CA 95134 (408) 943-2600

(408) 943-2600

A A

SCH Title :

Page Title :

Size

A4

Date: Sheet

5

4

3

Date: Sheet

TVII-B-H-8M 320-BGA CPU BOARD

AUTOMOTIVE ETHERNET-3

Document Number Re v

630-60569-01 01

Wednesday, Auguﬆ 21, 2019

2

Drawn By

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Approved By

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CYTVII-B-H-8M-320-CPU Evaluation Board User Guide, Document Number: 002-26716 Rev. *A 67

Figure A-29. Gigabit Ethernet-1

5

4

3

2

1

D

C

B

A A

GIG_ETH_TX_D5 {31}

GIG_ETH_TX_D4 {31}

GIG_ETH_TX_D3 {31}

GIG_ETH_TX_D2 {31}

GIG_ETH_TX_D1 {31}

GIG_ETH_TX_D0 {31}

GIG_ETH_TX_ER {31}

GIG_ETH_RX_CLK {31}

GIG_ETH_RX_D0 {31}

GIG_ETH_RX_D1 {31}

GIG_ETH_RX_D2 {31}

GIG_ETH_RX_D3 {31}

GIG_ETH_RX_D4 {31}

GIG_ETH_RX_D5 {31}

GIG_ETH_RX_D6 {31}

GIG_ETH_RX_D7 {31}

GIG_ETH_TX_EN_CTRL {31}

GIG_ETH_RX_DV_CTRL {31}

GIG_ETH_RX_ER {31}

GIG_ETH_REF_CLK {31}GIG_ETH_REF_CLK_R{12}

GIG_ETH_MDC {31}

GIG_ETH_MDIO {31}

GIG_ETH_TX_CLK {31}

GIG_ETH_TX_D7 {31}

GIG_ETH_TX_D6 {31}

GIG_ETH_TX_D7_R

{13,19}

GIG_ETH_TX_D6_R{13,19}

GIG_ETH_TX_D5_R{13,19}

GIG_ETH_TX_D4_R{17}

GIG_ETH_TX_D3_R{12,19}

GIG_ETH_TX_D2_R

{12,19}

GIG_ETH_TX_D1_R{12,19}

GIG_ETH_TX_D0_R{12,19}

GIG_ETH_TX_ER_R{13,19}

GIG_ETH_RX_CLK_R{12,19}

GIG_ETH_RX_D0_R

{12,19}

GIG_ETH_RX_D1_R

{12,19}

GIG_ETH_RX_D2_R{12,19}

GIG_ETH_RX_D3_R{12,19}

GIG_ETH_RX_D4_R{13,19}

GIG_ETH_RX_D5_R

{13,19}

GIG_ETH_RX_D6_R

{13,19}

GIG_ETH_RX_D7_R{13,19}

GIG_ETH_TX_EN_CTRL_R

{12,19}

GIG_ETH_RX_DV_CTRL_R

{12,19}

GIG_ETH_RX_ER_R

{13,19}

GIG_ETH_MDC_R{12,19}

GIG_ETH_MDIO_R

{12,19}

GIG_ETH_TX_CLK_R

{12,19}

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GIGABIT ETHERNET-1

VJYM SPPD

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TVII-B-H-8M 320-BGA CPU BOARD

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Wednesday, Auguﬆ 21, 2019

GIGABIT ETHERNET-1

VJYM SPPD

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A4

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Wednesday, Auguﬆ 21, 2019

GIGABIT ETHERNET-1

VJYM SPPD

R100 0 Ohm

R134 0 Ohm

R141 0 Ohm

R118 0 Ohm

R114 0 Ohm

R112 0 Ohm

R70 0 Ohm

R86 0 Ohm

R74 0 Ohm

R139 0 Ohm

R67 0 Ohm

R96 0 Ohm

R78 0 Ohm

R82 0 Ohm

R137 0 Ohm

R76 0 Ohm

R103 0 Ohm

R132 0 Ohm

R140 0 Ohm

R91 0 Ohm

R143 0 Ohm

R68 0 Ohm

R126 0 Ohm

R80 0 Ohm

R108 0 Ohm

GIGABIT ETHERNET - 1

Schematics of CPU Board

CYTVII-B-H-8M-320-CPU Evaluation Board User Guide, Document Number: 002-26716 Rev. *A 68

Figure A-30. Gigabit Ethernet-2

5

4

3

2

1

D

C

B B

A

FOR GMII & RGMII MODE

GB_TRSETN

GB_JTAG_CLK

GB_TDO

GB_TMS

GB_TDI

GIG_ETH_COL

GIG_ETH_CS

GB_RBIAS

GB_INT_C

GB_XO

GB_XI

GB_XO_R GB_XO

GB_XI

GIG_PHY_TX_CLK

VCC_3V3

GIG_ETH_TD_P_A

{33}

GIG_ETH_TD_M_A{33}

GIG_ETH_TD_P_B

{33}

GIG_ETH_TD_M_B

{33}

GIG_ETH_TD_P_C{33}

GIG_ETH_TD_M_C

{33}

GIG_ETH_TD_P_D

{33}

GIG_ETH_TD_M_D

{33}

GIG_ETH_MDC

{30,31}

GIG_ETH_MDIO{30,31}

GIG_ETH_TX_CLK{30,31}

GIG_ETH_TX_D7{30}

GIG_ETH_TX_D6{30}

GIG_ETH_TX_D5 {30}

GIG_ETH_TX_D4 {30}

GIG_ETH_TX_D3 {30}

GIG_ETH_TX_D2 {30}

GIG_ETH_TX_D1 {30}

GIG_ETH_TX_D0 {30}

GIG_ETH_TX_ER {30}

GIG_PHY_GTX_CLK {31}

GIG_ETH_RX_CLK {30}

GIG_ETH_RX_D0 {30}

GIG_ETH_RX_D1 {30}

GIG_ETH_RX_D2 {30}

GIG_ETH_RX_D3 {30}

GIG_ETH_RX_D4 {30}

GIG_ETH_RX_D5 {30}

GIG_ETH_RX_D6 {30}

GIG_ETH_RX_D7 {30}

GIG_ETH_TX_EN_CTRL {30}

GIG_ETH_RX_DV_CTRL {30}

GIG_ETH_RX_ER {30}

GIG_PHY_RESET {31}

GB_LD2 {33}

GB_LD1 {33}

GB_LD0 {33}

GIG_PHY_RESET{31} CPU_XRES {15,22,25,26,28,35,39}

GIG_ETH_TX_CLK

{30,31}

GIG_ETH_REF_CLK {30,31}

GIG_ETH_TX_CLK{30,31} GIG_PHY_GTX_CLK {31}

CLK_SOURCE_125M

{33}

GIG_ETH_REF_CLK {30,31}

GIG_PHY_CLK_OUT{33}

GIG_ETH_MDC {30,31}

GIG_ETH_MDIO {30,31}

SCH Title :

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A4

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Wednesday, Auguﬆ 21, 2019

GIGABIT ETHERNET-2

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TVII-B-H-8M 320-BGA CPU BOARD

A4

31 44

Wednesday, Auguﬆ 21, 2019

GIGABIT ETHERNET-2

VJYM SPPD

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TVII-B-H-8M 320-BGA CPU BOARD

A4

31 44

Wednesday, Auguﬆ 21, 2019

GIGABIT ETHERNET-2

VJYM SPPD

R116 0 Ohm

TP27

U5A

DP83867IR

RESERVED_1

1

TD_P_A

2

TD_M_A

3

TD_P_B

5

TD_M_B

6

RESERVED_2

7

RESERVED_3

9

TD_P_C

10

TD_M_C

11

TD_P_D

13

TD_M_D

14

RBIAS

15

RESERVED_4

16

X_O

18

X_I

19

MDC

20

MDIO

21

CLK_OUT

22

JTAG_TRSTN

24

JTAG_CLK

25

JTAG_TDO

26

JTAG_TMS

27

JTAG_TDI

28

TX_D6

32

TX_CLK

30

TX_D7

31

TX_D5

33

TX_D4

34

TX_D3

35

TX_D2

36

TX_D1

37

TX_D0

38

TX_ER

39

GTX_CLK

40

RX_CLK

43

RX_D0

44

RX_D1

45

RX_D2

46

RX_D3

47

RX_D4/GPIO

48

RX_D5/GPIO

49

RX_D6/GPIO

50

RXD_7/GPIO

51

TX_EN/TX_CTRL

52

RX_DV/RX_CTRL

53

RX_ER/GPIO

54

COL/GPIO

55

CS/GPIO

56

RESET_N

59

INT/PWDN

60

LED_2

61

LED_1

62

LED_0

63

TP26

TP28

R284 10K

R122 11K

TP33

C48

27pF/50V

R127 0 Ohm/2 Pin Jumper

TP29

TP30

R285

0 Ohm

DNI

R286 10K

R149 0 Ohm/2 Pin Jumper

C47

27pF/50V

R92 10K

R316 0 Ohm/2 Pin Jumper

R144 2 Pin Jumper

DNI

R104 10K

TP24

Y3

ABM8-25.000MHZ-B2-T

13

2 4

TP25

TP31

GIGABIT ETHERNET - 2

Schematics of CPU Board

CYTVII-B-H-8M-320-CPU Evaluation Board User Guide, Document Number: 002-26716 Rev. *A 69

Figure A-31. Gigabit Ethernet-3

5

4

3

2

1

D

C

B

A A

PLACE DECAPS NEAR TO IC PIN

GB_VDDA1P8

GB_VDDA1P8_1

VCC_2V5

VCC_1V1_LDO

VCC_3V3

VCC_1V1_LDO

VCC_2V5

VCC_3V3

SCH Title :

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GIGABIT ETHERNET-3

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TVII-B-H-8M 320-BGA CPU BOARD

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Wednesday, Auguﬆ 21, 2019

GIGABIT ETHERNET-3

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Wednesday, Auguﬆ 21, 2019

GIGABIT ETHERNET-3

VJYM SPPD

C59

10uF/16V

C40

1uF/16V

C49

0.1uF/25V

C25

1uF/16V

C39

0.1uF/25V

C45

1uF/16V

C23

0.1uF/25V

C43

0.1uF/25V

C24

1uF/16V

C37

10uF/16V

C51

1uF/16V

C36

10nF/16V

C22

0.1uF/25V

C54

1uF/16V

C52

0.1uF/25V

C34

1uF/16V

C29

1uF/16V

C58

10uF/16V

TP32

U5B

DP83867IR

VDDA2P5

4

VDD1P1

8

VDDA2P5

12

VDDA1P8

17

VDDIO

23

VDD1P1

29

VDDIO

41

VDD1P1

42

VDDIO

57

VDD1P1

58

VDDA1P8

64

GND

65

C50

0.1uF/25V

C30

0.1uF/25V

C53

1uF/16V

TP34

C57

10nF/16V

C38

0.1uF/25V

C56

10nF/16V

GIGABIT ETHERNET - 3

DECAPS FOR GIGABIT ETHERNET

Schematics of CPU Board

CYTVII-B-H-8M-320-CPU Evaluation Board User Guide, Document Number: 002-26716 Rev. *A 70

Figure A-32. Gigabit Ethernet-4

5

4

3

2

1

D

C

B

A A

DEFAULT OPEN

GB_LD2_R

TRCT4_C

TRCT1_C

TRCT2_C

TRCT3_C

GB_LD0_R

CLK_SOURCE_125M_SMA

CLK_SOURCE_125M_OSCVCC_3V3_OSC

VCC_3V3

GB_LD2{31}

GB_LD1 {31} GB_LD0 {31}

GIG_ETH_TD_P_A

{31}

GIG_ETH_TD_M_A

{31}

GIG_ETH_TD_P_B

{31}

GIG_ETH_TD_M_B

{31}

GIG_ETH_TD_P_C {31}

GIG_ETH_TD_M_C {31}

GIG_ETH_TD_P_D {31}

GIG_ETH_TD_M_D {31}

CLK_SOURCE_125M{31}

GIG_PHY_CLK_OUT {31}

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TVII-B-H-8M 320-BGA CPU BOARD

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Wednesday, Auguﬆ 21, 2019

GIGABIT ETHERNET-4

VJYM SPPD

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630-60569-01 01

TVII-B-H-8M 320-BGA CPU BOARD

A4

33 44

Wednesday, Auguﬆ 21, 2019

GIGABIT ETHERNET-4

VJYM SPPD

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A4

33 44

Wednesday, Auguﬆ 21, 2019

GIGABIT ETHERNET-4

VJYM SPPD

R151

0 Ohm

DNI

C69

0.01uF/25V

C136

0.1uF/25V

R287 470 ohm

J29

3 Pin Jumper

1

2

3

J26

CON_MCXJACK5_F

2

1

3 4 5

R283 470 ohm

R150

0 Ohm

DNI

C135

0.1uF/25V

C100

0.1uF/25V

J24

GIGABIT_RJ45

TRD1+

11

TRCT1

12

TRD1-

10

TRD2+

4

TRCT2

6

TRD2-

5

TRD3+

3

TRCT3

1

TRD3-

2

TRD4+

8

TRCT4

7

TRD4-

9

LED2_1

13

LED2-2

14

LED1_1

15

LED1_2

16

SHIELD17SHIELD

18

R147 0 Ohm

C99

0.1uF/25V

Y5

ECS-3953M-1250-BN-TR

TRI-STATE

1

GND

2

O/P

3

VDD

4

FB3

BLM18PG471SN1

GIGABIT ETHERNET - 4

CLOCK OPTIONS FOR 125MHz

RJ45

Schematics of CPU Board

CYTVII-B-H-8M-320-CPU Evaluation Board User Guide, Document Number: 002-26716 Rev. *A 71

Figure A-33. Audio Interface-1

5

4

3

2

1

D D

C C

B B

A A

VCC_3V3

AUDIO_0_I2S_RX_SDI

{10}

AUDIO_0_I2S_RX_SCK{16}

AUDIO_0_I2S_RX_WS{16}

AUDIO_0_CLK_I2S_IF{16}

AUDIO_0_I2S_MCLK{9}

AUDIO_0_I2S_TX_SCK{9}

AUDIO_0_I2S_TX_WS{9}

AUDIO_0_I2S_TX_SDO{16}

AUDIO_1_I2S_MCLK

{18,19}

AUDIO_I2S_MCLK {34}

AUDIO_I2S_TX_SCK {35}

AUDIO_I2S_TX_WS {35}

AUDIO_I2S_TX_SDO {35}

AUDIO_CLK_I2S_IF {34}

AUDIO_I2S_RX_SCK {35}

AUDIO_I2S_RX_WS {35}

AUDIO_I2S_RX_SDI {35}

AUDIO_1_I2S_TX_SCK

{18}

AUDIO_1_I2S_TX_WS{18}

AUDIO_1_I2S_TX_SDO{18,19}

AUDIO_1_CLK_I2S_IF

{18}

AUDIO_1_I2S_RX_SCK{18}

AUDIO_1_I2S_RX_WS{18}

AUDIO_1_I2S_RX_SDI

{10}

CLK_24_576M {34}

AUDIO_PHY_MCLK{35}

CLK_24_576M {34}

CLK_12M {34}

AUDIO_CLK_I2S_IF {34}

AUDIO_I2S_MCLK {34}

CLK_12M {34}

SCH Title :

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A4

34 44

Wednesday, Auguﬆ 21, 2019

AUDIO INTERFACE-1

VJYM SPPD

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A4

34 44

Wednesday, Auguﬆ 21, 2019

AUDIO INTERFACE-1

VJYM SPPD

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TVII-B-H-8M 320-BGA CPU BOARD

A4

34 44

Wednesday, Auguﬆ 21, 2019

AUDIO INTERFACE-1

VJYM SPPD

R2610 Ohm

DNI

R2980 Ohm

R2990 Ohm

DNI

C93

0.1uF/25V

R203 0 OhmDNI

R274

0 Ohm

Y7

ASE-24.576MHZ-LC-T

INH

1

Output

3

GND

2

VCC

4

R2960 Ohm

DNI

R2050 Ohm

DNI

R2600 Ohm

R2910 Ohm

DNI

C85

0.1uF/25V

R2070 Ohm

R2020 Ohm

Y6

ASE-12.000MHZ-LC-T

INH

1

Output

3

GND

2

VCC

4

R2080 Ohm

DNI

R2090 Ohm

DNI

R2730 Ohm

R238

0 Ohm

R2690 Ohm

R2630 Ohm

R2760 Ohm

DNI

R2390 Ohm

DNI

R2620 Ohm

DNI

AUDIO INTERFACE - 1

Schematics of CPU Board

CYTVII-B-H-8M-320-CPU Evaluation Board User Guide, Document Number: 002-26716 Rev. *A 72

Figure A-34. Audio Interface-2

Schematics of CPU Board

5

4

3

2

1

AUDIO_INTERFACE

D D

VCC_3V3 VCC_1V8_AU

VCC_3V3

R213 DNI

C

MIC_INPUT{35}

B

TP66

0 Ohm

R211 2.2K

AUDIO_SPI0_SS1{8,19}

C92

0.1uF/25V

R308 10K

MIC_BIAS AUDIO_MIC_IN

TP67 TP64 TP68 TP65

C81

C83

10uF/16V

0.1uF/25V

AUDIO_PHY_MCLK{34}

BB_SPI0_CLK{8,20,42}

BB_SPI0_MISO{8,19,41}

BB_SPI0_MOSI{8,19,41}

AUDIO_SPI_DAVN

AUDIO_AUX AUDIO_VBAT2 AUDIO_VBAT1 AUDIO_VREF

C143

0.1uF/25V

C90

10uF/16V

U11

1

DVSS

2

IOVDD

3

MCLK SCLK MISO MOSI SS DAV MICBIAS MICIN AUX VBAT2 VBAT1 VREF AVSS NC

PWD/ADWS

AIC26

DRVDD

RESET

DRVSS

33

4 5 6 7 8

9 10 11 12 13 14 15 16

DVDD AVDD

HPL

HPR

LRCK

DOUT

BCLK

VGND

NC3 NC2 NC1

GND

VCC_3V3

AUDIO_DVDD

C79

0.1uF/25V

R198 10K

32 20 24 21 25 26 27 28 29

DIN

30 31 23 22 19 18 17

R315 10K

R297 0 Ohm

AUDIO_I2S_ADWS

R290 0 Ohm

AUDIO_RESET{35}

AUDIO_HPL {35} AUDIO_HPR {35} AUDIO_RESET {35} AUDIO_I2S_TX_WS {34}

AUDIO_I2S_TX_SDO {34} AUDIO_I2S_RX_SDI {34} AUDIO_I2S_RX_SCK {34}

AUDIO_SPK_VGND {35}

FB2

C78

BLM18PG471SN1

10uF/16V

AUDIO_AVDD

AUDIO_I2S_RX_WS {34}

TP48

AUDIO_I2S_TX_SCK {34}

TP47

R304

C82

0.1uF/25V

DNI

BLM18PG471SN1

C80

10uF/16V

0 Ohm

VCC_3V3

FB1

R197 0 Ohm

C89

C87

10uF/16V

0.1uF/25V

CPU_XRES {15,22,25,26,28,31,39}

VCC_1V8_AUVCC_1V8

C

B

CYPRESS SEMICONDUCTOR

AUDIO JACK

J34

A A

SJ-43514-SMT-TR

5

1 4 3 6 5 2

HP_GND

AUDIO_HPR_C

47uF/6.3V

AUDIO_HPL_C

47uF/6.3V

MIC_INPUT {35}

C91

AUDIO_HPR {35}

C84

AUDIO_HPL {35}

4

FOR HEADPHONE USE 0E

DNI

R216 0 Ohm

R217

0 Ohm

3

AUDIO_SPK_VGND {35}

SCH Title :

Page Title :

Size

A4

Date: Sheet

TVII-B-H-8M 320-BGA CPU BOARD

AUDIO INTERFACE-2

Document Number Re v

630-60569-01 01

Wednesday, Auguﬆ 21, 2019

2

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198 CHAMPION COURT

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SAN JOSE, CA 95134

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CYTVII-B-H-8M-320-CPU Evaluation Board User Guide, Document Number: 002-26716 Rev. *A 73

Figure A-35. eMMC Interface

5

4

3

2

1

D

C C

B

A

VCC_3V3

EMMC_DATA3{9,19}

EMMC_CMD

{16,19}

EMMC_CLK

{16,19}

EMMC_DATA0{9,19} EMMC_DATA1

{9,19}

EMMC_DATA2

{9,19}

EMMC_CD{9,19} EMMC_WP{9,19}

SCH Title :

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A4

36 44

Wednesday, Auguﬆ 21, 2019

eMMC INTERFACE

VJYM SPPD

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A4

36 44

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eMMC INTERFACE

VJYM SPPD

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TVII-B-H-8M 320-BGA CPU BOARD

A4

36 44

Wednesday, Auguﬆ 21, 2019

eMMC INTERFACE

VJYM SPPD

R182 10K

U10

101-00708-64/GSD090012SEU

DATA3

1

CMD

2

GND

3

VDD

4

CLK

5

GND

6

DATA0

7

DATA1

8

DATA2

9

CD

10

WP

11

GND

12

GND

13

GND

14

GND

15

GND

16

GND

17

R181 10K

R180 10K

R177 10K

R179 10K

R183 10K

R168 10K

R178 10K

eMMC_INTERFACE

Schematics of CPU Board

CYTVII-B-H-8M-320-CPU Evaluation Board User Guide, Document Number: 002-26716 Rev. *A 74

Figure A-36. SMIF HS Connector

5

4

3

2

1

D D

C

B B

A

RESET_1 RESET_2 RESET_3 RESET_4

RFU_3

RFU_1

RFU_4 RFU_5

RFU_2

RFU_8

RFU_6

RFU_9 RFU_10

RFU_7

SMIF_CS3

SMIF_CK#

SMIF_CS2

VCC_1V8

VCC_3V3

VCC_1V8

VCC_3V3

VCC_5V

CPU_VDDIO3

VCC_5V

CPU_VDDIO3

SMIF_5V_1

SMIF_VDDIO_5

SMIF_1V8_47

SMIF_3V3_51

SMIF_1V8_48

SMIF_3V3_52

SMIF_5V_2

SMIF_VDDIO_6

GM_CS#1 {38,39}

GM_CS#0 {38,39}

GM_CK {38,39}

GM_DQ0 {38,39}

GM_DQ1 {38,39}

GM_DQ2 {38,39}

GM_DQ3 {38,39}

GM_DQ4 {38,39}

GM_DQ5 {38,39}

GM_DQ6 {38,39}

GM_DQ7 {38,39}

GM_CS#0_R{12,19,37}

GM_CK_R

{12,19,37}

GM_DQ0_R

{12,19,37}

GM_DQ1_R

{12,19,37}

GM_DQ2_R

{12,19,37}

GM_DQ3_R{12,19,37}

GM_DQ4_R

{12,19,37}

GM_DQ5_R

{12,19,37}

GM_DQ6_R

{12,19,37}

GM_DQ7_R

{12,19,37}

GM_DQ6_R{12,19,37}

GM_DQ4_R{12,19,37}

GM_DQ2_R

{12,19,37}

GM_DQ0_R

{12,19,37}

GM_CS#0_R{12,19,37}

GM_DQ5_R {12,19,37} GM_DQ7_R {12,19,37}

GM_DQ3_R {12,19,37}

GM_DQ1_R {12,19,37}

GM_RWDS_R{12,19,37}

GM_CK_R

{12,19,37}

GM_CS#1_R {12,19,37}

GM_CS#1_R

{12,19,37}

GM_RWDS_R

{12,19,37}

GM_RWDS {39}

SCH Title :

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01

TVII-B-H-8M 320-BGA CPU BOARD

A4

37 44

Wednesday, Auguﬆ 21, 2019

SMIF HS CONNECTOR

VJYM SPPD

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TVII-B-H-8M 320-BGA CPU BOARD

A4

37 44

Wednesday, Auguﬆ 21, 2019

SMIF HS CONNECTOR

VJYM SPPD

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01

TVII-B-H-8M 320-BGA CPU BOARD

A4

37 44

Wednesday, Auguﬆ 21, 2019

SMIF HS CONNECTOR

VJYM SPPD

TP53

TP43

R314 0 Ohm

R187 0 Ohm

TP52

C88

0.1uF/16V

DNI

R210 0 Ohm

TP62

R312 0 Ohm

R307 0 Ohm

R186

0 Ohm

TP42

R212 0 Ohm

TP60

R313 0 Ohm

TP57

C86

0.1uF/16V

DNI

R302 0 Ohm

R185 0 Ohm

R305 0 Ohm

J33

PCI_EXP_MINI_52POS_FEMALE

5V

1

GND

3

VDDIO

5

GND

7

D0

9

D2

11

GND

13

D4

15

D6

17

GND

19

CS0

21

CS2

23

GND

25

CK

27

CK#

29

GND

31

RWDS

33

RFU_1

35

RFU_2

37

RFU_3

39

RFU_4

41

RFU_5

43

GND

45

1.8V

47

GND

49

3.3V

51

GND

53

5V

2

GND

4

VDDIO

6

GND

8

D1

10

D3

12

GND

14

D5

16

D7

18

GND

20

CS1

22

CS3

24

GND

26

RESET_1

28

RESET_2

30

RESET_3

32

RESET_4

34

RFU_6

36

RFU_7

38

RFU_8

40

RFU_9

42

RFU_10

44

GND

46

1.8V

48

GND

50

3.3V

52

GND

54

R214 0 Ohm

TP58

TP41

R200 0 Ohm

R303 0 Ohm

TP40

R215 0 Ohm

R184 0 Ohm

TP44

R199 0 Ohm

TP39

TP59

R188 0 Ohm

TP51

R301 0 Ohm

TP45

TP46

R206 0 Ohm

TP61

SMIF HS CONNECTOR

Schematics of CPU Board

CYTVII-B-H-8M-320-CPU Evaluation Board User Guide, Document Number: 002-26716 Rev. *A 75

Figure A-37. Dual Quad-SPI

Schematics of CPU Board

5

4

3

2

1

DUAL QUAD- SPI

D

GM_DQ3

GM_DQ1{37,39}

VCC_3V3

C144

0.1uF/25V

U13

1

HOLD#/IO3

2

VCC

3

RESET#/RFU

4

DNU1

5

DNU2

6

RFU

7

CS#

8

SO/IO1

S25FL256SAGMFM000

C145

0.1uF/25V

U12

1

HOLD#/IO3

2

VCC

3

RESET#/RFU

4

DNU1

5

DNU2

6

RFU

7

CS#

8

SO/IO1

S25FL256SAGMFM000

SCK

SI/IO0

VIO/RFU

DNU3 DNU4

VSS

WP#/IO2

SCK

SI/IO0

VIO/RFU

DNU3 DNU4

VSS

WP#/IO2

VCC_3V3

16 15 14 13

NC

12 11 10 9

16 15 14 13

NC

12 11 10 9

GM_CK {37,39} GM_DQ0 {37,39}

GPIO_P16_0_R

GM_DQ2 {37,39}

GM_DQ4 {37,39}

GPIO_P14_6_R

GM_DQ6 {37,39}

R376 10K R377 0 Ohm

TP69

VCC_3V3

R379 10K R378 0 Ohm

TP70

GPIO_P16_0 {10,19}

GPIO_P14_6 {10,19}

VCC_3V3

DNI

R196 10K

R309 10K

{37,39}

MEM_RSTX{39}

{37,39}

QSPI_CS0

GM_DQ7{37,39}

QSPI_CS1

GM_DQ5

C

B B

GM_CS#0{37,39}

GM_CS#1{37,39}

R191

0 Ohm/2 Pin Jumper

VCC_3V3

R194 10K

R190

0 Ohm/2 Pin Jumper

D

C

CYPRESS SEMICONDUCTOR

CYPRESS SEMICONDUCTOR 198 CHAMPION COURT

198 CHAMPION COURT

198 CHAMPION COURT SAN JOSE, CA 95134

SAN JOSE, CA 95134

SAN JOSE, CA 95134 (408) 943-2600

(408) 943-2600

A A

SCH Title :

Page Title :

Size

A4

Date: Sheet

5

4

3

Date: Sheet

TVII-B-H-8M 320-BGA CPU BOARD

DUAL QUAD-SPI

Document Number

630-60569-01 01

Wednesday, Auguﬆ 21, 2019

2

Drawn By

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CYTVII-B-H-8M-320-CPU Evaluation Board User Guide, Document Number: 002-26716 Rev. *A 76

Figure A-38. H-Flash & H-SRAM

5

4

3

2

1

D D

C C

B B

A

HFLASH_CS0

HFLASH_RFU2

HFLASH_RSTO

HFLASH_INT

HFLASH_PSC

GM_CS#1_2

VCC_3V3

MEM_RSTX{38}

GM_RWDS

{37}

GM_DQ0 {37,38} GM_DQ1 {37,38} GM_DQ2 {37,38} GM_DQ3 {37,38} GM_DQ4 {37,38} GM_DQ5 {37,38} GM_DQ6 {37,38} GM_DQ7 {37,38}

GM_CK {37,38}

GM_CS#0 {37,38}

GM_CS#1 {37,38}

CPU_XRES{15,22,25,26,28,31,35}

GPIO_P16_1

,

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H-FLASH & H-SRAM

VJYM SPPD

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TVII-B-H-8M 320-BGA CPU BOARD

A4

39 44

Wednesday, Auguﬆ 21, 2019

H-FLASH & H-SRAM

VJYM SPPD

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TVII-B-H-8M 320-BGA CPU BOARD

A4

39 44

Wednesday, Auguﬆ 21, 2019

H-FLASH & H-SRAM

VJYM SPPD

C141

0.1uF/25V

R311 0 Ohm

DNI

R189

0 Ohm/2 Pin Jumper

TP54

C139

0.1uF/25V

R193

0 Ohm/2 Pin Jumper

C146

0.1uF/25V

C142

0.1uF/25V

TP63

TP55

R310 10K

U14

S27KL0641

RFU1

A2

CS#

A3

RESET#

A4

RFU2

A5

CK#

B1

CK

B2

Vss

B3

Vcc

B4

RFU3

B5

VssQ

C1

RFU4

C2

RWDS

C3

DQ2

C4

RFU5

C5

VccQ

D1

DQ1

D2

DQ0

D3

DQ3

D4

DQ4

D5

DQ7

E1

DQ6

E2

DQ5

E3

VccQ

E4

VssQ

E5

C140

0.1uF/25V

R374 10K

R201 10K

DNI

R195 10K

R306 10K

DNI

TP50

C147

0.1uF/25V

TP49

R192 10K

U15

S26KL512S

RSTO#

A2

CS2#

A3

RESET#

A4

INT#

A5

CK#

B1

CK

B2

VSS

B3

VCC

B4

RFU1

B5

VSSQ

C1

CS1#

C2

RWDS

C3

DQ2

C4

RFU2

C5

VCCQ

D1

DQ1

D2

DQ0

D3

DQ3

D4

DQ4

D5

DQ7

E1

DQ6

E2

DQ5

E3

VCCQ

E4

VSSQ

E5

R375 0 Ohm

H-FLASH

H-SRAM

Schematics of CPU Board

19}

CYTVII-B-H-8M-320-CPU Evaluation Board User Guide, Document Number: 002-26716 Rev. *A 77

Figure A-39. Base Board Connector - J35A

5

4

3

2

1

D D

C C

B B

A

This connects to J38 on the TVII Base board

BB_FRB_EN

BB_FRA_EN

BB_P_5V

BB_P_5V BB_P_12V

VCC_5V

BB_P_12V

VCC_12V

BB_CAN1_RXD{10,20}

BB_USER_LED8 {8,20}

BB_CAN1_TXD{10,20}

BB_CAN0_RXD{13,20}

BB_CAN0_TXD

{13,20}

BB_LIN1_TXD{16,20}

BB_LIN1_RXD

{16,20}

BB_LIN0_RXD

{8,20}

BB_LIN0_TXD{11,20}

BB_LIN0_WAKE

{8,20}

BB_LIN0_SLP

{11,20}

BB_LIN5_RXD

{11,20}

BB_LIN5_TXD{11,20}

BB_LIN5_WAKE{8,20}

BB_LIN5_SLP{11,20}

BB_LIN2_RXD

{18,20}

BB_LIN2_TXD

{18,20}

BB_LIN2_WAKE{8,20}

BB_LIN1_WAKE {8,20} BB_LIN1_SLP {16,20}

BB_SPI0_WP {12,20}

BB_SPI0_HOLD {12,20} BB_CAN_SPI1_MISO {17}

BB_CAN_SPI1_MOSI {17} BB_CAN_SPI1_SCK {17}

BB_GPIO_56_RESET {13,20}

BB_CAN1_S{13,20}

BB_FRA_RXD{9,20}

BB_FRA_TXD{9,20}

BB_FRA_TXEN{9,20}

BB_FRA_STBN{12,20}

BB_FRA_ERRN{13,20} BB_FRA_WAKE{9,20}

BB_FRB_RXD

{9,20}

BB_FRB_TXD{9,20}

BB_FRB_TXEN{9,20}

BB_FRB_STBN{13,20}

BB_FRB_ERRN

{9,20}

BB_FRB_WAKE

{13,20}

BB_CXPI_RXD{13,20}

BB_CXPI_TXD{8,20}

BB_CXPI_SELMS{13,20}

BB_CXPI_NSLP{13,20}

BB_CAN0_S {8,20}

BB_USER_LED9 {8,20}

SCH Title :

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TVII-B-H-8M 320-BGA CPU BOARD

A4

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BASE BOARD INTERFACE-J35A

VJYM SPPD

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630-60569-01

01

TVII-B-H-8M 320-BGA CPU BOARD

A4

40 44

Wednesday, Auguﬆ 21, 2019

BASE BOARD INTERFACE-J35A

VJYM SPPD

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TVII-B-H-8M 320-BGA CPU BOARD

A4

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Wednesday, Auguﬆ 21, 2019

BASE BOARD INTERFACE-J35A

VJYM SPPD

J35A

CON_PMC_90X2_F

1

3

5

7

9

11

13

15

17

19

21

23

25

27

29

31

33

35

37

39

41

43

45

47

49

51

53

55

57

59

61

63

65

67

69

71

73

75

77

79

81

83

85

87

89

2

4

6

8

10

12

14

16

18

20

22

24

26

28

30

32

34

36

38

40

42

44

46

48

50

52

54

56

58

60

62

64

66

68

70

72

74

76

78

80

82

84

86

88

90

181

182

183

184

185

186

R233

0 Ohm

TP16

DNI

TP17

DNI

R251 0 Ohm

BOARD TO BOARD CONNECTOR - J35A

Schematics of CPU Board

CYTVII-B-H-8M-320-CPU Evaluation Board User Guide, Document Number: 002-26716 Rev. *A 78

Figure A-40. Base Board Connector - J35B

5

4

3

2

1

D

C

B B

A A

This connects to J38 on the TVII Base board

BB_LIN2_SLP{18,20} BB_LIN3_RXD{11,20} BB_LIN3_TXD{11,20}

BB_LIN3_WAKE

{8,20}

BB_LIN3_SLP{11,20} BB_LIN4_RXD{13,20} BB_LIN4_TXD

{9,20}

BB_LIN4_WAKE

{8,20}

BB_LIN4_SLP{9,20}

BB_SPI0_MISO{8,19,35}

BB_USER_LED1

{13,20}

BB_USER_LED2{13,20} BB_USER_LED3{13,20} BB_USER_LED4{13,20} BB_USER_LED5

{13,20}

BB_USER_LED6

{13,20}

BB_USER_LED7{8,20}

BB_USER_BUTTON_1

{9,20}

BB_USER_BUTTON_2{13,20} BB_USER_BUTTON_3{13,20}

BB_SPI0_MOSI{8,19,35}

BB_USER_BUTTON_5

{12,20}

BB_UART0_RTS {18,20} BB_UART0_CTS {18,20}

BB_CAN3_TXD {11,20} BB_CAN3_RXD {11,20}

BB_I2C1_SDA{10,20} BB_I2C1_SCL{10,20} BB_CXPI_CLK

{8,20}

BB_ADC_POT{10,20}

UART_RX {18,24}

UART_TX {18,24}

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TVII-B-H-8M 320-BGA CPU BOARD

A4

41 44

Wednesday, Auguﬆ 21, 2019

BASE BOARD INTERFACE-J35B

VJYM SPPD

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630-60569-01 01

TVII-B-H-8M 320-BGA CPU BOARD

A4

41 44

Wednesday, Auguﬆ 21, 2019

BASE BOARD INTERFACE-J35B

VJYM SPPD

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630-60569-01 01

TVII-B-H-8M 320-BGA CPU BOARD

A4

41 44

Wednesday, Auguﬆ 21, 2019

BASE BOARD INTERFACE-J35B

VJYM SPPD

J35B

CON_PMC_90X2_F

91

93

95

97

99

101

103

105

107

109

111

113

115

117

119

121

123

125

127

129

131

133

135

137

139

141

143

145

147

149

151

153

155

157

159

161

163

165

167

169

171

173

175

177

179

92

94

96

98

100

102

104

106

108

110

112

114

116

118

120

122

124

126

128

130

132

134

136

138

140

142

144

146

148

150

152

154

156

158

160

162

164

166

168

170

172

174

176

178

180

187

188

189

190

191

192

BOARD TO BOARD CONNECTOR - J35B

Schematics of CPU Board

CYTVII-B-H-8M-320-CPU Evaluation Board User Guide, Document Number: 002-26716 Rev. *A 79

Figure A-41. Base Board Connector - J36A

5

4

3

2

1

D D

C C

B B

A A

This connects to J84 on the TVII Base board

BB_USER_BUTTON_4 {12,20} BB_USER_LED0 {13,20} BB_SPI0_SS0 {8,20} BB_SPI0_CLK {8,20,35}

BB_CAN2_TXD {16,20} BB_CAN2_RXD {16,20} BB_CAN_SPI1_SS0 {11,20} BB_CAN_SPI1_SS1 {11,20}

BB_CAN6_WAKE {13,20} BB_CAN7_WAKE {16,20}

BB_CAN2_S {13,20} BB_CAN3_S {8,20} BB_CAN4_S {8,20} BB_CAN5_S {8,20}

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Wednesday, Auguﬆ 21, 2019

BASE BOARD INTERFACE-J36A

VJYM SPPD

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630-60569-01 01

TVII-B-H-8M 320-BGA CPU BOARD

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Wednesday, Auguﬆ 21, 2019

BASE BOARD INTERFACE-J36A

VJYM SPPD

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TVII-B-H-8M 320-BGA CPU BOARD

A4

42 44

Wednesday, Auguﬆ 21, 2019

BASE BOARD INTERFACE-J36A

VJYM SPPD

J36A

CON_PMC_90X2_F

1

3

5

7

9

11

13

15

17

19

21

23

25

27

29

31

33

35

37

39

41

43

45

47

49

51

53

55

57

59

61

63

65

67

69

71

73

75

77

79

81

83

85

87

89

2

4

6

8

10

12

14

16

18

20

22

24

26

28

30

32

34

36

38

40

42

44

46

48

50

52

54

56

58

60

62

64

66

68

70

72

74

76

78

80

82

84

86

88

90

181

182

183

184

185

186

BOARD TO BOARD CONNECTOR - J36A

Schematics of CPU Board

CYTVII-B-H-8M-320-CPU Evaluation Board User Guide, Document Number: 002-26716 Rev. *A 80

Figure A-42. Base Board Connector - J36B

5

4

3

2

1

D

C

B B

A A

This connects to J84 on the TVII Base board

Place R81 closer to the Samtec Connector J35

BB_P_3V3

VCC_3V3

BB_CAN6_RXD

{10,20}

BB_CAN6_TXD{10,20} BB_CAN8_WAKE {8,20}

BB_CAN9_WAKE {13,20}

BB_CAN4_TXD {11,20} BB_CAN4_RXD {11,20}

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BASE BOARD INTERFACE-J36B

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CYPRESS SEMICONDUCTOR 198 CHAMPION COURT SAN JOSE, CA 95134 (408) 943-2600

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630-60569-01 01

TVII-B-H-8M 320-BGA CPU BOARD

A4

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Wednesday, Auguﬆ 21, 2019

BASE BOARD INTERFACE-J36B

VJYM SPPD

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Drawn By

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Approved By

630-60569-01 01

TVII-B-H-8M 320-BGA CPU BOARD

A4

43 44

Wednesday, Auguﬆ 21, 2019

BASE BOARD INTERFACE-J36B

VJYM SPPD

R300 0 OhmDNI

J36B

CON_PMC_90X2_F

91

93

95

97

99

101

103

105

107

109

111

113

115

117

119

121

123

125

127

129

131

133

135

137

139

141

143

145

147

149

151

153

155

157

159

161

163

165

167

169

171

173

175

177

179

92

94

96

98

100

102

104

106

108

110

112

114

116

118

120

122

124

126

128

130

132

134

136

138

140

142

144

146

148

150

152

154

156

158

160

162

164

166

168

170

172

174

176

178

180

187

188

189

190

191

192

BOARD TO BOARD CONNECTOR - J36B

Schematics of CPU Board

CYTVII-B-H-8M-320-CPU Evaluation Board User Guide, Document Number: 002-26716 Rev. *A 81

B. Component Assembly on CPU Board

This appendix shows the top and bottom assembly of the CYTVII-B-H-8M-320-CPU board.

CYTVII-B-H-8M-320-CPU Evaluation Board User Guide, Document Number: 002-26716 Rev. *A 82

Figure B-1. Component Assembly (Top)

U10

SD CARD

DEBUG INTERFACE

CORTEX DEBUG

J7

GND

R18

R14

R15

R16

J4

J5

2

10

R3 R4

C1

9

C3

TP4

R17

J13

R38

R39

R40

R41

R42

37

R43

R44

R45

R37

R46

R47

R48

R49

R51

R52

R53

R54

ARM_ETM

MICTOR

R9

LED4

TRSTN

R1 R2

SW1

J52

P1

LD2

R21

R22

R28

R29

R24

R25

R26

R31

R32

R33

J48

USER

LD1

J37

J38

J6

J8

J11

R34

16152

1

J22

TP2

TR2

1V1_TR

TP1

FL1

U1

3V3

C5

P2

16

15

33

3

J2 J3

R373

R8

C2

R12

R13

19

CORTEX

DEBUG + ETM

20

2

1

12

1

26

3

D2

F1

C4

C6 C7

C9

C8

D4

2

1

R50

R55

R56

R60

R62

R61

TP6

TVII - B - H - 8M - 320 - BGA CPU 600 - 60569 - 01 REV 01 WW: 1931

TP12

C12

C13

C14

5V

U2

14

13

FL3

R58

FL4

TP18

5V

TP5

R20

12V

FL2

D1

12V

J9

12V

TR1

R11

TP3

R5

R19

R6

R7

R10

LED1 - 1V1 LED2 - 3V3

LED3 - 5V

SW2

GND

J1

OFF

ON

J10

2

3

4

3

20

J12 19

ARM STANDARD JTAG

GIGABIT ETHERNET

RJ45

J2413 7 1

TP24

TP25

TP26

TP28

C40

C39

C36

C37

TP27

C29 C30

16 12 6

R104

17

C47

2

Y3

R116

C48

4

TP34

R122

33

48

U5

R92

C34 C38 C43

C45

49

64

TP29

TP31

R127

R144

R140

R137

R132

R68

R74

R78

R82

R91

R100

R108

R114

R67

R70

R76

R80

R86

R96

R103

R112

R118

R126

R134

R139

R141

R143

R149

R316

TP30

TP33

TP32

32

16

1

2

P12

2

C52

C51

UART TO USB TRANSCEIVER

TYPE - B MINI USB

J26

TX

LED5RXLED6

R147

R150

R151

C65

C68

C69

2

3V3

1

J29

3

GND

R167

Y5

4

C50 C54 C57 C59

15

16

1

2

R162

R163

J30

J31

28

C67

15

U8

J28

4

5

L4

4

3

FL5

2

FL6

C72

R165

R166

14

R171

TP38

R172

C77

R169

R170

R176

R175

J32

GND

C74

C73

C75

C76

R174

R173

U9

TP37

DUAL QUAD-SPI

H - FlASH & H - SRAM

R191

R190

R189

TP70

TP69

R195

R379

R378

U15

R375 R374

TP50

TP55

TP49

TP54

R194 R196

TP63

U13

U12

R377R376

A B C D E

5 4 3 2 1

U14

R192

R193

C86

C88

R187

R201

R188

R184 R185 R186

R199 R200

R206 R210 R212 R214 R215

SMIF HS CONNECTOR

J33

51

16

15

2

2 1

1

2

1

2

1

3

C63

R164

C70

C71

C66

R159

15

16

15

P17

P16 162

2

P15

P14

P13

16

J47

R349

P11

P9

P7

J50

J43

J42

J41

J49

J44

J39

J51

U6

20

1

R119

R146

R142

TP36

VDDA_R

R350

DGND

AGND

AGND_R

TP35

R370

R369 R239 R238

J46

R340 R339

R359

R360

15

11

1

R168

R320

R319 R317 R318

R358

R357

R182

R180

R178

R177

R179

R181

R183

17 15

52

18

16

2

TP43

TP46

TP53

TP59

TP62

TP40

TP42

TP45

TP52

TP58

TP61

TP39

TP41

TP44

TP51

TP57

TP60

AUDIO INTERFACE

I2S AUDIO

J34

TP48

C84

3.5MM

AUDIO JACK

R216

R127

R198

R197

TP56

GND

TP47

FB1

32 25

24

17

16

9

8

C83

U11

R211

R213

C92

FB2

C78

C79

C80

C82

C87

C89

C90

C91

TP65

TP64

TP67

B

C81

Y6

Y7

TP68

R202

R203

R209

R208

R205

R207

C24

C25

C22

C23

C49 C53 C56 C58

1V8 - LDO

ABCDEFGHJKLMNPRTUVWY

2V5 - LDO

C11

J40

C10

D3

1

3

1

3

4

J45

J23

P6P5

P4

16

22

2

P3

1

15

1

15

Y1

TP19

TP21

R64

R65

R66

C17 C18

3

R57

R59

U3

C15

C16

TP20

1V1

1P7

1V1_PMIC

J15

TP15

J21

VDDIO3

3V3

VDDIO2

TP11

VDDA

J18 J19

5V 5V

TP10

1

3V3

3

TP8

VDDIO1

TP13 VCCD

TP14

VDDIO4

J14

1V1

VCCD

VDDD

J17

J20

5V

VDDD

TP9

3V3

5V

1

3V3

3

J16

TP16

TP17

16

2

1

15

P8

2

1

16

15

CN1

R63

Y2

C20

C19

D - SUB 9

6

J25

AUTOMOTIVE ETHERNET

TP23

R72

R73

1

2

1

2

3

1

2

1

TP22

R69 R71

R75

R77

L1

R87

R97

C21

C27

L2

C26 C28

R83 R85 R90 R95 R99 R102 R106 R110

U4

36

28

27

19

18

C31 R89 R94

10

C42

D5

5

9

L3

C32

C33

C35

C41

C44

C46

R111

R107

R124

R130

R123 R129

R128

R136

R115

R81

R88

R98

R105

R113

R120

R79

R84

R93

R101

R109

R117

R121

R133

P10

15

16 R125 R131

R135 R138

C55

Y4

RESET

3

2

SW3

D6

R148

C60

R145

4

1

R152

R154

2

C62

C61

R153

U7 R155 R157

J27

R160 R161

LED7 XRES

R156

R158

C64

Component Assembly on CPU Board

CYTVII-B-H-8M-320-CPU Evaluation Board User Guide, Document Number: 002-26716 Rev. *A 83

Figure B-2. Component Assembly (Bottom)

R223

R222

R224

R225

R252

R253

R237 R236

R234

R235

R352 R351

R371 R372

R361

R362

R246

R247

R220

R232

C96

C97

C104

C116

C127

C134

Y8

4

C101 R277

C102 R278

2

C98

R279

R280

A

YWVUTRPNMLKJHGFEDCBA

20

1

C137

R269

R347

R348

R260

R262

R263 R261

R276

R290

R291

R297

R274

R296

R298

R299

R273

R342

R341 R368 R367

R365 R366

C109

C122

C121

C108

C132

C107

C133

C105 C106

C131 C126 C144 C110

C125 C115

C128 C123 C117

C124 C118 C113

C111 C112

C130 C129

R284

R285

R286

C99

C100

R283

C135

C136

R287

FB3

R289

R288

C138

R309

R311

C144

R310

C145

C140

C141

E D C B A

C146

515

1

C139

C147

R306

C142

R301

R302

R312

R313

R303

R305

R307

R314

179 121 119

61 59

62 60 2

J36

122 120

180

R304

R315

R300

C143

R308

R282

R257 R256

R218

C94

R219

C95

R221

C103

C120

C119

L5

1

5

6

9

179

R229

R230

R231

R226

R227

R228

R233

121 119

61

62

R251

60

2

J35

120

122

180

Component Assembly on CPU Board

CYTVII-B-H-8M-320-CPU Evaluation Board User Guide, Document Number: 002-26716 Rev. *A 84

C. Schematics of Base Board

This appendix contains the schematics of Traveo II Base board (CYTVII-B-E-BB).

CYTVII-B-H-8M-320-CPU Evaluation Board User Guide, Document Number: 002-26716 Rev. *A 85

Schematics of Base Board

Figure C-1. Block Diagram

5

D D

C C

B B

4

3

2

1

CYPRESS SEMICONDUCTOR

CYPRESS SEMICONDUCTOR 198 CHAMPION COURT

198 CHAMPION COURT

198 CHAMPION COURT SAN JOSE, CA 95134

SAN JOSE, CA 95134

SAN JOSE, CA 95134 (408) 943-2600

(408) 943-2600

A A

5

4

3

2

SCH Title :

TRAVEO II BASE BOARD

BLOCK DIAGRAM

Page Title :

Size

Document Number

B

5869234

Date:

Thursday, May 24, 2018

(408) 943-2600

Drawn By

BALA K SPPD

Sheet

1

Approved By

Rev

A

of

318

of

318

of

318

CYTVII-B-H-8M-320-CPU Evaluation Board User Guide, Document Number: 002-26716 Rev. *A 86

Figure C-2. BTOB Connector-01

5

Schematics of Base Board

4

3

2

1

BTOB CONNECTOR-01

J84A

1

3

5

7

9

11

13

15

17

19

21

23

25

27

29

31

33

35

37

39

41

43

45

47

49

51

53

55

57

59

61

63

65

67

69

71

73

75

77

79

81

83

85

87

89

181

182

1

1K

182

183

LD13SML-P12YTT86

2

184

185

186

184

185

186

P_3V3

2

4

6

8

10

12

14

16

18

20

22

24

26

28

30

32

34

36

38

40

42

44

46

48

50

52

54

56

58

60

62

64

66

68

70

72

74

76

78

80

82

84

86

88

90

CON_PMC_2X90_M

C9 10uF

4

C8

0.1uF

FL3

1

600E

BB_USER_BUTTON_4 16,17 BB_USER_LED0 16,18 SPI0_SS 15,17 SPI0_CLK 15,17

BB_EXP1_GPIO_1 18 BB_EXP1_GPIO_2 18 BB_EXP1_GPIO_3 18 BB_EXP1_GPIO_4 18

BB_EXP1_GPIO_5 18 BB_EXP1_GPIO_6 18

BB_EXP1_GPIO_7 18 BB_EXP1_GPIO_8 18 BB_EXP1_GPIO_9 18 BB_EXP1_GPIO_10 18

BB_EXP1_GPIO_11 18 BB_EXP1_GPIO_12 18 BB_EXP1_GPIO_13 18 BB_EXP1_GPIO_14 18

BB_EXP1_GPIO_15 18 BB_EXP1_GPIO_16 18

UART1_RX 17 UART1_TX 17 UART1_RTS 17 UART1_CTS 17 CAN2_TXD 6,17 CAN2_RXD 6,17 CAN_SPI1_SS0 8,17 CAN_SPI1_SS1 8,17 CAN_SPI1_SS2 9,17

CAN2_S 6,17 CAN3_S 6,17 CAN4_S 7,17 CAN5_S 7,17 CAN6_WAKE 8,17 CAN7_WAKE 8,17

VCC_3V3

2

C10

0.1uF

8

9

17

DEBUG_GPIO_1

17

DEBUG_GPIO_2

17

DEBUG_GPIO_3

17

DEBUG_GPIO_4

VCC_3V3

3

CAN6_TXD

CAN6_RXD8

CAN7_TXD8

CAN7_RXD8

CAN8_TXD9

CAN8_RXD9

CAN9_TXD

CAN9_RXD9

J80 HDR_1X3

TP13

TP14

TP15

Default 1-2

VCC_5V

123

VDD_IO_W

BB_PWM_117 BB_PWM_217 BB_PWM_3 BB_PWM_417 BB_PWM_517 BB_PWM_617 BB_PWM_717 BB_ADC_2 BB_ADC_317 BB_ADC_417 BB_ADC_517 BB_ADC_617 BB_ADC_7

BB_ADC_817

TP6

TP7

TP8

TP9

TP10

TP11

TP12

R21

5% 0402

5

D D

C C

17

B B

A A

J84B

91

93

95

97

99

101

103

105

107

109

111

113

115

117

119

121

123

125

127

129

131

133

135

137

139

141

143

145

147

149

151

153

155

157

159

161

163

165

167

169

171

173

175

177

179

187

188

FL4

1

600E

2

188

189

VDD_IO

190

191

192

190

191

192

2

92

94

96

98

100

102

104

106

108

110

112

114

116

118

120

122

124

126

128

130

132

134

136

138

140

142

144

146

148

150

152

154

156

158

160

162

164

166

168

170

172

174

176

178

180

CON_PMC_2X90_M

P_3V3

CAN8_WAKE 9,17

CAN9_WAKE 9,17 CAN5_TXD 7,17 CAN5_RXD 7,17 CAN4_TXD 7,17 CAN4_RXD 7,17

TP16

TP17

TP18

TP19

TP20

SCH Title :

TRAVEO II BASE BOARD

BTOB CONNECTOR-01

Page Title :

Size

Document Number

B

Date:

Document Number

5869234

Thursday, May 24, 2018

Drawn By

BALA K SPPD

CYPRESS SEMICONDUCTOR

CYPRESS SEMICONDUCTOR 198 CHAMPION COURT

198 CHAMPION COURT

198 CHAMPION COURT SAN JOSE, CA 95134

SAN JOSE, CA 95134

SAN JOSE, CA 95134 (408) 943-2600

(408) 943-2600

Approved By

Sheet

of

418

of

418

of

418

1

Rev

A

CYTVII-B-H-8M-320-CPU Evaluation Board User Guide, Document Number: 002-26716 Rev. *A 87

Figure C-3. BTOB Connector-02

5

4

3

2

1

D D

C C

B B

A A

BTOB CONNECTOR-02

Default closed

BB_I2C1_SDA

BB_I2C1_SCL

P_5V

P_12V

P_5V

VBAT

P_12V

VDD_IO

VCC_5V

CAN1_RXD

6,17

CAN1_TXD6,17 CAN1_S

6,17

CAN0_RXD

6,17

CAN0_TXD6,17

LIN1_TXD

10,17

LIN1_RXD10,17

LIN0_WAKE

10,17

LIN0_SLP

10,17

LIN0_RXD10,17

LIN0_TXD10,17

CXPI_SELMS15,17 CXPI_NSLP

15,17

CXPI_RXD15,17

CXPI_TXD

15,17

LIN5_WAKE

12,17

LIN5_SLP12,17

LIN5_RXD12,17

LIN5_TXD

12,17

LIN2_WAKE

11,17

LIN2_RXD11,17

LIN2_TXD11,17

LIN2_SLP

11,17

LIN3_WAKE

11,17

LIN3_SLP

11,17

LIN3_RXD11,17

LIN3_TXD11,17

LIN4_WAKE12,17 LIN4_SLP12,17

LIN4_RXD12,17

LIN4_TXD12,17

BB_I2C1_SDA

17

BB_I2C1_SCL17

CXPI_CLK15,18 BB_GPIO_3718

BB_HPMC_1 17 BB_HPMC_3 17 BB_HPMC_4 17

CAN_SPI1_SCK 8,9,18

BB_BOARD_RSTX_SET

BB_BOARD_RSTX

BB_GPIO_48 18 BB_GPIO_49 18 BB_GPIO_50 18 BB_GPIO_51 18 BB_GPIO_52 18 BB_GPIO_53 18 BB_GPIO_54 18 BB_GPIO_55 18

BB_GPIO_56_RESET 18

BB_PWM_8 18 BB_PWM_9 18 BB_PWM_10 18

UART0_RTS 18

UART0_TX 18

UART0_RX 18

UART0_CTS 18

SPI2_MOSI 18 SPI2_CLK 18

SPI2_MISO 18

SPI2_SS 18 CAN3_TXD 6,18 CAN3_RXD 6,18

FRA_RXD13

FRA_TXD

13

FRA_TXEN

13

FRA_STBN13 FRA_EN

13

FRA_ERRN13

FRA_WAKE

13

BB_USER_BUTTON_1

16,17

BB_USER_BUTTON_216,17 BB_USER_BUTTON_316,17

BB_USER_BUTTON_5

16,17

BB_USER_LED1

16,18

BB_USER_LED2

16,18

BB_USER_LED316,18 BB_USER_LED416,18 BB_USER_LED516,18 BB_USER_LED6

16,18

BB_USER_LED7

16,18

BB_USER_LED8 16,17

BB_USER_LED9 16,17

BB_ADC_POT

15,18

BB_ADC_1

18

DEBUG_GPIO_518 DEBUG_GPIO_618 DEBUG_GPIO_718 DEBUG_GPIO_818 DEBUG_GPIO_918 DEBUG_GPIO_1018 DEBUG_GPIO_1118 DEBUG_GPIO_1218

DEBUG_GPIO_13 18 DEBUG_GPIO_14 18 DEBUG_GPIO_15 18 DEBUG_GPIO_16 18 DEBUG_GPIO_17 18 DEBUG_GPIO_18 18 DEBUG_GPIO_19 18 DEBUG_GPIO_20 18

DEBUG_GPIO_21 5 DEBUG_GPIO_22 5 DEBUG_GPIO_23 18 DEBUG_GPIO_24 18 DEBUG_GPIO_25 5

DEBUG_GPIO_26 18 DEBUG_GPIO_27 18

BB_EXP2_GPIO_1 18 BB_EXP2_GPIO_2 18

BB_EXP2_GPIO_3 18 BB_EXP2_GPIO_4 18 BB_EXP2_GPIO_5 18

BB_EXP2_GPIO_6 18 BB_EXP2_GPIO_7 18 BB_EXP2_GPIO_8 18 BB_EXP2_GPIO_9 18 BB_EXP2_GPIO_10 18

BB_EXP2_GPIO_11 18 BB_EXP2_GPIO_12 18 BB_EXP2_GPIO_13 18 BB_EXP2_GPIO_14 18

BB_EXP2_GPIO_15 18 BB_EXP2_GPIO_16 18

SPI0_HOLD 15,18

SUPPLY_INH 14,17

SPI0_MISO15,18

SPI0_MOSI15,18

BB_HPMC_2 17

FRB_RXD14 FRB_TXD14 FRB_TXEN

14

FRB_STBN

14

FRB_EN

14

FRB_ERRN14 FRB_WAKE14

BB_ADC_917

BB_ADC_1017 BB_ADC_1117

CAN0_S 6,17 LIN1_WAKE 10,17 LIN1_SLP 10,17

SPI0_WP 15,17

CAN_SPI1_MISO 8,9,18

CAN_SPI1_MOSI 8,9,18

DEBUG_GPIO_21 5 DEBUG_GPIO_21_W 18

DEBUG_GPIO_22 5 DEBUG_GPIO_22_W 18

DEBUG_GPIO_25 5 DEBUG_GPIO_25_W 18

SCH Title :

Size

Document Number

Rev

Date:

Sheet

of

Page Title :

Drawn By

CYPRESS SEMICONDUCTOR 198 CHAMPION COURT SAN JOSE, CA 95134 (408) 943-2600

Approved By

5869234

A

TRAVEO II BASE BOARD

B

518

Thursday, May 24, 2018

BTOB CONNECTOR-02

BALA K SPPD

SCH Title :

Size

Document Number

Rev

Date:

Sheet

of

Page Title :

Drawn By

CYPRESS SEMICONDUCTOR 198 CHAMPION COURT SAN JOSE, CA 95134 (408) 943-2600

Approved By

5869234

A

TRAVEO II BASE BOARD

B

518

Thursday, May 24, 2018

BTOB CONNECTOR-02

BALA K SPPD

SCH Title :

Size

Document Number

Rev

Date:

Sheet

of

Page Title :

Drawn By

CYPRESS SEMICONDUCTOR 198 CHAMPION COURT SAN JOSE, CA 95134 (408) 943-2600

Approved By

5869234

A

TRAVEO II BASE BOARD

B

518

Thursday, May 24, 2018

BTOB CONNECTOR-02

BALA K SPPD

J38A

CON_PMC_2X90_M

1

3

5

7

9

11

13

15

17

19

21

23

25

27

29

31

33

35

37

39

41

43

45

47

49

51

53

55

57

59

61

63

65

67

69

71

73

75

77

79

81

83

85

87

89

2

4

6

8

10

12

14

16

18

20

22

24

26

28

30

32

34

36

38

40

42

44

46

48

50

52

54

56

58

60

62

64

66

68

70

72

74

76

78

80

82

84

86

88

90

181

182

183

184

185

186

C3

0.1uF

C1 10uF

J132

HDR_1X2

1 2

R2 1K

5% 0402

R101 4.7K_1%

DNI

TP5

J134

HDR_1X2

1 2

C2

0.1uF

TP2

C6

0.1uF

TP4

LD1

SML-P12YTT86

21

FL2

600E

1 2

C4 10uF

R102

4.7K_1%

DNI

J133

HDR_1X2

1 2

TP3

C5

0.1uF

LD2

SML-P12YTT86

21

FL1

600E

1

2

R3

1K

5% 0402

J38B

CON_PMC_2X90_M

91

93

95

97

99

101

103

105

107

109

111

113

115

117

119

121

123

125

127

129

131

133

135

137

139

141

143

145

147

149

151

153

155

157

159

161

163

165

167

169

171

173

175

177

179

92

94

96

98

100

102

104

106

108

110

112

114

116

118

120

122

124

126

128

130

132

134

136

138

140

142

144

146

148

150

152

154

156

158

160

162

164

166

168

170

172

174

176

178

180

187

188

189

190

191

192

TP1

Schematics of Base Board

CYTVII-B-H-8M-320-CPU Evaluation Board User Guide, Document Number: 002-26716 Rev. *A 88

Figure C-4. CAN-FD_0 to 3

5

Schematics of Base Board

4

3

2

1

R98 0E R99

0E

R100 120E

R108

0E

R109

0E

Default Open

CAN_FD_0

CON_DSUB_9_MM

A5 A9 A4 A8 A3

CAN0_H

A7

CAN0_L

A2 A6 A1

P6A

CAN_FD_2

CON_DSUB_9_MM

A5 A9 A4 A8 A3

CAN2_H

A7

CAN2_L

A2 A6 A1

P7A

R110 120E

VDD_IO

3

2

VDD_IO

3

2

VCC

GND

VCC

GND

CANH

CANL

CANH

CANL

NC

C50

+

C51

22uF_20V

0.1uF

CAN1_H_W

7

CAN1_L_W

6

J65

5

HDR_1X2

2

CAN1_H

CAN1_L

C54

+

C55

22uF_20V

0.1uF

CAN3_H_W

7

CAN3_L_W

6

J75

5

HDR_1X2

1

2

CAN3_H

CAN3_L

SCH Title :

TRAVEO II BASE BOARD

CAN-FD_0 TO 3

Page Title :

Size

Document Number

B

5869234

Date:

Thursday, May 24, 2018

J66

J68

HDR_1X2

SH2

5,17

SH1

SH2

SH1

Default Closed

3

Default Closed

CAN1_TXD

CAN1_RXD

CAN1_S5,17

Default Closed

CAN3_TXD5,18

CAN3_RXD5,18

CAN3_S4,17

Default Closed

HDR_1X2

2

J78 HDR_1X2

2

1

J67 HDR_1X2

J76 HDR_1X2

1

J77 HDR_1X2

2

1

2

1

2

1

CAN3_S_W

CAN1_TXD_W CAN1_RXD_W

CAN1_S_W

R93 10K

CAN3_TXD_W CAN3_RXD_W

R103 10K

U12

1

TXD

4

RXD

8

S

TJA1057GT

U14

1

TXD

4

RXD

8

S

TJA1057GT

2

VDD_IO

D D

C C

B B

4,17

A A

Default Closed

CAN0_TXD5,17

CAN0_RXD5,17

CAN0_S5,17

Default Closed

CAN2_TXD4,17

CAN2_RXD4,17

CAN2_S

Default Closed

J72 HDR_1X2

2

J83 HDR_1X2

2

5

J70 HDR_1X2

1

J71 HDR_1X2

J81 HDR_1X2

1

J82 HDR_1X2

1

2

CAN0_TXD_W CAN0_RXD_W

CAN0_S_W

1

2

R97 10K

1

2

CAN2_TXD_W CAN2_RXD_W

CAN2_S_W

1

2

R107 10K

U13

1

TXD

4

RXD

8

S

TJA1057GT

U15

1

TXD

4

RXD

8

S

TJA1057GT

3

2

VDD_IO

3

2

VCC

GND

VCC

GND

C52

22uF_20V

CANH

CANL

CANH

CANL

C53

+

0.1uF

CAN0_H_W

7

CAN0_L_W

6

J69

5

NC

HDR_1X2

Default Open

1

2

CAN0_H

CAN0_L

C56

+

C57

22uF_20V

0.1uF

CAN2_H_W

7

CAN2_L_W

6

J79

5

NC

CAN2_H

CAN2_L

4

HDR_1X2

1

2

CAN1_H

R94

0E

CAN1_L

R95 0E

Default Open

1

CAN3_H

R104 0E

CAN3_L

R105 0E

Default Open

R106 120E

Drawn By

BALA K SPPD

CAN_FD_1

CON_DSUB_9_MM

B5

SH4 B9 B4 B8 B3 B7 B2 B6 B1

SH3

P6B

R96 120E

CAN_FD_3

CON_DSUB_9_MM

B5

SH4 B9 B4 B8 B3 B7 B2 B6 B1

SH3

P7B

CYPRESS SEMICONDUCTOR

CYPRESS SEMICONDUCTOR 198 CHAMPION COURT

198 CHAMPION COURT

198 CHAMPION COURT SAN JOSE, CA 95134

SAN JOSE, CA 95134

SAN JOSE, CA 95134 (408) 943-2600

(408) 943-2600

Approved By

Sheet

of

618

of

618

of

618

1

Rev

A

CYTVII-B-H-8M-320-CPU Evaluation Board User Guide, Document Number: 002-26716 Rev. *A 89

Figure C-5. CAN-FD_4 & 5

5

4

3

2

1

D D

C C

B B

A A

CAN_FD_4

CAN_FD_5

Default Open

Default Closed

CAN4_L_W

CAN4_H_W

CAN4_L

CAN4_H

CAN4_S_W

CAN4_RXD_W

CAN4_TXD_W

CAN5_L_W

CAN5_H_W

CAN5_L

CAN5_H

CAN5_S_W

CAN5_RXD_W

CAN5_TXD_W

CAN4_H

CAN4_L

CAN5_H

CAN5_L

VDD_IO

CAN4_TXD4,17 CAN4_RXD4,17

CAN4_S4,17

CAN5_TXD

4,17

CAN5_RXD

4,17

CAN5_S4,17

SCH Title :

Size

Document Number

Rev

Date:

Sheet

of

Page Title :

Drawn By

CYPRESS SEMICONDUCTOR 198 CHAMPION COURT SAN JOSE, CA 95134 (408) 943-2600

Approved By

5869234

A

TRAVEO II BASE BOARD

B

718

Thursday, May 24, 2018

CAN-FD_4 TO 7

BALA K SPPD

SCH Title :

Size

Document Number

Rev

Date:

Sheet

of

Page Title :

Drawn By

CYPRESS SEMICONDUCTOR 198 CHAMPION COURT SAN JOSE, CA 95134 (408) 943-2600

Approved By

5869234

A

TRAVEO II BASE BOARD

B

718

Thursday, May 24, 2018

CAN-FD_4 TO 7

BALA K SPPD

SCH Title :

Size

Document Number

Rev

Date:

Sheet

of

Page Title :

Drawn By

CYPRESS SEMICONDUCTOR 198 CHAMPION COURT SAN JOSE, CA 95134 (408) 943-2600

Approved By

5869234

A

TRAVEO II BASE BOARD

B

718

Thursday, May 24, 2018

CAN-FD_4 TO 7

BALA K SPPD

J87 HDR_1X2

1

2

U17

TJA1057GT

TXD

1

GND

2

VCC

3

RXD

4

NC

5

CANL

6

CANH

7

S

8

+

C58

22uF_20V

J88 HDR_1X2

1

2

R111 10K

J90 HDR_1X2

1

2

+

C62

22uF_20V

C59

0.1uF

U16

TJA1057GT

TXD

1

GND

2

VCC

3

RXD

4

NC

5

CANL

6

CANH

7

S

8

R119 120E

R117

0E

J86 HDR_1X2

1

2

R113 0E

J92 HDR_1X2

1

2

P8A

CON_DSUB_9_MM

A1

A6

A2

A7

A3

A8

A4

A9

A5

SH1

SH2

P8B

CON_DSUB_9_MM

B1

B6

B2

B7

B3

B8

B4

B9

B5

SH3

SH4

J93 HDR_1X2

1

2

R116 10K

R112 0E

J85 HDR_1X2

1

2

C63

0.1uF

J91 HDR_1X2

1

2

R114 120E

R118

0E

Schematics of Base Board

CYTVII-B-H-8M-320-CPU Evaluation Board User Guide, Document Number: 002-26716 Rev. *A 90

Figure C-6. CAN-FD_6 & 7

5

4

3

2

1

D D

C C

B B

A A

Default Closed

Default Open

Default closed

Default Closed

Default Open

desolc tluafeD

CAN_FD_6

CAN_FD_7

Default closed

CAN6_RXD_W

CAN6_TXD_W

CAN6_H

CAN6_L

CAN6_INH_W

CAN6_L_W

CAN6_H_W

CAN6_L

CAN6_H

CAN_SPI1_MOSI_W CAN_SPI1_MISO_W

CAN_SPI1_MISO_W

CAN_SPI1_SCK_W

CAN_SPI1_SS0_W

CAN6_WAKE_W

CAN_SPI1_SCK_W

CAN_SPI1_SS0_W

CAN7_RXD_W

CAN7_TXD_W

CAN7_H

CAN7_L

CAN7_INH_W

CAN7_L_W

CAN7_H_W

CAN7_L

CAN7_H

CAN_SPI1_MISO_W

CAN7_WAKE_W

CAN_SPI1_SCK_W

CAN_SPI1_MOSI_W

CAN_SPI1_SS1_W

CAN_SPI1_MOSI_W CAN_SPI1_MISO_W

CAN_SPI1_SCK_W

CAN_SPI1_SS1_W

VDD_IO

VBAT

VDD_IO

VBAT

VDD_IO

VDD_IO VBAT

VDD_IO

VBAT

VCC_5V

CAN6_TXD

4

CAN6_RXD4

CAN6_INH 14

CAN_SPI1_MISO 5,8,9,18

CAN_SPI1_SCK 5,8,9,18

CAN_SPI1_SS0 4,17

CAN7_TXD4

CAN7_RXD4

CAN7_INH 14

CAN_SPI1_MISO 5,8,9,18

CAN_SPI1_SCK 5,8,9,18

CAN7_WAKE4,17

CAN6_WAKE

4,17

CAN_SPI1_MOSI 5,8,9,18

CAN_SPI1_SS1 4,17

CAN_SPI1_MOSI_W

8,9

CAN_SPI1_SCK_W8,9

CAN_SPI1_MISO_W8,9

CAN_SPI1_MOSI_W8,9

CAN_SPI1_SCK_W8,9

CAN_SPI1_MISO_W8,9

SCH Title :

Size

Document Number

Rev

Date:

Sheet

of

Page Title :

Drawn By

CYPRESS SEMICONDUCTOR 198 CHAMPION COURT SAN JOSE, CA 95134 (408) 943-2600

Approved By

5869234

A

TRAVEO II BASE BOARD

B

818

Thursday, May 24, 2018

CAN-FD_6 & 7

BALA K SPPD

SCH Title :

Size

Document Number

Rev

Date:

Sheet

of

Page Title :

Drawn By

CYPRESS SEMICONDUCTOR 198 CHAMPION COURT SAN JOSE, CA 95134 (408) 943-2600

Approved By

5869234

A

TRAVEO II BASE BOARD

B

818

Thursday, May 24, 2018

CAN-FD_6 & 7

BALA K SPPD

SCH Title :

Size

Document Number

Rev

Date:

Sheet

of

Page Title :

Drawn By

CYPRESS SEMICONDUCTOR 198 CHAMPION COURT SAN JOSE, CA 95134 (408) 943-2600

Approved By

5869234

A

TRAVEO II BASE BOARD

B

818

Thursday, May 24, 2018

CAN-FD_6 & 7

BALA K SPPD

J100

HDR_1X2

1 2

R129

0E

+

C67 22uF_20V

C77

0.1uF

R120

0E

R131 120E

J95 HDR_1X2

1

2

J104

HDR_1X2

1 2

P9A

CON_DSUB_9_MM

A1

A6

A2

A7

A3

A8

A4

A9

A5

SH1

SH2

J103

HDR_1X2

1 2

R124 10K

J107 HDR_1X2

1

2

J97 HDR_1X2

1

2

R122

4.7K_1%

+

C66 22uF_20V

R132

4.7K_1%

C71

0.1uF

R121

0E

J101

HDR_1X2

1

2

U18

TJA1145T

TXD

1

GND

2

VCC

3

RXD

4

VIO

5

SDO

6

INH

7

SCK

8

WAKE

9

BAT

10

SDI

11

CANL

12

CANH

13

SCSN

14

C80

4.7uF

J110

HDR_1X2

1

2

J98

HDR_1X2

1 2

C68

0.1uF

J99

HDR_1X2

1 2

R127 10K

J106

HDR_1X2

1 2

R125

0E

C78

0.1uF

R126

0E

P9B

CON_DSUB_9_MM

B1

B6

B2

B7

B3

B8

B4

B9

B5

SH3

SH4

J96

HDR_1X2

1 2

J109 HDR_1X2

1

2

R130 120E

J105

HDR_1X2

1 2

C70

0.1uF

U19

TJA1145T

TXD

1

GND

2

VCC

3

RXD

4

VIO

5

SDO

6

INH

7

SCK

8

WAKE

9

BAT

10

SDI

11

CANL

12

CANH

13

SCSN

14

J108 HDR_1X2

1

2

C79

4.7uF

J94 HDR_1X2

1

2

R128 0E

C69

0.1uF

Schematics of Base Board

CYTVII-B-H-8M-320-CPU Evaluation Board User Guide, Document Number: 002-26716 Rev. *A 91

Figure C-7. CAN-FD_8 & 9

5

4

3

2

1

D D

C C

B B

A A

Default Closed

Default Open

Default closed

Default Closed

Default Open

desolc tluafeD

CAN_FD_8

CAN_FD_9

Default closed

CAN8_RXD_W

CAN8_TXD_W

CAN8_H

CAN8_L

CAN8_INH_W

CAN8_L_W

CAN8_H_W

CAN8_L

CAN8_H

CAN_SPI1_MISO_W

CAN8_WAKE_W

CAN_SPI1_SCK_W

CAN9_RXD_W

CAN9_TXD_W

CAN9_H

CAN9_L

CAN9_INH_W

CAN9_L_W

CAN9_H_W

CAN9_L

CAN9_H

CAN_SPI1_MISO_W

CAN9_WAKE_W

CAN_SPI1_SCK_W

CAN_SPI1_MOSI_W

CAN_SPI1_SS2_W

CAN_SPI1_MOSI_W

CAN_SPI1_SS2_W

CAN_SPI1_MOSI_W CAN_SPI1_MISO_W

CAN_SPI1_SCK_W

CAN_SPI1_SS2_W

CAN_SPI1_MOSI_W CAN_SPI1_MISO_W

CAN_SPI1_SCK_W

CAN_SPI1_SS2_W

VDD_IO

VBAT

VDD_IO

VBAT

VDD_IO

VBAT

VDD_IO VBAT

VCC_5V

CAN8_TXD

4

CAN8_RXD4

CAN8_INH 14

CAN_SPI1_MISO 5,8,9,18

CAN_SPI1_SCK 5,8,9,18

CAN9_TXD4

CAN9_RXD4

CAN9_INH 14

CAN_SPI1_MISO 5,8,9,18

CAN_SPI1_SCK 5,8,9,18

CAN9_WAKE4,17

CAN8_WAKE

4,17

CAN_SPI1_MOSI 5,8,9,18

CAN_SPI1_SS2 4,9,17

CAN_SPI1_MOSI 5,8,9,18

CAN_SPI1_SS2 4,9,17

CAN_SPI1_MOSI_W

8,9

CAN_SPI1_SCK_W8,9

CAN_SPI1_MISO_W8,9

CAN_SPI1_MOSI_W8,9

CAN_SPI1_SCK_W8,9

CAN_SPI1_MISO_W8,9

SCH Title :

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918

Thursday, May 24, 2018

CAN-FD_8 & 9

BALA K SPPD

SCH Title :

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918

Thursday, May 24, 2018

CAN-FD_8 & 9

BALA K SPPD

SCH Title :

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A

TRAVEO II BASE BOARD

B

918

Thursday, May 24, 2018

CAN-FD_8 & 9

BALA K SPPD

J131 HDR_1X2

1

2

C86

0.1uF

P10A

CON_DSUB_9_MM

A1

A6

A2

A7

A3

A8

A4

A9

A5

SH1

SH2

J118

HDR_1X2

1 2

R140

0E

J116

HDR_1X2

1 2

C90

4.7uF

J119 HDR_1X2

1

2

+

C81 22uF_20V

J120 HDR_1X2

1

2

J111

HDR_1X2

1

2

C85

0.1uF

J112 HDR_1X2

1

2

J124

HDR_1X2

1 2

J114 HDR_1X2

1

2

R134

0E

C88

0.1uF

R133

0E

J125

HDR_1X2

1

2

J115

HDR_1X2

1 2

J121

HDR_1X2

1 2

C84

0.1uF

C83

0.1uF

R138 10K

C89

4.7uF

J117

HDR_1X2

1 2

+

C82 22uF_20V

U21

TJA1145T

TXD

1

GND

2

VCC

3

RXD

4

VIO

5

SDO

6

INH

7

SCK

8

WAKE

9

BAT

10

SDI

11

CANL

12

CANH

13

SCSN

14

R144

4.7K_1%

C87

0.1uF

U20

TJA1145T

TXD

1

GND

2

VCC

3

RXD

4

VIO

5

SDO

6

INH

7

SCK

8

WAKE

9

BAT

10

SDI

11

CANL

12

CANH

13

SCSN

14

R136 0E

P10B

CON_DSUB_9_MM

B1

B6

B2

B7

B3

B8

B4

B9

B5

SH3

SH4

R135 10K

J123

HDR_1X2

1 2

J122

HDR_1X2

1 2

R141

4.7K_1%

R137

0E

R143 120E

R142 120E

J113 HDR_1X2

1

2

R139

0E

Schematics of Base Board

CYTVII-B-H-8M-320-CPU Evaluation Board User Guide, Document Number: 002-26716 Rev. *A 92

Figure C-8. LIN Interface_0 to 1

5

Schematics of Base Board

4

3

2

1

J58

LIN0_INTERFACE

LIN_VS

+

C46 22uF_20V

7

VBAT

GND

5

D26

1N4002-T

TXD RXD

INH

TJA1021T/20/C

Default Closed

LIN0_SLP5,17

D D

C47

0.1uF

Default Open

J59

1 2

HDR_1X2

C C

J61

Default Closed

B B

LIN0_WAKE5,17

HDR_1X2

C49 220pF

R92

C48 1000pF

2

1

1K

LIN0_WAKE_N

LIN0_BUS

LIN0_EN

VDD_IO

D25

21

1N4148W-7-F

R91

4.7K_1%

U11

3

WAKE_N

6

LIN

2

SLP_N

LIN0_WAKE_N

Default Closed

21

VDD_IO

R89

4.7K_1%

LIN0_TXD_W

4

LIN0_RXD_W

1

8

R88

J57

1 2 3

HDR_1X3

HDR_1X2

2

J60 HDR_1X2

2

0E

LIN0_BUS_W

J62 HDR_1X2

1

2

1

LIN0_BUS

J63 HDR_1X2

1

VBAT

1

2

LIN0_INH 14

R11

VDD_IO

R90

4.7K_1%

CON_DSUB_9_MM

A5 A9 A4 A8 A3 A7 A2 A6 A1

P5A

Default closed

LIN0_BUS

0E

SH2

SH1

LIN0_TXD 5,17

LIN0_RXD 5,17

LIN0_EN

LIN1_INTERFACE

Default Open

J52

1 2

HDR_1X2

Default Closed

LIN1_WAKE5,17

J54 HDR_1X2

R87

C44 1000pF

C45 220pF

2

1

1K

LIN1_WAKE_N

LIN1_BUS

LIN1_EN

VDD_IO

D24

1N4148W-7-F

R86

4.7K_1%

C43

0.1uF

21

U10

3

WAKE_N

6

LIN

2

SLP_N

LIN1_WAKE_N

+

LIN_VS

C42 22uF_20V

7

VBAT

GND

TJA1021T/20/C

5

5,17

1

TXD RXD

INH

D23

1N4002-T

LIN1_SLP

Default Closed

2

VDD_IO

R84

4.7K_1%

4 1

8

R83 0E

J44

1 2 3

HDR_1X3

J51 HDR_1X2

J53 HDR_1X2

LIN1_TXD_W LIN1_RXD_W

LIN1_BUS_W

J55 HDR_1X2

2

1

LIN1_BUS

J56 HDR_1X2

1

VBAT

1

VBAT

1

2

LIN1_INH 14

R7 0E

VDD_IO

CON_DSUB_9_MM

B5 B9 B4 B8 B3 B7 B2 B6 B1

P5B

Default closed

LIN1_BUS

R85

4.7K_1%

SH4

SH3

LIN1_TXD 5,17

LIN1_RXD 5,17

LIN1_EN

CYPRESS SEMICONDUCTOR

CYPRESS SEMICONDUCTOR 198 CHAMPION COURT

198 CHAMPION COURT

198 CHAMPION COURT SAN JOSE, CA 95134

SAN JOSE, CA 95134

SAN JOSE, CA 95134 (408) 943-2600

(408) 943-2600

A A

5

4

3

2

SCH Title :

TRAVEO II BASE BOARD

LIN INTERFACE_0 TO 1

Page Title :

Size

Document Number

B

5869234

Date:

Thursday, May 24, 2018

(408) 943-2600

Drawn By

BALA K SPPD

Sheet

1

Approved By

of

10 18

of

10 18

of

10 18

Rev

A

CYTVII-B-H-8M-320-CPU Evaluation Board User Guide, Document Number: 002-26716 Rev. *A 93

Figure C-9. LIN Interface_2 to 3

5

4

3

2

1

D D

C C

B B

A A

LIN2_INTERFACE

LIN3_INTERFACE

Default closed

Default Closed

Default Open

LIN2_WAKE_N

LIN2_BUS

LIN3_WAKE_N

LIN3_BUS

LIN3_EN

LIN2_BUS

LIN3_BUS

LIN2_RXD_W

LIN2_TXD_W

LIN3_RXD_W

LIN3_TXD_W

LIN2_WAKE_N

LIN2_EN

LIN3_WAKE_N

LIN3_EN

LIN2_BUS

LIN2_BUS_W

LIN3_BUS

LIN3_BUS_W

LIN2_EN

VDD_IO

LIN_VS

VBAT

VDD_IO

LIN3_INH 14

LIN2_INH 14

LIN2_RXD 5,17

LIN2_TXD 5,17

LIN3_RXD 5,17

LIN3_TXD 5,17

LIN2_SLP

5,17

LIN3_SLP5,17

LIN2_WAKE

5,17

LIN3_WAKE5,17

SCH Title :

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Date:

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of

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B

11 18

Thursday, May 24, 2018

LIN INTERFACE_2 TO 3

BALA K SPPD

SCH Title :

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Date:

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B

11 18

Thursday, May 24, 2018

LIN INTERFACE_2 TO 3

BALA K SPPD

SCH Title :

Size

Document Number

Rev

Date:

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of

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Approved By

5869234

A

TRAVEO II BASE BOARD

B

11 18

Thursday, May 24, 2018

LIN INTERFACE_2 TO 3

BALA K SPPD

J34 HDR_1X2

1

2

D14

1N4002-T

2

1

C37

0.1uF

R70

4.7K_1%

P4A

CON_DSUB_9_MM

A1

A6

A2

A7

A3

A8

A4

A9

A5

SH1

SH2

R77 1K

D16

1N4148W-7-F

21

R6 0E

J39

HDR_1X2

1 2

U7

TJA1021T/20/C

SLP_N

2

WAKE_N

3

GND

5

LIN

6

VBAT

7

INH

8

TXD

4

RXD

1

C33

0.1uF

C35 220pF

R67 0E

+

C36 22uF_20V

C34 1000pF

R69

4.7K_1%

J43 HDR_1X2

1

2

J37 HDR_1X2

1

2

D22

1N4148W-7-F

21

J40 HDR_1X2

1

2

+

C32 22uF_20V

R68

4.7K_1%

R72

0E

C39 220pF

J35 HDR_1X2

1

2

U8

TJA1021T/20/C

SLP_N

2

WAKE_N

3

GND

5

LIN

6

VBAT

7

INH

8

TXD

4

RXD

1

J31

HDR_1X2

1 2

J32 HDR_1X2

1

2

C38 1000pF

R5 0E

R75

4.7K_1%

J41 HDR_1X2

1

2

J42 HDR_1X2

1

2

J33 HDR_1X2

1

2

R71

1K

J36

HDR_1X3

1 2 3

J30 HDR_1X2

1

2

R74

4.7K_1%

J28

HDR_1X3

1 2 3

P4B

CON_DSUB_9_MM

B1

B6

B2

B7

B3

B8

B4

B9

B5

SH3

SH4

D21

1N4002-T

21

R73

4.7K_1%

Schematics of Base Board

CYTVII-B-H-8M-320-CPU Evaluation Board User Guide, Document Number: 002-26716 Rev. *A 94

Figure C-10. LIN Interface_4 to 5

5

4

3

2

1

D D

C C

B B

A A

LIN4_INTERFACE

LIN5_INTERFACE

Default closed

Default Closed

Default Open

LIN4_WAKE_N

LIN4_BUS

LIN5_WAKE_N

LIN5_BUS

LIN5_EN

LIN4_EN

LIN4_BUS

LIN5_BUS

LIN4_RXD_W

LIN4_TXD_W

LIN5_RXD_W

LIN5_TXD_W

LIN4_WAKE_N

LIN4_EN

LIN5_WAKE_N

LIN5_EN

LIN4_BUS

LIN4_BUS_W

LIN5_BUS

LIN5_BUS_W

VDD_IO

LIN_VS

VBAT

VDD_IO

LIN5_INH 14

LIN4_INH 14

LIN4_RXD 5,17

LIN4_TXD 5,17

LIN5_RXD 5,17

LIN5_TXD 5,17

LIN4_SLP5,17

LIN5_SLP

5,17

LIN4_WAKE

5,17

LIN5_WAKE5,17

SCH Title :

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Date:

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12 18

Thursday, May 24, 2018

LIN INTERFACE_4 TO 5

BALA K SPPD

SCH Title :

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Date:

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B

12 18

Thursday, May 24, 2018

LIN INTERFACE_4 TO 5

BALA K SPPD

SCH Title :

Size

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Date:

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of

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Drawn By

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TRAVEO II BASE BOARD

B

12 18

Thursday, May 24, 2018

LIN INTERFACE_4 TO 5

BALA K SPPD

R57 0E

C26 1000pF

R59

4.7K_1%

R4

0E

D10

1N4148W-7-F

21

J23

HDR_1X2

1 2

J27 HDR_1X2

1

2

D9

1N4002-T

21

J21

HDR_1X3

1 2 3

J18 HDR_1X2

1

2

U5

TJA1021T/20/C

SLP_N

2

WAKE_N

3

GND

5

LIN

6

VBAT

7

INH

8

TXD

4

RXD

1

J20 HDR_1X2

1

2

R62

0E

C31 220pF

J24 HDR_1X2

1

2

J15

HDR_1X3

1 2 3

J26 HDR_1X2

1

2

D7

1N4002-T

2

1

J17 HDR_1X2

1

2

J22 HDR_1X2

1

2

C30 1000pF

R58

4.7K_1%

C29

0.1uF

J25 HDR_1X2

1

2

R65

4.7K_1%

C24

0.1uF

P3B

CON_DSUB_9_MM

B1

B6

B2

B7

B3

B8

B4

B9

B5

SH3

SH4

R61

1K

J19 HDR_1X2

1

2

U6

TJA1021T/20/C

SLP_N

2

WAKE_N

3

GND

5

LIN

6

VBAT

7

INH

8

TXD

4

RXD

1

+

C28 22uF_20V

R1 0E

J16

HDR_1X2

1 2

R64

4.7K_1%

P3A

CON_DSUB_9_MM

A1

A6

A2

A7

A3

A8

A4

A9

A5

SH1

SH2

+

C25 22uF_20V

J10 HDR_1X2

1

2

R66 1K R63

4.7K_1%

D8

1N4148W-7-F

21

R60

4.7K_1%

C27 220pF

Schematics of Base Board

CYTVII-B-H-8M-320-CPU Evaluation Board User Guide, Document Number: 002-26716 Rev. *A 95

Figure C-11. FlexRay-01 & Reset

5

4

3

2

1

D D

C C

B B

A A

Default 1-2

Place C67, C68, C69 &C70 close to pin

FLEXRAY INTERFACE -01

RESET

FRA_EN_W

FRA_STBN_W

FRA_BGE

FRA_TXD_W

FRA_TXEN_W

FRA_RXD_W

FRA_BP FRA_BM

BB_RST_NP

FRA_EN_W

FRA_WAKE_N

FRA_BP_W FRA_BM_W

FRA_INH_W

FRA_ERRN_W

FRA_WAKE

VDD_IO

VBAT

VDD_IO

VBAT

VDD_IO

FRA_STBN

5

FRA_TXD

5

FRA_TXEN5

FRA_RXD5

FRA_EN5

FRA_INH 14

FRA_ERRN 5

FRA_WAKE5

SCH Title :

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Date:

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of

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Thursday, May 24, 2018

FLEXRAY-01 & RESET

BALA K SPPD

SCH Title :

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A

TRAVEO II BASE BOARD

B

13 18

Thursday, May 24, 2018

FLEXRAY-01 & RESET

BALA K SPPD

SCH Title :

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Date:

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of

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A

TRAVEO II BASE BOARD

B

13 18

Thursday, May 24, 2018

FLEXRAY-01 & RESET

BALA K SPPD

R50

0E

R46

0E

R47 0E

P2A

CON_DSUB_9_MM

A1

A6

A2

A7

A3

A8

A4

A9

A5

SH1

SH2

SW6

7914J-1-000E

1 3

2 4

R13 10K

R45 0E

R41 10K

R39 10K

C15

0.1uF

C14

0.1uF

J7

HDR_1X3

1

2

3

C22

4.7uF

C7

0.1uF

R25 0E

R48

0E

R28 1M

J64

HDR_1X2

1

2

R32 10K

U3

TJA1081TS

INH

1

EN

2

VIO

3

TXD

4

TXEN

5

RXD

6

BGE

7

STBN

8

RXEN

9

ERRN

10

VBAT

11

WAKE

12

GND

13

BM

14

BP

15

VCC

16

R34

0E

C21

0.1uF

L2

4000E

1

3

2

4

R49

0E

L4 180nH

R23 0E

DNI

C12

4.7uF

R36 10K

R30 100E

U1

LM3724IM5-4.63/NOPB

GND1GND

2

RESET

3

MR

4

VCC

5

Schematics of Base Board

CYTVII-B-H-8M-320-CPU Evaluation Board User Guide, Document Number: 002-26716 Rev. *A 96

Schematics of Base Board

Figure C-12. FlexRay-02 & INH

5

FLEXRAY INTERFACE-02

VDD_IO

D D

16

FRB_BGE

4 6

5 9

7

8

12

2

U4

TXD RXD

TXEN RXEN

BGE

STBN

WAKE

EN

TJA1081TS

R53

FRB_TXD5

R55 0E

FRB_RXD5

R54

FRB_TXEN5

FRB_EN

VDD_IO

R40 10K

R35 10K

R38 10K

R31 10K

R56

R26

R51 0E

FRB_STBN5

FRB_WAKE

5

C C

B B

FRB_TXD_W FRB_ERRN_W

0E

FRB_RXD_W

FRB_TXEN_W

0E

FRB_STBN_W

0E

FRB_WAKE_N

0E

FRB_EN_W

FRB_STBN_W

FRB_BGE

FRB_WAKE

4

VBAT

Place C72, C73, C74 & C75 close to pin

11

3

VCC

13

10

ERRN

VIO

1

VBAT

INH

15

BP

14

BM

GND

FRB_INH_W

FRB_BP_W FRB_BM_W

VDD_IO

R33

R52

C23

4.7uF

0E

C18

0.1uF

FRB_ERRN 5

FRB_INH 14

VBAT

C13

4.7uF

3

DNI

R22

0E

L1

1

2

4000E

C19

0.1uF

4

3

HDR_1X3

J8

FRB_BP FRB_BM

3 2 1

Default 1-2

CON_DSUB_9_MM

L3 180nH

C20

0.1uF

B5

SH4 B9 B4 B8 B3 B7 B2 B6 B1

SH3

P2B

R29 100E

R27 1M

2

SUPPLY_INH

LIN0_INH10

LIN1_INH

10

LIN2_INH11

LIN3_INH11

LIN4_INH12

LIN5_INH12

FRA_INH

13

FRB_INH14

CAN6_INH

8

CAN7_INH

8

CAN8_INH

9

CAN9_INH9

SUPPLY_INH_W

2

1

D17 1N4148W-7-F

2

1

1N4148W-7-F

D15

2 1

D20 1N4148W-7-F

2 1

D12 1N4148W-7-F

2 1

1N4148W-7-F

D11

2 1

D13 1N4148W-7-F

2 1

D19 1N4148W-7-F

2 1

1N4148W-7-F

D18

2 1

D4 1N4148W-7-F

2 1

1N4148W-7-F

D1

2 1

D2 1N4148W-7-F

2 1

D3 1N4148W-7-F

VDD_IO

R76 20K

R20

4.7K_1%

DNI

1

J73 HDR_1X2

2

1

Default Closed

SUPPLY_INH 5,17

CYPRESS SEMICONDUCTOR

CYPRESS SEMICONDUCTOR 198 CHAMPION COURT

198 CHAMPION COURT

198 CHAMPION COURT SAN JOSE, CA 95134

SAN JOSE, CA 95134

SAN JOSE, CA 95134 (408) 943-2600

(408) 943-2600

A A

5

4

3

2

SCH Title :

TRAVEO II BASE BOARD

FLEXRAY-02 & INH

Page Title :

Size

Document Number

B

5869234

Date:

Thursday, May 24, 2018

(408) 943-2600

Drawn By

BALA K SPPD

Sheet

1

Approved By

of

14 18

of

14 18

of

14 18

Rev

A

CYTVII-B-H-8M-320-CPU Evaluation Board User Guide, Document Number: 002-26716 Rev. *A 97

Figure C-13. CXPI, EEPROM & POT

5

4

3

2

1

D D

C C

B B

A A

Default Closed

Default closed

CXPI_INTERFACE

Default Closed

EEPROM INTERFACE

Default closed

POTENTIOMETER

Default Open

Default Closed

CXPI_RXD_W

CXPI_TXD_W

CXPI_CLK_W

CXPI_NSLP_W

CXPI_SELMS_W

CXPI_CLK_W

CXPI_NSLP_W

CXPI_SELMS_W

SPI0_CLK_W

SPI0_MOSI_W

SPI0_WP_n

SPI0_HOLD_n

SPI0_MISO_W

SPI0_SS_n_W

SPI0_WP_n

SPI0_HOLD_n

SPI0_SS_n_W

CXPI_BUS

VDD_IO

ANALOG_VCC

VDD_IO

ANALOG_VCC

VDD_IO

CXPI_VS

VBAT

VDD_IO

CXPI_TXD5,17

CXPI_RXD5,17

CXPI_CLK 5,18

CXPI_NSLP 5,17

CXPI_SELMS 5,17

SPI0_MOSI5,18

SPI0_CLK4,17

SPI0_MISO 5,18

SPI0_SS4,17

BB_ADC_POT

5,18

SPI0_HOLD5,18

SPI0_WP5,17

SCH Title :

Size

Document Number

Rev

Date:

Sheet

of

Page Title :

Drawn By

CYPRESS SEMICONDUCTOR 198 CHAMPION COURT SAN JOSE, CA 95134 (408) 943-2600

Approved By

5869234

A

TRAVEO II BASE BOARD

B

15 18

Thursday, May 24, 2018

CXPI, EEPROM & POT

BALA K SPPD

SCH Title :

Size

Document Number

Rev

Date:

Sheet

of

Page Title :

Drawn By

CYPRESS SEMICONDUCTOR 198 CHAMPION COURT SAN JOSE, CA 95134 (408) 943-2600

Approved By

5869234

A

TRAVEO II BASE BOARD

B

15 18

Thursday, May 24, 2018

CXPI, EEPROM & POT

BALA K SPPD

SCH Title :

Size

Document Number

Rev

Date:

Sheet

of

Page Title :

Drawn By

CYPRESS SEMICONDUCTOR 198 CHAMPION COURT SAN JOSE, CA 95134 (408) 943-2600

Approved By

5869234

A

TRAVEO II BASE BOARD

B

15 18

Thursday, May 24, 2018

CXPI, EEPROM & POT

BALA K SPPD

J12

HDR_1X2

1 2

J45 HDR_1X2

1

2

C61

0.1uF

J47 HDR_1X2

1

2

R43

4.7K_1%

C41

0.1uF

J50 HDR_1X2

1

2

J48 HDR_1X2

1

2

+

C11 22uF_20V

J11 HDR_1X2

1

2

R80 10K

U9

25LC320A

CS

1

SO

2

WP

3

VSS

4

SI

5

SCK

6

HOLD

7

VCC

8

R82 10K

R115 1K

5% 0402

R24 1K

C65 33pF

R79 10K

DNI

R44 4.7K_1%

J14 HDR_1X2

1

2

C60

0.1uF

J13

HDR_1X2

1 2

R78 10K

DNI

J89 HDR_1X2

1

2

U2

S6BT112A01

RXD

1

NSLP

2

CLK

3

TXD

4

GND

5

BUS

6

BAT

7

SELMS

8

POT1 PTV09A-4015U-B103

1 3

2

SH1

SH2

D5

1N4002-T

21

J6 HDR_1X2

1

2

FL5

600E

1 2

R37

4.7K_1%

C64

0.1uF

R42

4.7K_1%

C16

0.1uF

J9

HDR_1X2

1 2

J49 HDR_1X2

1

2

D6 1N4148W-7-F

21

C17 220pF

R81 10K

C40

10uF

P1

CON_DSUB_9_M

9

8

7

6

5

4

3

2

1

10

11

J46 HDR_1X2

1

2

Schematics of Base Board

CYTVII-B-H-8M-320-CPU Evaluation Board User Guide, Document Number: 002-26716 Rev. *A 98

Figure C-14. User_Led & Pushbutton

5

Schematics of Base Board

4

3

2

1

USER_LED INTERFACE

BB_USER_LED0_W

BB_USER_LED0

4,18

BB_USER_LED1

5,18

D D

BB_USER_LED25,18

BB_USER_LED35,18

BB_USER_LED85,17

BB_USER_LED95,17

R16 0E

R17

R18

R19 0E

R8

R9 0E

BB_USER_LED1_W

0E

BB_USER_LED2_W

0E

BB_USER_LED3_W

BB_USER_LED8_W

0E

BB_USER_LED9_W

2 1

LD9

LD10

LD11

LD12

LD3

LD4 LTST-C150GKT

2 1

2

2 1

2

2 1

LTST-C150GKT

1

LTST-C150GKT

1

LTST-C150GKT

USER_BUTTON INTERFACE

C C

J102

Default Closed

BB_USER_BUTTON_15,17

5,17

BB_USER_BUTTON_2 BB_USER_BUTTON_35,17 BB_USER_BUTTON_44,17 BB_USER_BUTTON_55,17

B B

A A

5

1 3 5 7 9

HDR_2X5

2 4 6 8 10

BB_USER_BUTTON_1_W BB_USER_BUTTON_2_W BB_USER_BUTTON_3_W BB_USER_BUTTON_4_W BB_USER_BUTTON_5_W

4

NOTE: 5-RED & 5-GREEN LED COLOR

RA3

1K

1

8

2

7

3

6

45

RA1

1K

1

8

2

7

3

6

4

5

C76

0.1uF

C75

0.1uF

123

VDD_IO

678

5,18

4 5

RA4 10K

BB_USER_LED4

BB_USER_LED5

BB_USER_LED6

BB_USER_LED7

C74

0.1uF

3

C73

0.1uF

R10

R12

R14

R15

BB_USER_LED4_W

0E

BB_USER_LED5_W

0E

BB_USER_LED6_W

0E

BB_USER_LED7_W

0E

R123 10K

C72

0.1uF

2

LD5 LTST-C150GKT

2

LD6

2 1

LD7

2

LD8

16

RA5 100E

1 2

15

3

14

4

13

5

12 11

6

10

7 8

9

2

1

LTST-C150GKT

1

LTST-C150GKT

SCH Title :

Page Title :

Size

B

Date:

RA2 1K

1

8

2

7 6

3

5

4

SW1

13

4

2

7914J-1-000E

SW2

13

4

2

7914J-1-000E

SW3

3

1

24

7914J-1-000E

SW4

3

1

4

2

7914J-1-000E

SW5

13

4

2

7914J-1-000E

CYPRESS SEMICONDUCTOR

CYPRESS SEMICONDUCTOR 198 CHAMPION COURT

198 CHAMPION COURT

198 CHAMPION COURT SAN JOSE, CA 95134

SAN JOSE, CA 95134

SAN JOSE, CA 95134 (408) 943-2600

(408) 943-2600

TRAVEO II BASE BOARD

USER_LED & PUSHBUTTON

Document Number

5869234

Thursday, May 24, 2018

Drawn By

BALA K SPPD

Sheet

1

Approved By

16 18

Rev

A

of

CYTVII-B-H-8M-320-CPU Evaluation Board User Guide, Document Number: 002-26716 Rev. *A 99

infineon CYTVII-B-H-8M-320-CPU User Manual

Specifications and Main Features

Frequently Asked Questions

User Manual

Contents

Safety Information

Regulatory Compliance

General Safety Instructions

ESD Protection

Handling Boards

1. Introduction

1.1 Precautions and Warnings

2. Overview

2.1 Functional Overview

2.1.1 Block Diagram

2.1.2 Through-Hole Test Points

2.1.3 USB Connector

2.1.4 Ethernet Connector (Automotive Ethernet)

2.1.5 Ethernet Connector (Gigabit Ethernet)

2.1.6 On-board SMIF Devices

2.1.7 SD Card Connector

2.1.8 Audio Connector

3. Operation

4. Connections and Settings

4.1 Evaluation Board Connections

4.1.1 Base Board Connections

4.1.2 CPU Board Connections

4.1.3 Reset Switch

4.1.4 User Switch

4.1.5 User LED

4.2 Power Supply Settings

4.3 External Power Supply Control Signals Settings

5. Power Management IC (PMIC)

5.1 Power Management IC (PMIC) Module

5.1.1 PMIC Module - CYTVII-PMIC8M

5.1.2 Input / Output Pin Descriptions

A. Schematics of CPU Board

B. Component Assembly on CPU Board

C. Schematics of Base Board