Infineon CIPOS IFCMxxU65 Series, CIPOS IFCM20U65GD, CIPOS IFCM30U65GD Application Note
AN2016-19 Application Note Please read the Important Notice and Warnings at the end of this document <Revision 2.0>
www.infineon.com <2018-02-06>
AN2016-19 Application Note
Control Integrated POwer System (CIPOS™)
3-Phase Interleaved PFC IPM (IFCMxxU65yz) Reference Board
About this document
Scope and Purpose
The scope of this application note is to describe the product reference board of the CIPOS™ Mini 3-phase
interleaved PFC IPM and the basic requirements for operating the product in a recommended mode.
Environmental conditions were considered in the design of the reference board. The design was tested as
described in this document but not qualified regarding safety requirements or manufacturing and operation
over the whole operating temperature range or lifetime. The boards provided by Infineon are subject to
functional testing only.
Reference boards are not subject to the same procedures as regular products regarding Returned Material
Analysis (RMA), Process Change notification (PCN) and Product Discontinuation (PD). Reference boards are
intended to be used under laboratory conditions by specialists only.
Intended Audience
Power electronics engineers who want to evaluate the CIPOS™ Mini 3-phase interleaved PFC IPM.
Table of Contents
1 Introduction .................................................................................................................. 3
2 Schematic ..................................................................................................................... 4
3 External Connection....................................................................................................... 5
3.1 Signal Connector ..................................................................................................................................... 5
3.2 Current Sensing Connector ..................................................................................................................... 5
3.3 ITRIP Connector....................................................................................................................................... 5
3.4 Power Terminals ..................................................................................................................................... 5
4 Key Parameters Setting .................................................................................................. 6
4.1 Circuit of Input Signals (LINx) ................................................................................................................. 6
4.2 Over Current Protection .......................................................................................................................... 6
4.2.1 Current Sensing Resistor Selection ................................................................................................... 7
4.2.2 Delay Time .......................................................................................................................................... 8
4.3 Temperature Monitor and Thermal Protection ..................................................................................... 9
5 Boost PFC Circuit Setting ............................................................................................... 11
5.1 Target Specification .............................................................................................................................. 11
5.2 Boost Inductor ....................................................................................................................................... 11
5.3 Output Capacitor ................................................................................................................................... 12
6 Part List ....................................................................................................................... 13
7 PCB Design Guide .......................................................................................................... 14
7.1 Layout of Reference Board.................................................................................................................... 14
8 Peripheral Components Connection................................................................................ 16
9 Evaluation Example of Reference Board .......................................................................... 17
9.1 Evaluation Results ................................................................................................................................. 17
AN2016-19 Application Note 2 <Revision 2.0>
<2018-02-06>
Control Integrated POwer System (CIPOS™)
3-Phase Interleaved PFC IPM (IFCMxxU65yz) Reference Board
Table of Contents
10 Reference .................................................................................................................... 18
AN2016-19 Application Note 3 <Revision 2.0>
<2018-02-06>
Introduction
Control Integrated POwer System (CIPOS™)
3-Phase Interleaved PFC IPM (IFCMxxU65yz) Reference Board
1 Introduction
This reference board is composed of IFCM20U65GD, minimum peripheral components and three current
sensing resistors. It is designed for customers to evaluate the performance of the CIPOS™ Mini 3-phase
interleaved PFC IPM with simple connections of control signals and power wires. Figure 1 shows the external
view of the reference board.
This application note also describes how to design the key parameters and PCB layout.
Top view Bottom view
Figure 1 Reference board pictures
1
2
3
4
5 6 7 8
9
10
11
12
13
14
15
16
17
18
192021
22
23
24
25
26
27
28
VDD
VFO
ITRIP
LIN(X)
LIN(Y)
LIN(Z)
VSS
LO2
LO1
Bridge Diode
CIPOS
TM
Power
Connector
Power
Connectors
Signal connectors to controller
Reference Board
AC
SMPS
Controller
Thermistor
(Optional)
Inverter
Power
Connector
Filters & Itrip, Fo & temperature
monitor circuits
Figure 2 Application example
AN2016-19 Application Note 4 <Revision 2.0>
<2018-02-06>
Schematic
Control Integrated POwer System (CIPOS™)
3-Phase Interleaved PFC IPM (IFCMxxU65yz) Reference Board
2 Schematic
Figure 3 shows a circuitry of the reference board.
The reference board consists of interface circuit, snubber capacitor, Over Current (OC) protection circuit, fault
output circuit, current sensing resistors and passive parts etc.
Figure 3 Circuit of the reference board
Note: The “VDD5V” on the CN1 Connector 11 pin 9 denotes the control signal supply voltage such as 5V or 3.3V
AN2016-19 Application Note 5 <Revision 2.0>
<2018-02-06>
External Connection
Control Integrated POwer System (CIPOS™)
3-Phase Interleaved PFC IPM (IFCMxxU65yz) Reference Board
3 External Connection
3.1 Signal Connector
Table 1 Pin description of the signal connector (CN1, 11-pin, 2.5mm pin pitch)
Pin No.
Name
Description
1 ~ 3
NC
No connection
4
LIN(X)
Control signal input for phase X IGBT
5
LIN(Y)
Control signal input for phase Y IGBT
6
LIN(Z)
Control signal input for phase Z IGBT
7
VFO
Fault output signal
8
NTC
Temperature monitor output signal
9
VDD5V
External 5V or 3.3V supply for control signal
10
VDD15V
External 15V supply for module power
11
GND
Ground
3.2 Current Sensing Connector
Table 2 Pin description of the current sensing connector (CN2, 6-pin, 2.5mm pin pitch)
Pin No.
Name
Description
1
CS3
Emitter of phase Z IGBT
2
CS2
Emitter of phase Y IGBT
3
CS1
Emitter of phase X IGBT
4 ~ 6
GND
Ground
3.3 ITRIP Connector
Table 3 Pin description of the ITRIP connector (CN3, 3-pin, 2.5mm pin pitch)
Pin No.
Name
Description
1
N3
Current sensing signal of phase X
2
N2
Current sensing signal of phase Y
3
N1
Current sensing signal of phase Z
3.4 Power Terminals
Table 4 Pin description of power terminals
Terminal No.
Name
Desctiption
P P Cathode of PFC diode
X X Collector of phase X IGBT
Y Y Collector of phase Y IGBT
Z Z Collector of phase Z IGBT
N1, N2
GND
Ground
AN2016-19 Application Note 6 <Revision 2.0>
<2018-02-06>
Key Parameters Setting
Control Integrated POwer System (CIPOS™)
3-Phase Interleaved PFC IPM (IFCMxxU65yz) Reference Board
4 Key Parameters Setting
4.1 Circuit of Input Signals (LINx)
The input signals are compatible with either TTL or CMOS levels. The logic level can go down to 3.3V. The
maximum input voltage of the input signal pin is clamped to 10.5V by the internal Zener diode. However the
recommended voltage range of input voltage is up to 5V. The input signals LINx are active high.
These pins have an internal pull-down structure with a pull-down resistor, which is nominal 5kΩ. The input
noise filter inside the CIPOS™ Mini interleaved PFC IPM suppresses short pulses and prevents a false IGBT
driving from an unintentional operation. The input noise filter time (t
FLIN
) is typically 270ns. This means that the
input signal must stay on more than 270ns so that the driver IC detects the normal PWM input for a correct IGBT
driving. CIPOS™ Mini interleaved PFC IPM can be connected directly to the controller without an external input
RC filter due to the internal pull down resistor and input noise filter, as shown in Figure 4.
Input
Noise
Filter
LINx
Controller
(MCU or DSP)
t
FILIN
=270ns
Vz=10.5V
5kΩ
Figure 4 Internal pull-down resistor and input noise filter on input signal pin
4.2 Over Current Protection
Over Current (OC) protection level is decided by ITRIP positive going threshold voltage (V
IT,TH+
) and current
sensing resistance. When the ITRIP voltage exceeds V
IT,TH+
, the module turns off all 3 IGBTs and the fault flag is
activated during fault-output duration time, typically 65µs.
Low Side IGBT
Collector Current
Sensing Voltage
of the shunt resistor
Fault Output Signal
OC Reference Voltage
RC circuit time
constant delay
OC
Typ. 65s Typ. 65s
t
ITRIP
LINx
LOx
t
ITRIP
OC
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