INFINEON C868 User Manual

Data Sheet, V 1.0, May 2003

C868

8-Bit Single-Chip Microcontroller

Microcontrollers

Never stop thinking.

Edition 2003-05
Published by Infineon Technologies AG,

St.-Martin-Strasse 53,
D-81541 München, Germany

© Infineon Technologies AG 2003.

All Rights Reserved.

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Terms of delivery and rights to technical change reserved.
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Data Sheet, V 1.0, May 2003

C868

8-Bit Single-Chip Microcontroller

Microcontrollers

Never stop thinking.

C868
Revision History: 2003-05 V 1.0

Previous Version: ­Page Subjects (major changes since last revision)

Current data updated
Description of I2C included

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C8688-Bit Single-Chip Microcontroller

C800 Family

C868

Advance Information

• C800 core :
–Fully compatible to standard 8051 microcontroller
–Superset of the 8051 architecture with 8 datapointers

• 40 MHz internal CPU clock
–external clock of 6.67 - 10.67 MHz at 50% duty cycle
–300 ns instruction cycle ti me (@37.5 MHz CPU cloc k)

• 8 Kbyte on-chip Program ROM for C868-1R and 8 KByte on-chip Program RAM for
C868-1S

• In-system programming support for programming the XRAM(C868-1R) or XRAM/
Program RAM(C868-1S)
–This feature is realized through 4KB Boot ROM

• 256 byte on-chip RAM

• 256 byte on-chip XRAM

(further features are on the next page)

RAM

256 × 8

XRAM

256 × 8

ROM/RAM

8K × 8

Boot ROM

4K x 8

Timer 0
Timer 1

CPU

8 datapointers

Watchdog Timer

8-bit

UART

Timer 2

16-bit

Capture/
Compare

Unit

16-bit Compare

Unit

8-Bit ADC

Port 1

Port 3

I/O
5-bit
Input

3-bit

I/O
8-bit

Analog/

Digital

Input

Figure 1 C868 Functional Units

Data Sheet 5 V 1.0, 2003-05

C868

• One 8-bit and one 5 bits general purpose push-pull I/O ports
– Enhanced sink current o f 10 mA on Port 1/3 (total max current of 43 mA @ 100

• Three 16-bit timers/counters
–Timer 0 / 1 (C501 compatible)
–Timer 2 (up/down counter feature)
–Timer 1 or 2 can be used for serial baudrate generator

• Capture/compare unit for PWM signal generation
–3-channel, 16-bit capture/compare unit
–1-channel, 16-bit compare unit

• Full duplex serial interface (UART)

• 5 channel 8-bit A/D Converter

– Start of conversion can be synchronized to capture/compare timer 12/13.

• 13 interrupt vectors with four priority levels

• Programmable 16-bit Watchdog Timer

• Brown out detection

• Power Saving Modes
–Slow-down mode
–Idle mode (can be combined with slow-down mode)
–Power-down mode with wake up capability through INT0

or RxD pins.

• Single power supply of 3.3V, internal voltage regulator for core voltage of 2.5V.

• P-DSO-28-1, P-TSSOP-38-1 packages

• Temperature ranges:

SAF-C868-1RR BA, SAF-C868-1SR BA, SAF-C868-1RG BA, SAF-C868-1SG BA,
SAF-C868A-1RR BA, SAF-C868A-1SR BA, SAF-C868A-1RG BA, SAF-C868A-1SG
BA, SAF-C868P-1SR BA, SAF-C868P-1SG BA T

= – 40 to 85 oC

A

SAK-C868-1RR BA, SAK-C868-1SR BA, SAK-C868-1RG BA, SAK-C868-1SG BA,
SAK-C868A-1RR BA, SAK-C868A-1SR BA, SAK-C868A-1RG BA, SAK-C868A-1SG
BA, SAK-C868P-1SR BA, SAK-C868P-1SG BA T

= – 40 to 125 oC

A

o

C)

Data Sheet 6 V 1.0, 2003-05

C868

V

DDPVSSP

V

AREF

V

AGND

Port 1
5-bit Digital I/O

3-bit Digial Input
Port 3

RESET

ALE/BSL

CTRAP

TxD
RxD

C868

8-bit Digital I/O

5 ADC channels

4 External
Interrupts

V

V

DDC

SSC

Figure 2 Logic Symbol

Data Sheet 7 V 1.0, 2003-05

C868

P1.4/RxD

P1.3/INT3

P1.1/EXF2

P1.0/TxD

P1.5/CCPOS0/T2/INT0

P1.6/CCPOS1/T2EX/INT1

P1.7/CCPOS2/INT2/AN2

V

/AN0

/AN1

V

AGND

V

P1.2

NC

NC
NC

DDP

V

SSP

AREF

AN3

AN4

NC
NC

1

2
3

4

5

6

7

8
9

10

11
12
13
14

15
16
17
18
19

C868

RESET

38
37

P3.7/CC60

36

P3.6/COUT60

35

NC

34

ALE/BSL

33

P3.1/CTRAP

32

P3.0/COUT63

31

P3.4/COUT61

30

XTAL2

29

XTAL1

28

V

27

V

26

P3.3/CC62

25

P3.2/COUT62

24

P3.5/CC61

23

NC

22

NC

21

NC

20

NC

DDC

SSC

Figure 3 C868 Pin Configuration P-TSSOP-38 Package (top view)

P3.4/COUT61

P3.0/COUT63

P3.1/CTRAP

ALE/BSL

P3.6/COUT60

P3.7/CC60

RESET

P1.4/RxD

P1.3/INT3

P1.2

P1.1/EXF2

P1.0/TxD

V

DDP

V

SSP

1
2
3

4
5

6
7
8
9

10
11
12

13
14

C868

XTAL2

28

27

XTAL1

26

V

DDC

25

V

SSC

P3.3/CC62

24

P3.2/COUT62

23

P3.5/CC61

22

21

AN4

20

AN3

19

V

AREF

18

V

AGND

17

P1.7/CCPOS2/INT2/AN2

16

P1.6/CCPOS1/T2EX/INT1/AN1

15

P1.5/CCPOS0/T2/INT0

/AN0

Figure 4 C868 Pin Configuration P-DSO-28 Package (top view)

Data Sheet 8 V 1.0, 2003-05

Table 1 Pin Definitions and Functions
Symbol Pin Numbers I/O*) Function

P1.0–
P1.4
P1.5­P1.7

P­DSO­28

12-8
15-17

P­TSSOP­38

6,4-1
11-13

I/OIPort 1

is a combination of 5 bits of pus h-pull bi directiona l I/
O ports and 3 bits of input ports.
As alternate digital functions, port 1 contains the
interrupt 3, timer 2 overflow flag, rece ive data input
and transmit data output of serial interface. The
alternate functions are assigned to the pins of port
1 as follows:

12
11
10
9
8

6
4
3
2
1

P1.0/TxD Transmit data of serial interface
P1.1/EXF2 Timer 2 overflow flag
P1.2
P1.3/INT3 Interrupt 3
P1.4/RxD Receive data of serial interface, Use as
wakeup source from powerdown if bit WS of
PMCON0 is set.

C868

The input ports are a ls o i nte rrupt po rts , i npu t to th e
timer2, CCU6 modules and ADC:

15 11 I P1.5/Input to Counter 2/External Interrupt 0 Input/

Analog Input Channel 0
External interrupt input or Hall input signal , counte r
2 input or input channel 0 to the ADC unit. Use as
wakeup source from powerdown if bit WS of
PMCON0 is cleared.

16 12 I P1.6/Timer 2 Trigger/External Interrupt 1 Input/

Analog Input Channel 1
External interrupt input or Hall input signal, input
channel 1 to the ADC unit, trigger to Timer 2.

17 13 I P1.7/External Interrupt 2 Input/

Analog Input Channel 2
External interrupt input or Hall input signal and inpu t
channel 2 to the ADC unit.

*)I=Input
O=Output

Data Sheet 9 V 1.0, 2003-05

Table 1 Pin Definitions and Functions
Symbol Pin Numbers I/O*) Function

P3.0–
P3.7

P­DSO­28

2,3,23,
24,1,
22,5,6

P­TSSOP­38

32,33,25,
26,31,24,
36,37

I/O Port 3

is an 8-bit push-pull bidirec tio nal I/O po rt. Thi s po rt
also serves as alternate functions for the CCU6
functions. The functions are assigned to the pins of
port 3 as follows :

C868

V

AREF

V

AGND

2
3
23
24
1
22
5
6

19 15 – Reference voltage for the A/D converter.
18 14 – Reference ground for the A/D converter.

32
33
25
26
31
24
36
37

P3.0/COUT63 16 bit compare channe l outp ut
P3.1/CTRAP CCU trap input
P3.2/COUT62 Output of capture/compare ch 2
P3.3/CC62 Input/output of capture/compare ch 2
P3.4/COUT61 Output of capture/compare ch 1
P3.5/CC61 I nput/outpu t of capture/compare ch 1
P3.6/COUT60 Output of capture/compare ch 0
P3.7/CC60 Input/output of capture/compare ch 0

AN4 21 17 I Analog Input Channel 4

is input channel 4 to the ADC unit.

AN3 20 16 I Analog Input Channel 3

is input channel 3 to the ADC unit.

RESET

738 IRESET

A low level on this pin for two machine cycle while
the oscillator is running resets the device.

ALE/BSL 4 34 I/O Address Latch Enable/Bootstrap Mode

A low level on th is pin during res et allows the d evice
to go into the bootstrap mode. After reset, this pin
will output the address latch enable signal. The
ALE can be disabled by bit EALE in SFR

SYSCON0.
V
V

SSP
DDP

14 10 – IO Ground (0V)
13 9 – IO Power Supply (+3.3V)

*)I=Input
O=Output

Data Sheet 10 V 1.0, 2003-05

Table 1 Pin Definitions and Functions
Symbol Pin Numbers I/O*) Function

V
V

SSC
DDC

P­DSO­28

25 27 – Core Ground (0V)
26 28 O Core Internal Reference (+2.5V)

P­TSSOP­38

Connect 2*68 - 470nF ceramic capacitor across

this pin and core ground.
NC – 5,7,8,18,

– Not connected

19,20,21,
22,23,35

XTAL1 27 29 I XTAL1

Output of the inverting oscillator amplifier.
XTAL2 28 30 O XTAL2

Input to the inverting os cillator amplifier an d input to

the internal clock generation circuits.

To drive the device from an external clock sourc e,

XTAL2 should be driven, while XTAL1 is left

unconnected.
*)I=Input

O=Output

C868

Data Sheet 11 V 1.0, 2003-05

V

DDC

V

SSC

XTAL1

XTAL2

C868

OSC

PLL

XRAM

256 x 8

RAM

256 x 8

ROM/

RAM

8k x 8

C868

Boot/
Self
Test
ROM
4k x 8

RESET

4 external
interrupts

V

AREF

V

AGND

5-Bit
Analog In

CPU

8 datapointers

Programmable
Watchdog Timer

Timer 0

Timer 1

Timer 2

UART

Capture/Compare

Unit

Interrupt Unit

A/D Converter

8-Bit

Port 1

Port 3

Port 1
5-bit
digital

I/O
and

3-bit
digital
input

Port 3

8-bit

digital

I/O

V

DDP

V

SSP

Figure 5 Block Diagram of the C868

Data Sheet 12 V 1.0, 2003-05

C868

CPU

The C868 is efficient both as a controller and as an arithmeti c processor. It has extens ive
facilities for bi nary and BCD ar ithmetic and e xcels in i ts bit-handli ng capabili ties. Efficie nt
use of program memory results from an instruction set consisting of 44% one-byte, 41%
two-byte, and 15% three-byte instructions. With a 10.67 MHz external crystal (giving a
40MHz CPU clock), 58% of the instructions execute in 300 ns.

PSW
Program Status Word Register [Reset value: 00

D7

H

CY AC F0 RS1 RS0 OV F1 P

rwh rwh rw rw rw rwh rw rwh

D6

H

D5

H

D4

H

D3

H

D2

H

D1

H

Field Bits Typ Description
P 0rwhParity Flag

Set/cleared by hardware after each instruction to
indicate an odd/even number of "one" bits in the
accumulator, i.e. even parity.

F1 1rwGeneral Purpose Flag
OV 2rwhOverflow Flag

Used by arithmetic in structions.

RS0
RS1

3
4

rw Register Bank select control bits

These bits are used to select one of the four register
banks.

Table 2 :

RS1 RS0 Function

0 0 Bank 0 selected, data address 00H-07
0 1 Bank 1 selected, data address 08H-0F
1 0 Bank 2 selected, data address 10H-17
1 1 Bank 3 selected, data address 18H-1F

D0

H

H

H
H
H
H

]

F0 5rwGeneral Purpose Flag
AC 6rwhAuxiliary Carry Flag

Used by instruction s which exec ute BCD operations .

CY 7rwhCarry Flag

Used by arithmetic in structions.

Data Sheet 13 V 1.0, 2003-05

Memory Organization

The C868 CPU manipulates operands in the following five address spaces:

– up to 8 Kbyte of RAM internal program memory : 8K ROM for C868-1R

: 8K RAM for C868-1S

– 4 Kbyte of internal Self test and Boot ROM
– 256 bytes of internal data memory
– 256 bytes of internal XRAM data memory
– 128 byte special function register area

Figure 0-1 illustrates the memory address spaces of the C868.

FFFF

FF00

H

H

indirect

addr.

Internal

RAM

Function

Internal

RAM

Internal
Self Test
and Boot
ROM
(4 KByte)

Internal

1FFF

0000

Internal
XRAM

H

H

direct
addr.

Special

Regs.

7F

00

H

H

C868

FF

H

80

H

"Code Space"

"Data Space"

"Internal Data Space"

Figure 0-1 C868 Memory Map

Data Sheet 14 V 1.0, 2003-05

The various chip modes supported are shown in Figure 6.

Normal

Mode

C868

Bootstrap

Mode

Normal

XRAM

Mode

Bootstrap

XRAM

Hardware
Software

Mode

Figure 6 Entry and exit of Chip Modes

A valid hardware reset would, of course, override any of the above entry or exit
procedures.

Table 0-1 Hardware and Software Selection of Chipmodes
Operating Mode

Hardware Selection Software Selection

(Chipmode)

Normal Mode ALE/BSL pin = high

RESET

rising edge

ALE/BSL = don’t care;
setting bits BSLEN, SWAP = 0,0;
execute unlocking sequence

Normal XRAM Mode Not possible setting bits BSLEN,SWAP = 0,1;

execute unlocking sequence

Bootstrap XRAM Mode Not possible setting bits BSLEN,SWAP = 1,1;

execute unlocking sequence

Bootstrap Mode ALE/BSL pin = low

RESET rising edge

ALE/BSL = don’t care;
setting bits BSLEN, SWAP = 1,0;
execute unlocking sequence

Data Sheet 15 V 1.0, 2003-05

Table 3 Normal Memory Configuration

C868

Chip

Memory Space Memory Boundary

Mode

Normal Code Space ROM/RAM: 0000

Internal Data Space XRAM: FF00H to FFFF

to 1FFF

H

H

Bootstrap Code Space Boot ROM: 0000H to 0FFF

Internal Data Space XRAM: FF00H to FFFF

H

ROM/RAM: 0000H to 1FFF
Normal

XRAM
Bootstrap

XRAM

Code Space XRAM: FF00H to FFFF

H

Data Space ROM/RAM: 0000H to 1FFF
Code Space Boot ROM: 0000H to 0FFF

XRAM: FF00H to FFFF

H

Data Space ROM/RAM: 0000H to 1FFF

H

H

H

H

H

H

Data Sheet 16 V 1.0, 2003-05

C868

Bootstrap loader

The C868, includes a bootstrap mode, which is activated by setting the ALE/BSL pin at
logic low with a pul ld ow n and Tx D p in at logic high with a pu llup at the rising e dg e o f th e

. Or it can be entered by software, that is by setting BSLEN bit and resetting

RESET
SWAP bit in SFR SYSCON1 accompany by an unlock sequence.

In the bootstrap mode , software routi nes of the b ootstrap load er located in th e boot ROM
will be executed. Its pur pos e i s to allow the easy and quick programmin g of the int ernal
SRAM (0000
the MCU is in-circuit. It also provides a way to program SRAM or XRAM through
bootstrapping from an external SPI or I2C EEPROM.

The first action of the bootstrap lo ader is to detect the presence of EEPROM and its type,
SPI or I2C, and check the first byte of the serial EEPROM. If the first byte is 0A5
MCU would enter Phase A to download from the EEPROM. Otherwise, it will enter
Phase B to establish a serial communication with the connected host. Bootstrapping
from the serial EEPROM can also be done in phase B if it is invoked by the host.

Phase B consists of two functional parts that represent two phases:

• Phase I: Establish a serial connection and automatically synchronize to the transfer

speed (baud rate) of the serial communication partner (host).

• Phase II: Perform the serial communication with the host. The host controls the

communication by sending special header information, which select one of the
working modes. These modes are:

to 1FFFH) or XRAM (FF00H to FFFFH) via serial interface (UART) while

H

H

, the

Table 4 Serial Communication Modes of Phase B
Modes Description

0 Transfer a customer program from the host to the SRAM (0000

) or XRAM (FF00H -FFFFH). Then return to the beginning of

1FFF

H

to

H

phase II and wait for the next command from the host.
1 Execute a customer program in the XRAM at start address FF00
2 Execute a customer program in the SRAM at start address 0000

.

H

.

H

3 Transfer a customer program from the SPI EEPROM to the SRAM

(0000H to 1FFFH) or XRAM (FF00H -FFFFH). Then return to the

beginning of phase II and wait for the next command from the host.
4 Transfer a customer program from the I2C EEPROM to the SRAM

(0000

to 1FFFH) or XRAM (FF00H -FFFFH). Then return to the

H

beginning of phase II and wait for the next command from the host.
5-9 reserved

The phases of the bootstrap loader are illustrated in Figure 7.

Data Sheet 17 V 1.0, 2003-05

Phase A

Bootstrap from

serial

EEPROM

EEPROM (first byte)

Yes

Start

Read serial

byte=A5H? No

Init serial interface 0

and synchronize to

the host baud rate

Phase B

Receive header
block from host

C868

Phase B, Phase I

Phase B, Phase II

Activate Mode 4

Load program from

I2C serial EEPROM

to SRAM/XRAM

Activate Mode 3

Activate mode 0

Load custom code

to SRAM/XRAM

Activate Mode 1
Execute custom

program in XRAM

Select working

mode

Activate Mode 2
Execute custom

program in SRAM

Load program from SPI serial

EEPROM to SRAM/XRAM

Figure 7 The phases of the Bootstrap Loader

The serial communication is activated in phase B. Using a full duplex serial cable
(RS232), the MCU must be connected to the serial port of the host computer as shown
in Figure 8.

Serial Cable

PC

full duplex, RS232

C868

Host Computer
Serial Interface

(asynchronous, 8N1)

Serial Interface,
UART Mode 1

(asynchronous, 8N1)

Figure 8 Bootstrap Loader Interface to the PC

Data Sheet 18 V 1.0, 2003-05

C868

VCC VCC

P1.3
P1.1
P1.2

240R

1

/CS

6

SCK

5

SI

2

SO

/HOLD

/WP

VCC

GN

7
3
8
4

D

1

A0

6

A1

5

A2

2

GN
D

VCC

WP

SCL

SDA

7
3
8
4

3K3

P1.1
P1.2

a) SPI EEPRO M connection

b) I2C EEPROM connection

Figure 9 EEPROM connections for a) SPI and b) I2C

Data Sheet 19 V 1.0, 2003-05

C868

Reset and Brownout

The reset input is an active low input. An internal Schmitt trigger is used at the input for
noise rejection. The RESET
only exit from reset condition after the PLL lock had been detected.

During RESET

at transition from low to high, C868 will go into normal mode if ALE/BSL
is high and bootstrap loading mode if ALE/BSL is low. A pullup to V
ground is recommended for pin ALE/BSL. TXD should have a pu llup to V
not be stimulated externally during reset, as a logic low at this pin will cause the chip to
go into test mode if ALE/BSL is low.

Figure 10 shows the possible reset circuits, note that the RESET

internal pullup resistance.

pin must be held low fo r at l east tbd usec . Bu t the CPU will

or pulldown to

DDP

and should

DDP

pin does not have an

a)

V

DDP

C868 BA

RESET

b) c)

C868 BA

&

RESET

V

DDP

C868 BA

RESET

Figure 10 Reset Circuitries

An on-chip analog circuit detects brownout, if the core voltage V
threshold voltage V

THRESHOLD

active for tbd usec then the device will reset. When V
V

THRESHOLD

while RESET is high, the reset is released once PLL is locked for 4096

momentarily while RESET pin is high. If this detect ion is

recovers by exceeding

DDC

dips below the

DDC

clocks. Bit BO in the PMCON0 register is set when brownout detected if brownout
detection was enabled, this bit is cleared by hardware reset RESET and software. All
ports are tristated during brownout.

The V

THRESHOLD

has a nominal value of 1.47V, a minimum value of 1.1V and a

maximum value of 1.8V.

Data Sheet 20 V 1.0, 2003-05

C868

Clock system

The C868 clock system cons ist of the on-chip oscillat or, PLL and m ultipl exer sta ge. The
programmable Slow Down Divider (SDD) divides the PLL output clock frequency by a
factor of 1...32 which is specified via CMCON.REL. The system clock is switched from
the PLL output to the output from the SDD when slowdown mode is selected.

clkin

PLL

clkout

f

PLL

SDD

XTAL1

XTAL2

On-Chip

Osc

f

OSC

Figure 11 Block Diagram of the Clock Generation

MUX

system
clock (

f

SYS

)

Data Sheet 21 V 1.0, 2003-05

The PLL output frequency is determined by:

C868

f

PLL

= f

VCO

15

/ K = × f

K

OSC

The range for the VCO frequency is given by:
100 MHz ≤ f

≤ 160 MHz [2]

VCO

The relationship between the input frequency and VCO frequency is given by:

f

=15× f

VCO

OSC

This gives the range for the input frequency which is given by:

6.67 MHz ≤ f

Table 5 Output Frequencies

K-Factor f

Selected
Factor

2 000
4 010

1)

5
6 100
8 101

1)

9
10 111
16 001

1)

These odd factors should not be used (not tested because off the unsymmetrical duty cycle).

2) Shaded combinations should not be used because they are above the maximum CPU frequency of 40MHz.

KDIV f

100 MHz

50 80 50 linear depending on f
25 40 50
20 32 40

16.67 26.67 50

12.5 20 50

11.11 17.78 44
10 16 50

6.25 10 50

011

110

B

B

B

B

B

B

B

B

≤ 10.67 MHz [4]

OSC

f

Derived from Various Output Factors

PLL

VCO

=

Duty
Cycle [%]

PLL

=

f

VCO

Jitter

160 MHz

at f

=100MHz: +/-300ps

VCO

=160MHz: +/-250ps

at f

VCO

additional jitter for odd Kdiv
factors tbd.

[1]

[3]

VCO

Data Sheet 22 V 1.0, 2003-05

C868

Figure 12 shows the recommended oscillator circuitries for crystal and external clock

operation.

Crystal Oscillator Mode

XTAL2

6.67-10.67
MHz

C = 20 pF ± 10 pF for crystal operation
(incl. StrayCapacitance)

C868

XTAL1

Driving from External Source

External Oscillator

Signal

N.C.

XTAL2

XTAL1

Figure 12 Recommended Oscillator Circuit

In this application the on-chip oscillator is used as a crystal-controlled, positive­reactance oscillator (a more detailed schematic is given in Figure 13). lt is operated in
its fundamental response mode as an inductive reactor in parallel resonance with a
capacitor external to the chip. The crystal specifications and capacitances are non­critical. In this circ uit tbd pF can b e used as single capacitanc e at any freque ncy together
with a good quality crystal. A ceramic resonator can be used in place of the crystal in
cost-critical applications. If a ceramic resonator is used, the two capacitors normally
have different values depending on the oscillator frequency. We recommend consulting
the manufacturer of the ceramic resonator for value specifications of these capacitors.

Data Sheet 23 V 1.0, 2003-05

C868

To internal

timing circuitry

XTAL1

*) Crystal or ceramic resonato r

XTAL2

*)

C

C

1

2

C868

Figure 13 On-Chip Oscillator Circuitry

To drive the C868 with an external clock source, the external clock signal has to be
applied to XTA L2, as show n in Figure 14. XTAL1 has to be left unconnected. A pullup
resistor is s ugges ted ( to incr ease t he nois e marg in), bu t is op tion al if VOH of the drivi ng

V

gate corresponds to the

External
Clock
Signal

specification of XTAL2.

IH2

V

DDC

N.C.

C868

XTAL1

XTAL2

Figure 14 External Clock Source

Data Sheet 24 V 1.0, 2003-05

C868

0.1 Special Function Registers

All registers, except the program counter and the four general purpose register banks,
reside in the special function register area. The special function register area consists
of two portions: the standard special function register area and the mapped special
function register area. For accessing the mapped special function area, bit RMAP in
special function register SYSCON0 must be set. All other special function registers are
located in the standard special function register area which is accessed when RMAP is
cleared (“0“).

SYSCON0
System Control Register 0 [Reset value: XX10XXX1

76543210

--EALE RMAP - - - XMAP0

r r rw rw r r r rw

Field Bits Typ Description

RMAP

- [7:2] r reserved;

The functions of the shaded bits are not described here

4rw

Special Function Register Map Control

RMAP = 0 : The access to the non-mapped (standard)

special function register area is enabled.

RMAP = 1 : The access to the mapped special function

register area is enabled.

returns ’0’ if read; should be written with ’0’;

B

]

As long as bit R MA P is s et , th e mapped special fun cti on reg is ter area can be accessed.
This bit is not cleared automatically by hardware. Thus, when non-mapped/mapped
registers are to be accessed, the bi t RMAP must be cleared/se t respectively by softwa re.

The 109 special function registers (SFR) include pointers and registers that provide an
interface between the CP U and the other on-c hip peri pherals. Al l avail able SFRs whose
address bits 0-2 are 0 (e.g. 80H, 88H, 90H, ..., F0H, F8H ) are bit- ad dressabl e. Tot ally
there are 128 directly addressable bits within the SFR area.

All SFRs are list ed in Table 6 and Table 7.In Table 6 they are organized in groups w hich
refer to the functional blocks of the C868-1R, C868-1S. Table 7 illustrates the contents
(bits) of the SFRs

Data Sheet 25 V 1.0, 2003-05