INFINEON C515C User Manual

Data Sheet, Feb. 2003

C515C

8-Bit Single-Chip Microcontroller

Microcontrollers

Never stop thinking.

Edition 2003-02 Published by Infineon Technologies AG,

St.-Martin-Strasse 53, 81669 München, Germany

Attention please!

The information herein is given to describe certain components and shall not be considered as a guarantee of characteristics.

Terms of delivery and rights to technical change reserved. We hereby disclaim any and all warranties, including but not limited to warranties of non-infringement, regarding

circuits, descriptions and charts stated herein.

Information

For further information on technology, delivery terms and conditions and prices please contact your nearest Infineon Technologies Office in Germany or our Infineon Technologies Representatives worldwide (www.infineon.com).

Warnings

Due to technical requirements components may contain dangerous substances. For information on the types in question please contact your nearest Infineon Technologies Office.

Infineon Technologies Components may only be used in life-support devices or systems with the express written approval of Infineon Technologies, if a failure of such components can reasonably be expected to cause the failure of that life-support device or system, or to affect the safety or effectiveness of that device or system. Life support devices or systems are intended to be implanted in the human body, or to support and/or maintain and sustain and/or protect human life. If they fail, it is reasonable to assume that the health of the user or other persons may be endangered.

Data Sheet, Feb. 2003

C515C

8-Bit Single-Chip Microcontroller

Microcontrollers

Never stop thinking.

C515C Data Sheet

Revision History: 2003-02

Previous Version: 2000-08 Page Subjects (major changes since last revision)

Enhanced Hooks Technology™ is a trademark of Infineon Technologies.

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Any information within this document that you feel is wrong, unclear or missing at all? Your feedback will help us to continuously improve the quality of this document. Please send your proposal (including a reference to this document) to:

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Features

• Full upward compatibility with SAB 80C515A

• On-chip program memory (with optional memory protection) – C515C-8R 64 Kbytes on-chip ROM – C515C-8E 64 Kbytes on-chip OTP – alternatively up to 64 Kbytes external program memory

• 256 bytes on-chip RAM

• 2 Kbytes of on-chip XRAM

• Up to 64 Kbytes external data memory

• Superset of the 8051 architecture with 8 datapointers

• Up to 10 MHz external operating frequency (1 external clock)

• On-chip emulation support logic (Enhanced Hooks Technology)

• Current optimized oscillator circuit and EMI optimized design

µs instruction cycle time at 6 MHz

C515C8-Bit Single-Chip Microcontroller

(further features are on next page)

SSC (SPI)

Interface

Oscillator

Watchdog

Power

Save Modes

Idle/

Power down

Slow down

On-Chip Emulation Support Module

Port 7 Port 6 Port 5 Port 4

I/O I/O I/OAnalog/

Digital

Input

Full-CAN

Controller

10 Bit ADC

(8 inputs)

Timer 2

Capture/Compare Unit

XRAM

2k x 8

CPU

8 Datapointer

Program Memory

C515C-8R : 64k x 8 ROM

C515C-8E : 64k x 8 OTP

RAM

256 x 8

USART

Port 0

Port 1

Bit8

Port 2

Port 3

I/O

MCA03646

Figure 1 C515C Functional Units

Data Sheet 1 2003-02

• Eight ports: 48 + 1 digital I/O lines, 8 analog inputs – Quasi-bidirectional port structure (8051 compatible) – Port 5 selectable for bidirectional port structure (CMOS voltage levels)

• Full-CAN controller on-chip – 256 register/data bytes are located in external data memory area – max. 1 MBaud at 8 - 10 MHz operating frequency

• Three 16-bit timer/counters – Timer 2 can be used for compare/capture functions

• 10-bit A/D converter with multiplexed inputs and built-in self calibration

• Full duplex serial interface with programmable baudrate generator (USART)

• SSC synchronous serial interface (SPI compatible) – Master and slave capable – Programmable clock polarity/clock-edge to data phase relation – LSB/MSB first selectable – 2.5 MHz transfer rate at 10 MHz operating frequency

• Seventeen interrupt vectors, at four priority levels selectable

• Extended watchdog facilities – 15-bit programmable watchdog timer – Oscillator watchdog

• Power saving modes –Slow-down mode – Idle mode (can be combined with slow-down mode) – Software power-down mode with wake-up capability through INT0

or RXDC pin

– Hardware power-down mode

• CPU running condition output pin

• ALE can be switched off

• Multiple separate

DD/VSS

pin pairs

• P-MQFP-80-1 package

• Temperature Ranges: SAB-C515C versions: SAF-C515C versions: SAH-C515C versions:

Note: Versions for extended temperature range -40

= 0 to 70 °C

= -40 to 85 °C

= -40 to 110 °C

°C to 110 °C (SAH-C515C) are

available on request.

C515C

The C515C is an enhanced, upgraded version of the SAB 80C515A 8-bit microcontroller which additionally provides a full CAN interface, a SPI compatible synchronous serial interface, extended power save provisions, additional on-chip RAM, 64K of on-chip program memory, two new external interrupts and RFI related improvements. With a maximum external clock rate of 10 MHz it achieves a 600 ns instruction cycle time (1

µs

at 6 MHz).

Data Sheet 2 2003-02

C515C

The C515C-8R contains a non-volatile 64 Kbytes read-only program memory. The C515C-L is identical to the C515C-8R, except that it lacks the on-chip program memory. The C515C-8E is the OTP version in the C515C microcontroller with an on-chip 64 Kbytes one-time programmable (OTP) program memory. The C515C is mounted in a P-MQFP-80-1 package.

If compared to the C515C-8R and C515C-L, the C515C-8E OTP version additionally provides two features:

• The wake-up from software power down mode can, additionally to the external pin P3.2/INT0 P4.7/RXDC.

• For power consumption reasons the on-chip CAN controller can be switched off.

Table 1 Differences in Internal Program Memory of the C505 MCUs Device Internal Program Memory

wake-up capability, also be triggered alternatively by a second pin

ROM OTP

C515C-LM

––

C515C-8RM 64 Kbytes – C515C-8EM – 64 Kbytes

Note: The term C515C refers to all versions described within this document unless

otherwise noted.

Ordering Information

The ordering code for Infineon Technologies’ microcontrollers provides an exact reference to the required product. This ordering code identifies:

• The derivative itself, i.e. its function set

• The specified temperature rage

• The package and the type of delivery

For the available ordering codes for the C515C please refer to the “Product information Microcontrollers”, which summarizes all available microcontroller variants.

Note: The ordering codes for the Mask-ROM versions are defined for each product after

verification of the respective ROM code.

Data Sheet 3 2003-02

C515C

XTAL1 XTAL2

ALE PSEN EA

RESET PE/SWD HWPD CPUR

SSE1

DDE1

SSE2

DDE2

C515C

AREFAGND

Port 0 8 Bit Digital I/O

Port 1 8 Bit Digital I/O

Port 2 8 Bit Digital I/O

Port 3 8 Bit Digital I/O

Port 4 8 Bit Digital I/O

Port 5 8 Bit Digital I/O

Port 6 8 Bit Analog/ Digital Inputs

Port 7

1 Bit Digital I/O

SS1

DD1

Figure 2 Logic Symbol

SSCLK

DDCLK

SSEXT

DDEXT

MCL02714

Data Sheet 4 2003-02

C515C

DDEXT

P0.7/AD7

P5.7

P0.6/AD6

P0.5/AD5

P0.4/AD4

P0.3/AD3

P0.2/AD2

SSEXT

P0.1/AD1

P0.0/AD0EAALE

PSEN

CPUR

P2.7/A15

P2.6/A14

P2.5/A13

P2.4/A12

P2.3/A11

4142434445464748495051525354555657585960

P5.6 P5.5 P5.4 P5.3 P5.2 P5.1 P5.0

DDE2

HWPD

SSE2

N.C. P4.0/ADST P4.1/SCLK

P4.2/SRI PE/SWD

P4.3/STO

P4.4/SLS

P4.5/INT8

P4.6/TXDC

P4.7/RXDC

62 63 64 65 66 67 68 69 70 71 72 73 74 75 76 77 78 79 80

345

4061 39 38 37 36 35 34 33 32

C515C

31 30 29 28 27 26 25 24 23 22 21

13 14 15

P2.2/A10 P2.1/A9 P2.0/A8 XTAL1 XTAL2

SSE1

SS1

DD1

DDE1

P1.0/INT3/CC0 P1.1/INT4/CC1 P1.2/INT5/CC2 P1.3/INT6/CC3 P1.4/INT2 P1.5/T2EX P1.6/CLKOUT P1.7/T2 P7.0/INT7 P3.7/RD P3.6/WR

N.C.

AREF

RESET

AGND

P6.7/AIN7

P6.5/AIN5

P6.6/AIN6

P6.3/AIN3

P6.4/AIN4

P6.2/AIN2

SSCLK

DDCLK

P6.0/AIN0

P6.1/AIN1

P3.1/TXD

P3.0/RXD

P3.2/INT0

P3.3/INT1

P3.4/T0

P3.5/T1

MCP02715

Figure 3 C515C Pin Configuration P-MQFP-80-1 (top view)

Data Sheet 5 2003-02

Table 2 Pin Definitions and Functions Symbol Pin Number I/O

Function

P-MQFP-80-1

C515C

RESET

1IRESET

A low level on this pin for the duration of two machine cycles while the oscillator is running resets the C515C. A small internal pullup resistor permits power-on reset using only a capacitor connected to

AREF

AGND

3–Reference voltage for the A/D converter 4–Reference ground for the A/D converter

P6.0-P6.7 12-5 I Port 6

is an 8-bit unidirectional input port to the A/D converter. Port pins can be used for digital input, if voltage levels simultaneously meet the specifications high/low input voltages and for the eight multiplexed analog inputs.

P7.0 / INT7

23 I/O Port 7

is an 1-bit quasi-bidirectional I/O port with internal pull-up resistor. When a 1 is written to P7.0 it is pulled high by an internal pull-up resistor, and in that state can be used as input. As input, P7.0 being externally pulled low will source current ( DC characteristics) because of the internal pull-up resistor. If P7.0 is used as interrupt input, its output latch must be programmed to a one (1). The secondary function is assigned to the port 7 pin as follows: P7.0 INT7

, Interrupt 7 input

, in the

Data Sheet 6 2003-02

Table 2 Pin Definitions and Functions (cont’d)

Symbol Pin Number I/O

Function

P-MQFP-80-1

C515C

P3.0-P3.7 15-22

19 20 21

I/O Port 3

is an 8-bit quasi-bidirectional I/O port with internal pullup resistors. Port 3 pins that have 1's written to them are pulled high by the internal pullup resistors, and in that state can be used as inputs. As inputs, port 3 pins being externally pulled low will source current ( the internal pullup resistors. Port 3 also contains the interrupt, timer, serial port and external memory strobe pins that are used by various options. The output latch corresponding to a secondary function must be programmed to a one (1) for that function to operate. The secondary functions are assigned to the pins of port 3, as follows: P3.0 RXD Receiver data input (asynch.) or

P3.1 TXD Transmitter data output (asynch.)

P3.2 INT0

P3.3 INT1

P3.4 T0 Timer 0 counter input P3.5 T1 Timer 1 counter input P3.6 WR

P3.7 RD

, in the DC characteristics) because of

data input/output (synch.) of serial interface

or clock output (synch.) of serial interface External interrupt 0 input / timer 0 gate control input External interrupt 1 input / timer 1 gate control input

WR control output; latches the data byte from port 0 into the external data memory RD control output; enables the external data memory

Data Sheet 7 2003-02

Table 2 Pin Definitions and Functions (cont’d) Symbol Pin Number I/O

Function

P-MQFP-80-1

C515C

P1.0 - P1.7 31-24

27 26

25 24

I/O Port 1

is an 8-bit quasi-bidirectional I/O port with internal pullup resistors. Port 1 pins that have 1's written to them are pulled high by the internal pullup resistors, and in that state can be used as inputs. As inputs, port 1 pins being externally pulled low will source current ( the internal pullup resistors. The port is used for the low-order address byte during program verification. Port 1 also contains the interrupt, timer, clock, capture and compare pins that are used by various options. The output latch corresponding to a secondary function must be programmed to a one (1) for that function to operate (except when used for the compare functions). The secondary functions are assigned to the port 1 pins as follows: P1.0 INT3

P1.1 INT4 CC1 Interrupt 4 input / compare 1

P1.2 INT5 CC2 Interrupt 5 input / compare 2

P1.3 INT6 CC3 Interrupt 6 input / compare 3

P1.4 INT2 P1.5 T2EX Timer 2 external reload / trigger

P1.6 CLKOUT System clock output P1.7 T2 Counter 2 input

, in the DC characteristics) because of

CC0 Interrupt 3 input / compare 0

output / capture 0 input

output / capture 1 input

output / capture 2 input

output / capture 3 input Interrupt 2 input

input

XTAL2 36 I XTAL2

Input to the inverting oscillator amplifier and input to the internal clock generator circuits. To drive the device from an external clock source, XTAL2 should be driven, while XTAL1 is left unconnected. Minimum and maximum high and low times as well as rise/fall times specified in the AC characteristics must be observed.

Data Sheet 8 2003-02

Table 2 Pin Definitions and Functions (cont’d)

Symbol Pin Number I/O

Function

P-MQFP-80-1

XTAL1 37 O XTAL1

Output of the inverting oscillator amplifier.

P2.0-P2.7 38-45 I/O Port 2

is an 8-bit quasi-bidirectional I/O port with internal pullup resistors. Port 2 pins that have 1's written to them are pulled high by the internal pullup resistors, and in that state can be used as inputs. As inputs, port 2 pins being externally pulled low will source current (

, in the DC characteristics) because of

the internal pullup resistors. Port 2 emits the high-order address byte during fetches from external program memory and during accesses to external data memory that use 16-bit addresses (MOVX @DPTR). In this application it uses strong internal pullup resistors when issuing 1's. During accesses to external data memory that use 8-bit addresses (MOVX @Ri), port 2 issues the contents of the P2 special function register.

C515C

CPUR

PSEN

46 O CPU Running Condition

This output pin is at low level when the CPU is running and program fetches or data accesses in the external data memory area are executed. In idle mode, hardware and software power down mode, and with an active RESET

signal CPUR is set to high level. CPUR

can be typically used for switching external

memory devices into power saving modes.

47 O The Program Store Enable

output is a control signal that enables the external program memory to the bus during external fetch operations. It is activated every six oscillator periods, except during external data memory accesses. The signal remains high during internal program execution.

Data Sheet 9 2003-02

Table 2 Pin Definitions and Functions (cont’d)

Symbol Pin Number I/O

Function

P-MQFP-80-1

ALE 48 O The Address Latch Enable

output is used for latching the address into external memory during normal operation. It is activated every six oscillator periods, except during an external data memory access. ALE can be switched off when the program is executed internally.

C515C

49 I External Access Enable

When held high, the C515C executes instructions always from the internal ROM. When held low, the C515C fetches all instructions from external program memory.

Note: For the ROM protection version EA

P0.0-P0.7 52-59 I/O Port 0

is an 8-bit open-drain bidirectional I/O port. Port 0 pins that have 1's written to them float, and in that state can be used as high-impedance inputs. Port 0 is also the multiplexed low-order address and data bus during accesses to external program and data memory. In this application it uses strong internal pullup resistors when issuing 1's. Port 0 also outputs the code bytes during program verification in the C515C. External pullup resistors are required during program verification.

pin is

latched during reset.

P5.0-P5.7 67-60 I/O Port 5

is an 8-bit quasi-bidirectional I/O port with internal pullup resistors. Port 5 pins that have 1's written to them are pulled high by the internal pullup resistors, and in that state can be used as inputs. As inputs, port 5 pins being externally pulled low will source current (

, in the DC characteristics) because of

the internal pullup resistors. Port 5 can also be switched into a bidirectional mode, in which CMOS levels are provided. In this bidirectional mode, each port 5 pin can be programmed individually as input or output.

Data Sheet 10 2003-02

Table 2 Pin Definitions and Functions (cont’d)

Symbol Pin Number I/O

Function

P-MQFP-80-1

C515C

HWPD

69 I Hardware Power Down

P4.0-P4.7 72-74, 76-80

72 73

74 76 77 78 79

A low level on this pin for the duration of one machine cycle while the oscillator is running resets the C515C. A low level for a longer period will force the part to power down mode with the pins floating.

I/O Port 4

is an 8-bit quasi-bidirectional I/O port with internal pull-up resistors. Port 4 pins that have 1’s written to them are pulled high by the internal pull-up resistors, and in that state can be used as inputs. As inputs, port 4 pins being externally pulled low will source current ( the internal pull-up resistors. P4 also contains the external A/D converter control pin, the SSC pins, the CAN controller input/output lines, and the external interrupt 8 input. The output latch corresponding to a secondary function must be programmed to a one (1) for that function to operate. The alternate functions are assigned to port 4 as follows: P4.0 ADST P4.1 SCLK SSC Master Clock Output /

P4.2 SRI SSC Receive Input P4.3 STO SSC Transmit Output P4.4 SLS P4.5 INT8 P4.6 TXDC Transmitter output of the CAN

P4.7 RXDC Receiver input of the CAN controller

, in the DC characteristics) because of

External A/D converter start pin

SSC Slave Clock Input

Slave Select Input External interrupt 8 input

controller

Data Sheet 11 2003-02

Table 2 Pin Definitions and Functions (cont’d)

Symbol Pin Number I/O

Function

P-MQFP-80-1

/SWD 75 I Power saving mode enable / Start watchdog

timer

A low level on this pin allows the software to enter the power down, idle and slow down mode. In case the low level is also seen during reset, the watchdog timer function is off on default. Use of the software controlled power saving modes is blocked, when this pin is held on high level. A high level during reset performs an automatic start of the watchdog timer immediately after reset. When left unconnected this pin is pulled high by a weak internal pull-up resistor.

C515C

SSCLK

DDCLK

DDE1

DDE2

SSE1

SSE2

DD1

SS1

13 – Ground (0 V) for on-chip oscillator

This pin is used for ground connection of the on-chip oscillator circuit.

14 – Supply voltage for on-chip oscillator

This pin is used for power supply of the on-chip oscillator circuit.

32 68

– Supply voltage for I/O ports

These pins are used for power supply of the I/O ports during normal, idle, and power down mode.

35 70

– Ground (0 V) for I/O ports

These pins are used for ground connections of the I/O ports during normal, idle, and power down mode.

33 – Supply voltage for internal logic

This pins is used for the power supply of the internal logic circuits during normal, idle, and power down mode.

34 – Ground (0 V) for internal logic

This pin is used for the ground connection of the internal logic circuits during normal, idle, and power down mode.

Data Sheet 12 2003-02

Table 2 Pin Definitions and Functions (cont’d) Symbol Pin Number I/O

Function

P-MQFP-80-1

C515C

DDEXT

50 – Supply voltage for external access pins

This pin is used for power supply of the I/O ports and control signals which are used during external accesses (for Port 0, Port 2, ALE, PSEN

SSEXT

and P3.7/RD

51 – Ground (0 V) for external access pins

This pin is used for the ground connection of the I/O ports and control signals which are used during external accesses (for Port 0, Port 2, ALE, PSEN P3.6/WR

, and P3.7/RD).

N.C. 2, 71 – Not connected

These pins should not be connected.

I = Input; O = Output

, P3.6/WR,

Data Sheet 13 2003-02

C515C

XTAL1 XTAL2

ALE

PSEN

CPUR

PE/SWD

HWPD

RESET

Oscillator Watchdog

OSC & Timing

CPU

8 Datapointers

Programmable

Watchdog Timer

Timer 0

Timer 1

Timer 2

Capture

Compare Unit

XRAM 2k x 8 256 x 8

RAM ROM/OTP

64k x 8

Emulation

Support

Logic

Port 0

Port 1

Port 2

Multiple

DD SS

Lines

Port 0 8 Bit Digital I/O

Port 1 8 Bit Digital I/O

Port 2 8 Bit Digital I/O

USART

Baud Rate Generator

SSC (SPI) Interface

Full-CAN

Controller

256 Byte

Reg./Data

Interrupt Unit

AREF

AGND

A/D Converter

S & H

10 Bit

MUX

Figure 4 Block Diagram of the C515C

Port 3

Port 4

Port 5

Port 6

Port 7

C515C

Port 3 8 Bit Digital I/O

Port 4 8 Bit Digital I/O

Port 5 8 Bit Digital I/O

Port 6 8 Bit Analog/

Digital Inputs

Port 7 1 Bit Digital I/O

MCB03647

Data Sheet 14 2003-02

C515C

CPU

The C515C is efficient both as a controller and as an arithmetic processor. It has extensive facilities for binary and BCD arithmetic and excels in its bit-handling capabilities. Efficient use of program memory results from an instruction set consisting of 44% one-byte, 41% two-byte, and 15% three-byte instructions. With a 6 MHz crystal, 58% of the instructions are executed in 1

PSW Special Function Register (D0

Bit No. MSB LSB

µs (10 MHz: 600 ns).

) Reset Value: 00

CY AC F0 RS1 RS0 OV F1 PD0

Bit Function

CY Carry Flag

Used by arithmetic instruction.

AC Auxiliary Carry Flag

Used by instructions which execute BCD operations. F0 General Purpose Flag RS1

RS0

These bits are used to select one of the four register banks.

RS1 RS0 Function

0 0 Bank 0 selected, data address 00 0 1 Bank 1 selected, data address 08H-0F 1 0 Bank 2 selected, data address 10H-17 1 1 Bank 3 selected, data address 18H-1F

PSW

-07

OV Overflow Flag

Used by arithmetic instruction. F1 General Purpose Flag PParity Flag

Set/cleared by hardware after each instruction to indicate an

odd/even number of “one” bits in the accumulator, i.e. even parity.

Data Sheet 15 2003-02

C515C

Memory Organization

The C515C CPU manipulates data and operands in the following five address spaces:

• up to 64 Kbytes of internal/external program memory

• up to 64 Kbytes of external data memory

• 256 bytes of internal data memory

• 256 bytes CAN controller registers / data memory

• 2 Kbytes of internal XRAM data memory

• a 128 byte special function register area

Figure 5 illustrates the memory address spaces of the C515C.

Alternatively

FFFF

Internal

(EA = 1)

External

(EA = 0)

0000

"Code Space"

FFFF

F800 F7FF

F700

H H

Indirect

Address

Internal

RAM

Internal

RAM

Direct

Address

Special Function Register

MCD02717

Internal

XRAM

External

Data

Memory

External

"Data Space" "Internal Data Space"

(2 KByte)

Int. CAN

Controller

(256 Byte)

F6FF

0000

Figure 5 C515C Memory Map

Data Sheet 16 2003-02

C515C

Control of XRAM/CAN Controller Access

The XRAM in the C515C is a memory area that is logically located at the upper end of the external memory space, but is integrated on the chip. Because the XRAM and the CAN controller is used in the same way as external data memory the same instruction types (MOVX) must be used for accessing the XRAM. Two bits in SFR SYSCON, XMAP0 and XMAP1, control the accesses to the XRAM and the CAN controller.

SYSCON Special Function Register (B1

Bit No. MSB LSB

76543210

) C515C-8R Reset Value: X010XX01

C515C-8E Reset Value: X010X001

B B

–PMOD

The function of the shaded bits is not described in this section.

EALE RMAP –

CSWO XMAP1

XMAP0

SYSCON

Bit Function

XMAP1 XRAM/CAN controller visible access control

Control bit for RD

/WR signals during XRAM/CAN Controller accesses. If addresses are outside the XRAM/CAN controller address range or if XRAM is disabled, this bit has no effect. XMAP1 = 0: The signals RD

and WR are not activated during

accesses to the XRAM/CAN Controller

XMAP1 = 1: Ports 0, 2 and the signals RD

and WR are activated during accesses to XRAM/CAN Controller. In this mode, address and data information during XRAM/CAN Controller accesses are visible externally.

XMAP0 Global XRAM/CAN controller access enable/disable control

XMAP0 = 0: The access to XRAM and CAN controller is enabled. XMAP0 = 1: The access to XRAM and CAN controller is disabled

(default after reset). All MOVX accesses are performed via the external bus. Further, this bit is hardware protected.

Bit XMAP0 is hardware protected. If it is reset once (XRAM/CAN controller access enabled) it cannot be set by software. Only a reset operation will set the XMAP0 bit again.

Data Sheet 17 2003-02

C515C

The XRAM/CAN controller can be accessed by read/write instructions (MOVX A,DPTR, MOVX @DPTR,A), which use the 16-bit DPTR for indirect addressing. For accessing the XRAM or CAN controller, the effective address stored in DPTR must be in the range of F700

The XRAM can be also accessed by read/write instructions (MOVX A,@Ri, MOVX @Ri,A), which use only an 8-bit address (indirect addressing with registers R0 or R1). Therefore, a special page register XPAGE which provides the upper address information (A8-A15) during 8-bit XRAM accesses. The behaviour of Port 0 and P2 during a MOVX access depends on the control bits XMAP0 and XMAP1 in register SYSCON and on the state of pin

to FFFFH.

EA. Table 3 lists the various operating conditions.

Data Sheet 18 2003-02

C515C

Table 3 Behaviour of P0/P2 and RD

00 10 X1

= 0 MOVX

@DPTR

MOVX @ Ri

DPTR < XRAM/CAN address range

DPTR

≥

XRAMCAN address range

XPAGE < XRAMCAN addr. page range

XPAGE

≥

XRAMCAN addr. page range

a) P0/P2→Bus b) RD

/WR active c) ext.memory is used

a) P0/P2 (RD b) RD c) XRAM is used

a) P0→Bus P2 b) RD c) ext.memory is used

a) P0 (RD P2 b) RD c) XRAM is used

→Bus

/WR-Data)

/WR inactive

→I/O

/WR active

→Bus

/WR-Data)

→I/O

/WR inactive

/WR During MOVX Accesses

XMAP1, XMAP0

a) P0/P2→Bus b) RD

/WR active c) ext.memory is used

a) P0/P2 (RD b) RD c) XRAM is used

a) P0→Bus P2 b) RD c) ext.memory is used

a) P0 (RD P2 b) RD c) XRAM is used

→Bus

/WR-Data)

/WR active

→I/O

/WR active

→Bus

/WR-Data only)

→I/O

/WR active

a) P0/P2→Bus b) RD c) ext.memory is used

a) P0/P2→Bus

b) RD c) ext.memory is used

a) P0→Bus P2

→I/O

b) RD c) ext.memory is used

a) P0→Bus P2

→I/O

b) RD c) ext.memory is used

/WR active

= 1 MOVX

@DPTR

MOVX @ Ri

DPTR < XRAM/CAN address range

DPTR

≥

XRAMCAN address range

XPAGE < XRAMCAN addr. page range

XPAGE

≥

XRAMCAN addr. page range

a) P0/P2→Bus b) RD

/WR active c) ext.memory is used

a) P0/P2

b) RD/WR inactive c) XRAM is used

a) P0→Bus P2 b) RD c) ext.memory is used

a) P2 P0/P2

b) RD c) XRAM is used

→Ι/0

→I/O

/WR active

→I/O

/WR inactive

a) P0/P2→Bus b) RD

/WR active c) ext.memory is used

a) P0/P2 (RD b) RD c) XRAM is used

a) P0→Bus P2 b) RD c) ext.memory is used

a) P0 (RD P2 b) RD c) XRAM is used

→Bus

/WR-Data)

/WR active

→I/O

/WR active

→Bus

/WR-Data)

→I/O

/WR active

a) P0/P2→Bus b) RD

/WR active c) ext.memory is used

a) P0/P2→Bus

b) RD

/WR active c) ext.memory is used

a) P0→Bus P2

→I/O

b) RD

/WR active c) ext.memory is used

a) P0→Bus P2

→I/O

b) RD

/WR active c) ext.memory is used

modes compatible to 8051/C501 family

Data Sheet 19 2003-02

Reset and System Clock

C515C

The reset input is an active low input at pin RESET internally, the RESET

pin must be held low for at least two machine cycles (12 oscillator

periods) while the oscillator is running. A pullup resistor is internally connected to

. Since the reset is synchronized

allow a power-up reset with an external capacitor only. An automatic reset can be

obtained when

is applied by connecting the RESET pin to VSS via a capacitor.

Figure 6 shows the possible reset circuitries.

b)a)

RESET

C515C

RESET

C515C

RESET

C515C

MCS02721

Figure 6 Reset Circuitries

Figure 7 shows the recommended oscillator circiutries for crystal and external clock

operation.

Data Sheet 20 2003-02

C515C

Crystal/Resonator Oscillator Mode Driving from External Source

2 - 10 MHz

Crystal Mode :

XTAL1

XTAL2 XTAL2

C = 20 pF ± 10 pF (incl. stray capacitance)

:Resonator Mode

= depends on selected ceramic resonatorC

N.C.

External Oscillator Signal

XTAL1

MCT02765

Figure 7 Recommended Oscillator Circuitries

Multiple Datapointers

As a functional enhancement to the standard 8051 architecture, the C515C contains eight 16-bit datapointers instead of only one datapointer. The instruction set uses just one of these datapointers at a time. The selection of the actual datapointer is done in the special function register DPSEL. Figure 8 illustrates the datapointer addressing mechanism.

Datapointer

DPTR 0000

.0.1.2

DPTR7

DPTR0

DPH(83 ) DPL(82 )

External Data Memory

MCD00779

-----

DPSEL(92 )

DPSEL Selected

.2 .1 .0

0 0 1 DPTR 1 0 1 0 DPTR 2 0 1 1 DPTR 3 1 0 0 DPTR 4 1 0 1 DPTR 5 1 1 0 DPTR 6 1 1 1 DPTR 7

Figure 8 External Data Memory Addressing using Multiple Datapointers

Data Sheet 21 2003-02

C515C

Enhanced Hooks Emulation Concept

The Enhanced Hooks Emulation Concept of the C500 microcontroller family is a new, innovative way to control the execution of C500 MCUs and to gain extensive information on the internal operation of the controllers. Emulation of on-chip ROM based programs is possible, too.

Each production chip has built-in logic for the support of the Enhanced Hooks Emulation Concept. Therefore, no costly bond-out chips are necessary for emulation. This also ensure that emulation and production chips are identical.

The Enhanced Hooks Technology, which requires embedded logic in the C500 allows the C500 together with an EH-IC to function similar to a bond-out chip. This simplifies the design and reduces costs of an ICE-system. ICE-systems using an EH-IC and a compatible C500 are able to emulate all operating modes of the different versions of the C500 microcontrollers. This includes emulation of ROM, ROM with code rollover and ROMless modes of operation. It is also able to operate in single step mode and to read the SFRs after a break.

SYSCON

PCON TCON

Optional I/O Ports

ICE-System Interface

to Emulation Hardware

RESET

ALE

PSEN

C500

MCU Interface Circuit

Port 3 Port 1

Port

Target System Interface

RSYSCON

RPCON RTCON

Enhanced Hooks

RPort 0RPort 2

EH-IC

TEA TALE TPSEN

MCS03280

Figure 9 Basic C500 MCU Enhanced Hooks Concept Configuration

Port 0, port 2 and some of the control lines of the C500 based MCU are used by Enhanced Hooks Emulation Concept to control the operation of the device during emulation and to transfer informations about the program execution and data transfer between the external emulation hardware (ICE-system) and the C500 MCU.

Data Sheet 22 2003-02

C515C

Special Function Registers

The registers, except the program counter and the four general purpose register banks, reside in the special function register area. The special function register area consists of two portions: the standard special function register area and the mapped special function register area. Two special function registers of the C515C (PCON1 and DIR5) are located in the mapped special function register area. For accessing the mapped special function register area, bit RMAP in special function register SYSCON must be set. All other special function registers are located in the standard special function register area which is accessed when RMAP is cleared (“0”). As long as bit RMAP is set, mapped special function register area can be accessed. This bit is not cleared by hardware automatically. Thus, when non-mapped/mapped registers are to be accessed, the bit RMAP must be cleared/set by software, respectively each.

SYSCON Special Function Register (B1

) C515C-8R Reset Value: X010XX01

C515C-8E Reset Value: X010X001

B B

Bit No. MSB LSB

76543210

–PMOD

The function of the shaded bits is not described in this section.

EALE RMAP –

CSWO XMAP1

XMAP0

SYSCON

Bit Function

RMAP Special function register map bit

RMAP = 0: The access to the non-mapped (standard) special

function register area is enabled (reset value).

RMAP = 1: The access to the mapped special function register

area is enabled.

The 59 special function registers (SFRs) in the standard and mapped SFR area include pointers and registers that provide an interface between the CPU and the other on-chip peripherals. The SFRs of the C515C are listed in Table 4 and Table 5. In Table 4 they are organized in groups which refer to the functional blocks of the C515C. The CANSFRs are also included in Table 4. Table 5 illustrates the contents of the SFRs in numeric order of their addresses. Table 6 list the CAN-SFRs in numeric order of their addresses.

Data Sheet 23 2003-02

C515C

Table 4 Special Function Registers - Functional Block

Block Symbol Name Addr Contents after

Reset

CPU ACC

B DPH DPL DPSEL PSW SP SYSCON

A/DConverter

ADCON0 ADCON1 ADDATH ADDATL

Interrupt System

IEN0 IEN1

IEN2

IP0 IP1 TCON T2CON SCON

IRCON

XRAM XPAGE

SYSCON

Ports P0

P1 P2 P3 P4 P5 DIR5 P6 P7 SYSCON

Watchdog WDTREL

IEN0

IEN1

IP0

Accumulator B-Register Data Pointer, High Byte Data Pointer, Low Byte Data Pointer Select Register Program Status Word Register Stack Pointer

System Control Register C515C-8R

C515C-8E

A/D Converter Control Register 0 A/D Converter Control Register 1 A/D Converter Data Register High Byte A/D Converter Data Register Low Byte

Interrupt Enable Register 0 Interrupt Enable Register 1 Interrupt Enable Register 2 Interrupt Priority Register 0 Interrupt Priority Register 1 Timer Control Register Timer 2 Control Register Serial Channel Control Register Interrupt Request Control Register

Page Address Register for Extended on-chip XRAM and CAN Controller

System Control Register C515C-8R

C515C-8E

Port 0 Port 1 Port 2 Port 3 Port 4 Port 5 Port 5 Direction Register Port 6, Analog/Digital Input Port 7

System Control Register C515C-8R

C515C-8E

Watchdog Timer Reload Register Interrupt Enable Register 0 Interrupt Enable Register 1 Interrupt Priority Register 0

E0 F0

83 82 92

81 B1 B1

DC D9 DA

A8 B8

9A A9 B9

88 C8 98 C0

B1 B1

80 90 A0 B0 E8 F8 F8

DB FA B1

A8 B8

H H H

H H

H H H

H H

H H H

2)4)

XXXXX000 00

X010XX01 X010X001

0XXXX000 00

00XXXXXX 00

XX00X00X 00

0X000000 00

X010XX01 X010X001

– XXXXXXX1 X010XX01 X010X001

Data Sheet 24 2003-02

C515C

Table 4 Special Function Registers - Functional Block (cont’d)

Block Symbol Name Addr Contents after

Reset

Serial Channel

CAN Controller

ADCON0 PCON

SBUF SCON SRELL SRELH

CR SR IR BTR0 BTR1 GMS0 GMS1 UGML0 UGML1 LGML0 LGML1 UMLM0

UMLM1

LMLM0

LMLM1

MCR0 MCR1 UAR0 UAR1 LAR0 LAR1 MCFG DB0n DB1n DB2n DB3n DB4n DB5n DB6n DB7n

A/D Converter Control Register 0 Power Control Register Serial Channel Buffer Register Serial Channel Control Register Serial Channel Reload Register, low byte Serial Channel Reload Register, high byte

Control Register Status Register Interrupt Register Bit Timing Register Low Bit Timing Register High Global Mask Short Register Low Global Mask Short Register High Upper Global Mask Long Register Low Upper Global Mask Long Register High Lower Global Mask Long Register Low Lower Global Mask Long Register High Upper Mask of Last Message Register Low Upper Mask of Last Message Register High Lower Mask of Last Message Register Low Lower Mask of Last Message Register High Message Object Registers: Message Control Register Low Message Control Register High Upper Arbitration Register Low Upper Arbitration Register High Lower Arbitration Register Low Lower Arbitration Register High Message Configuration Register Message Data Byte 0 Message Data Byte 1 Message Data Byte 2 Message Data Byte 3 Message Data Byte 4 Message Data Byte 5 Message Data Byte 6 Message Data Byte 7

F700 F701 F702 F704 F705 F706 F707 F708 F709 F70A F70B F70C

F70D

F70E

F70F

F7n0 F7n1 F7n2 F7n3 F7n4 F7n5 F7n6 F7n7 F7n8 F7n9 F7nA F7nB F7nC F7nD F7nE

00 00 XX 00 D9 XXXXXX11

101

0UUUUUUU

UUU11111

UUUUU000

UUUUUU00

H H

Data Sheet 25 2003-02

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