INFINEON C505, C505C, C505A, C505CA User Manual

C505 C505C

Data Sheet, Dec. 2000

C505A C505CA

8-Bit Single-Chip Microcontroller

Microcontrollers

Never stop thinking.

Edition 2000-12 Published by Infineon Technologies AG,

St.-Martin-Strasse 53, D-81541 München, Germany

Attention please!

The information herein is given to descr ibe certain components and shall not be considere d as warranted characteristics.

Terms of delivery and rights to technical change reserved. We hereby disclaim any and all warranties, including but not limited to warranties of non-infringement, regarding

circuits, descriptions and charts stated her ein. Infineon Technologies is an approved CECC manufacturer.

Information

For further information on tech nology, delivery terms and conditions and prices please contact your nearest Infineon Technologies Office in Germany or our Infineon Technologies Representatives worldwide (see address list).

Warnings

Due to technical requirements co mponents may contain dangerous substan ce s. For information on the t yp es in question please contact your neares t Infineon Technologies Office.

Infineon Technologies Components may only be used in life-support devices or systems with the express written approval of Infineon T echnologies, if a f ailure of such components can reasonably be expected to cause the failure of that lif e - su ppo rt de vi ce o r system, or to aff ec t th e sa fety or effectiveness of th a t d evice or system. L i fe support devices or systems are inten ded to be implante d in the human body, or to support and/or maintain and sustain and/or protect human life. If they fail, it is reasonable to assume that the health of the user or other persons may be endangered.

C505 C505C

Data Sheet, Dec. 2000

C505A C505CA

8-Bit Single-Chip Microcontroller

Microcontrollers

Never stop thinking.

C505/C505C/C505A/C505CA Data Sheet Revision History : Current Version : 2000-12

Previous Releases : 08.00, 06.00, 07.99, 12.97 Page

(in previous version

24 24 Version register VR2 for C505A-4R/C505CA-4R BB step is updated.

Page (in current version)

Subjects (major changes since last revision)

Controller Area Network (CAN): License of Robert Bosch GmbH

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8-Bit Single-Chip Microcontroller C500 Family

Advance Information

• Fully compatible to standard 8051 microcontroller

• Superset of the 8051 architecture with 8 datapointers

• Up to 20 MHz operating frequency

– 375 ns instruction cycle time @16 MHz – 300 ns instruction cycle time @20 MHz (50 % duty cycle)

• On-chip program memory (with optional memory protection)

– C505(C)(A)-2R : 16K byte on-chip ROM – C505A-4R/C505CA-4R: 32K byte on-chip ROM – C505A-4E/C505CA-4E: 32K byte on-chip OTP – alternatively up to 64k byte external program memory

• 256 byte on-chip RAM

• On-chip XRAM

– C505/C505C : 256 byte – C505A/C505CA : 1K byte

(more features on next page)

C505/C505C/C505A/

C505CA

Oscillator Watchdog

A/D Converter

C505/C505C : 8-bit

C505A/C505CA : 10-bit

Timer 2

Full-CAN Controller

C505C/C505CA only

Watchdog Timer

On-Chip Emulation Support Module

Figure 1 C505 Functional Units

XRAM

C505/C505C: 256 byte

C505A/C505CA: 1K byte

Timer

0

Timer

1

Program Memory

C505A-4R/C505CA -4R : 32K ROM

C505A-4E/C505CA-4E : 32K OTP

C500

Core

8 Datapointers

C505(C)(A)-2R : 16K ROM

RAM

256 byte

8-bit

USART

Port 0

Port 1

Port 2

Port 3

Port 4

I/O

8 analog inputs / 8 digit. I/O

I/O

I/O (2-bit I/O port)

Data Sheet 1 12.00

C505/C505C/C505A/C505CA

Features (continued) :

• 32 + 2 digital I/O lines

– Four 8-bit digital I/O ports – One 2-bit digital I/O port (port 4) – Port 1 with mixed analog/digital I/O capability

• Three 16-bit timers/counters

– Timer 0 / 1 (C501 compatible) – Timer 2 with 4 channels for 16-bit capture/compare operation

• Full duplex serial interface with programmable baudrate generator (USART)

• Full CAN Module, version 2.0 B compliant (C505C and C505CA only)

– 256 register/data bytes located in external data memory area – 1 MBaud CAN baudrate when operating frequency is equal to or above 8 MHz – internal CAN clock prescaler when input frequency is over 10 MHz

• On-chip A/D Converter

– up to 8 analog inputs – C505/C505C : 8-bit resolution – C505A/C505CA: 10-bit resolution

• Twelve interrupt sources with four priority levels

• On-chip emulation support logic (Enhanced Hooks Technology

TM

)

• Programmable 15-bit watchdog timer

• Oscillator watchdog

• Fast power on reset

• Power Saving Modes

– Slow-down mode – Idle mode (can be combined with slow-down mode) – Software power-down mode with wake up capability through P3.2/INT0

or P4.1/RXDC pin

• P-MQFP-44 package

• Pin configuration is compatible to C501, C504, C511/C513-family

• Temperature ranges:

SAB-C505 versions T SAF-C505 versions T SAH-C505 versions T SAK-C505 versions T

= 0 to 70 °C

A

= -40 to 85°C

A

= -40 to 110°C

A

= -40 to 125°C

A

Data Sheet 2 12.00

Table 1 Differences in Functionality of the C505 MCUs

C505/C505C/C505A/C505CA

Device Internal Program Memory XRAM Size A/D Converter

ROM OTP

C505-2R 16K byte – 256 byte 8 Bit – C505-L – – 256 byte 8 Bit – C505C-2R 16K byte – 256 byte 8 Bit √ C505C-L – – 256 byte 8 Bit √ C505A-4R 32K byte – 1K byte 10 Bit – C505A-2R 16K byte – 1K byte 10 Bit – C505A-L – – 1K byte 10 Bit – C505CA-4R 32K byte – 1K byte 10 Bit √ C505CA-2R 16K byte – 1K byte 10 Bit √ C505CA-L – – 1 K byte 10 Bit √ C505A-4E – 32K byte 1K byte 10 Bit – C505CA-4E – 32K byte 1K byte 10 Bit √

Note: The term C505 refers to all versions described within this document unless otherwise noted.

However the term C505 may also be restricted by the context to refer to only CAN-less derivatives with 8-Bit ADC which are C505-2R and C505-L in this document.

Resolution

CAN Controller

Note: The term C505(C)(A)-2R, for simplicity, is used to stand for C505 16K byte ROM versions

within this document which are C505-2R, C505C-2R, C505A-2R and C505CA-2R.

Ordering Information

The ordering code for Infineon Technologies’ microcontrollers provides an exact reference to the required product. This ordering code identifies:

• the derivative itself, i.e. its function set

• the specificed temperature rage

• the package and the type of delivery

For the available ordering codes for the C505 please refer to the “Product information Microcontrollers”, which summarizes all available microcontroller variants.

Data Sheet 3 12.00

C505/C505C/C505A/C505CA

V

DDVSS

RESET

Figure 2 Logic Symbol

V

AREF

V

AGND

XTAL1 XTAL2

EA

ALE

PSEN

C505 C505C C505A

C505CA

Port 0 8-bit Digital I/O

Port 1 8-bit Digital I/O / 8-bit Analog Inputs

Port 2 8-bit Digital I/O

Port 3 8-bit Digital I/O

Port 4 2-bit Digital I/O

Note: The ordering codes for the Mask-ROM versions are defined for each product after

verification of the respective ROM code.

Data Sheet 4 12.00

C505/C505C/C505A/C505CA

P0.4 / AD4

P0.5 / AD5

P0.6 / AD6

P0.3 / AD3 P0.2 / AD2 P0.1 / AD1 P0.0 / AD0

V

AREF

V

AGND

P1.0 / AN0 / INT3

/ CC0 P1.1 / AN1 / INT4 / CC1 P1.2 / AN2 / INT5 / CC2 P1.3 / AN3 / INT6 / CC3

P1.4 / AN4

P0.7 / AD7EAP4.1 / RXDC

32 31 30 29 28 27 26 25 24 23

33

34 35 36 37 38 39 40 41 42 43 44

123456789 10 11

C505C C505A

C505CA

C505

ALE

PSEN

P2.5 / A13

P2.6 / A14

P2.7 / A15

22 21 20 19 18 17 16 15 14 13 12

P2.4 / A12 P2.3 / A11 P2.2 / A10 P2.1 / A9 P2.0 / A8

V

DD

V

SS

XTAL1 XTAL2 P3.7 / RD P3.6 / WR

RESET

P3.1 / TxD

P3.0 / RxD

P3.2 / INT0

P4.0 / TXDC

P1.7 / AN7 / T2

P1.5 / AN5 / T2EX

P1.6 / AN6 / CLKOUT

This pin functionality is not ava ilable in the C505/C505A.

Figure 3 C505 Pin Configuration P-MQFP-44 Package (Top View)

P3.3 / INT1

P3.4 / T0

P3.5 / T1

Data Sheet 5 12.00

Table 2 Pin Definitions and Functions

C505/C505C/C505A/C505CA

Symbol Pin Number I/O

*)

P1.0-P1.7 40-44,1-3

40

41

42

43

44 1

2

3

I/O Port 1

Function

is an 8-bit quasi-bidirecti onal port with internal pull-up arrangement. Port 1 pins can be used for digital inpu t/output or as analog inputs of the A/D converter. Port 1 pins that have 1’s written to them are pulled high by internal pull-up transistors and in that state can be used as inputs. As inputs, port 1 pins being externally pulled low will source current (I internal pullup transistors. Port 1 pins are assigned to be used as analog inputs via the register P1ANA. As secondary digital functions, port 1 c ontains the i nterrupt, timer, clock, capture and compare pins. The output latch corresponding to a secondary function must be programmed to a one (1) for that function to operate (except for compare functions). The secondary functions are assigned to the pins of port 1 as follows:

P1.0 / AN0 / INT3

P1.1 / AN1 / INT4 / CC1 Analog input channel 1/

P1.2 / AN2 / INT5 / CC2 Analog input channel 2 /

P1.3 / AN3 / INT6 / CC3 Analog input channel 3

P1.4 / AN4 Analog input channel 4 P1.5 / AN5 / T2EX Analog input channel 5 / Timer 2

P1.6 / AN6 / CLKOUT Analog input channel 6 /

P1.7 / AN7 / T2 Analog input channel 7 /

Port 1 is used for the low-order address byte during program verification of the C505 ROM versions (i.e. C505(C)(A)-2R/ C505A-4R/C505CA-4R).

, in the DC characteristics) because of the

IL

/ CC0 Analog input channel 0

interrupt 3 input / capture/compare channel 0 I/O

interrupt 4 input / capture/compare channel 1 I/O

interrupt 5 input / capture/compare channel 2 I/O

interrupt 6 input / capture/compare channel 3 I/O

external reload / trigger input

system clock output

counter 2 input

*) I = Input

O=Output

Data Sheet 6 12.00

Table 2 Pin Definitions and Functions (cont’d)

C505/C505C/C505A/C505CA

Symbol Pin Number I/O

Function

*)

RESET 4 I RESET

A high level on this pin for two machine cycle while the oscillator is running resets the device. An internal diffused resistor to V external capacitor to V

P3.0-P3.7 5, 7-13

I/O Port 3

is an 8-bit quasi-bidirecti onal port with internal pull-up arrangement. Port 3 pins that have 1’s written to them are pulled high by t he internal pull-up tr ansistors and in tha t state can be used as inputs. As inputs, port 3 pins being externally pulled low will source current (I characteristics) because of the internal pullup transistors. The output latch corresponding to a secondary function must be programmed to a one (1) for that function to operate (except for TxD and WR assigned to the pins of port 3 as follows:

5

7

8

9

10 11 12

13

P3.0 / RxD Receiver data input (asynch.) or data

P3.1 / TxD Transmitter data output (asynch.) or

P3.2 / INT0

P3.3 / INT1

P3.4 / T0 Timer 0 counter input P3.5 / T1 Timer 1 counter input P3.6 / WR

P3.7 / RD

permits power-on reset using only an

SS

.

DD

, in the DC

IL

). The secondary functio ns are

input/output (synch.) of serial interface

clock output (synch.) of serial interface External interrupt 0 input / timer 0 gate control input External interrupt 1 input / timer 1 gate control input

WR control output; latches the data byte from port 0 into the external data memory RD control output; enables the external data memory

*) I = Input

O=Output

Data Sheet 7 12.00

Table 2 Pin Definitions and Functions (cont’d)

C505/C505C/C505A/C505CA

Symbol Pin Number I/O

*)

P4.0 P4.1

XTAL2 14 O XTAL2

XTAL1 15 I XTAL1

6 28

I/O I/O

Function

Port 4

is a 2-bit quasi-bidirectional por t with internal pull-up arrangement. Port 4 pins that have 1’s written to them are pulled high by t he internal pull-up tr ansistors and in tha t state can be used as inputs. As inputs, port 4 pins being externally pulled low will source current (I characteristics) because of the internal pullup transistors. The output latch corresponding to the secondary function RXDC must be programmed to a one (1) for that functi on to operate. The secondary functions are assigned to the two pins of port 4 as follows (C505C and C505CA only) : P4.0 / TXDC Transmitter output of CAN controller P4.1 / RXDC Receiver input of CAN controller

Output of the inverting oscillator amplifier.

Input to the inverting oscillator amplifier and input to the internal clock generator circuits. To drive the device from an external clock source, XTAL1 should be driven, while XTAL2 is left unconnected. To operate above a frequency of 16 MHz, a duty cycle of the etxernal clock signal of 50 % should be maintained. Minimum and maximum high and low times as well as rise/ fall times specified in the AC character istics must be observed.

, in the DC

IL

*) I = Input

O=Output

Data Sheet 8 12.00

Table 2 Pin Definitions and Functions (cont’d)

C505/C505C/C505A/C505CA

Symbol Pin Number I/O

*)

P2.0-P2.7 18-25 I/O Port 2

PSEN

26 O The Program Store Enable

Function

is a an 8-bit quasi-bidirectional I/O port with internal pullup resistors. Port 2 pins that have 1’s written to them a re pulled high by the internal pullup res istors, and in that st ate can be used as inputs. As inputs, port 2 pins being e xternally pulled low will source current (I because of the internal pullup resistors. Port 2 emits the high-order ad dress byte during fetches from ex ternal program memor y and during accesses to external data memory that use 16-bit addresses (MOVX @DPTR). In this application it uses strong internal pullup transistors when issuing 1s. During accesses to external data memory that use 8-bit addresses (M OVX @Ri), port 2 issues the contents of the P2 special function register and uses only the internal pullup resistors.

output is a control signal that enables the external program memory to the bus during extern al fetch operations. It is activated every three oscillator periods except during external data m emory accesses. Remains high dur ing internal prog ram execution. This pin should n ot be driven during reset operation.

, in the DC characteristics)

IL

ALE 27 O The Address Latch Enable

output is used for latching the low-byte of the address into external memory during normal operation. It is activated every three oscillator periods exc ept during an external data memory access. When instructions are executed from internal ROM or OTP (EA disabled by bit EALE in SFR SYSCON. ALE should not be driven during reset operation.

*) I = Input

O=Output

=1) the ALE generation can be

Data Sheet 9 12.00

Table 2 Pin Definitions and Functions (cont’d)

C505/C505C/C505A/C505CA

Symbol Pin Number I/O

Function

*)

EA 29 I External Access Enable

When held at high level, instructions are fetched from th e internal program memory when the PC is less than 4000 (C505(C)(A)-2R) or 8000 4E/C505CA-4E). When held at low level, the C505 fetches all instructions from external program memory. For the C505 romless versions (i.e. C505-L, C505C-L, C505A-L and C505CA-L) this pin must be tied low. For the ROM protection version EA reset.

P0.0-P0.7 37-30 I/O Port 0

is an 8-bit open-drain bidirectional I/O port. Port 0 pins that have 1’s written to them float, and in that state can be used as high-impendance in puts. Port 0 is also the multiplexe d low-order address and data bus during accesses to external program or data memory. In this application it uses strong internal pullup transistors when issuing 1’s. Port 0 also outputs the code bytes during program verification in the C505 ROM versions. External pullup resistors are required during program verification.

(C505A-4R/C505CA-4R/C505A-

H

pin is latched during

H

V

AREF

V

AGND

V

SS

V

DD

*) I = Input

O=Output

38 – Reference voltage for the A/D converter. 39 – Reference ground for the A/D converter. 16 – Ground (0V) 17 – Power Supply (+5V)

Data Sheet 10 12.00

a

XTAL1 XTAL2

RESET

PSEN

V

DD

Vss

ALE

EA

Oscillator Watchdog

OSC & Timing

CPU

8 datapointers

Programmable Watchdog Timer

XRAM

1)

256 Byte or 1K Byte

RAM

256 Byte

C505/C505C/C505A/C505CA

ROM/

OTP

1)

16K or 32K

Byte

Port 0

Port 0 8-bit digit. I/O

V

AREF

AGND

Timer 0

Timer 1

Timer 2

USART

Baudrate generator

Full-CAN Controller

Interrupt Unit

A/D Converter

8-/10-Bit

S&H

1)

MUX

Port 1

8-bit digit. I/O / 8-bit analog In

Port 2

Port 3

Port 4

256 Byte

Reg./Dat

Port 2 8-bit digit. I/O

Port 3 8-bit digit. I/O

Port 4 2-bit digit. I/O

Emulation

Support

Logic

C505C/C505CA only.

1) Please refer to Table 1 for device specific configuration.

Figure 4 Block Diagram of the C505/C505C/C505A/C505CA

Data Sheet 11 12.00

C505/C505C/C505A/C505CA

CPU

The C505 is efficient both as a controller and as an arithmetic processor. It has extensive facilities for binary and BCD arithmetic and excels in its bit-handling capabilities. Efficient use of program memory results from an instruction s et consisting of 44 % one-byte, 41 % two-byte , and 15% threebyte instructions. With a 16 MHz crystal, 58% of the instructions are executed in 375 ns (20MHz: 300 ns).

Special Function Register PSW (Address D0H) Reset Value : 00H

Bit No. MSB LSB

H

D7

CY AC F0 RS1 RS0 OV F1 PD0

H

D6

H

D5

H

D4

Bit Function

CY Carry Flag

Used by arithmetic instruction.

AC Auxiliary Carry Flag

Used by instructions which execute BCD operations.

F0 General Purpose Flag RS1

RS0

Register Bank Select Control Bits

These bits are used to select one of the four register banks.

RS1 RS0 Function

0 0 Bank 0 selected, data address 00H-07 0 1 Bank 1 selected, data address 08H-0F 1 0 Bank 2 selected, data address 10H-17 1 1 Bank 3 selected, data address 18H-1F

H

D3

H

D2

H

D1

H

D0

H

PSW

H H H H

OV Overflow Flag

Used by arithmetic instruction.

F1 General Purpose Flag P Parity Flag

Set/cleared by hardware after each instruction to indicate an odd/even

number of "one" bits in the accumulator, i.e. even parity.

Data Sheet 12 12.00

C505/C505C/C505A/C505CA

Memory Organization

The C505 CPU manipulates operands in the following four address spaces:

– On-chip program memory :16K byte ROM (C505(C)(A)-2R) or

32K byte ROM (C505A-4R/C505CA-4R) or 32K byte OTP (C505A-4E/C505CA-4E)

– Totally up to 64K byte internal/external program memory – up to 64 Kbyte of external data memory – 256 bytes of internal data memory – Internal XRAM data memory :256 byte (C505/C505C)

1K byte (C505A/C505CA)

– a 128 byte special function register area

Figure 5 illustrates the memory address spaces of the C505 versions.

Alternatively

FFFF

H

Ext.

4000 /

H

8000

H

3FFF / 7FFF

Int.

(EA = 1)

Ext.

(EA = 0)

0000

"Code Space" "Data Space" "Internal Data Space"

"Data Space" F700 to FFFF :

Device

C505

C505C

C505A

C505CA

HH

CAN Area

F700 F7FF

HH

F700 F7FF

HH

Unused Area

F700 FEFF F800 FEFF F700 FBFF F800 FBFF

Ext.

Data

Memory

H H

Ext.

Data

Memory

H

XRAM Area

HH HH H H

FF00 FFFF FF00 FFFF

FC00 FFFF

H

FC00 FFFF

H

FFFF

Internal

XRAM

Unused

Area

Int. CAN

H

See table below for detailed Data Memory partitioning

Contr.

(256 Byte)

F6FF

H

F700

Indirect

H

Addr.

Internal

RAM

0000

H

HH HH HH HH

FF

H

80

H

Internal

RAM

Direct

Addr.

Special

Function

Regs.

7F

H

00

H

MCB03632

FF

80

H

Figure 5 C505 Memory Map Memory Map

Data Sheet 13 12.00

C505/C505C/C505A/C505CA

Reset and System Clock

The reset input is an active high input at pin RESET. Since the reset is synchronized internally, the RESET pin must be held high for at least two machine cycles (12 oscillator periods) while the oscillator is running. A pulldown resist or is internally connected to an external capacitor only. An automatic reset can be obtained when the RESET pin to

V

via a capacitor. Figure 6 shows the possible reset circuitries.

DD

V

to allow a power-up reset with

SS

V

is applied by connecting

DD

a)

C505

V

DD

C505C C505A

C505CA

b)

C505 C505C C505A

C505CA

+

RESET

&

c)

V

DD

V

DD

C505 C505C C505A

+

C505CA

RESET

Figure 6 Reset Circuitries

Data Sheet 14 12.00

C505/C505C/C505A/C505CA

Figure 7 shows the recommended oscillator circuits for crystal and external clock operation.

C

XTAL2

C505

2-20 MHz

C

C = 20pF ± 10pF for crystal operation

C = 20 pF ± 10pF for crystal operation

C505C C505A

C505CA

XTAL1

V

External

Clock

Signal

Figure 7 Recommended Oscillator Circuitries

DD

N.C.

XTAL2

C505 C505C C505A

C505CA

XTAL1

Data Sheet 15 12.00

C505/C505C/C505A/C505CA

Multiple Datapointers

As a functional enhancement to the standard 8051 architecture, the C505 contains eight 16-bit datapointers instead of only one datapointer. The in struction set uses just one of these datapointers at a time. The selection of the actual datapointer is done in the special function regsiter DPSEL.

Figure 8 illustrates the datapointer addressing mechanism.

Datapointer

DPTR 0000

.0.1.2

DPTR7

DPTR0

DPH(83 ) DPL(82 )

HH

-----

DPSEL(92 )

DPSEL Selected

.2 .1 .0

0 0 1 DPTR 1 0 1 0 DPTR 2 0 1 1 DPTR 3 1 0 0 DPTR 4 1 0 1 DPTR 5 1 1 0 DPTR 6 1 1 1 DPTR 7

H

Figure 8 External Data Memory Addressing using Multiple Datapointers

External Data Memory

MCD00779

Data Sheet 16 12.00

C505/C505C/C505A/C505CA

Enhanced Hooks Emulation Concept

The Enhanced Hooks Emulation Concept of the C500 microcontroller family is a new, innovative way to control the execution of C500 MCUs and to gain extensive information on the internal operation of the controllers. Emulation of on-chip ROM based programs is possible, too.

Each production chip has built-in logic for the supprt of the Enhanced Hooks Emulation Concept. Therefore, no costly bond-out chips are necessary for emulation. This also ensure that emulation and production chips are identical.

1)

TM

The Enhanced Hooks Technology together with an EH-IC to function similar to a bond-ou t chip. This simpli fies the design and redu ces costs of an ICE-system. ICE-systems using an EH-IC and a compatible C500 are able to emulate all operating modes of the different versions of the C500 microcontrollers. This includes emulation of ROM, ROM with code rollover and ROMless modes of operation. It is also able to operate in single step mode and to read the SFRs after a break.

, which requires embedded logic in the C500 allows the C500

to Emulation Hardware

SYSCON

PCON

TCON

RESET

EA

ALE

PSEN

RSYSCON

RPCON RTCON

C500 MCU Interface Circuit

Optional

I/O Ports

Figure 9 Basic C500 MCU Enhanced Hooks Concept Configuration

Port 3 Port 1

Port 0 Port 2

Target System Interface

ICE-System Interface

EH-IC

Enhanced Hooks

RPort 0RPort 2

TEA TALE TPSEN

MCS02647

Port 0, port 2 and some of the control lines of the C500 based MCU are used by Enhanced Hooks Emulation Concept to control the operation of the device during emulation and to transfer informations about the programm execution and data transfer between the external emulation hardware (ICE-system) and the C500 MCU.

1)

“Enhanced Hooks Technology“ is a trademark and patent of Metalink Corporation licensed to Infineon Technologies.

Data Sheet 17 12.00

C505/C505C/C505A/C505CA

Special Function Registers

The registers, except the program counter and the four general purpose register banks, reside in the special function register area. The special function register area consists of two portions : the standard special function register area and the mapp ed spec ial func tion regi ster area. Fiv e spec ial function register of the C505 (PCON1,P1ANA, VR0, VR1, VR2) are located in the mapped special function register area. For accessing the mapped special function regi ster area, bit RMAP in special function register SYSCON must be set. All other special function registers are located in the standard special function register area which is accessed when RMAP is cleared (“0“).

The registers and data locations of the CAN controller (CAN-SFRs) are located in the external data memory area at addresses F700H to F7FFH..

Special Function Register SYSCON (Address B1H) Reset Value : XX100X01 (C505CA only) Reset Value : XX100001

Bit No. MSB LSB

76543210

B1

H

Bit Function

RMAP Special function register map bit

CSWO CAN Controller switch-off bit

––

The functions of the shaded bits are not described here.

1) This bit is only available in the C505CA.

RMAP = 0 : The access to the non-mapped (standard) special function register

RMAP = 1 : The access to the mapped special function register area is enabled.

CSWO = 0 : CAN Controller is enabled (default after reset). CSWO = 1 : CAN Controller is switched off.

EALE RMAP CMOD

area is enabled.

CSWO

1)

XMAP1

XMAP0

SYSCON

B B

As long as bit RMAP is set, mapped special function register area can be accessed. This bit is not cleared by hardware automatically. Thus, when non-mapped/mapped regist ers are to be accessed, the bit RMAP must be cleared/set respectively by software.

All SFRs with addresses where address bits 0-2 are 0 (e.g. 80H, 88H, 90H, 98H, ..., F8H, FFH) are bitaddressable.

The 52 special function registers (SFRs) in the standard and mapped SFR area include pointers and registers that provide an interface between the CPU and the other on-chip peripherals. The SFRs of the C505 are listed in Table 3 and Table 4. In Table 3 they are organized in groups which refer to the functional blocks of the C505. The CAN-SFRs (applicable for the C505C and C505CA only) are also included in Table 3. Table 4 illustrates the contents of the SFRs in numeric order of their addresses. Table 5 list the CAN-SFRs in numeric order of their addresses.

Data Sheet 18 12.00

C505/C505C/C505A/C505CA

Table 3 Special Function Registers - Functional Blocks

Block Symbol Name Address Contents after

Reset

CPU ACC

B DPH DPL DPSEL PSW SP SYSCON

VR0 VR1 VR2

A/DConverter

ADCON0 ADCON1 ADDAT ADST ADDATH

4)

Accumulator B-Register Data Pointer, High Byte Data Pointer, Low Byte Data Pointer Select Register Program Status Word Register Stack Pointer

2)

System Control Register

Version Register 0 Version Register 1

4)

Version Register 2

2)

A/D Converter Control Register 0 A/D Converter Control Register 1 A/D Converter Data Reg. (C505/C505C) A/D Converter Start Reg. (C505/C505C) A/D Converter High Byte Data Register

E0 F0

83 82 92

D0

81 B1

FC FD FE

D8

DC D9 DA D9

H

H H H

H

1)

H H

1)

H

(C505A/C505CA)

ADDATL

A/D Converter Low Byte Data Register

DA

H

(C505A/C505CA)

P1ANA

Interrupt System

IEN0 IEN1 IP0 IP1 TCON T2CON SCON IRCON

XRAM XPAGE

2) 4)

Port 1 Analog Input Selection Register

2)

Interrupt Enable Register 0 Interrupt Enable Register 1 Interrupt Priority Register 0 Interrupt Priority Register 1

2)

Timer Control Register

2)

Timer 2 Control Register

2)

Serial Channel Control Register Interrupt Request Control Register

Page Address Register for Extended on-chip

90

A8 B8

A9 B9

88 C8 98 C0

91

H

H H

H

1)

XRAM and CAN Controller

SYSCON

1) Bit-addressable special fun ction registers

2) This special function register is listed repeatedly since some bits of it also belong to other functional blocks.

3) “X“ means that the value is undefined and the location is reserved

4) This SFR is a mapped SFR. For ac ce ssing this SFR, bit RMAP in SFR SYSCON must be set.

5) The content of this SFR varies with t he ac t ual s t ep of the C505 (eg. 01

6) C505 / C505A/C505C only

7) C505CA only

2)

System Control Register

B1

H

for the first step)

H

00

H

00

H

00

H

00

H

XXXXX000 00

H

07

H

XX100X01 XX100001 C5

H

05

H

5)

00X00000 01XXX000 00

H

3)

XX

H

00

H

00XXXXXX

FF

H

00

H

00

H

00

H

XX000000 00

H

00X00000 00

H

00

H

00

H

XX100X01 XX100001

B

3) 7)

B

3)

3) 7)

3)

3) 6)

3)

3) 6)

Data Sheet 19 12.00

C505/C505C/C505A/C505CA

Table 3 Special Function Registers - Functional Blocks (cont’d)

Block Symbol Name Address Contents after

Reset

Ports P0

P1 P1ANA P2 P3 P4

Serial Channel

ADCON0 PCON

2)

SBUF SCON SRELL SRELH

Timer 0/ Timer 1

TCON TH0 TH1 TL0 TL1 TMOD

Compare/ Capture Unit / Timer 2

CCEN CCH1 CCH2 CCH3 CCL1 CCL2 CCL3 CRCH CRCL TH2 TL2 T2CON

2)

IEN0

2)

IEN1

Watchdog WDTREL

2)

IEN0

2)

IEN1

2)

IP0

Pow. Save Modes

1) Bit-addressable special function registers

2) This special function register is listed repeatedly since some bits of it also belong to other functional blocks.

3) “X“ means that the value is undefined and the location is reserved

4) SFR is located in the mapped SFR area. For accessing this SFR, bit RMAP in SFR SYSCON must be set.

PCON PCON1

2)

Port 0 Port 1

2) 4)

Port 1 Analog Input Selection Register Port 2 Port 3 Port 4

2)

A/D Converter Control Register 0 Power Control Register Serial Channel Buffer Register Serial Channel Control Register Serial Channel Reload Register, low byte Serial Channel Reload Register, high byte

Timer 0/1 Control Register Timer 0, High Byte Timer 1, High Byte Timer 0, Low Byte Timer 1, Low Byte Timer Mode Register

Comp./Capture Enable Reg. Comp./Capture Reg. 1, High Byte Comp./Capture Reg. 2, High Byte Comp./Capture Reg. 3, High Byte Comp./Capture Reg. 1, Low Byte Comp./Capture Reg. 2, Low Byte Comp./Capture Reg. 3, Low Byte Reload Register High Byte Reload Register Low Byte Timer 2, High Byte Timer 2, Low Byte Timer 2 Control Register Interrupt Enable Register 0 Interrupt Enable Register 1

Watchdog Timer Reload Register Interrupt Enable Register 0 Interrupt Enable Register 1 Interrupt Priority Register 0

Power Control Register

4)

Power Control Register 1

80

H

90

H

90

H

A0

H

B0

H

E8H D8

H

87

H

99

H

98

H

AA

H

BA

H

88

H

8C

H

8D

H

8A

H

8B

H

89

H

C1

H

C3

H

C5

H

C7

H

C2

H

C4

H

C6

H

CB

H

CA

H

CD

H

CC

H

C8

H

A8

H

B8

H

86

H

A8

H

B8

H

A9

H

87

H

88

H

1)

FF

H

FF

H

FF

H

FF

H

FF

1)

H

XXXXXX11 00X00000

00

H

3)

XX

H

00

H

D9

H

XXXXXX11 00

H

00

H

00

H

00

H

00

H

00

H

3)

00

H

00

H

00

H

00

H

00

H

00

H

00

H

00

H

00

H

00

H

00

H

00X00000 00

H

00

H

00

H

00

H

00

H

00

H

00

H

0XX0XXXX

B

3)

B

3)

B

Data Sheet 20 12.00

C505/C505C/C505A/C505CA

Table 3 Special Function Registers - Functional Blocks (cont’d)

Block Symbol Name Address Contents after

Reset

CAN Controller

(C505C/ C505CA only)

CR SR IR BTR0 BTR1 GMS0 GMS1 UGML0 UGML1 LGML0 LGML1 UMLM0 UMLM1 LMLM0 LMLM1

Control Register Status Register Interrupt Register Bit Timing Register Low Bit Timing Register High Global Mask Short Register Low Global Mask Short Register High Upper Global Mask Long Register Low Upper Global Mask Long Register High Lower Global Mask Long Register Low Lower Global Mask Long Register High Upper Mask of Last Message Register Low Upper Mask of Last Message Register High Lower Mask of Last Message Register Low Lower Mask of Last Message Register High

F700 F701 F702 F704 F705 F706 F707 F708 F709 F70A F70B F70C F70D F70E F70F

H H H H H H H H H

H

H H H H H

01

H

3)

XX

H

3)

XX

H

3)

UU

H

0UUUUUUU

3)

UU

H

UUU11111

3)

UU

H

3)

UU

H

3)

UU

H

UUUUU000

3)

UU

H

3)

UU

H

3)

UU

H

UUUUU000

B

Message Object Registers : MCR0 MCR1 UAR0 UAR1 LAR0 LAR1 MCFG DB0 DB1 DB2 DB3 DB4 DB5 DB6 DB7

1) Bit-addressable special fun ction registers

2) This special function register is listed repeatedly since some bits of it also belong to other functional blocks.

3) “X“ means that the value is undefined and the location is reserved. “U“ means that the value is unchanged by a reset operation. “U“ values are undefined (as “X“) after a power-on reset operation

4) SFR is located in the mapped SFR area. For accessing this SFR, bit RM AP in SFR SYSCON must be set.

5) The notation “n“ (n= 1 to F) in the me ssage object address definition def ines the number of the related

message object.

Message Control Register Low Message Control Register High Upper Arbitration Register Low Upper Arbitration Register High Lower Arbitration Register Low Lower Arbitration Register High Message Configuration Register Message Data Byte 0 Message Data Byte 1 Message Data Byte 2 Message Data Byte 3 Message Data Byte 4 Message Data Byte 5 Message Data Byte 6 Message Data Byte 7

F7n0 F7n1 F7n2 F7n3 F7n4 F7n5 F7n6 F7n7 F7n8 F7n9 F7nA F7nB F7nC F7nD F7nE

H H H H H H H H H H

H H H H H

5)

3)

UU

H

3)

UU

H

3)

UU

H

3)

UU

H

3)

UU

H

UUUUU000 UUUUUU00

3)

XX

H

3)

XX

H

3)

XX

H

3)

XX

H

3)

XX

H

3)

XX

H

3)

XX

H

3)

XX

H

B

3)

Data Sheet 21 12.00

C505/C505C/C505A/C505CA

Table 4 Contents of the SFRs, SFRs in numeric order of their addresses

Addr Register Content

Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0

after

80 81 82 83 86

2)

P0 FF

H

SP 07

H

DPL 00

H

DPH 00

H

WDTREL 00

H

Reset

H H H H H

1)

.7 .6 .5 .4 .3 .2 .1 .0 .7 .6 .5 .4 .3 .2 .1 .0 .7 .6 .5 .4 .3 .2 .1 .0 .7 .6 .5 .4 .3 .2 .1 .0 WDT

.6 .5 .4 .3 .2 .1 .0

PSEL 87 88 88

89 8A 8B 8C 8D 90

PCON 00

H

2)

TCON 00

H

3)

PCON1 0XX0-

H

TMOD 00

H

TL0 00

H

TL1 00

H

TH0 00

H

TH1 00

H

2)

P1 FF

H

H H

XXXX

H H H H H H

SMOD PDS IDLS SD GF1 GF0 PDE IDLE

TF1 TR1 TF0 TR0 IE1 IT1 IE0 IT0

EWPD – – WS – – – –

B

GATE C/T

M1 M0 GATE C/T M1 M0 .7 .6 .5 .4 .3 .2 .1 .0 .7 .6 .5 .4 .3 .2 .1 .0 .7 .6 .5 .4 .3 .2 .1 .0 .7 .6 .5 .4 .3 .2 .1 .0 T2 CLK-

T2EX .4 INT6 INT5 INT4 .INT3

OUT

3)

90 91 92

98 99 A0 A8 A9 AA

1) X means that the value is undefined and the location is reserved

2) Bit-addressable special function registers

3) SFR is located in the mapped SF R ar ea. Fo r ac ce s sin g th is SF R, bit RMAP in SFR SYSCON must be set.

P1ANA FF

H

XPAGE 00

H

DPSEL XXXX-

H

2)

SCON 00

H

SBUF XX

H

2)

P2 FF

H

2)

IEN0 00

H

IP0 00

H

SRELL D9

H

H H

X000

H

H H H H

H

EAN7 EAN6 EAN5 EAN4 EAN3 EAN2 EAN1 EAN0 .7 .6 .5 .4 .3 .2 .1 .0 –––––.2 .1 .0

B

SM0 SM1 SM2 REN TB8 RB8 TI RI .7 .6 .5 .4 .3 .2 .1 .0 .7 .6 .5 .4 .3 .2 .1 .0 EA WDT ET2 ES ET1 EX1 ET0 EX0 OWDS WDTS .5 .4 .3 .2 .1 .0 .7 .6 .5 .4 .3 .2 .1 .0

Data Sheet 22 12.00

C505/C505C/C505A/C505CA

Table 4 Contents of the SFRs, SFRs in numeric order of their addresses (cont’d)

Addr Register Content

Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0

after

H

H H

H H H H H H

H H H H H

1)

RD WR T1 T0 INT1 INT0 TxD RxD ––EALE RMAP CMOD – XMAP1 XMAP0

B

––EALE RMAP CMOD CSWO XMAP1 XMAP0

B

EXEN2 SWDT EX6 EX5 EX4 EX3 ECAN EADC ––.5 .4 .3 .2 .1 .0

B

––––––.1 .0

B

EXF2 TF2 IEX6 IEX5 IEX4 IEX3 SWI IADC COCAH3COCAL3COCAH2COCAL2COCAH1COCAL1COCAH0COCAL

.7 .6 .5 .4 .3 .2 .1 .0 .7 .6 .5 .4 .3 .2 .1 .0 .7 .6 .5 .4 .3 .2 .1 .0 .7 .6 .5 .4 .3 .2 .1 .0 .7 .6 .5 .4 .3 .2 .1 .0 .7 .6 .5 .4 .3 .2 .1 .0 T2PS I3FR – T2R1 T2R0 T2CM T2I1 T2I0

B

.7 .6 .5 .4 .3 .2 .1 .0 .7 .6 .5 .4 .3 .2 .1 .0 .7 .6 .5 .4 .3 .2 .1 .0 .7 .6 .5 .4 .3 .2 .1 .0 CY AC F0 RS1 RS0 OV F1 P BD CLK – BSY ADM MX2 MX1 MX0

B

Reset

2)

B0 B1

B1

B8 B9

P3 FF

H

SYSCON

H

3)

SYSCON

H

4)

2)

IEN1 00

H

IP1 XX00-

H

XX100X01

XX100001

0000

BA

SRELH XXXX-

H

XX11

2)

C0 C1

C2 C3 C4 C5 C6 C7 C8

IRCON 00

H

CCEN 00

H

CCL1 00

H

CCH1 00

H

CCL2 00

H

CCH2 00

H

CCL3 00

H

CCH3 00

H

2)

T2CON 00X0-

H

0000 CA CB CC CD D0 D8

CRCL 00

H

CRCH 00

H

TL2 00

H

TH2 00

H

2)

PSW 00

H

2)

ADCON0 00X0-

H

0000

1) X means that the value is undefined and the location is reserved

2) Bit-addressable special function registers

3) C505 /C505C/C505A only

4) C505CA only

0

Data Sheet 23 12.00