INFINEON C167CR, C167SR User Manual

Data Sheet, V3.3, Feb. 2005

C167CR C167SR

16-Bit Single-Chip Microcontroller

Microcontrollers

Never stop thinking.

Edition 2005-02

Published by Infineon Technologies AG, St.-Martin-Strasse 53, 81669 München, Germany

Attention please!

The information herein is given to describe certain components and shall not be considered as a guarantee of characteristics.

Terms of delivery and rights to technical change reserved. We hereby disclaim any and all warranties, including but not limited to warranties of non-infringement, regarding

circuits, descriptions and charts stated herein.

Information

For further information on technology, delivery terms and conditions and prices please contact your nearest Infineon Technologies Office (www.infineon.com).

Warnings

Due to technical requirements components may contain dangerous substances. For information on the types in question please contact your nearest Infineon Technologies Office.

Infineon Technologies Components may only be used in life-support devices or systems with the express written approval of Infineon Technologies, if a failure of such components can reasonably be expected to cause the failure of that life-support device or system, or to affect the safety or effectiveness of that device or system. Life support devices or systems are intended to be implanted in the human body, or to support and/or maintain and sustain and/or protect human life. If they fail, it is reasonable to assume that the health of the user or other persons may be endangered.

Data Sheet, V3.3, Feb. 2005

C167CR C167SR

16-Bit Single-Chip Microcontroller

Microcontrollers

Never stop thinking.

C167CR, C167SR

Revision History: 2005-02 V3.3

Previous Version: V3.2, 2001-07

V3.1, 2000-04 V3.0, 2000-02 1999-10 (Introduction of clock-related timing) 1999-06 1999-03 (Summarizes and replaces all older docs) 1998-03 (C167SR/CR, 25 MHz Addendum)

07.97 / 12.96 (C167CR-4RM)

12.96 (C167CR-16RM)

06.95 (C167CR, C167SR)

06.94 / 05.93 (C167)

Page Subjects (major changes since last revision)

all The layout of several graphics and text structures has been adapted to

company documentation rules, obvious typographical errors have been corrected.

all The contents of this document have been re-arranged into numbered

sections and a table of contents has been added.

6 BGA-type added to product list

8 Pin designation corrected (pin 78)

9 Input threshold control added to Port 6

17

…

25 Pin diagram and pin description for BGA package added

45 Port 6 added to input-threshold controlled ports

85 Mechanical package drawing corrected (P-MQFP-144-8)

86 Mechanical package drawing added (P-BGA-176-2)

We Listen to Your Comments

Any information within this document that you feel is wrong, unclear or missing at all? Your feedback will help us to continuously improve the quality of this document. Please send your proposal (including a reference to this document) to:

mcdocu.comments@infineon.com

Template: mc_a5_ds_tmplt.fm / 4 / 2004-09-15

C167CR

C167SR

Table of Contents

1 Summary of Features

• High Performance 16-bit CPU with 4-Stage Pipeline – 80/60 ns Instruction Cycle Time at 25/33 MHz CPU Clock – 400/303 ns Multiplication (16 × 16 bits), 800/606 ns Division (32 / 16 bits) – Enhanced Boolean Bit Manipulation Facilities – Additional Instructions to Support HLL and Operating Systems – Register-Based Design with Multiple Variable Register Banks – Single-Cycle Context Switching Support – 16 Mbytes Total Linear Address Space for Code and Data – 1024 Bytes On-Chip Special Function Register Area

• 16-Priority-Level Interrupt System with 56 Sources, Sample-Rate down to 40/30 ns

• 8-Channel Interrupt-Driven Single-Cycle Data Transfer Facilities via Peripheral Event Controller (PEC)

• Clock Generation via on-chip PLL (factors 1:1.5/2/2.5/3/4/5), via prescaler or via direct clock input

• On-Chip Memory Modules – 2 Kbytes On-Chip Internal RAM (IRAM) – 2 Kbytes On-Chip Extension RAM (XRAM) – 128/32 Kbytes On-Chip Mask ROM

• On-Chip Peripheral Modules – 16-Channel 10-bit A/D Converter with Programmable Conversion Time

down to 7.8 µs – Two 16-Channel Capture/Compare Units – 4-Channel PWM Unit – Two Multi-Functional General Purpose Timer Units with 5 Timers – Two Serial Channels (Synchronous/Asynchronous and

High-Speed-Synchronous) – On-Chip CAN Interface (Rev. 2.0B active) with 15 Message Objects

(Full CAN / Basic CAN)

• Up to 16 Mbytes External Address Space for Code and Data – Programmable External Bus Characteristics for Different Address Ranges – Multiplexed or Demultiplexed External Address/Data Buses with 8-Bit or 16-Bit

Data Bus Width – Five Programmable Chip-Select Signals – Hold- and Hold-Acknowledge Bus Arbitration Support

• Idle and Power Down Modes

• Programmable Watchdog Timer and Oscillator Watchdog

Data Sheet 4 V3.3, 2005-02

C167CR

C167SR

Summary of Features

• Up to 111 General Purpose I/O Lines, partly with Selectable Input Thresholds and Hysteresis

• Supported by a Large Range of Development Tools like C-Compilers, Macro-Assembler Packages, Emulators, Evaluation Boards, HLL-Debuggers, Simulators, Logic Analyzer Disassemblers, Programming Boards

• On-Chip Bootstrap Loader

• 144-Pin MQFP Package

• 176-Pin BGA Package

Ordering Information

The ordering code for Infineon microcontrollers provides an exact reference to the required product. This ordering code identifies:

• the derivative itself, i.e. its function set, the temperature range, and the supply voltage

• the package and the type of delivery.

1)

For the available ordering codes for the C167CR please refer to the “Product Catalog Microcontrollers”, which summarizes all available microcontroller variants.

Note: The ordering codes for Mask-ROM versions are defined for each product after

verification of the respective ROM code.

This document describes several derivatives of the C167 group. Table 1 enumerates these derivatives and summarizes the differences. As this document refers to all of these derivatives, some descriptions may not apply to a specific product.

For simplicity all versions are referred to by the term C167CR throughout this document.

1) The external connections of the C167CR in P-BGA-176-2 are referred to as pins throughout this document,

although they are mechanically realized as solder balls.

Data Sheet 5 V3.3, 2005-02

Table 1 C167CR Derivative Synopsis

Derivative

1)

Program

XRAM Size Operating

ROM Size

C167CR

C167SR

Summary of Features

Package

Frequency

SAK-C167SR-LM

– 2 Kbytes 25 MHz P-MQFP-144-8

SAB-C167SR-LM

SAK-C167SR-L33M

– 2 Kbytes 33 MHz P-MQFP-144-8

SAB-C167SR-L33M

SAK-C167CR-LM

– 2 Kbytes 25 MHz P-MQFP-144-8 SAF-C167CR-LM SAB-C167CR-LM

SAK-C167CR-L33M

– 2 Kbytes 33 MHz P-MQFP-144-8 SAB-C167CR-L33M

SAK-C167CR-4RM

32 Kbytes 2 Kbytes 25 MHz P-MQFP-144-8 SAB-C167CR-4RM

SAK-C167CR-4R33M

32 Kbytes 2 Kbytes 33 MHz P-MQFP-144-8 SAB-C167CR-4R33M

SAK-C167CR-16RM 128 Kbytes 2 Kbytes 25 MHz P-MQFP-144-8

SAK-C167CR-16R33M 128 Kbytes 2 Kbytes 33 MHz P-MQFP-144-8

SAK-C167CR-LE – 2 Kbytes 25 MHz P-BGA-176-2

1) This Data Sheet is valid for devices manufactured in 0.5 µm technology, i.e. devices starting with and including

design step GA(-T)6.

Data Sheet 6 V3.3, 2005-02

C167CR

C167SR

General Device Information

2 General Device Information

2.1 Introduction

The C167CR derivatives are high performance derivatives of the Infineon C166 Family of full featured single-chip CMOS microcontrollers. They combine high CPU performance (up to 16.5 million instructions per second) with high peripheral functionality and enhanced IO-capabilities. They also provide clock generation via PLL and various on-chip memory modules such as program ROM, internal RAM, and extension RAM.

V

AREF AGND

V

DDVSS

XTAL1 XTAL2

RSTIN RSTOUT

NMI

EA

READY

ALE RD WR/WRL

Port 5 16 Bit

Figure 1 Logic Symbol

C167CR

Port 0 16 Bit

Port 1 16 Bit

Port 2 16 Bit

Port 3 15 Bit

Port 4 8 Bit

Port 6 8 Bit

Port 7 8 Bit

Port 8 8 Bit

MCL04411

Data Sheet 7 V3.3, 2005-02

C167CR

C167SR

General Device Information

2.2 Pin Configuration and Definition for P-MQFP-144-8

The pins of the C167CR are described in detail in Table 2, including all their alternate functions. Figure 2 summarizes all pins in a condensed way, showing their location on the 4 sides of the package.

Note: The P-BGA-176-2 is described in Table 3 and Figure 3.

P6.0/CS0 P6.1/CS1 P6.2/CS2 P6.3/CS3 P6.4/CS4

P6.5/HOLD

P6.6/HLDA

P6.7/BREQ P8.0/CC16IO P8.1/CC17IO P8.2/CC18IO P8.3/CC19IO P8.4/CC20IO P8.5/CC21IO P8.6/CC22IO P8.7/CC23IO

V V

P7.0/POUT0 P7.1/POUT1 P7.2/POUT2

P7.3/POUT3 P7.4/CC28IO P7.5/CC29IO P7.6/CC30IO P7.7/CC31IO

P5.0/AN0 P5.1/AN1 P5.2/AN2 P5.3/AN3 P5.4/AN4 P5.5/AN5 P5.6/AN6 P5.7/AN7 P5.8/AN8 P5.9/AN9

SS

VDDV

144

143

1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17

DD

18

SS

19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36

373839

AREF

AGND

V

SS

RSTIN

RSTOUT

NMI

142

141

404142

P5.11/AN11/T5EUD

P5.10/AN10/T6EUD

XTAL2

V

XTAL1

139

140

138

137

434445

P5.13/AN13/T5IN

P5.12/AN12/T6IN

P5.15/AN15/T2EUD

P5.14/AN14/T4EUD

DD

V

136

SS

V

P1H.4/A12/CC24IO

P1H.5/A13/CC25IO

P1H.6/A14/CC26IO

P1H.7/A15/CC27IO

133

135

134

132

464748

495051

DD

V

P2.2/CC2IO

P2.1/CC1IO

P2.0/CC0IO

P1H.0/A8

P1H.1/A9

P1H.2/A10

P1H.3/A11

130

131

129

128

C167CR

525354

P2.6/CC6IO

P2.5/CC5IO

P2.4/CC4IO

P2.3/CC3IO

DD

P1L.6/A6

VSSV

P1L.7/A7

127

124

126

125

555657

SS

DD

V

P2.7/CC7IO

P2.8/CC8IO/EX0IN

P1L.0/A0

P1L.1/A1

P1L.2/A2

P1L.3/A3

P1L.4/A4

P1L.5/A5

121

123

122

585960

P2.9/CC9IO/EX1IN

P2.10/CC10IO/EX2IN

118

120

119

616263

P2.14/CC14IO/EX6IN

P2.13/CC13IO/EX5IN

P2.12/CC12IO/EX4IN

P2.11/CC11IO/EX3IN

P0H.7/AD15

115

117

116

114

646566

676869

P3.0/T0IN

P3.2/CAPIN

P3.1/T6OUT

P2.15/CC15IO/EX7IN/T7IN

VSSV

112

113

111

110

707172

SS

V

P3.5/T4IN

P3.4/T3EUD

P3.3/T3OUT

109

108 107 106 105 104 103 102 101 100

V

P0H.1/AD9

P0H.2/AD10

P0H.3/AD11

P0H.4/AD12

P0H.5/AD13

P0H.6/AD14

DD

P0H.0/AD8 P0L.7/AD7 P0L.6/AD6 P0L.5/AD5 P0L.4/AD4 P0L.3/AD3 P0L.2/AD2 P0L.1/AD1 P0L.0/AD0 EA

99

ALE

98

READY

97 96

WR/WRL

95

RD

94

V

SS

93

V

DD

92

P4.7/A23 P4.6/A22/CAN1_TxD

91 90

P4.5/A21/CAN1_RxD

89

P4.4/A20

88

P4.3/A19 P4.2/A18

87

P4.1/A17

86

P4.0/A16

85

OWE

84 83

V

SS

82

V

DD

81

P3.15/CLKOUT

80

P3.13/SCLK

79

P3.12/BHE/WRH

78

P3.11/RxD0

77

P3.10/TxD0 P3.9/MTSR

76

P3.8/MRST

75

P3.7/T2IN

74

P3.6/T3IN

73

DD

MCP04410

Figure 2 Pin Configuration P-MQFP-144-8 (top view)

Data Sheet 8 V3.3, 2005-02

General Device Information

Table 2 Pin Definitions and Functions P-MQFP-144-8

C167CR

C167SR

Symbol Pin

No.

P6

P6.0 P6.1 P6.2 P6.3 P6.4 P6.5 P6.6

P6.7

1 2 3 4 5 6 7

8

P8

P8.0 P8.1 P8.2 P8.3 P8.4 P8.5 P8.6 P8.7

9 10 11 12 13 14 15 16

Input Outp.

IO

O O O O O I I/O

O

IO

I/O I/O I/O I/O I/O I/O I/O I/O

Function

Port 6 is an 8-bit bidirectional I/O port. It is bit-wise programmable for input or output via direction bits. For a pin configured as input, the output driver is put into highimpedance state. Port 6 outputs can be configured as push/pull or open drain drivers. The input threshold of Port 6 is selectable (TTL or special). The Port 6 pins also serve for alternate functions: CS0 CS1 CS2 CS3 CS4 HOLD HLDA

Chip Select 0 Output Chip Select 1 Output Chip Select 2 Output Chip Select 3 Output Chip Select 4 Output External Master Hold Request Input Hold Acknowledge Output (master mode) or Input (slave mode)

BREQ

Bus Request Output

Port 8 is an 8-bit bidirectional I/O port. It is bit-wise programmable for input or output via direction bits. For a pin configured as input, the output driver is put into highimpedance state. Port 8 outputs can be configured as push/pull or open drain drivers. The input threshold of Port 8 is selectable (TTL or special). The following Port 8 pins also serve for alternate functions: CC16IO CAPCOM2: CC16 Capture Inp./Compare Outp. CC17IO CAPCOM2: CC17 Capture Inp./Compare Outp. CC18IO CAPCOM2: CC18 Capture Inp./Compare Outp. CC19IO CAPCOM2: CC19 Capture Inp./Compare Outp. CC20IO CAPCOM2: CC20 Capture Inp./Compare Outp. CC21IO CAPCOM2: CC21 Capture Inp./Compare Outp. CC22IO CAPCOM2: CC22 Capture Inp./Compare Outp. CC23IO CAPCOM2: CC23 Capture Inp./Compare Outp.

Data Sheet 9 V3.3, 2005-02

General Device Information

Table 2 Pin Definitions and Functions P-MQFP-144-8 (cont’d)

C167CR

C167SR

Symbol Pin

No.

P7

P7.0 P7.1 P7.2 P7.3 P7.4 P7.5 P7.6 P7.7

19 20 21 22 23 24 25 26

P5

P5.0 P5.1 P5.2 P5.3 P5.4 P5.5 P5.6 P5.7 P5.8 P5.9 P5.10 P5.11 P5.12 P5.13 P5.14 P5.15

27 28 29 30 31 32 33 34 35 36 39 40 41 42 43 44

Input Outp.

IO

O O O O I/O I/O I/O I/O

I

I I I I I I I I I I I I I I I I

Function

Port 7 is an 8-bit bidirectional I/O port. It is bit-wise programmable for input or output via direction bits. For a pin configured as input, the output driver is put into highimpedance state. Port 7 outputs can be configured as push/pull or open drain drivers. The input threshold of Port 7 is selectable (TTL or special). The following Port 7 pins also serve for alternate functions: POUT0 PWM Channel 0 Output POUT1 PWM Channel 1 Output POUT2 PWM Channel 2 Output POUT3 PWM Channel 3 Output CC28IO CAPCOM2: CC28 Capture Inp./Compare Outp. CC29IO CAPCOM2: CC29 Capture Inp./Compare Outp. CC30IO CAPCOM2: CC30 Capture Inp./Compare Outp. CC31IO CAPCOM2: CC31 Capture Inp./Compare Outp.

Port 5 is a 16-bit input-only port with Schmitt-Trigger characteristic. The pins of Port 5 also serve as analog input channels for the A/D converter, or they serve as timer inputs: AN0 AN1 AN2 AN3 AN4 AN5 AN6 AN7 AN8 AN9 AN10, T6EUD GPT2 Timer T6 Ext. Up/Down Ctrl. Inp. AN11, T5EUD GPT2 Timer T5 Ext. Up/Down Ctrl. Inp. AN12, T6IN GPT2 Timer T6 Count Inp. AN13, T5IN GPT2 Timer T5 Count Inp. AN14, T4EUD GPT1 Timer T4 Ext. Up/Down Ctrl. Inp. AN15, T2EUD GPT1 Timer T5 Ext. Up/Down Ctrl. Inp.

Data Sheet 10 V3.3, 2005-02

General Device Information

Table 2 Pin Definitions and Functions P-MQFP-144-8 (cont’d)

C167CR

C167SR

Symbol Pin

No.

P2

P2.0 P2.1 P2.2 P2.3 P2.4 P2.5 P2.6 P2.7 P2.8

P2.9

P2.10

P2.11

P2.12

P2.13

P2.14

P2.15

47 48 49 50 51 52 53 54 57

58

59

60

61

62

63

64

Input Outp.

IO

I/O I/O I/O I/O I/O I/O I/O I/O I/O I I/O I I/O I I/O I I/O I I/O I I/O I I/O I I

Function

Port 2 is a 16-bit bidirectional I/O port. It is bit-wise programmable for input or output via direction bits. For a pin configured as input, the output driver is put into highimpedance state. Port 2 outputs can be configured as push/pull or open drain drivers. The input threshold of Port 2 is selectable (TTL or special). The following Port 2 pins also serve for alternate functions: CC0IO CAPCOM1: CC0 Capture Inp./Compare Output CC1IO CAPCOM1: CC1 Capture Inp./Compare Output CC2IO CAPCOM1: CC2 Capture Inp./Compare Output CC3IO CAPCOM1: CC3 Capture Inp./Compare Output CC4IO CAPCOM1: CC4 Capture Inp./Compare Output CC5IO CAPCOM1: CC5 Capture Inp./Compare Output CC6IO CAPCOM1: CC6 Capture Inp./Compare Output CC7IO CAPCOM1: CC7 Capture Inp./Compare Output CC8IO CAPCOM1: CC8 Capture Inp./Compare Output, EX0IN Fast External Interrupt 0 Input CC9IO CAPCOM1: CC9 Capture Inp./Compare Output, EX1IN Fast External Interrupt 1 Input CC10IO CAPCOM1: CC10 Capture Inp./Compare Outp., EX2IN Fast External Interrupt 2 Input CC11IO CAPCOM1: CC11 Capture Inp./Compare Outp., EX3IN Fast External Interrupt 3 Input CC12IO CAPCOM1: CC12 Capture Inp./Compare Outp., EX4IN Fast External Interrupt 4 Input CC13IO CAPCOM1: CC13 Capture Inp./Compare Outp., EX5IN Fast External Interrupt 5 Input CC14IO CAPCOM1: CC14 Capture Inp./Compare Outp., EX6IN Fast External Interrupt 6 Input CC15IO CAPCOM1: CC15 Capture Inp./Compare Outp., EX7IN Fast External Interrupt 7 Input, T7IN CAPCOM2: Timer T7 Count Input

Data Sheet 11 V3.3, 2005-02

General Device Information

Table 2 Pin Definitions and Functions P-MQFP-144-8 (cont’d)

C167CR

C167SR

Symbol Pin

No.

P3

P3.0 P3.1 P3.2 P3.3 P3.4 P3.5 P3.6 P3.7 P3.8 P3.9 P3.10 P3.11 P3.12

P3.13 P3.15

65 66 67 68 69 70 73 74 75 76 77 78 79

80 81

Input Outp.

IO

I O I O I I I I I/O I/O O I/O O O I/O O

Function

Port 3 is a 15-bit bidirectional I/O port. It is bit-wise programmable for input or output via direction bits. For a pin configured as input, the output driver is put into highimpedance state. Port 3 outputs can be configured as push/pull or open drain drivers. The input threshold of Port 3 is selectable (TTL or special). The following Port 3 pins also serve for alternate functions: T0IN CAPCOM1 Timer T0 Count Input T6OUT GPT2 Timer T6 Toggle Latch Output CAPIN GPT2 Register CAPREL Capture Input T3OUT GPT1 Timer T3 Toggle Latch Output T3EUD GPT1 Timer T3 External Up/Down Control Input T4IN GPT1 Timer T4 Count/Gate/Reload/Capture Inp. T3IN GPT1 Timer T3 Count/Gate Input T2IN GPT1 Timer T2 Count/Gate/Reload/Capture Inp. MRST SSC Master-Receive/Slave-Transmit Inp./Outp. MTSR SSC Master-Transmit/Slave-Receive Outp./Inp. TxD0 ASC0 Clock/Data Output (Async./Sync.) RxD0 ASC0 Data Input (Async.) or Inp./Outp. (Sync.) BHE WRH

External Memory High Byte Enable Signal,

External Memory High Byte Write Strobe SCLK SSC Master Clock Output / Slave Clock Input. CLKOUT System Clock Output (= CPU Clock)

OWE (

V

PP

)

84 I Oscillator Watchdog Enable. This input enables the oscillator

watchdog when high or disables it when low e.g. for testing purposes. An internal pull-up device holds this input high if nothing is driving it. For normal operation pin OWE should be high or not connected. In order to drive pin OWE low draw a current of at least 200 µA.

Data Sheet 12 V3.3, 2005-02

General Device Information

Table 2 Pin Definitions and Functions P-MQFP-144-8 (cont’d)

C167CR

C167SR

Symbol Pin

No.

P4

Input Outp.

IO

Function

Port 4 is an 8-bit bidirectional I/O port. It is bit-wise programmable for input or output via direction bits. For a pin configured as input, the output driver is put into highimpedance state. Port 4 can be used to output the segment address lines and for serial bus interfaces:

P4.0 P4.1 P4.2 P4.3 P4.4 P4.5

P4.6

P4.7

85 86 87 88 89 90

91

92

O O O O O O I O O O

A16 Least Significant Segment Address Line A17 Segment Address Line A18 Segment Address Line A19 Segment Address Line A20 Segment Address Line A21 Segment Address Line, CAN1_RxD CAN 1 Receive Data Input A22 Segment Address Line, CAN1_TxD CAN 1 Transmit Data Output A23 Most Significant Segment Address Line

RD 95 O External Memory Read Strobe. RD

external instruction or data read access.

is activated for every

WR

/

WRL

96 O External Memory Write Strobe. In WR-mode this pin is

activated for every external data write access. In WRL

-mode this pin is activated for low byte data write accesses on a 16-bit bus, and for every data write access on an 8-bit bus. See WRCFG in register SYSCON for mode selection.

READY

97 I Ready Input. When the Ready function is enabled, a high

level at this pin during an external memory access will force the insertion of memory cycle time waitstates until the pin returns to a low level. An internal pull-up device will hold this pin high when nothing is driving it.

ALE 98 O Address Latch Enable Output. Can be used for latching the

address into external memory or an address latch in the multiplexed bus modes.

EA

99 I External Access Enable pin. A low level at this pin during and

after Reset forces the C167CR to begin instruction execution out of external memory. A high level forces execution out of the internal program memory. “ROMless” versions must have this pin tied to ‘0’.

Data Sheet 13 V3.3, 2005-02

General Device Information

Table 2 Pin Definitions and Functions P-MQFP-144-8 (cont’d)

C167CR

C167SR

Symbol Pin

No.

PORT0

P0L.0-7

100107

P0H.0-7

108, 111117

PORT1

P1L.0-7

118125

P1H.0-7

128135

P1H.4 P1H.5 P1H.6 P1H.7

132 133 134 135

Input

Function

Outp.

IO PORT0 consists of the two 8-bit bidirectional I/O ports P0L

and P0H. It is bit-wise programmable for input or output via direction bits. For a pin configured as input, the output driver is put into high-impedance state. In case of an external bus configuration, PORT0 serves as the address (A) and address/data (AD) bus in multiplexed bus modes and as the data (D) bus in demultiplexed bus modes.

Demultiplexed bus modes:

8-bit data bus: P0H = I/O, P0L = D7 - D0 16-bit data bus: P0H = D15 - D8, P0L = D7 - D0

Multiplexed bus modes:

8-bit data bus: P0H = A15 - A8, P0L = AD7 - AD0 16-bit data bus: P0H = AD15 - AD8, P0L = AD7 - AD0

IO

PORT1 consists of the two 8-bit bidirectional I/O ports P1L and P1H. It is bit-wise programmable for input or output via direction bits. For a pin configured as input, the output driver is put into high-impedance state. PORT1 is used as the 16-bit address bus (A) in demultiplexed bus modes and also after switching from a demultiplexed bus mode to a multiplexed bus mode. The following PORT1 pins also serve for alternate functions:

I I I I

CC24IO CAPCOM2: CC24 Capture Input CC25IO CAPCOM2: CC25 Capture Input CC26IO CAPCOM2: CC26 Capture Input CC27IO CAPCOM2: CC27 Capture Input

XTAL2 XTAL1

137 138

O I

XTAL2: Output of the oscillator amplifier circuit. XTAL1: Input to the oscillator amplifier and input to the

internal clock generator To clock the device from an external source, drive XTAL1, while leaving XTAL2 unconnected. Minimum and maximum high/low and rise/fall times specified in the AC Characteristics must be observed.

Data Sheet 14 V3.3, 2005-02

General Device Information

Table 2 Pin Definitions and Functions P-MQFP-144-8 (cont’d)

C167CR

C167SR

Symbol Pin

No.

Input Outp.

Function

RSTIN 140 I/O Reset Input with Schmitt-Trigger characteristics. A low level

at this pin while the oscillator is running resets the C167CR. An internal pull-up resistor permits power-on reset using only a capacitor connected to

V

SS

. A spike filter suppresses input pulses < 10 ns. Input pulses > 100 ns safely pass the filter. The minimum duration for a safe recognition should be 100 ns + 2 CPU clock cycles. In bidirectional reset mode (enabled by setting bit BDRSTEN in register SYSCON) the RSTIN

line is internally pulled low for the duration of the internal reset sequence upon any reset (HW, SW, WDT). See note below this table.

Note: To let the reset configuration of PORT0 settle and to let

the PLL lock a reset duration of ca. 1 ms is recommended.

RST OUT

141 O Internal Reset Indication Output. This pin is set to a low level

when the part is executing either a hardware-, a software- or a watchdog timer reset. RSTOUT

remains low until the EINIT

(end of initialization) instruction is executed.

NMI

V

AREF

V

AGND

142 I Non-Maskable Interrupt Input. A high to low transition at this

pin causes the CPU to vector to the NMI trap routine. When the PWRDN (power down) instruction is executed, the NMI pin must be low in order to force the C167CR to go into power down mode. If NMI

is high, when PWRDN is executed, the part will continue to run in normal mode. If not used, pin NMI

should be pulled high externally.

37 – Reference voltage for the A/D converter.

38 – Reference ground for the A/D converter.

Data Sheet 15 V3.3, 2005-02

General Device Information

Table 2 Pin Definitions and Functions P-MQFP-144-8 (cont’d)

C167CR

C167SR

Symbol Pin

No.

V

DD

17, 46, 56, 72, 82, 93,

Input

Function

Outp.

– Digital Supply Voltage:

+ 5 V during normal operation and idle mode. ≥ 2.5 V during power down mode.

109, 126, 136, 144

V

SS

18, 45,

– Digital Ground. 55, 71, 83, 94, 110, 127, 139, 143

Note: The following behavioural differences must be observed when the bidirectional

reset is active:

• Bit BDRSTEN in register SYSCON cannot be changed after EINIT and is cleared automatically after a reset.

• The reset indication flags always indicate a long hardware reset.

• The PORT0 configuration is treated as if it were a hardware reset. In particular, the bootstrap loader may be activated when P0L.4 is low.

•Pin RSTIN

may only be connected to external reset devices with an open drain output

driver.

• A short hardware reset is extended to the duration of the internal reset sequence.

Data Sheet 16 V3.3, 2005-02

C167CR

C167SR

General Device Information

2.3 Pin Configuration and Definition for P-BGA-176-2

The pins1) of the C167CR are described in detail in Table 3, including all their alternate functions. Figure 3 summarizes all pins in a condensed way, showing their location on the bottom of the package.

Note: The P-MQFP-144-8 is described in Table 2 and Figure 2.

1 2 3 4 5 6 7 8 9 1011121314

A

B

C

D

E

F

G

H

J

K

L

V

AREF

P5.11

V

AGND

P5.13

P5.12

V

SS

P2.1

V

DD

P2.7

V

P2.9 P2.10 P2.12

P2.13

P2.14

P2.15

P3.2 P3.12

SS

P5.0 P7.7

P5.2P5.5 P7.3

P5.4

P5.6P5.9

P5.3 P7.1

P5.1

P5.7P5.10

P5.14P5.15

P2.0 P2.2

P2.3

P2.4P2.6 P2.5

P2.8

V

DD

P2.11

P3.1

V

DD

V

SS

V

SS

P7.6

P7.5

P7.4

P4.2

V

P8.5

SS

V

P7.2

P7.0

P4.6

DD

P8.7

P8.6

RD P0.12 P0.11

P8.4P5.8

P8.2

P0.1

P8.0

P6.6

P6.2

P0.8

P6.4P6.7P8.1

P6.1

P6.5

V

P6.3P8.3

V

RST

P1.9 P1.12P1.10

P1.7

P1.4 P1.5

P0.14

P0.9

V

IN

SS

DD

RST OUT

V

SS

V

SS

P0.15

P0.13

P0.10

P6.0

XTAL2

P1.15

P1.8

P1.6

P1.2

NMIXTAL1

V

DD

P1.14

P1.13

P1.11

V

DD

P1.3

P1.1P1.0

A

B

C

D

E

F

G

H

J

K

L

M

N

P3.4 P3.7 P3.8 P3.10 P4.7

P

1 2 3 4 5 6 7 8 9 1011121314

P3.6

P3.11P3.3P3.0

P3.13

V

DD

P3.15

P4.1

OWE

P4.0P3.9P3.5

P4.5

P4.3

P4.4

V

EA

SS

WR P0.0 P0.4

REA

V

DD

DY

P0.3

ALE

P0.5

P0.2

V

DD

P0.7

P0.6

M

N

P

Not connected or thermal ground

mc_c167crle_pindiagram.vsd

Figure 3 Pin Configuration P-BGA-176-2 (top view)

1) The external connections of the C167CR in P-BGA-176-2 are referred to as pins throughout this document,

although they are mechanically realized as solder balls.

Data Sheet 17 V3.3, 2005-02

General Device Information

Table 3 Pin Definitions and Functions P-BGA-176-2

C167CR

C167SR

Symbol Pin

Num.

P5

P5.0 P5.1 P5.2 P5.3 P5.4 P5.5 P5.6 P5.7 P5.8 P5.9 P5.10 P5.11 P5.12 P5.13 P5.14 P5.15

A5 D5 A4 C5 B4 A3 C4 D4 B3 C3 D3 C1 D1 D2 E3 E2

Input Outp.

I

I I I I I I I I I I I I I I I I

Function

Port 5 is a 16-bit input-only port with Schmitt-Trigger characteristic. The pins of Port 5 also serve as analog input channels for the A/D converter, or they serve as timer inputs: AN0 AN1 AN2 AN3 AN4 AN5 AN6 AN7 AN8 AN9 AN10, T6EUD GPT2 Timer T6 Ext. Up/Down Ctrl. Inp. AN11, T5EUD GPT2 Timer T5 Ext. Up/Down Ctrl. Inp. AN12, T6IN GPT2 Timer T6 Count Inp. AN13, T5IN GPT2 Timer T5 Count Inp. AN14, T4EUD GPT1 Timer T4 Ext. Up/Down Ctrl. Inp. AN15, T2EUD GPT1 Timer T5 Ext. Up/Down Ctrl. Inp.

P7

P7.0 P7.1 P7.2 P7.3 P7.4 P7.5 P7.6 P7.7

D7 C7 B7 A7 D6 C6 B6 A6

IO

O O O O I/O I/O I/O I/O

Port 7 is an 8-bit bidirectional I/O port. It is bit-wise programmable for input or output via direction bits. For a pin configured as input, the output driver is put into highimpedance state. Port 7 outputs can be configured as push/pull or open drain drivers. The input threshold of Port 7 is selectable (TTL or special). The following Port 7 pins also serve for alternate functions: POUT0 PWM Channel 0 Output POUT1 PWM Channel 1 Output POUT2 PWM Channel 2 Output POUT3 PWM Channel 3 Output CC28IO CAPCOM2: CC28 Capture Inp./Compare Outp. CC29IO CAPCOM2: CC29 Capture Inp./Compare Outp. CC30IO CAPCOM2: CC30 Capture Inp./Compare Outp. CC31IO CAPCOM2: CC31 Capture Inp./Compare Outp.

Data Sheet 18 V3.3, 2005-02

General Device Information

Table 3 Pin Definitions and Functions P-BGA-176-2 (cont’d)

C167CR

C167SR

Symbol Pin

Num.

P8

P8.0 P8.1 P8.2 P8.3 P8.4 P8.5 P8.6 P8.7

B10 A10 D9 C9 B9 A9 D8 C8

P6

P6.0 P6.1 P6.2 P6.3 P6.4 P6.5 P6.6

P6.7

A13 B12 D10 C11 A12 B11 C10

A11

Input Outp.

IO

I/O I/O I/O I/O I/O I/O I/O I/O

IO

O O O O O I I/O

O

Function

Port 8 is an 8-bit bidirectional I/O port. It is bit-wise programmable for input or output via direction bits. For a pin configured as input, the output driver is put into highimpedance state. Port 8 outputs can be configured as push/pull or open drain drivers. The input threshold of Port 8 is selectable (TTL or special). The following Port 8 pins also serve for alternate functions: CC16IO CAPCOM2: CC16 Capture Inp./Compare Outp. CC17IO CAPCOM2: CC17 Capture Inp./Compare Outp. CC18IO CAPCOM2: CC18 Capture Inp./Compare Outp. CC19IO CAPCOM2: CC19 Capture Inp./Compare Outp. CC20IO CAPCOM2: CC20 Capture Inp./Compare Outp. CC21IO CAPCOM2: CC21 Capture Inp./Compare Outp. CC22IO CAPCOM2: CC22 Capture Inp./Compare Outp. CC23IO CAPCOM2: CC23 Capture Inp./Compare Outp.

Port 6 is an 8-bit bidirectional I/O port. It is bit-wise programmable for input or output via direction bits. For a pin configured as input, the output driver is put into highimpedance state. Port 6 outputs can be configured as push/pull or open drain drivers. The input threshold of Port 6 is selectable (TTL or special). The Port 6 pins also serve for alternate functions: CS0 CS1 CS2 CS3 CS4 HOLD HLDA

Chip Select 0 Output Chip Select 1 Output Chip Select 2 Output Chip Select 3 Output Chip Select 4 Output External Master Hold Request Input Hold Acknowledge Output (master mode) or Input (slave mode)

BREQ

Bus Request Output

NMI

C14 I Non-Maskable Interrupt Input. A high to low transition at this

pin causes the CPU to vector to the NMI trap routine. When the PWRDN (power down) instruction is executed, the NMI pin must be low in order to force the C167CR to go into power down mode. If NMI

is high, when PWRDN is executed, the part will continue to run in normal mode. If not used, pin NMI

Data Sheet 19 V3.3, 2005-02

should be pulled high externally.

General Device Information

Table 3 Pin Definitions and Functions P-BGA-176-2 (cont’d)

C167CR

C167SR

Symbol Pin

Num.

XTAL2 XTAL1

RST

D13 C13

D12 O Internal Reset Indication Output. This pin is set to a low level

OUT

RSTIN

E11 I/O Reset Input with Schmitt-Trigger characteristics. A low level

Input Outp.

O I

Function

XTAL2: Output of the oscillator amplifier circuit. XTAL1: Input to the oscillator amplifier and input to the

internal clock generator. To clock the device from an external source, drive XTAL1, while leaving XTAL2 unconnected. Minimum and maximum high/low and rise/fall times specified in the AC Characteristics must be observed.

when the part is executing either a hardware-, a software- or a watchdog timer reset. RSTOUT

remains low until the EINIT

(end of initialization) instruction is executed.

at this pin while the oscillator is running resets the C167CR. An internal pull-up resistor permits power-on reset using only a capacitor connected to

V

SS

. A spike filter suppresses input pulses < 10 ns. Input pulses > 100 ns safely pass the filter. The minimum duration for a safe recognition should be 100 ns + 2 CPU clock cycles. In bidirectional reset mode (enabled by setting bit BDRSTEN in register SYSCON) the RSTIN

line is internally pulled low for the duration of the internal reset sequence upon any reset (HW, SW, WDT). See note below this table.

Note: To let the reset configuration of PORT0 settle and to let

the PLL lock a reset duration of ca. 1 ms is recommended.

Data Sheet 20 V3.3, 2005-02

General Device Information

Table 3 Pin Definitions and Functions P-BGA-176-2 (cont’d)

C167CR

C167SR

Symbol Pin

Num.

PORT1

P1L.0-7

K13, K14, J13, J14, H11, H12, H13, G11

P1H.0-3

G13, F11, F12,

G14 P1H.4 P1H.5 P1H.6 P1H.7

F13

F14

E14

E13

Input Outp.

IO

I I I I

Function

PORT1 consists of the two 8-bit bidirectional I/O ports P1L and P1H. It is bit-wise programmable for input or output via direction bits. For a pin configured as input, the output driver is put into high-impedance state. PORT1 is used as the 16-bit address bus (A) in demultiplexed bus modes and also after switching from a demultiplexed bus mode to a multiplexed bus mode.

The following PORT1 pins also serve for alternate functions: CC24IO CAPCOM2: CC24 Capture Input CC25IO CAPCOM2: CC25 Capture Input CC26IO CAPCOM2: CC26 Capture Input CC27IO CAPCOM2: CC27 Capture Input

PORT0

P0L.0-7

P0H.0-7

RD

IO PORT0 consists of the two 8-bit bidirectional I/O ports P0L N10, L9, P11, M10, N11, M11, P12, N12 L10, K11, L12, L14, L13,

and P0H. It is bit-wise programmable for input or output via direction bits. For a pin configured as input, the output driver is put into high-impedance state. In case of an external bus configuration, PORT0 serves as the address (A) and address/data (AD) bus in multiplexed bus modes and as the data (D) bus in demultiplexed bus modes.

Demultiplexed bus modes:

8-bit data bus: P0H = I/O, P0L = D7 - D0 16-bit data bus: P0H = D15 - D8, P0L = D7 - D0

Multiplexed bus modes:

8-bit data bus: P0H = A15 - A8, P0L = AD7 - AD0

16-bit data bus: P0H = AD15 - AD8, P0L = AD7 - AD0 K12, J11, J12

L8 O External Memory Read Strobe. RD is activated for every

external instruction or data read access.

Data Sheet 21 V3.3, 2005-02

General Device Information

Table 3 Pin Definitions and Functions P-BGA-176-2 (cont’d)

C167CR

C167SR

Symbol Pin

Num.

Input Outp.

Function

EA M9 I External Access Enable pin. A low level at this pin during and

after Reset forces the C167CR to begin instruction execution

out of external memory. A high level forces execution out of

the internal program memory.

“ROMless” versions must have this pin tied to ‘0’.

WR

/

WRL

N9 O External Memory Write Strobe. In WR-mode this pin is

activated for every external data write access. In WRL

-mode this pin is activated for low byte data write accesses on a 16-bit bus, and for every data write access on an 8-bit bus. See WRCFG in register SYSCON for mode selection.

READY

P9 I Ready Input. When the Ready function is enabled, a high

level at this pin during an external memory access will force the insertion of memory cycle time waitstates until the pin returns to a low level. An internal pull-up device will hold this pin high when nothing is driving it.

ALE P10 O Address Latch Enable Output. Can be used for latching the

address into external memory or an address latch in the multiplexed bus modes.

P4

IO

Port 4 is an 8-bit bidirectional I/O port. It is bit-wise programmable for input or output via direction bits. For a pin configured as input, the output driver is put into highimpedance state. Port 4 can be used to output the segment address lines and for serial bus interfaces:

P4.0 P4.1 P4.2 P4.3 P4.4 P4.5

P4.6

P4.7

P6 M6 L6 N7 P7 M7

L7

N8

O O O O O O I O O O

A16 Least Significant Segment Address Line A17 Segment Address Line A18 Segment Address Line A19 Segment Address Line A20 Segment Address Line A21 Segment Address Line, CAN1_RxD CAN 1 Receive Data Input A22 Segment Address Line, CAN1_TxD CAN 1 Transmit Data Output A23 Most Significant Segment Address Line

Data Sheet 22 V3.3, 2005-02

General Device Information

Table 3 Pin Definitions and Functions P-BGA-176-2 (cont’d)

C167CR

C167SR

Symbol Pin

Num.

OWE (

V

PP

)

N6 I Oscillator Watchdog Enable. This input enables the oscillator

P3

P3.0 P3.1 P3.2 P3.3 P3.4 P3.5 P3.6 P3.7 P3.8 P3.9 P3.10 P3.11 P3.12

P3.13 P3.15

M1 K3 L2 M2 N1 P2 M3 N2 N3 P3 N4 M4 L4

P4 N5

Input Outp.

IO

I O I O I I I I I/O I/O O I/O O O I/O O

Function

watchdog when high or disables it when low e.g. for testing purposes. An internal pull-up device holds this input high if nothing is driving it. For normal operation pin OWE should be high or not connected. In order to drive pin OWE low draw a current of at least 200 µA.

Port 3 is a 15-bit bidirectional I/O port. It is bit-wise programmable for input or output via direction bits. For a pin configured as input, the output driver is put into highimpedance state. Port 3 outputs can be configured as push/pull or open drain drivers. The input threshold of Port 3 is selectable (TTL or special). The following Port 3 pins also serve for alternate functions: T0IN CAPCOM1 Timer T0 Count Input T6OUT GPT2 Timer T6 Toggle Latch Output CAPIN GPT2 Register CAPREL Capture Input T3OUT GPT1 Timer T3 Toggle Latch Output T3EUD GPT1 Timer T3 External Up/Down Control Input T4IN GPT1 Timer T4 Count/Gate/Reload/Capture Inp. T3IN GPT1 Timer T3 Count/Gate Input T2IN GPT1 Timer T2 Count/Gate/Reload/Capture Inp. MRST SSC Master-Receive/Slave-Transmit Inp./Outp. MTSR SSC Master-Transmit/Slave-Receive Outp./Inp. TxD0 ASC0 Clock/Data Output (Async./Sync.) RxD0 ASC0 Data Input (Async.) or Inp./Outp. (Sync.) BHE WRH

External Memory High Byte Enable Signal,

External Memory High Byte Write Strobe SCLK SSC Master Clock Output / Slave Clock Input. CLKOUT System Clock Output (= CPU Clock)

Data Sheet 23 V3.3, 2005-02

General Device Information

Table 3 Pin Definitions and Functions P-BGA-176-2 (cont’d)

C167CR

C167SR

Symbol Pin

Num.

P2

P2.0 P2.1 P2.2 P2.3 P2.4 P2.5 P2.6 P2.7 P2.8

P2.9

P2.10

P2.11

P2.12

P2.13

P2.14

P2.15

F3 F2 F4 G4 G3 G2 G1 H1 H4

J1

J2

J4

J3

K1

K2

L1

Input Outp.

IO

I/O I/O I/O I/O I/O I/O I/O I/O I/O I I/O I I/O I I/O I I/O I I/O I I/O I I/O I I

Function

Port 2 is a 16-bit bidirectional I/O port. It is bit-wise programmable for input or output via direction bits. For a pin configured as input, the output driver is put into highimpedance state. Port 2 outputs can be configured as push/pull or open drain drivers. The input threshold of Port 2 is selectable (TTL or special). The following Port 2 pins also serve for alternate functions: CC0IO CAPCOM1: CC0 Capture Inp./Compare Output CC1IO CAPCOM1: CC1 Capture Inp./Compare Output CC2IO CAPCOM1: CC2 Capture Inp./Compare Output CC3IO CAPCOM1: CC3 Capture Inp./Compare Output CC4IO CAPCOM1: CC4 Capture Inp./Compare Output CC5IO CAPCOM1: CC5 Capture Inp./Compare Output CC6IO CAPCOM1: CC6 Capture Inp./Compare Output CC7IO CAPCOM1: CC7 Capture Inp./Compare Output CC8IO CAPCOM1: CC8 Capture Inp./Compare Output, EX0IN Fast External Interrupt 0 Input CC9IO CAPCOM1: CC9 Capture Inp./Compare Output, EX1IN Fast External Interrupt 1 Input CC10IO CAPCOM1: CC10 Capture Inp./Compare Outp., EX2IN Fast External Interrupt 2 Input CC11IO CAPCOM1: CC11 Capture Inp./Compare Outp., EX3IN Fast External Interrupt 3 Input CC12IO CAPCOM1: CC12 Capture Inp./Compare Outp., EX4IN Fast External Interrupt 4 Input CC13IO CAPCOM1: CC13 Capture Inp./Compare Outp., EX5IN Fast External Interrupt 5 Input CC14IO CAPCOM1: CC14 Capture Inp./Compare Outp., EX6IN Fast External Interrupt 6 Input CC15IO CAPCOM1: CC15 Capture Inp./Compare Outp., EX7IN Fast External Interrupt 7 Input, T7IN CAPCOM2: Timer T7 Count Input

V

AREF

V

AGND

Data Sheet 24 V3.3, 2005-02

B2 – Reference voltage for the A/D converter.

C2 – Reference ground for the A/D converter.

General Device Information

Table 3 Pin Definitions and Functions P-BGA-176-2 (cont’d)

C167CR

C167SR

Symbol Pin

Num.

V

DD

B8, C12, D14, F1, H3, H14, K4, M5, M12, P8

V

SS

A8, D11, E1, E12, G12, H2, L3, L5, L11, M8

Input

Function

Outp.

– Digital Supply Voltage:

+ 5 V during normal operation and idle mode. ≥ 2.5 V during power down mode.

– Digital Ground.

Note: The following behavioural differences must be observed when the bidirectional

reset is active:

• Bit BDRSTEN in register SYSCON cannot be changed after EINIT and is cleared automatically after a reset.

• The reset indication flags always indicate a long hardware reset.

• The PORT0 configuration is treated as if it were a hardware reset. In particular, the bootstrap loader may be activated when P0L.4 is low.

•Pin RSTIN

may only be connected to external reset devices with an open drain output

driver.

• A short hardware reset is extended to the duration of the internal reset sequence.

Data Sheet 25 V3.3, 2005-02