INFINEON C167CS-4R, C167CS-L User Manual

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Data Sheet, V2.2, Aug. 2001

C167CS-4R C167CS-L

16-Bit Single-Chip Microcontroller

Microcontrollers

Never stop thinking.

Edition 2001-08

Published by Infineon Technologies AG, St.-Martin-Strasse 53, D-81541 München, Germany

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The information herein is given to describe certain components and shall not be considered as warranted characteristics.

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Data Sheet, V2.2, Aug. 2001

C167CS-4R C167CS-L

16-Bit Single-Chip Microcontroller

Microcontrollers

Never stop thinking.

C167CS

Revision History: 2001-08 V2.2

Previous Version: 2000-12 V2.1 (Intermediate version)

2000-06 V2.0 1999-06 1999-03 (Advance Information)

Page Subjects (major changes from V2.1, 2000-12 to V2.2, 2001-08)

4Figure2 corrected (pins 98, 99)

25, 27 Figure 5 and Figure 6 updated

50ff Output voltage/current specification improved

52f Limit values for

IDO

and I

increased due to the usage of a standard

PDR

oscillator

54 Figure 10 corrected

57 Figure 12 updated for 40 MHz

59 Clock parameters adjusted

60 TUE note includes P1H

76 Package drawing updated

Page Subjects (major changes from V2.0, 2000-06 to V2.1, 2000-12)

All Maximum operating frequency updated to 40 MHz

2 Derivative table updated

52 RSTIN

level for IDD corrected to VIL (was V

53 Current unit corrected to

µA

IL2

)

56 Input clock range adjusted

60f Note 5 detailed

64 Parameters

, tc12, tc13, tc14, tc15, tc16, tc17, tc18, tc19 changed

65 Relative bus timing parameters added

70 Parameter

changed, notes adapted

71 Notes adapted

72 Parameter tc

changed

75 Parameters

New package due to new assembly line. MQFP-144-1 for current deliveries only, will be discontinued.

, t43, t44, t46, t47 changed

Controller Area Network (CAN): License of Robert Bosch GmbH

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C167CS16-Bit Single-Chip Microcontroller

C166 Family

C167CS-4R, C167CS-L

• High Performance 16-bit CPU with 4-Stage Pipeline – 80/60/50 ns Instruction Cycle Time at 25/33/40 MHz CPU Clock – 400/303/250 ns Multiplication (16 – Enhanced Boolean Bit Manipulation Facilities – Additional Instructions to Support HLL and Operating Systems – Register-Based Design with Multiple Variable Register Banks – Single-Cycle Context Switching Support – 16 MBytes Total Linear Address Space for Code and Data – 1024 Bytes On-Chip Special Function Register Area

• 16-Priority-Level Interrupt System with 56 Sources, Sample-Rate down to 40/30/25 ns

• 8-Channel Interrupt-Driven Single-Cycle Data Transfer Facilities via Peripheral Event Controller (PEC)

• Clock Generation via on-chip PLL (factors 1:1.5/2/2.5/3/4/5), via prescaler or via direct clock input

• On-Chip Memory Modules – 3 KBytes On-Chip Internal RAM (IRAM) – 8 KBytes On-Chip Extension RAM (XRAM) – 32 KBytes On-Chip Program Mask ROM

• On-Chip Peripheral Modules – 24-Channel 10-bit A/D Converter with Programmable Conversion Time

down to 7.8 – Two 16-Channel Capture/Compare Units – 4-Channel PWM Unit – Two Multi-Functional General Purpose Timer Units with 5 Timers – Two Serial Channels (Synchronous/Asynchronous and High-Speed-Synchronous) – Two On-Chip CAN Interfaces (Rev. 2.0B active) with 2

(Full CAN/Basic CAN), can work on one bus with 30 objects – On-Chip Real Time Clock

• Up to 16 MBytes External Address Space for Code and Data – Programmable External Bus Characteristics for Different Address Ranges – Multiplexed or Demultiplexed External Address/Data Buses with 8-Bit or 16-Bit

Data Bus Width – Five Programmable Chip-Select Signals – Hold- and Hold-Acknowledge Bus Arbitration Support

• Idle, Sleep, and Power Down Modes with Flexible Power Management

• Programmable Watchdog Timer and Oscillator Watchdog

• Up to 111 General Purpose I/O Lines, partly with Selectable Input Thresholds and Hysteresis

µs

× 16 bit), 800/606/500 ns Division (32-/16-bit)

× 15 Message Objects

Data Sheet 1 V2.2, 2001-08

C167CS-4R

C167CS-L

• Supported by a Large Range of Development Tools like C-Compilers, Macro-Assembler Packages, Emulators, Evaluation Boards, HLL-Debuggers, Simulators, Logic Analyzer Disassemblers, Programming Boards

• On-Chip Bootstrap Loader

• 144-Pin MQFP Package

This document describes several derivatives of the C167 group. Table 1 enumerates these derivatives and summarizes the differences. As this document refers to all of these derivatives, some descriptions may not apply to a specific product.

Table 1 C167CS Derivative Synopsis

Derivative

Program Memory Operating Frequency

SAK-C167CS-LM

--- 25 MHz

SAB-C167CS-LM

SAK-C167CS-L33M

--- 33 MHz

SAB-C167CS-L33M

SAK-C167CS-L40M

--- 40 MHz

SAB-C167CS-L40M

SAK-C167CS-4RM

32 KByte ROM 25 MHz

SAB-C167CS-4RM

SAK-C167CS-4R33M

32 KByte ROM 33 MHz

SAB-C167CS-4R33M

SAK-C167CS-4R40M

32 KByte ROM 40 MHz

SAB-C167CS-4R40M

This Data Sheet is valid for devices starting with and including design step BA.

For simplicity all versions are referred to by the term C167CS throughout this document.

Data Sheet 2 V2.2, 2001-08

C167CS-4R

C167CS-L

Ordering Information

The ordering code for Infineon microcontrollers provides an exact reference to the required product. This ordering code identifies:

• the derivative itself, i.e. its function set, the temperature range, and the supply voltage

• the package and the type of delivery.

For the available ordering codes for the C167CS please refer to the “Product Catalog Microcontrollers”, which summarizes all available microcontroller variants.

Note: The ordering codes for Mask-ROM versions are defined for each product after

verification of the respective ROM code.

Introduction

The C167CS derivatives are high performance derivatives of the Infineon C166 Family of full featured single-chip CMOS microcontrollers. They combine high CPU performance (up to 20 million instructions per second) with high peripheral functionality and enhanced IO-capabilities. They also provide clock generation via PLL and various on-chip memory modules such as program ROM, internal RAM, and extension RAM.

XTAL1 XTAL2

RSTIN RSTOUT

NMI

READY

ALE RD WR/WRL

Port 5 16 Bit

AREF AGND

C167CS

DDVSS

MCL04411

Port 0 16 Bit

Port 1 16 Bit

Port 2 16 Bit

Port 3 15 Bit

Port 4 8 Bit

Port 6 8 Bit

Port 7 8 Bit

Port 8 8 Bit

Figure 1 Logic Symbol

Data Sheet 3 V2.2, 2001-08

Pin Configuration

(top view)

C167CS-4R

C167CS-L

P6.0/CS0 P6.1/CS1 P6.2/CS2 P6.3/CS3

P6.4/CS4 P6.5/HOLD P6.6/HLDA P6.7/BREQ

*P8.0/CC16IO *P8.1/CC17IO *P8.2/CC18IO *P8.3/CC19IO

P8.4/CC20IO P8.5/CC21IO P8.6/CC22IO P8.7/CC23IO

V V

P7.0/POUT0 P7.1/POUT1 P7.2/POUT2

P7.3/POUT3 P7.4/CC28IO P7.5/CC29IO P7.6/CC30IO P7.7/CC31IO

P5.0/AN0 P5.1/AN1 P5.2/AN2 P5.3/AN3 P5.4/AN4 P5.5/AN5 P5.6/AN6 P5.7/AN7 P5.8/AN8 P5.9/AN9

NMI

RSTOUT

RSTIN

144

143

141

140

142

2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17

19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36

373839

404142

P5.12/AN12/T6IN

P5.10/AN10/T6EUD

P5.11/AN11/T5EUD

S S

XTAL1

P1H.7/A15/CC27IO

XTAL2

138

137

139

P5.13/AN13/T5IN

135

136

434445

464748

P5.14/AN14/T4EUD

P5.15/AN15/T2EUD

P1H.6/A14/CC26IO

P1H.5/A13/CC25IO

P1H.4/A12/CC24IO

P1H.3/A11

P1H.2/A10

P1H.1/A9

134

132

131

130

129

133

C167CS

495051

525354

P2.0/CC0IO

P2.1/CC1IO

P2.2/CC2IO

P2.3/CC3IO

P2.4/CC4IO

P2.5/CC5IO

S S

P1H.0/A8

128

126

127

555657

S S

P2.6/CC6IO

P2.7/CC7IO

P1L.7/A7/AN23

P1L.6/A6/AN22

P1L.5/A5/AN21

P1L.4/A4/AN20

P1L.3/A3/AN19

125

123

122

124

121

585960

D D

P2.8/CC8IO/EX0IN

P2.9/CC9IO/EX1IN

P2.10/CC10IO/EX2IN

P2.11/CC11IO/EX3IN

P1L.2/A2/AN18

P1L.1/A1/AN17

P1L.0/A0/AN16

P0H.7/AD15

P0H.6/AD14

P0H.5/AD13

P0H.4/AD12

120

119

117

116

646566

P3.0/T0IN

114

115

676869

P3.2/CAPIN

P3.1/T6OUT

118

616263

P2.12/CC12IO/EX4IN

P2.13/CC13IO/EX5IN

P2.14/CC14IO/EX6IN

P2.15/CC15IO/EX7IN/T7IN

P0H.3/AD11

P0H.2/AD10

P0H.1/AD9

113

111

110

112

707172

P3.5/T4IN

P3.3/T3OUT

P3.4/T3EUD

S S

109

108 107 106 105 104 103 102 101 100

P0H.0/AD8 P0L.7/AD7 P0L.6/AD6 P0L.5/AD5 P0L.4/AD4 P0L.3/AD3 P0L.2/AD2 P0L.1/AD1 P0L.0/AD0

ALE

READY

WR/WRL

P4.7/A23/*

92 91

P4.6/A22/*

P4.5/A21/*

P4.4/A20/*

P4.3/A19

P4.2/A18

P4.1/A17

P4.0/A16

N.C.

P3.15/CLKOUT/

FOUT P3.13/SCLK

80 79

P3.12/BHE/WRH

P3.111/RxD0

P3.10/TxD0

P3.9/MTSR

P3.8/MRST

P3.7/T2IN

P3.6/T3IN

MCP04431

Figure 2

*) The marked pins of Port 4 and Port 8 can have CAN interface lines assigned to them.

Table 2 on the pages below lists the possible assignments.

Data Sheet 4 V2.2, 2001-08

Table 2 Pin Definitions and Functions

C167CS-4R

C167CS-L

Symbol Pin

Num.

P6.0 P6.1 P6.2 P6.3 P6.4 P6.5 P6.6

P6.7

1 2 3 4 5 6 7

P8.0

P8.1

P8.2

P8.3

P8.4 P8.5 P8.6 P8.7

13 14 15 16

Input Outp.

O O O O O I I/O

I/O I I I/O O O I/O I I I/O I I I/O I/O I/O I/O

Function

Port 6 is an 8-bit bidirectional I/O port. It is bit-wise programmable for input or output via direction bits. For a pin configured as input, the output driver is put into highimpedance state. Port 6 outputs can be configured as push/ pull or open drain drivers. The Port 6 pins also serve for alternate functions: CS0 CS1 CS2 CS3 CS4 HOLD HLDA

Chip Select 0 Output Chip Select 1 Output Chip Select 2 Output Chip Select 3 Output Chip Select 4 Output External Master Hold Request Input Hold Acknowledge Output (master mode) or Input (slave mode)

BREQ

Bus Request Output

Port 8 is an 8-bit bidirectional I/O port. It is bit-wise programmable for input or output via direction bits. For a pin configured as input, the output driver is put into highimpedance state. Port 8 outputs can be configured as push/ pull or open drain drivers. The input threshold of Port 8 is selectable (TTL or special). Port 8 pins provide inputs/ outputs for CAPCOM2 and serial interface lines.

CC16IO CAPCOM2: CC16 Capture Inp./Compare Outp., CAN1_RxD CAN 1 Receive Data Input, CAN2_RxD CAN 2 Receive Data Input CC17IO CAPCOM2: CC17 Capture Inp./Compare Outp., CAN1_TxD CAN 1 Transmit Data Output, CAN2_TxD CAN 2 Transmit Data Output CC18IO CAPCOM2: CC18 Capture Inp./Compare Outp., CAN1_RxD CAN 1 Receive Data Input, CAN2_RxD CAN 2 Receive Data Input CC19IO CAPCOM2: CC19 Capture Inp./Compare Outp., CAN1_TxD CAN 1 Transmit Data Output, CAN2_TxD CAN 2 Transmit Data Output CC20IO CAPCOM2: CC20 Capture Inp./Compare Outp. CC21IO CAPCOM2: CC21 Capture Inp./Compare Outp. CC22IO CAPCOM2: CC22 Capture Inp./Compare Outp. CC23IO CAPCOM2: CC23 Capture Inp./Compare Outp.

Data Sheet 5 V2.2, 2001-08

Table 2 Pin Definitions and Functions (cont’d)

C167CS-4R

C167CS-L

Symbol Pin

Num.

P7.0 P7.1 P7.2 P7.3 P7.4 P7.5 P7.6 P7.7

P5.0 P5.1 P5.2 P5.3 P5.4 P5.5 P5.6 P5.7 P5.8 P5.9 P5.10 P5.11 P5.12 P5.13 P5.14 P5.15

19 20 21 22 23 24 25 26

27 28 29 30 31 32 33 34 35 36 39 40 41 42 43 44

Input Outp.

O O O O I/O I/O I/O I/O

I I I I I I I I I I I I I I I I

Function

Port 7 is an 8-bit bidirectional I/O port. It is bit-wise programmable for input or output via direction bits. For a pin configured as input, the output driver is put into highimpedance state. Port 7 outputs can be configured as push/ pull or open drain drivers. The input threshold of Port 7 is selectable (TTL or special). The following Port 7 pins also serve for alternate functions: POUT0 PWM Channel 0 Output POUT1 PWM Channel 1 Output POUT2 PWM Channel 2 Output POUT3 PWM Channel 3 Output CC28IO CAPCOM2: CC28 Capture Inp./Compare Outp. CC29IO CAPCOM2: CC29 Capture Inp./Compare Outp. CC30IO CAPCOM2: CC30 Capture Inp./Compare Outp. CC31IO CAPCOM2: CC31 Capture Inp./Compare Outp.

Port 5 is a 16-bit input-only port with Schmitt-Trigger char. The pins of Port 5 also serve as analog input channels for the A/D converter, or they serve as timer inputs: AN0 AN1 AN2 AN3 AN4 AN5 AN6 AN7 AN8 AN9 AN10, T6EUD GPT2 Timer T6 Ext. Up/Down Ctrl. Inp. AN11, T5EUD GPT2 Timer T5 Ext. Up/Down Ctrl. Inp. AN12, T6IN GPT2 Timer T6 Count Inp. AN13, T5IN GPT2 Timer T5 Count Inp. AN14, T4EUD GPT1 Timer T4 Ext. Up/Down Ctrl. Inp. AN15, T2EUD GPT1 Timer T2 Ext. Up/Down Ctrl. Inp.

Data Sheet 6 V2.2, 2001-08

Table 2 Pin Definitions and Functions (cont’d)

C167CS-4R

C167CS-L

Symbol Pin

Num.

P2.0 P2.1 P2.2 P2.3 P2.4 P2.5 P2.6 P2.7 P2.8

P2.9

P2.10

P2.11

P2.12

P2.13

P2.14

P2.15

47 48 49 50 51 52 53 54 57

Input Outp.

I/O I/O I/O I/O I/O I/O I/O I/O I/O I I/O I I/O I I/O I I/O I I/O I I/O I I/O I I

Function

Port 2 is a 16-bit bidirectional I/O port. It is bit-wise programmable for input or output via direction bits. For a pin configured as input, the output driver is put into highimpedance state. Port 2 outputs can be configured as push/ pull or open drain drivers. The input threshold of Port 2 is selectable (TTL or special). The following Port 2 pins also serve for alternate functions: CC0IO CAPCOM1: CC0 Capture Inp./Compare Output CC1IO CAPCOM1: CC1 Capture Inp./Compare Output CC2IO CAPCOM1: CC2 Capture Inp./Compare Output CC3IO CAPCOM1: CC3 Capture Inp./Compare Output CC4IO CAPCOM1: CC4 Capture Inp./Compare Output CC5IO CAPCOM1: CC5 Capture Inp./Compare Output CC6IO CAPCOM1: CC6 Capture Inp./Compare Output CC7IO CAPCOM1: CC7 Capture Inp./Compare Output CC8IO CAPCOM1: CC8 Capture Inp./Compare Output, EX0IN Fast External Interrupt 0 Input CC9IO CAPCOM1: CC9 Capture Inp./Compare Output, EX1IN Fast External Interrupt 1 Input CC10IO CAPCOM1: CC10 Capture Inp./Compare Outp., EX2IN Fast External Interrupt 2 Input CC11IO CAPCOM1: CC11 Capture Inp./Compare Outp., EX3IN Fast External Interrupt 3 Input CC12IO CAPCOM1: CC12 Capture Inp./Compare Outp., EX4IN Fast External Interrupt 4 Input CC13IO CAPCOM1: CC13 Capture Inp./Compare Outp., EX5IN Fast External Interrupt 5 Input CC14IO CAPCOM1: CC14 Capture Inp./Compare Outp., EX6IN Fast External Interrupt 6 Input CC15IO CAPCOM1: CC15 Capture Inp./Compare Outp., EX7IN Fast External Interrupt 7 Input, T7IN CAPCOM2: Timer T7 Count Input

Note: During Sleep Mode a spike filter on the EXnIN

interrupt inputs suppresses input pulses <10 ns. Input pulses >100 ns safely pass the filter.

Data Sheet 7 V2.2, 2001-08

Table 2 Pin Definitions and Functions (cont’d)

C167CS-4R

C167CS-L

Symbol Pin

Num.

P3.0 P3.1 P3.2 P3.3 P3.4 P3.5 P3.6 P3.7 P3.8 P3.9 P3.10 P3.11 P3.12

P3.13 P3.15

65 66 67 68 69 70 73 74 75 76 77 78 79

80 81

Input Outp.

I O I O I I I I I/O I/O O I/O O O I/O O O

Function

Port 3 is a 15-bit bidirectional I/O port. It is bit-wise programmable for input or output via direction bits. For a pin configured as input, the output driver is put into highimpedance state. Port 3 outputs can be configured as push/ pull or open drain drivers. The input threshold of Port 3 is selectable (TTL or special). The following Port 3 pins also serve for alternate functions: T0IN CAPCOM1 Timer T0 Count Input T6OUT GPT2 Timer T6 Toggle Latch Output CAPIN GPT2 Register CAPREL Capture Input T3OUT GPT1 Timer T3 Toggle Latch Output T3EUD GPT1 Timer T3 External Up/Down Control Input T4IN GPT1 Timer T4 Count/Gate/Reload/Capture Inp T3IN GPT1 Timer T3 Count/Gate Input T2IN GPT1 Timer T2 Count/Gate/Reload/Capture Inp MRST SSC Master-Receive/Slave-Transmit Inp./Outp. MTSR SSC Master-Transmit/Slave-Receive Outp./Inp. T

×D0 ASC0 Clock/Data Output (Async./Sync.)

×D0 ASC0 Data Input (Async.) or Inp./Outp. (Sync.)

BHE WRH SCLK SSC Master Clock Output / Slave Clock Input. CLKOUT System Clock Output (= CPU Clock) FOUT Programmable Frequency Output

External Memory High Byte Enable Signal, External Memory High Byte Write Strobe

N.C. 84 – This pin is not connected in the C167CS.

No connection to the PCB is required.

Data Sheet 8 V2.2, 2001-08

Table 2 Pin Definitions and Functions (cont’d)

C167CS-4R

C167CS-L

Symbol Pin

Num.

P4.0 P4.1 P4.2 P4.3 P4.4

P4.5

P4.6

P4.7

85 86 87 88 89

Input Outp.

O O O O O I O I O O O O I O I

Function

Port 4 is an 8-bit bidirectional I/O port. It is bit-wise programmable for input or output via direction bits. For a pin configured as input, the output driver is put into highimpedance state. The Port 4 outputs can be configured as push/pull or open drain drivers. The input threshold of Port 4 is selectable (TTL or special). Port 4 can be used to output the segment address lines and for serial interface lines:

A16 Least Significant Segment Address Line A17 Segment Address Line A18 Segment Address Line A19 Segment Address Line A20 Segment Address Line, CAN2_RxD CAN 2 Receive Data Input A21 Segment Address Line, CAN1_RxD CAN 1 Receive Data Input A22 Segment Address Line, CAN1_TxD CAN 1 Transmit Data Output, CAN2_TxD CAN 2 Transmit Data Output A23 Most Significant Segment Address Line, CAN1_RxD CAN 1 Receive Data Input, CAN2_TxD CAN 2 Transmit Data Output, CAN2_RxD CAN 2 Receive Data Input

95 O External Memory Read Strobe. RD is activated for every

external instruction or data read access.

WRL

96 O External Memory Write Strobe. In WR-mode this pin is

activated for every external data write access. In WRL

-mode this pin is activated for low byte data write accesses on a 16-bit bus, and for every data write access on an 8-bit bus. See WRCFG in register SYSCON for mode selection.

READY 97 I Ready Input. When the Ready function is enabled, a high

level at this pin during an external memory access will force the insertion of memory cycle time waitstates until the pin returns to a low level. An internal pullup device will hold this pin high when nothing is driving it.

Data Sheet 9 V2.2, 2001-08

Table 2 Pin Definitions and Functions (cont’d)

C167CS-4R

C167CS-L

Symbol Pin

Num.

ALE 98 O Address Latch Enable Output. Can be used for latching the

PORT0

P0L.0-7

P0H.0-7

99 I External Access Enable pin. A low level at this pin during and

100107 108, 111117

Input Outp.

IO PORT0 consists of the two 8-bit bidirectional I/O ports P0L

Function

address into external memory or an address latch in the multiplexed bus modes.

after Reset forces the C167CS to begin instruction execution out of external memory. A high level forces execution out of the internal program memory. “ROMless” versions must have this pin tied to ‘0’.

and P0H. It is bit-wise programmable for input or output via direction bits. For a pin configured as input, the output driver is put into high-impedance state. In case of an external bus configuration, PORT0 serves as the address (A) and address/data (AD) bus in multiplexed bus modes and as the data (D) bus in demultiplexed bus modes.

Demultiplexed bus modes:

Data Path Width: 8-bit 16-bit P0L.0 – P0L.7: D0 – D7 D0 – D7 P0H.0 – P0H.7: I/O D8 – D15

Multiplexed bus modes:

Data Path Width: 8-bit 16-bit P0L.0 – P0L.7: AD0 – AD7 AD0 – AD7 P0H.0 – P0H.7: A8 – A15 AD8 – AD15

Data Sheet 10 V2.2, 2001-08

Table 2 Pin Definitions and Functions (cont’d)

C167CS-4R

C167CS-L

Symbol Pin

Num.

PORT1

P1L.0-7

P1H.0-7

P1L.0 P1L.1 P1L.2 P1L.3 P1L.4 P1L.5 P1L.6 P1L.7 P1H.4 P1H.5 P1H.6 P1H.7

118125 128135

118 119 120 121 122 123 124 125 132 133 134 135

Input Outp.

I I I I I I I I I/O I/O I/O I/O

Function

PORT1 consists of the two 8-bit bidirectional I/O ports P1L and P1H. It is bit-wise programmable for input or output via direction bits. For a pin configured as input, the output driver is put into high-impedance state. PORT1 is used as the 16-bit address bus (A) in demultiplexed bus modes and also after switching from a demultiplexed bus mode to a multiplexed bus mode. The following PORT1 pins also serve for alternate functions: AN16 Analog Input Channel 16 AN17 Analog Input Channel 17 AN18 Analog Input Channel 18 AN19 Analog Input Channel 19 AN20 Analog Input Channel 20 AN21 Analog Input Channel 21 AN22 Analog Input Channel 22 AN23 Analog Input Channel 23 CC24IO CAPCOM2: CC24 Capture Inp./Compare Outp. CC25IO CAPCOM2: CC25 Capture Inp./Compare Outp. CC26IO CAPCOM2: CC26 Capture Inp./Compare Outp. CC27IO CAPCOM2: CC27 Capture Inp./Compare Outp.

XTAL2 XTAL1

137 138

O I

XTAL2: Output of the oscillator amplifier circuit. XTAL1: Input to the oscillator amplifier and input to

the internal clock generator To clock the device from an external source, drive XTAL1, while leaving XTAL2 unconnected. Minimum and maximum high/low and rise/fall times specified in the AC Characteristics must be observed.

Data Sheet 11 V2.2, 2001-08

Table 2 Pin Definitions and Functions (cont’d)

C167CS-4R

C167CS-L

Symbol Pin

Num.

Input Outp.

Function

RSTIN 140 I/O Reset Input with Schmitt-Trigger characteristics. A low level

at this pin while the oscillator is running resets the C167CS. An internal pullup resistor permits power-on reset using only a capacitor connected to

. A spike filter suppresses input pulses <10 ns. Input pulses >100 ns safely pass the filter. The minimum duration for a safe recognition should be 100 ns + 2 CPU clock cycles. In bidirectional reset mode (enabled by setting bit BDRSTEN in register SYSCON) the RSTIN

line is internally pulled low for the duration of the internal reset sequence upon any reset (HW, SW, WDT). See note below this table.

Note: To let the reset configuration of PORT0 settle and to

let the PLL lock a reset duration of ca. 1 ms is recommended.

RST OUT

141 O Internal Reset Indication Output. This pin is set to a low level

when the part is executing either a hardware-, a software- or a watchdog timer reset. RSTOUT

remains low until the EINIT

(end of initialization) instruction is executed.

NMI

AREF

AGND

142 I Non-Maskable Interrupt Input. A high to low transition at this

pin causes the CPU to vector to the NMI trap routine. When the PWRDN (power down) instruction is executed, the NMI pin must be low in order to force the C167CS to go into power down mode. If NMI

is high, when PWRDN is executed, the part will continue to run in normal mode. If not used, pin NMI

should be pulled high externally.

37 – Reference voltage for the A/D converter.

38 – Reference ground for the A/D converter.

Data Sheet 12 V2.2, 2001-08

Table 2 Pin Definitions and Functions (cont’d)

C167CS-4R

C167CS-L

Symbol Pin

Num.

17, 46, 56, 72, 82, 93,

Input

Function

Outp.

– Digital Supply Voltage:

+5 V during normal operation and idle mode.

≥2.5 V during power down mode.

109, 126, 136, 144

18, 45,

– Digital Ground. 55, 71, 83, 94, 110, 127, 139, 143

The CAN interface lines are assigned to ports P4 and P8 under software control. Within the CAN module several assignments can be selected.

Note: The following behaviour differences must be observed when the bidirectional reset

is active:

• Bit BDRSTEN in register SYSCON cannot be changed after EINIT and is cleared automatically after a reset.

• The reset indication flags always indicate a long hardware reset.

• The PORT0 configuration is treated like on a hardware reset. Especially the bootstrap

loader may be activated when P0L.4 is low.

• Pin RSTIN

may only be connected to external reset devices with an open drain output

driver.

• A short hardware reset is extended to the duration of the internal reset sequence.

Data Sheet 13 V2.2, 2001-08

C167CS-4R

C167CS-L

Functional Description

The architecture of the C167CS combines advantages of both RISC and CISC processors and of advanced peripheral subsystems in a very well-balanced way. In addition the on-chip memory blocks allow the design of compact systems with maximum performance.

Figure 3 gives an overview of the different on-chip components and of the advanced,

high bandwidth internal bus structure of the C167CS.

Note: All time specifications refer to a CPU clock of 40 MHz

(see definition in the AC Characteristics section).

ProgMem

ROM

32 KByte

XRAM

6+2 KByte

CAN2

Rev 2.0B active

CAN1

Rev 2.0B active

XBUS Control

Port 4

External Bus

Control

Port 6

Port 0

EBC

Instr. / Data

) x u

m e

it D

-B 6

(1 S U B X ip h

-C n O

Port 1

External Instr. / Data

Interrupt Controller

ADC

10-Bit

16+8

Channels

ASC0

(USART)

BRGen

Port 5 Port 3

C166-Core

CPU

SSC

(SPI)

BRGen

PEC

16-Level

Priority

Interrupt Bus

GPT

Data

IRAM

Internal

Dual Port

3 KByte

RAM

Osc / PLL

RTC WDT

Peripheral Data Bus

PWM CCOM1

Port 7

CCOM2

Port 8

MCB04323_7CS

XTAL

Port 2

Figure 3 Block Diagram

The program memory, the internal RAM (IRAM) and the set of generic peripherals are connected to the CPU via separate buses. A fourth bus, the XBUS, connects external resources as well as additional on-chip resources, the X-Peripherals (see Figure 3).

The XBUS resources (XRAM, CAN) of the C167CS can be individually enabled or disabled during initialization. Register XPERCON selects the required modules which are then enabled by setting the general X-Peripheral enable bit XPEN (SYSCON.2). Modules that are disabled consume neither address space nor port pins.

Note: The default value of register XPERCON after reset selects 2 KByte XRAM and

module CAN1, so the default XBUS resources are compatible with the C167CR.

Data Sheet 14 V2.2, 2001-08

C167CS-4R

C167CS-L

Memory Organization

The memory space of the C167CS is configured in a Von Neumann architecture which means that code memory, data memory, registers and I/O ports are organized within the same linear address space which includes 16 MBytes. The entire memory space can be accessed bytewise or wordwise. Particular portions of the on-chip memory have additionally been made directly bitaddressable.

The C167CS incorporates 32 KBytes of on-chip mask-programmable ROM (not in the ROM-less derivative, of course) for code or constant data. The 32 KBytes of the on-chip ROM can be mapped either to segment 0 or segment 1.

3 KBytes of on-chip Internal RAM (IRAM) are provided as a storage for user defined variables, for the system stack, general purpose register banks and even for code. A register bank can consist of up to 16 wordwide (R0 to R15) and/or bytewide (RL0, RH0, …, RL7, RH7) so-called General Purpose Registers (GPRs).

1024 bytes (2 Register areas (SFR space and ESFR space). SFRs are wordwide registers which are used for controlling and monitoring functions of the different on-chip units. Unused SFR addresses are reserved for future members of the C166 Family.

8 KBytes of on-chip Extension RAM (XRAM), organized as two blocks of 2 KByte and 6 KByte, respectively, are provided to store user data, user stacks, or code. The XRAM is accessed like external memory and therefore cannot be used for the system stack or for register banks and is not bitaddressable. The XRAM permits 16-bit accesses with maximum speed.

In order to meet the needs of designs where more memory is required than is provided on chip, up to 16 MBytes of external RAM and/or ROM can be connected to the microcontroller.

× 512 bytes) of the address space are reserved for the Special Function

Data Sheet 15 V2.2, 2001-08

C167CS-4R

C167CS-L

External Bus Controller

All of the external memory accesses are performed by a particular on-chip External Bus Controller (EBC). It can be programmed either to Single Chip Mode when no external memory is required, or to one of four different external memory access modes, which are as follows:

– 16-/18-/20-/24-bit Addresses, 16-bit Data, Demultiplexed – 16-/18-/20-/24-bit Addresses, 16-bit Data, Multiplexed – 16-/18-/20-/24-bit Addresses, 8-bit Data, Multiplexed – 16-/18-/20-/24-bit Addresses, 8-bit Data, Demultiplexed

In the demultiplexed bus modes, addresses are output on PORT1 and data is input/ output on PORT0 or P0L, respectively. In the multiplexed bus modes both addresses and data use PORT0 for input/output.

Important timing characteristics of the external bus interface (Memory Cycle Time, Memory Tri-State Time, Length of ALE and Read Write Delay) have been made programmable to allow the user the adaption of a wide range of different types of memories and external peripherals. In addition, up to 4 independent address windows may be defined (via register pairs ADDRSELx / BUSCONx) which control the access to different resources with different bus characteristics. These address windows are arranged hierarchically where BUSCON4 overrides BUSCON3 and BUSCON2 overrides BUSCON1. All accesses to locations not covered by these 4 address windows are controlled by BUSCON0.

Up to 5 external CS external glue logic. The C167CS offers the possibility to switch the CS unlatched mode. In this mode the internal filter logic is switched off and the CS are directly generated from the address. The unlatched CS CSCFG (SYSCON.6).

Access to very slow memories or memories with varying access times is supported via a particular ‘Ready’ function.

A HOLD resources with other bus masters. The bus arbitration is enabled by setting bit HLDEN in register PSW. After setting HLDEN once, pins P6.7 … P6.5 (BREQ are automatically controlled by the EBC. In Master Mode (default after reset) the HLDA pin is an output. By setting bit DP6.7 to ‘1’ the Slave Mode is selected where pin HLDA is switched to input. This allows to directly connect the slave controller to another master controller without glue logic.

For applications which require less than 16 MBytes of external memory space, this address space can be restricted to 1 MByte, 256 KByte, or to 64 KByte. In this case Port 4 outputs four, two, or no address lines at all. It outputs all 8 address lines, if an address space of 16 MBytes is used.

/HLDA protocol is available for bus arbitration and allows to share external

signals (4 windows plus default) can be generated in order to save

outputs to an

signals

mode is enabled by setting

, HLDA, HOLD)

Data Sheet 16 V2.2, 2001-08

C167CS-4R

C167CS-L

Note: When one or both of the on-chip CAN Modules are used with the interface lines

assigned to Port 4, the CAN lines override the segment address lines and the segment address output on Port 4 is therefore limited to 6/4 bits i.e. address lines A21/A19 … A16. CS addressable external memory.

Central Processing Unit (CPU)

The main core of the CPU consists of a 4-stage instruction pipeline, a 16-bit arithmetic and logic unit (ALU) and dedicated SFRs. Additional hardware has been spent for a separate multiply and divide unit, a bit-mask generator and a barrel shifter.

Based on these hardware provisions, most of the C167CS’s instructions can be executed in just one machine cycle which requires 50 ns at 40 MHz CPU clock. For example, shift and rotate instructions are always processed during one machine cycle independent of the number of bits to be shifted. All multiple-cycle instructions have been optimized so that they can be executed very fast as well: branches in 2 cycles, a 16 16 bit multiplication in 5 cycles and a 32-/16-bit division in 10 cycles. Another pipeline optimization, the so-called ‘Jump Cache’, allows reducing the execution time of repeatedly performed jumps in a loop from 2 cycles to 1 cycle.

lines can be used to increase the total amount of

ROM

CPU

SP STKOV STKUN

Exec. Unit

Instr. Ptr.

Instr. Reg.

4-Stage

Pipeline

PSW

SYSCON

BUSCON 0 BUSCON 1 BUSCON 2 BUSCON 3 BUSCON 4 ADDRSEL 4

Data Page Ptr. Code Seg. Ptr.

MDH

MDL

Mul/Div-HW

Bit-Mask Gen

ALU

(16-bit)

Barrel - Shifter

Context Ptr.

ADDRSEL 1 ADDRSEL 2 ADDRSEL 3

R15

General

Purpose

Registers

Internal

RAM

R15

MCB02147

Figure 4 CPU Block Diagram

Data Sheet 17 V2.2, 2001-08

C167CS-4R

C167CS-L

The CPU has a register context consisting of up to 16 wordwide GPRs at its disposal. These 16 GPRs are physically allocated within the on-chip RAM area. A Context Pointer (CP) register determines the base address of the active register bank to be accessed by the CPU at any time. The number of register banks is only restricted by the available internal RAM space. For easy parameter passing, a register bank may overlap others.

A system stack of up to 1024 words is provided as a storage for temporary data. The system stack is allocated in the on-chip RAM area, and it is accessed by the CPU via the stack pointer (SP) register. Two separate SFRs, STKOV and STKUN, are implicitly compared against the stack pointer value upon each stack access for the detection of a stack overflow or underflow.

The high performance offered by the hardware implementation of the CPU can efficiently be utilized by a programmer via the highly efficient C167CS instruction set which includes the following instruction classes:

– Arithmetic Instructions – Logical Instructions – Boolean Bit Manipulation Instructions – Compare and Loop Control Instructions – Shift and Rotate Instructions – Prioritize Instruction – Data Movement Instructions – System Stack Instructions – Jump and Call Instructions – Return Instructions – System Control Instructions – Miscellaneous Instructions

The basic instruction length is either 2 or 4 bytes. Possible operand types are bits, bytes and words. A variety of direct, indirect or immediate addressing modes are provided to specify the required operands.

Data Sheet 18 V2.2, 2001-08

C167CS-4R

C167CS-L

Interrupt System

With an interrupt response time within a range from just 5 to 12 CPU clocks (in case of internal program execution), the C167CS is capable of reacting very fast to the occurrence of non-deterministic events.

The architecture of the C167CS supports several mechanisms for fast and flexible response to service requests that can be generated from various sources internal or external to the microcontroller. Any of these interrupt requests can be programmed to being serviced by the Interrupt Controller or by the Peripheral Event Controller (PEC).

In contrast to a standard interrupt service where the current program execution is suspended and a branch to the interrupt vector table is performed, just one cycle is ‘stolen’ from the current CPU activity to perform a PEC service. A PEC service implies a single byte or word data transfer between any two memory locations with an additional increment of either the PEC source or the destination pointer. An individual PEC transfer counter is implicitly decremented for each PEC service except when performing in the continuous transfer mode. When this counter reaches zero, a standard interrupt is performed to the corresponding source related vector location. PEC services are very well suited, for example, for supporting the transmission or reception of blocks of data. The C167CS has 8 PEC channels each of which offers such fast interrupt-driven data transfer capabilities.

A separate control register which contains an interrupt request flag, an interrupt enable flag and an interrupt priority bitfield exists for each of the possible interrupt sources. Via its related register, each source can be programmed to one of sixteen interrupt priority levels. Once having been accepted by the CPU, an interrupt service can only be interrupted by a higher prioritized service request. For the standard interrupt processing, each of the possible interrupt sources has a dedicated vector location.

Fast external interrupt inputs are provided to service external interrupts with high precision requirements. These fast interrupt inputs feature programmable edge detection (rising edge, falling edge or both edges).

Software interrupts are supported by means of the ‘TRAP’ instruction in combination with an individual trap (interrupt) number.

Table 3 shows all of the possible C167CS interrupt sources and the corresponding

hardware-related interrupt flags, vectors, vector locations and trap (interrupt) numbers.

Note: Interrupt nodes which are not used by associated peripherals, may be used to

generate software controlled interrupt requests by setting the respective interrupt request bit (xIR).

Data Sheet 19 V2.2, 2001-08

Table 3 C167CS Interrupt Nodes

C167CS-4R

C167CS-L

Source of Interrupt or PEC Service Request

Request Flag

Enable Flag

Interrupt Vector

Vector Location

CAPCOM Register 0 CC0IR CC0IE CC0INT 00’0040

CAPCOM Register 1 CC1IR CC1IE CC1INT 00’0044

CAPCOM Register 2 CC2IR CC2IE CC2INT 00’0048

CAPCOM Register 3 CC3IR CC3IE CC3INT 00’004C

CAPCOM Register 4 CC4IR CC4IE CC4INT 00’0050

CAPCOM Register 5 CC5IR CC5IE CC5INT 00’0054

CAPCOM Register 6 CC6IR CC6IE CC6INT 00’0058

CAPCOM Register 7 CC7IR CC7IE CC7INT 00’005C

CAPCOM Register 8 CC8IR CC8IE CC8INT 00’0060

CAPCOM Register 9 CC9IR CC9IE CC9INT 00’0064

CAPCOM Register 10 CC10IR CC10IE CC10INT 00’0068

CAPCOM Register 11 CC11IR CC11IE CC11INT 00’006C

CAPCOM Register 12 CC12IR CC12IE CC12INT 00’0070

Trap Number

CAPCOM Register 13 CC13IR CC13IE CC13INT 00’0074

CAPCOM Register 14 CC14IR CC14IE CC14INT 00’0078

CAPCOM Register 15 CC15IR CC15IE CC15INT 00’007C

CAPCOM Register 16 CC16IR CC16IE CC16INT 00’00C0

CAPCOM Register 17 CC17IR CC17IE CC17INT 00’00C4

CAPCOM Register 18 CC18IR CC18IE CC18INT 00’00C8

CAPCOM Register 19 CC19IR CC19IE CC19INT 00’00CC

CAPCOM Register 20 CC20IR CC20IE CC20INT 00’00D0

CAPCOM Register 21 CC21IR CC21IE CC21INT 00’00D4

CAPCOM Register 22 CC22IR CC22IE CC22INT 00’00D8

CAPCOM Register 23 CC23IR CC23IE CC23INT 00’00DC

CAPCOM Register 24 CC24IR CC24IE CC24INT 00’00E0

CAPCOM Register 25 CC25IR CC25IE CC25INT 00’00E4

CAPCOM Register 26 CC26IR CC26IE CC26INT 00’00E8

CAPCOM Register 27 CC27IR CC27IE CC27INT 00’00EC

CAPCOM Register 28 CC28IR CC28IE CC28INT 00’00E0

CAPCOM Register 29 CC29IR CC29IE CC29INT 00’0110

Data Sheet 20 V2.2, 2001-08

Table 3 C167CS Interrupt Nodes (cont’d)

C167CS-4R

C167CS-L

Source of Interrupt or PEC Service Request

Request Flag

Enable Flag

Interrupt Vector

Vector Location

CAPCOM Register 30 CC30IR CC30IE CC30INT 00’0114

CAPCOM Register 31 CC31IR CC31IE CC31INT 00’0118

CAPCOM Timer 0 T0IR T0IE T0INT 00’0080

CAPCOM Timer 1 T1IR T1IE T1INT 00’0084

CAPCOM Timer 7 T7IR T7IE T7INT 00’00F4

CAPCOM Timer 8 T8IR T8IE T8INT 00’00F8

GPT1 Timer 2 T2IR T2IE T2INT 00’0088

GPT1 Timer 3 T3IR T3IE T3INT 00’008C

GPT1 Timer 4 T4IR T4IE T4INT 00’0090

GPT2 Timer 5 T5IR T5IE T5INT 00’0094

GPT2 Timer 6 T6IR T6IE T6INT 00’0098

GPT2 CAPREL Reg. CRIR CRIE CRINT 00’009C

A/D Conversion

ADCIR ADCIE ADCINT 00’00A0

Complete

Trap Number

A/D Overrun Error ADEIR ADEIE ADEINT 00’00A4

ASC0 Transmit S0TIR S0TIE S0TINT 00’00A8

ASC0 Transmit Buffer S0TBIR S0TBIE S0TBINT 00’011C

ASC0 Receive S0RIR S0RIE S0RINT 00’00AC

ASC0 Error S0EIR S0EIE S0EINT 00’00B0

SSC Transmit SCTIR SCTIE SCTINT 00’00B4

SSC Receive SCRIR SCRIE SCRINT 00’00B8

SSC Error SCEIR SCEIE SCEINT 00’00BC

PWM Channel 0 … 3 PWMIR PWMIE PWMINT 00’00FC

CAN Interface 1 XP0IR XP0IE XP0INT 00’0100

CAN Interface 2 XP1IR XP1IE XP1INT 00’0104

Unassigned node XP2IR XP2IE XP2INT 00’0108

PLL/OWD and RTC XP3IR XP3IE XP3INT 00’010C

Data Sheet 21 V2.2, 2001-08

C167CS-4R

C167CS-L

The C167CS also provides an excellent mechanism to identify and to process exceptions or error conditions that arise during run-time, so-called ‘Hardware Traps’. Hardware traps cause immediate non-maskable system reaction which is similar to a standard interrupt service (branching to a dedicated vector table location). The occurrence of a hardware trap is additionally signified by an individual bit in the trap flag register (TFR). Except when another higher prioritized trap service is in progress, a hardware trap will interrupt any actual program execution. In turn, hardware trap services can normally not be interrupted by standard or PEC interrupts.

Table 4 shows all of the possible exceptions or error conditions that can arise during run-

time:

Table 4 Hardware Trap Summary

Exception Condition Trap

Flag

Reset Functions:

– – Hardware Reset – Software Reset – W-dog Timer Overflow

Class A Hardware Traps:

– Non-Maskable Interrupt – Stack Overflow – Stack Underflow

NMI

STKOF

STKUF

Class B Hardware Traps:

– Undefined Opcode – Protected Instruction

UNDOPC

PRTFLT

Fault

– Illegal Word Operand

ILLOPA

Access

– Illegal Instruction

ILLINA

Access

– Illegal External Bus

ILLBUS

Access

Trap Vector

RESET RESET RESET

NMITRAP STOTRAP STUTRAP

BTRAP BTRAP

BTRAP

Vector Location

00’0000 00’0000 00’0000

00’0008 00’0010 00’0018

00’0028 00’0028

00’0028

Trap Number

Trap Priority

III III III

II II II

I I

Reserved –– [2C

Software Traps

–– Any – TRAP Instruction

–

]

[00’0000 00’01FC

–

[0B

]

Any

–

]

[00 7F

–

]

–

Current CPU

Priority in steps of 4

Data Sheet 22 V2.2, 2001-08

C167CS-4R

C167CS-L

Capture/Compare (CAPCOM) Units

The CAPCOM units support generation and control of timing sequences on up to 32 channels with a maximum resolution of 16 TCL. The CAPCOM units are typically used to handle high speed I/O tasks such as pulse and waveform generation, pulse width modulation (PMW), Digital to Analog (D/A) conversion, software timing, or time recording relative to external events.

Four 16-bit timers (T0/T1, T7/T8) with reload registers provide two independent time bases for the capture/compare register array.

The input clock for the timers is programmable to several prescaled values of the internal system clock, or may be derived from an overflow/underflow of timer T6 in module GPT2. This provides a wide range of variation for the timer period and resolution and allows precise adjustments to the application specific requirements. In addition, external count inputs for CAPCOM timers T0 and T7 allow event scheduling for the capture/compare registers relative to external events.

Both of the two capture/compare register arrays contain 16 dual purpose capture/ compare registers, each of which may be individually allocated to either CAPCOM timer T0 or T1 (T7 or T8, respectively), and programmed for capture or compare function. Each register has one port pin associated with it which serves as an input pin for triggering the capture function, or as an output pin to indicate the occurrence of a compare event.

When a capture/compare register has been selected for capture mode, the current contents of the allocated timer will be latched (‘capture’d) into the capture/compare register in response to an external event at the port pin which is associated with this register. In addition, a specific interrupt request for this capture/compare register is generated. Either a positive, a negative, or both a positive and a negative external signal transition at the pin can be selected as the triggering event. The contents of all registers which have been selected for one of the five compare modes are continuously compared with the contents of the allocated timers. When a match occurs between the timer value and the value in a capture/compare register, specific actions will be taken based on the selected compare mode.

Data Sheet 23 V2.2, 2001-08

C167CS-4R

C167CS-L

Table 5 Compare Modes (CAPCOM)

Compare Modes Function

Mode 0 Interrupt-only compare mode;

several compare interrupts per timer period are possible.

Mode 1 Pin toggles on each compare match;

several compare events per timer period are possible.

Mode 2 Interrupt-only compare mode;

only one compare interrupt per timer period is generated.

Mode 3 Pin set ‘1’ on match; pin reset ‘0’ on compare time overflow;

only one compare event per timer period is generated.

Double Register Mode

Two registers operate on one pin; pin toggles on each compare match; several compare events per timer period are possible.

Data Sheet 24 V2.2, 2001-08

C167CS-4R

C167CS-L

Reload Reg. TxREL

CPU

TxIN

GPT2 Timer T6

Over/Underflow

CCxIO

16 Capture Inputs

16 Compare Outputs

CCxIO

CPU

GPT2 Timer T6

Over/Underflow

2n : 1f

Input

Control

Mode

Control

(Capture

Compare)

Input

Control

CAPCOM Timer Tx

16-Bit

Capture/ Compare Registers

CAPCOM Timer Ty

Interrupt Request (TxIR)

16 Capture/Compare

Interrupt Request

Interrupt Request (TyIR)

x = 0, 7 y = 1, 8 n = 3 … 10

Reload Reg. TyREL

MCB02143B

Figure 5 CAPCOM Unit Block Diagram

PWM Module

The Pulse Width Modulation Module can generate up to four PWM output signals using edge-aligned or center-aligned PWM. In addition the PWM module can generate PWM burst signals and single shot outputs. The frequency range of the PWM signals covers 5 Hz to 20 MHz (referred to a CPU clock of 40 MHz), depending on the resolution of the PWM output signal. The level of the output signals is selectable and the PWM module can generate interrupt requests.

Data Sheet 25 V2.2, 2001-08

C167CS-4R

C167CS-L

General Purpose Timer (GPT) Unit

The GPT unit represents a very flexible multifunctional timer/counter structure which may be used for many different time related tasks such as event timing and counting, pulse width and duty cycle measurements, pulse generation, or pulse multiplication.

The GPT unit incorporates five 16-bit timers which are organized in two separate modules, GPT1 and GPT2. Each timer in each module may operate independently in a number of different modes, or may be concatenated with another timer of the same module.

Each of the three timers T2, T3, T4 of module GPT1 can be configured individually for one of four basic modes of operation, which are Timer, Gated Timer, Counter, and Incremental Interface Mode. In Timer Mode, the input clock for a timer is derived from the CPU clock, divided by a programmable prescaler, while Counter Mode allows a timer to be clocked in reference to external events. Pulse width or duty cycle measurement is supported in Gated Timer Mode, where the operation of a timer is controlled by the ‘gate’ level on an external input pin. For these purposes, each timer has one associated port pin (TxIN) which serves as gate or clock input. The maximum resolution of the timers in module GPT1 is 16 TCL.

The count direction (up/down) for each timer is programmable by software or may additionally be altered dynamically by an external signal on a port pin (TxEUD) to facilitate e.g. position tracking.

In Incremental Interface Mode the GPT1 timers (T2, T3, T4) can be directly connected to the incremental position sensor signals A and B via their respective inputs TxIN and TxEUD. Direction and count signals are internally derived from these two input signals, so the contents of the respective timer Tx corresponds to the sensor position. The third position sensor signal TOP0 can be connected to an interrupt input.

Timer T3 has an output toggle latch (T3OTL) which changes its state on each timer overflow/underflow. The state of this latch may be output on pin T3OUT e.g. for time out monitoring of external hardware components, or may be used internally to clock timers T2 and T4 for measuring long time periods with high resolution.

In addition to their basic operating modes, timers T2 and T4 may be configured as reload or capture registers for timer T3. When used as capture or reload registers, timers T2 and T4 are stopped. The contents of timer T3 is captured into T2 or T4 in response to a signal at their associated input pins (TxIN). Timer T3 is reloaded with the contents of T2 or T4 triggered either by an external signal or by a selectable state transition of its toggle latch T3OTL. When both T2 and T4 are configured to alternately reload T3 on opposite state transitions of T3OTL with the low and high times of a PWM signal, this signal can be constantly generated without software intervention.

Data Sheet 26 V2.2, 2001-08

C167CS-4R

C167CS-L

T2EUD

CPU

T2IN

CPU

T3IN

T3EUD

T4IN

CPU

T4EUD

n = 3 … 10

U/D

Interrupt

2n : 1f

Mode

Control

Mode

Control

Mode

Control

GPT1 Timer T2

Reload

Capture

Toggle FF

GPT1 Timer T3 T3OTL

U/D

Capture

Reload

GPT1 Timer T4

U/D

Request (T2IR)

Interrupt Request (T3IR)

T3OUT

Interrupt Request (T4IR)

MCT04825

Figure 6 Block Diagram of GPT1

With its maximum resolution of 8 TCL, the GPT2 module provides precise event control and time measurement. It includes two timers (T5, T6) and a capture/reload register (CAPREL). Both timers can be clocked with an input clock which is derived from the CPU clock via a programmable prescaler or with external signals. The count direction (up/ down) for each timer is programmable by software or may additionally be altered dynamically by an external signal on a port pin (TxEUD). Concatenation of the timers is supported via the output toggle latch (T6OTL) of timer T6, which changes its state on each timer overflow/underflow.

The state of this latch may be used to clock timer T5, and/or it may be output on pin T6OUT. The overflows/underflows of timer T6 can additionally be used to clock the CAPCOM timers T0 or T1, and to cause a reload from the CAPREL register. The CAPREL register may capture the contents of timer T5 based on an external signal transition on the corresponding port pin (CAPIN), and timer T5 may optionally be cleared

Data Sheet 27 V2.2, 2001-08

C167CS-4R

C167CS-L

after the capture procedure. This allows the C167CS to measure absolute time differences or to perform pulse multiplication without software overhead.

The capture trigger (timer T5 to CAPREL) may also be generated upon transitions of GPT1 timer T3’s inputs T3IN and/or T3EUD. This is especially advantageous when T3 operates in Incremental Interface Mode.

T5EUD

T5IN

CAPIN

T6IN

CPU

2n : 1f

Mode

Control

MUX

CT3

Mode

Control

Clear

Capture

U/D

GPT2 Timer T5

GPT2 CAPREL

GPT2 Timer T6

U/D

T6OTL

Interrupt Request

T6OUT

Other Timers

T6EUD

MCB03999

n = 2 … 9

Figure 7 Block Diagram of GPT2

Data Sheet 28 V2.2, 2001-08

C167CS-4R

C167CS-L

Real Time Clock

The Real Time Clock (RTC) module of the C167CS consists of a chain of 3 divider blocks, a fixed 8:1 divider, the reloadable 16-bit timer T14, and the 32-bit RTC timer (accessible via registers RTCH and RTCL). The RTC module is directly clocked with the on-chip oscillator frequency divided by 32 via a separate clock driver ( and is therefore independent from the selected clock generation mode of the C167CS. All timers count up.

The RTC module can be used for different purposes:

• System clock to determine the current time and date

• Cyclic time based interrupt

• 48-bit timer for long term measurements

RTC

= f

OSC

/32)

T14REL

Reload

T14 8:1

RTCLRTCH

RTC

Interrupt Request

MCD04432

Figure 8 RTC Block Diagram

Note: The registers associated with the RTC are not affected by a reset in order to

maintain the correct system time even when intermediate resets are executed.

Data Sheet 29 V2.2, 2001-08

C167CS-4R

C167CS-L

A/D Converter

For analog signal measurement, a 10-bit A/D converter with 24 multiplexed input channels (16 standard channels and 8 extension channels) and a sample and hold circuit has been integrated on-chip. It uses the method of successive approximation. The sample time (for loading the capacitors) and the conversion time is programmable and can so be adjusted to the external circuitry.

Overrun error detection/protection is provided for the conversion result register (ADDAT): either an interrupt request will be generated when the result of a previous conversion has not been read from the result register at the time the next conversion is complete, or the next conversion is suspended in such a case until the previous result has been read.

For applications which require less than 24 analog input channels, the remaining channel inputs can be used as digital input port pins.

The A/D converter of the C167CS supports four different conversion modes. In the standard Single Channel conversion mode, the analog level on a specified channel is sampled once and converted to a digital result. In the Single Channel Continuous mode, the analog level on a specified channel is repeatedly sampled and converted without software intervention. In the Auto Scan mode, the analog levels on a prespecified number of channels (standard or extension) are sequentially sampled and converted. In the Auto Scan Continuous mode, the number of prespecified channels is repeatedly sampled and converted. In addition, the conversion of a specific channel can be inserted (injected) into a running sequence without disturbing this sequence. This is called Channel Injection Mode.

The Peripheral Event Controller (PEC) may be used to automatically store the conversion results into a table in memory for later evaluation, without requiring the overhead of entering and exiting interrupt routines for each data transfer.

After each reset and also during normal operation the ADC automatically performs calibration cycles. This automatic self-calibration constantly adjusts the converter to changing operating conditions (e.g. temperature) and compensates process variations.

These calibration cycles are part of the conversion cycle, so they do not affect the normal operation of the A/D converter.

In order to decouple analog inputs from digital noise and to avoid input trigger noise those pins used for analog input can be disconnected from the digital IO or input stages under software control. This can be selected for each pin separately via registers P5DIDIS (Port 5 Digital Input Disable) and P1DIDIS (PORT1 Digital Input Disable).

Data Sheet 30 V2.2, 2001-08

C167CS-4R

C167CS-L

Serial Channels

Serial communication with other microcontrollers, processors, terminals or external peripheral components is provided by two serial interfaces with different functionality, an Asynchronous/Synchronous Serial Channel (ASC0) and a High-Speed Synchronous Serial Channel (SSC).

The ASC0 is upward compatible with the serial ports of the Infineon 8-bit microcontroller families and supports full-duplex asynchronous communication at up to 781 Kbit/s/

1.03 Mbit/s/1.25 Mbit/s and half-duplex synchronous communication at up to 3.1/

4.1 Mbit/s/5.0 Mbit/s (@ 25/33/40 MHz CPU clock). A dedicated baud rate generator allows to set up all standard baud rates without oscillator tuning. For transmission, reception and error handling 4 separate interrupt vectors are provided. In asynchronous mode, 8- or 9-bit data frames are transmitted or received, preceded by a start bit and terminated by one or two stop bits. For multiprocessor communication, a mechanism to distinguish address from data bytes has been included (8-bit data plus wake up bit mode). In synchronous mode, the ASC0 transmits or receives bytes (8 bits) synchronously to a shift clock which is generated by the ASC0. The ASC0 always shifts the LSB first. A loop back option is available for testing purposes. A number of optional hardware error detection capabilities has been included to increase the reliability of data transfers. A parity bit can automatically be generated on transmission or be checked on reception. Framing error detection allows to recognize data frames with missing stop bits. An overrun error will be generated, if the last character received has not been read out of the receive buffer register at the time the reception of a new character is complete.

The SSC supports full-duplex synchronous communication at up to 6.25/8.25/10 Mbit/s (@ 25/33/40 MHz CPU clock). It may be configured so it interfaces with serially linked peripheral components. A dedicated baud rate generator allows to set up all standard baud rates without oscillator tuning. For transmission, reception and error handling 3 separate interrupt vectors are provided. The SSC transmits or receives characters of 2 … 16 bits length synchronously to a shift clock which can be generated by the SSC (master mode) or by an external master (slave mode). The SSC can start shifting with the LSB or with the MSB and allows the selection of shifting and latching clock edges as well as the clock polarity. A number of optional hardware error detection capabilities has been included to increase the reliability of data transfers. Transmit and receive error supervise the correct handling of the data buffer. Phase and baudrate error detect incorrect serial data.

Data Sheet 31 V2.2, 2001-08

C167CS-4R

C167CS-L

CAN-Modules

The integrated CAN-Modules handle the completely autonomous transmission and reception of CAN frames in accordance with the CAN specification V2.0 part B (active), i.e. the on-chip CAN-Modules can receive and transmit standard frames with 11-bit identifiers as well as extended frames with 29-bit identifiers.

The modules provide Full CAN functionality on up to 15 message objects each. Message object 15 may be configured for Basic CAN functionality. Both modes provide separate masks for acceptance filtering which allows to accept a number of identifiers in Full CAN mode and also allows to disregard a number of identifiers in Basic CAN mode. All message objects can be updated independent from the other objects and are equipped for the maximum message length of 8 bytes.

The bit timing is derived from the XCLK and is programmable up to a data rate of 1 Mbit/ s. Each CAN-Module uses two pins of Port 4 or Port 8 to interface to an external bus transceiver. The interface pins are assigned via software.

Module CAN2 is identical with the first one, except that it uses a separate address area and a separate interrupt node.

The two CAN modules can be internally coupled by assigning their interface pins to the same two port pins, or they can interface to separate CAN buses.

Note: When any CAN interface is assigned to Port 4, the respective segment address

lines on Port 4 cannot be used. This will limit the external address space.

Watchdog Timer

The Watchdog Timer represents one of the fail-safe mechanisms which have been implemented to prevent the controller from malfunctioning for longer periods of time.

The Watchdog Timer is always enabled after a reset of the chip, and can only be disabled in the time interval until the EINIT (end of initialization) instruction has been executed. Thus, the chip’s start-up procedure is always monitored. The software has to be designed to service the Watchdog Timer before it overflows. If, due to hardware or software related failures, the software fails to do so, the Watchdog Timer overflows and generates an internal hardware reset and pulls the RSTOUT external hardware components to be reset.

The Watchdog Timer is a 16-bit timer, clocked with the system clock divided by 2/4/128/

256. The high byte of the Watchdog Timer register can be set to a prespecified reload value (stored in WDTREL) in order to allow further variation of the monitored time interval. Each time it is serviced by the application software, the high byte of the Watchdog Timer is reloaded. Thus, time intervals between 12.8 monitored (@ 40 MHz). The default Watchdog Timer interval after reset is 3.27 ms (@ 40 MHz).

pin low in order to allow

µs and 419 ms can be

Data Sheet 32 V2.2, 2001-08

C167CS-4R

C167CS-L

Parallel Ports

The C167CS provides up to 111 I/O lines which are organized into eight input/output ports and one input port. All port lines are bit-addressable, and all input/output lines are individually (bit-wise) programmable as inputs or outputs via direction registers. The I/O ports are true bidirectional ports which are switched to high impedance state when configured as inputs. The output drivers of five I/O ports can be configured (pin by pin) for push/pull operation or open-drain operation via control registers. During the internal reset, all port pins are configured as inputs.

The input threshold of Port 2, Port 3, Port 7, and Port 8 is selectable (TTL or CMOS like), where the special CMOS like input threshold reduces noise sensitivity due to the input hysteresis. The input threshold may be selected individually for each byte of the respective ports.

All port lines have programmable alternate input or output functions associated with them. All port lines that are not used for these alternate functions may be used as general purpose IO lines.

PORT0 and PORT1 may be used as address and data lines when accessing external memory, while Port 4 outputs the additional segment address bits A23/19/17 … A16 in systems where segmentation is enabled to access more than 64 KBytes of memory. Port 2, Port 8 and Port 7 (and parts of PORT1) are associated with the capture inputs or compare outputs of the CAPCOM units and/or with the outputs of the PWM module. Port 6 provides optional bus arbitration signals (BREQ signals. Port 3 includes alternate functions of timers, serial interfaces, the optional bus control signal BHE frequency output FOUT). Port 5 (and parts of PORT1) is used for the analog input channels to the A/D converter or timer control signals.

The edge characteristics (transition time) and driver characteristics (output current) of the C167CS’s port drivers can be selected via the Port Output Control registers (POCONx).

/WRH, and the system clock output CLKOUT (or the programmable

, HLDA, HOLD) and chip select

Data Sheet 33 V2.2, 2001-08

C167CS-4R

C167CS-L

Oscillator Watchdog

The Oscillator Watchdog (OWD) monitors the clock signal generated by the on-chip oscillator (either with a crystal or via external clock drive). For this operation the PLL provides a clock signal which is used to supervise transitions on the oscillator clock. This PLL clock is independent from the XTAL1 clock. When the expected oscillator clock transitions are missing the OWD activates the PLL Unlock/OWD interrupt node and supplies the CPU with the PLL clock signal. Under these circumstances the PLL will oscillate with its basic frequency.

In direct drive mode the PLL base frequency is used directly ( In prescaler mode the PLL base frequency is divided by 2 (

= 2 … 5 MHz).

CPU

= 1 … 2.5 MHz).

CPU

Note: The CPU clock source is only switched back to the oscillator clock after a

hardware reset.

The oscillator watchdog can be disabled by setting bit OWDDIS in register SYSCON. In this case (OWDDIS = ‘1’) the PLL remains idle and provides no clock signal, while the CPU clock signal is derived directly from the oscillator clock or via prescaler or SDD. Also no interrupt request will be generated in case of a missing oscillator clock.

Note: At the end of a reset bit OWDDIS reflects the inverted level of pin RD

at that time. Thus the oscillator watchdog may also be disabled via hardware by (externally) pulling the RD

line low upon a reset, similar to the standard reset configuration via

PORT0.

Data Sheet 34 V2.2, 2001-08

C167CS-4R

C167CS-L

Power Management

The C167CS provides several means to control the power it consumes either at a given time or averaged over a certain timespan. Three mechanisms can be used (partly in parallel):

• Power Saving Modes switch the C167CS into a special operating mode (control via instructions). Idle Mode stops the CPU while the peripherals can continue to operate. Sleep Mode and Power Down Mode stop all clock signals and all operation (RTC may optionally continue running). Sleep Mode can be terminated by external interrupt signals.

• Clock Generation Management controls the distribution and the frequency of internal and external clock signals (control via register SYSCON2). Slow Down Mode lets the C167CS run at a CPU clock frequency of for prescaler operation) which drastically reduces the consumed power. The PLL can be optionally disabled while operating in Slow Down Mode. External circuitry can be controlled via the programmable frequency output FOUT.

• Peripheral Management permits temporary disabling of peripheral modules (control via register SYSCON3). Each peripheral can separately be disabled/enabled. A group control option disables a major part of the peripheral set by setting one single bit.

/1 … 32 (half

OSC

The on-chip RTC supports intermittent operation of the C167CS by generating cyclic wakeup signals. This offers full performance to quickly react on action requests while the intermittent sleep phases greatly reduce the average power consumption of the system.

Data Sheet 35 V2.2, 2001-08

C167CS-4R

C167CS-L

Instruction Set Summary

Table 6 lists the instructions of the C167CS in a condensed way.

The various addressing modes that can be used with a specific instruction, the operation of the instructions, parameters for conditional execution of instructions, and the opcodes for each instruction can be found in the “C166 Family Instruction Set Manual”.

This document also provides a detailed description of each instruction.

Table 6 Instruction Set Summary

Mnemonic Description Bytes

ADD(B) Add word (byte) operands 2 / 4 ADDC(B) Add word (byte) operands with Carry 2 / 4 SUB(B) Subtract word (byte) operands 2 / 4 SUBC(B) Subtract word (byte) operands with Carry 2 / 4 MUL(U) (Un)Signed multiply direct GPR by direct GPR (16-16-bit) 2 DIV(U) (Un)Signed divide register MDL by direct GPR (16-/16-bit) 2 DIVL(U) (Un)Signed long divide reg. MD by direct GPR (32-/16-bit) 2 CPL(B) Complement direct word (byte) GPR 2 NEG(B) Negate direct word (byte) GPR 2 AND(B) Bitwise AND, (word/byte operands) 2 / 4 OR(B) Bitwise OR, (word/byte operands) 2 / 4 XOR(B) Bitwise XOR, (word/byte operands) 2 / 4 BCLR Clear direct bit 2 BSET Set direct bit 2 BMOV(N) Move (negated) direct bit to direct bit 4 BAND, BOR,

BXOR BCMP Compare direct bit to direct bit 4 BFLDH/L Bitwise modify masked high/low byte of bit-addressable

CMP(B) Compare word (byte) operands 2 / 4

AND/OR/XOR direct bit with direct bit 4

direct word memory with immediate data

CMPD1/2 Compare word data to GPR and decrement GPR by 1/2 2 / 4 CMPI1/2 Compare word data to GPR and increment GPR by 1/2 2 / 4 PRIOR Determine number of shift cycles to normalize direct

word GPR and store result in direct word GPR SHL / SHR Shift left/right direct word GPR 2 ROL / ROR Rotate left/right direct word GPR 2 ASHR Arithmetic (sign bit) shift right direct word GPR 2

Data Sheet 36 V2.2, 2001-08

C167CS-4R

C167CS-L

Table 6 Instruction Set Summary (cont’d)

Mnemonic Description Bytes

MOV(B) Move word (byte) data 2 / 4 MOVBS Move byte operand to word operand with sign extension 2 / 4 MOVBZ 2 / 4 JMPA, JMPI,

JMPR JMPS Jump absolute to a code segment 4 J(N)B Jump relative if direct bit is (not) set 4 JBC Jump relative and clear bit if direct bit is set 4 JNBS Jump relative and set bit if direct bit is not set 4 CALLA, CALLI,

CALLR CALLS Call absolute subroutine in any code segment 4 PCALL Push direct word register onto system stack and call

TRAP Call interrupt service routine via immediate trap number 2 PUSH, POP Push/pop direct word register onto/from system stack 2 SCXT Push direct word register onto system stack and update

RET Return from intra-segment subroutine 2

Move byte operand to word operand with zero extension

Jump absolute/indirect/relative if condition is met 4

Call absolute/indirect/relative subroutine if condition is met 4

absolute subroutine

RETS Return from inter-segment subroutine 2 RETP Return from intra-segment subroutine and pop direct

word register from system stack RETI Return from interrupt service subroutine 2 SRST Software Reset 4 IDLE Enter Idle Mode 4 PWRDN Enter Power Down Mode (supposes NMI SRVWDT Service Watchdog Timer 4 DISWDT Disable Watchdog Timer 4 EINIT Signify End-of-Initialization on RSTOUT ATOMIC Begin ATOMIC sequence 2 EXTR Begin EXTended Register sequence 2 EXTP(R) Begin EXTended Page (and Register) sequence 2 / 4 EXTS(R) Begin EXTended Segment (and Register) sequence 2 / 4 NOP Null operation 2

-pin being low) 4

-pin 4

Data Sheet 37 V2.2, 2001-08

C167CS-4R

C167CS-L

Special Function Registers Overview

Table 7 lists all SFRs which are implemented in the C167CS in alphabetical order.

Bit-addressable SFRs are marked with the letter “b” in column “Name”. SFRs within the Extended SFR-Space (ESFRs) are marked with the letter “E” in column “Physical

Address”. Registers within on-chip X-peripherals are marked with the letter “X” in column “Physical Address”.

An SFR can be specified via its individual mnemonic name. Depending on the selected addressing mode, an SFR can be accessed via its physical address (using the Data Page Pointers), or via its short 8-bit address (without using the Data Page Pointers).

Table 7 C167CS Registers, Ordered by Name

Name Physical

Address

ADCIC b FF98

ADCON b FFA0

ADDAT FEA0

ADDAT2 F0A0

ADDRSEL1 FE18

ADDRSEL2 FE1A

ADDRSEL3 FE1C

ADDRSEL4 FE1E

ADEIC b FF9A

BUSCON0 b FF0C

BUSCON1 b FF14

BUSCON2 b FF16

8-Bit Addr.

E 50

Description Reset

A/D Converter End of Conversion

Interrupt Control Register

A/D Converter Control Register 0000

A/D Converter Result Register 0000

A/D Converter 2 Result Register 0000

Address Select Register 1 0000

Address Select Register 2 0000

Address Select Register 3 0000

Address Select Register 4 0000

A/D Converter Overrun Error Interrupt

Control Register

Bus Configuration Register 0 0XX0

Bus Configuration Register 1 0000

Bus Configuration Register 2 0000

Value

0000

BUSCON3 b FF18

BUSCON4 b FF1A

C1BTR EF04

C1CSR EF00

C1GMS EF06

C1PCIR EF02

C1LGML EF0AHX --- CAN1 Lower Global Mask Long UUUU

C1LMLM EF0EHX --- CAN1 Lower Mask of Last Message UUUU

Data Sheet 38 V2.2, 2001-08

Bus Configuration Register 3 0000

Bus Configuration Register 4 0000

X --- CAN1 Bit Timing Register UUUU

X --- CAN1 Control/Status Register XX01

X --- CAN1 Global Mask Short UFUU

X --- CAN1 Port Control/Interrupt Register XXXX

Table 7 C167CS Registers, Ordered by Name (cont’d)

C167CS-4R

C167CS-L

Name Physical

Address

C1UAR EFn2

C1UGML EF08

8-Bit Addr.

Description Reset

Value

X --- CAN1 Upper Arbitration Reg. (msg. n) UUUU

X --- CAN1 Upper Global Mask Long UUUU

C1UMLM EF0CHX --- CAN1 Upper Mask of Last Message UUUU

C2BTR EE04

C2CSR EE00

C2GMS EE06

C2PCIR EE02

X --- CAN2 Bit Timing Register UUUU

X --- CAN2 Control/Status Register XX01

X --- CAN2 Global Mask Short UFUU

X --- CAN2 Port Control/Interrupt Register XXXX

C2LGML EE0AHX --- CAN2 Lower Global Mask Long UUUU

C2LMLM EE0EHX --- CAN2 Lower Mask of Last Message UUUU

C2UAR EEn2

C2UGML EE08

X --- CAN2 Upper Arbitration Reg. (msg. n) UUUU

X --- CAN2 Upper Global Mask Long UUUU

C2UMLM EE0CHX --- CAN2 Upper Mask of Last Message UUUU

CAPREL FE4A

GPT2 Capture/Reload Register 0000

CC0 FE80

CC0IC b FF78

CC1 FE82

CC10 FE94

CC10IC b FF8C

CC11 FE96

CC11IC b FF8E

CC12 FE98

CC12IC b FF90

CC13 FE9A

CC13IC b FF92

CC14 FE9C

CC14IC b FF94

CC15 FE9E

CC15IC b FF96

CAPCOM Register 0 0000

CAPCOM Reg. 0 Interrupt Ctrl. Reg. 0000

CAPCOM Register 1 0000

CAPCOM Register 10 0000

CAPCOM Reg. 10 Interrupt Ctrl. Reg. 0000

CAPCOM Register 11 0000

CAPCOM Reg. 11 Interrupt Ctrl. Reg. 0000

CAPCOM Register 12 0000

CAPCOM Reg. 12 Interrupt Ctrl. Reg. 0000

CAPCOM Register 13 0000

CAPCOM Reg. 13 Interrupt Ctrl. Reg. 0000

CAPCOM Register 14 0000

CAPCOM Reg. 14 Interrupt Ctrl. Reg. 0000

CAPCOM Register 15 0000

CAPCOM Reg. 15 Interrupt Ctrl. Reg. 0000

CC16 FE60

CC16IC b F160

Data Sheet 39 V2.2, 2001-08

E B0

CAPCOM Register 16 0000

CAPCOM Reg. 16 Interrupt Ctrl. Reg. 0000

Table 7 C167CS Registers, Ordered by Name (cont’d)

C167CS-4R

C167CS-L

Name Physical

Address

CC17 FE62

CC17IC b F162

CC18 FE64

CC18IC b F164

CC19 FE66

CC19IC b F166

CC1IC b FF7A

CC2 FE84

CC20 FE68

CC20IC b F168

CC21 FE6A

CC21IC b F16A

CC22 FE6C

8-Bit Addr.

E B1

E B2

E B3

E B4

E B5

Description Reset

CAPCOM Register 17 0000

CAPCOM Reg. 17 Interrupt Ctrl. Reg. 0000

CAPCOM Register 18 0000

CAPCOM Reg. 18 Interrupt Ctrl. Reg. 0000

CAPCOM Register 19 0000

CAPCOM Reg. 19 Interrupt Ctrl. Reg. 0000

CAPCOM Reg. 1 Interrupt Ctrl. Reg. 0000

CAPCOM Register 2 0000

CAPCOM Register 20 0000

CAPCOM Reg. 20 Interrupt Ctrl. Reg. 0000

CAPCOM Register 21 0000

CAPCOM Reg. 21 Interrupt Ctrl. Reg. 0000

CAPCOM Register 22 0000

Value

CC22IC b F16C

CC23 FE6E

CC23IC b F16E

CC24 FE70

CC24IC b F170

CC25 FE72

CC25IC b F172

CC26 FE74

CC26IC b F174

CC27 FE76

CC27IC b F176

CC28 FE78

CC28IC b F178

CC29 FE7A

CC29IC b F184

E B6

E B7

E B8

E B9

E BA

E BB

E BC

E C2

CAPCOM Reg. 22 Interrupt Ctrl. Reg. 0000

CAPCOM Register 23 0000

CAPCOM Reg. 23 Interrupt Ctrl. Reg. 0000

CAPCOM Register 24 0000

CAPCOM Reg. 24 Interrupt Ctrl. Reg. 0000

CAPCOM Register 25 0000

CAPCOM Reg. 25 Interrupt Ctrl. Reg. 0000

CAPCOM Register 26 0000

CAPCOM Reg. 26 Interrupt Ctrl. Reg. 0000

CAPCOM Register 27 0000

CAPCOM Reg. 27 Interrupt Ctrl. Reg. 0000

CAPCOM Register 28 0000

CAPCOM Reg. 28 Interrupt Ctrl. Reg. 0000

CAPCOM Register 29 0000

CAPCOM Reg. 29 Interrupt Ctrl. Reg. 0000

CC2IC b FF7C

CC3 FE86

Data Sheet 40 V2.2, 2001-08

CAPCOM Reg. 2 Interrupt Ctrl. Reg. 0000

CAPCOM Register 3 0000

Table 7 C167CS Registers, Ordered by Name (cont’d)

C167CS-4R

C167CS-L

Name Physical

Address

CC30 FE7C

CC30IC b F18C

CC31 FE7E

CC31IC b F194

CC3IC b FF7E

CC4 FE88

CC4IC b FF80

CC5 FE8A

CC5IC b FF82

CC6 FE8C

CC6IC b FF84

CC7 FE8E

CC7IC b FF86

8-Bit Addr.

E C6

E CA

Description Reset

CAPCOM Register 30 0000

CAPCOM Reg. 30 Interrupt Ctrl. Reg. 0000

CAPCOM Register 31 0000

CAPCOM Reg. 31 Interrupt Ctrl. Reg. 0000

CAPCOM Reg. 3 Interrupt Ctrl. Reg. 0000

CAPCOM Register 4 0000

CAPCOM Reg. 4 Interrupt Ctrl. Reg. 0000

CAPCOM Register 5 0000

CAPCOM Reg. 5 Interrupt Ctrl. Reg. 0000

CAPCOM Register 6 0000

CAPCOM Reg. 6 Interrupt Ctrl. Reg. 0000

CAPCOM Register 7 0000

CAPCOM Reg. 7 Interrupt Ctrl. Reg. 0000

Value

CC8 FE90

CC8IC b FF88

CC9 FE92

CC9IC b FF8A

CCM0 b FF52

CCM1 b FF54

CCM2 b FF56

CCM3 b FF58

CCM4 b FF22

CCM5 b FF24

CCM6 b FF26

CCM7 b FF28

CP FE10

CRIC b FF6A

CSP FE08

CAPCOM Register 8 0000

CAPCOM Reg. 8 Interrupt Ctrl. Reg. 0000

CAPCOM Register 9 0000

CAPCOM Reg. 9 Interrupt Ctrl. Reg. 0000

CAPCOM Mode Control Register 0 0000

CAPCOM Mode Control Register 1 0000

CAPCOM Mode Control Register 2 0000

CAPCOM Mode Control Register 3 0000

CAPCOM Mode Control Register 4 0000

CAPCOM Mode Control Register 5 0000

CAPCOM Mode Control Register 6 0000

CAPCOM Mode Control Register 7 0000

CPU Context Pointer Register FC00

GPT2 CAPREL Interrupt Ctrl. Reg. 0000

CPU Code Seg. Pointer Reg. (read only) 0000

DP0L b F100

DP0H b F102

Data Sheet 41 V2.2, 2001-08

E 80

E 81

P0L Direction Control Register 00

P0H Direction Control Register 00

Table 7 C167CS Registers, Ordered by Name (cont’d)

C167CS-4R

C167CS-L

Name Physical

Address

DP1L b F104

DP1H b F106

DP2 b FFC2

DP3 b FFC6

DP4 b FFCA

DP6 b FFCE

DP7 b FFD2

DP8 b FFD6

DPP0 FE00

DPP1 FE02

DPP2 FE04

DPP3 FE06

EXICON b F1C0

8-Bit Addr.

E 82

E 83

E E0

Description Reset

P1L Direction Control Register 00

P1H Direction Control Register 00

Port 2 Direction Control Register 0000

Port 3 Direction Control Register 0000

Port 4 Direction Control Register 00

Port 6 Direction Control Register 00

Port 7 Direction Control Register 00

Port 8 Direction Control Register 00

CPU Data Page Pointer 0 Reg. (10 bits) 0000

CPU Data Page Pointer 1 Reg. (10 bits) 0001

CPU Data Page Pointer 2 Reg. (10 bits) 0002

CPU Data Page Pointer 3 Reg. (10 bits) 0003

External Interrupt Control Register 0000

Value

EXISEL b F1DAHE ED

FOCON b FFAA

IDCHIP F07C

IDMANUF F07E

IDMEM F07A

IDMEM2 F076

IDPROG F078

E 3E

E 3F

E 3D

E 3B

E 3C

ISNC b F1DEHE EF

MDC b FF0E

MDH FE0C

MDL FE0E

ODP2 b F1C2

ODP3 b F1C6

E E1

E E3

ODP4 b F1CAHE E5

ODP6 b F1CEHE E7

External Interrupt Source Select Reg. 0000

Frequency Output Control Register 0000

Identifier 0CXX

Identifier 1820

Identifier X040

Identifier XXXX

Interrupt Subnode Control Register 0000

CPU Multiply Divide Control Register 0000

CPU Multiply Divide Reg. – High Word 0000

CPU Multiply Divide Reg. – Low Word 0000

Port 2 Open Drain Control Register 0000

Port 3 Open Drain Control Register 0000

Port 4 Open Drain Control Register 00

Port 6 Open Drain Control Register 00

ODP7 b F1D2H EE9

ODP8 b F1D6

Data Sheet 42 V2.2, 2001-08

E EB

Port 7 Open Drain Control Register 00

Port 8 Open Drain Control Register 00

Table 7 C167CS Registers, Ordered by Name (cont’d)

C167CS-4R

C167CS-L

Name Physical

Address

ONES b FF1E

P0H b FF02

P0L b FF00

P1DIDIS FEA4

P1H b FF06

P1L b FF04

P2 b FFC0

P3 b FFC4

P4 b FFC8

P5 b FFA2

P5DIDIS b FFA4

P6 b FFCC

P7 b FFD0

8-Bit Addr.

Description Reset

Value

Constant Value 1’s Register (read only) FFFF

Port 0 High Reg. (Upper half of PORT0) 00

Port 0 Low Reg. (Lower half of PORT0) 00

Port 1 Digital Input Disable Register 0000

Port 1 High Reg. (Upper half of PORT1) 00

Port 1 Low Reg. (Lower half of PORT1) 00

Port 2 Register 0000

Port 3 Register 0000

Port 4 Register (8 bits) 00

Port 5 Register (read only) XXXX

Port 5 Digital Input Disable Register 0000

Port 6 Register (8 bits) 00

Port 7 Register (8 bits) 00

P8 b FFD4

PECC0 FEC0

PECC1 FEC2

PECC2 FEC4

PECC3 FEC6

PECC4 FEC8

PECC5 FECA

PECC6 FECC

PECC7 FECE

PICON b F1C4

POCON0H F082

POCON0L F080

POCON1H F086

POCON1L F084

POCON2 F088

E E2

E 41

E 40

E 43

E 42

E 44

Port 8 Register (8 bits) 00

PEC Channel 0 Control Register 0000

PEC Channel 1 Control Register 0000

PEC Channel 2 Control Register 0000

PEC Channel 3 Control Register 0000

PEC Channel 4 Control Register 0000

PEC Channel 5 Control Register 0000

PEC Channel 6 Control Register 0000

PEC Channel 7 Control Register 0000

Port Input Threshold Control Register 0000

Port P0H Output Control Register 0000

Port P0L Output Control Register 0000

Port P1H Output Control Register 0000

Port P1L Output Control Register 0000

Port P2 Output Control Register 0000

POCON20 F0AAHE 55

POCON3 F08A

Data Sheet 43 V2.2, 2001-08

E 45

Dedicated Pin Output Control Register 0000

Port P3 Output Control Register 0000

Table 7 C167CS Registers, Ordered by Name (cont’d)

C167CS-4R

C167CS-L

Name Physical

Address

POCON4 F08C

POCON6 F08E

POCON7 F090

POCON8 F092

PP0 F038

PP1 F03A

PP2 F03C

PP3 F03E

PSW b FF10

PT0 F030

PT1 F032

PT2 F034

PT3 F036

8-Bit Addr.

E 46

E 47

E 48

E 49

E 1C

E 1D

E 1E

E 1F

E 18

E 19

E 1A

E 1B

Description Reset

Port P4 Output Control Register 0000

Port P6 Output Control Register 0000

Port P7 Output Control Register 0000

Port P8 Output Control Register 0000

PWM Module Period Register 0 0000

PWM Module Period Register 1 0000

PWM Module Period Register 2 0000

PWM Module Period Register 3 0000

CPU Program Status Word 0000

PWM Module Up/Down Counter 0 0000

PWM Module Up/Down Counter 1 0000

PWM Module Up/Down Counter 2 0000

PWM Module Up/Down Counter 3 0000

Value

PTCR F0AEHE 57

PW0 FE30

PW1 FE32

PW2 FE34

PW3 FE36

PWMCON0 b FF30

PWMCON1 b FF32

PWMIC b F17E

RP0H b F108

E BF

E 84

Port Temperature Compensation Reg. 0000

PWM Module Pulse Width Register 0 0000

PWM Module Pulse Width Register 1 0000

PWM Module Pulse Width Register 2 0000

PWM Module Pulse Width Register 3 0000

PWM Module Control Register 0 0000

PWM Module Control Register 1 0000

PWM Module Interrupt Control Register 0000

System Start-up Config. Reg. (Rd. only) XX

RSTCON b F1E0Hm --- Reset Control Register 00XX

RTCH F0D6

RTCL F0D4

S0BG FEB4

E 6B

E 6A

RTC High Register XXXX

RTC Low Register XXXX

Serial Channel 0 Baud Rate Generator

0000

Reload Register

S0CON b FFB0

Serial Channel 0 Control Register 0000

S0EIC b FF70

Data Sheet 44 V2.2, 2001-08

Serial Channel 0 Error Interrupt Ctrl. Reg 0000

Table 7 C167CS Registers, Ordered by Name (cont’d)

C167CS-4R

C167CS-L

Name Physical

Address

S0RBUF FEB2

S0RIC b FF6E

S0TBIC b F19C

S0TBUF FEB0

S0TIC b FF6C

SP FE12

SSCBR F0B4

SSCCON b FFB2

SSCEIC b FF76

8-Bit Addr.

E CE

E 5A

Description Reset

Serial Channel 0 Receive Buffer Reg.

(read only)

Serial Channel 0 Receive Interrupt

Control Register

Serial Channel 0 Transmit Buffer

Interrupt Control Register

Serial Channel 0 Transmit Buffer

Serial Channel 0 Transmit Interrupt

Control Register

CPU System Stack Pointer Register FC00

SSC Baudrate Register 0000

SSC Control Register 0000

SSC Error Interrupt Control Register 0000

Value

0000

SSCRB F0B2

SSCRIC b FF74

SSCTB F0B0

SSCTIC b FF72

STKOV FE14

STKUN FE16

SYSCON b FF12

E 59

E 58

SYSCON1 b F1DCHE EE

SYSCON2 b F1D0

SYSCON3 b F1D4

T0 FE50

T01CON b FF50

T0IC b FF9C

T0REL FE54

T1 FE52

E E8

E EA

SSC Receive Buffer XXXX

SSC Receive Interrupt Control Register 0000

SSC Transmit Buffer 0000

SSC Transmit Interrupt Control Register 0000

CPU Stack Overflow Pointer Register FA00

CPU Stack Underflow Pointer Register FC00

CPU System Configuration Register

CPU System Configuration Register 1 0000

CPU System Configuration Register 2 0000

CPU System Configuration Register 3 0000

CAPCOM Timer 0 Register 0000

CAPCOM Timer 0 and Timer 1 Ctrl. Reg. 0000

CAPCOM Timer 0 Interrupt Ctrl. Reg. 0000

CAPCOM Timer 0 Reload Register 0000

CAPCOM Timer 1 Register 0000

0XX0

T1IC b FF9E

T1REL FE56

Data Sheet 45 V2.2, 2001-08

CAPCOM Timer 1 Interrupt Ctrl. Reg. 0000

CAPCOM Timer 1 Reload Register 0000

Table 7 C167CS Registers, Ordered by Name (cont’d)

C167CS-4R

C167CS-L

Name Physical

Address

T14 F0D2

T14REL F0D0

T2 FE40

T2CON b FF40

T2IC b FF60

T3 FE42

T3CON b FF42

T3IC b FF62

T4 FE44

T4CON b FF44

T4IC b FF64

T5 FE46

T5CON b FF46

8-Bit Addr.

E 69

E 68

Description Reset

RTC Timer 14 Register XXXX

RTC Timer 14 Reload Register XXXX

GPT1 Timer 2 Register 0000

GPT1 Timer 2 Control Register 0000

GPT1 Timer 2 Interrupt Control Register 0000

GPT1 Timer 3 Register 0000

GPT1 Timer 3 Control Register 0000

GPT1 Timer 3 Interrupt Control Register 0000

GPT1 Timer 4 Register 0000

GPT1 Timer 4 Control Register 0000

GPT1 Timer 4 Interrupt Control Register 0000

GPT2 Timer 5 Register 0000

GPT2 Timer 5 Control Register 0000

Value

T5IC b FF66

T6 FE48

T6CON b FF48

T6IC b FF68

T7 F050

T78CON b FF20

T7IC b F17A

T7REL F054

T8 F052

T8IC b F17C

T8REL F056

TFR b FFAC

WDT FEAE

WDTCON b FFAE

XP0IC b F186

E 28

E BE

E 2A

E 29

E BF

E 2B

E C3

GPT2 Timer 5 Interrupt Control Register 0000

GPT2 Timer 6 Register 0000

GPT2 Timer 6 Control Register 0000

GPT2 Timer 6 Interrupt Control Register 0000

CAPCOM Timer 7 Register 0000

CAPCOM Timer 7 and 8 Control Reg. 0000

CAPCOM Timer 7 Interrupt Ctrl. Reg. 0000

CAPCOM Timer 7 Reload Register 0000

CAPCOM Timer 8 Register 0000

CAPCOM Timer 8 Interrupt Ctrl. Reg. 0000

CAPCOM Timer 8 Reload Register 0000

Trap Flag Register 0000

Watchdog Timer Register (read only) 0000

Watchdog Timer Control Register

CAN1 Module Interrupt Control Register 0000

00XX

XP1IC b F18E

XP2IC b F196

Data Sheet 46 V2.2, 2001-08

E C7

E CB

CAN2 Module Interrupt Control Register 0000

Unassigned Interrupt Control Register 0000

Table 7 C167CS Registers, Ordered by Name (cont’d)

C167CS-4R

C167CS-L

Name Physical

Address

XP3IC b F19E

XPERCON F024

ZEROS b FF1C

The system configuration is selected during reset.

The reset value depends on the indicated reset source.

8-Bit Addr.

E CF

E 12

Description Reset

RTC/PLL Interrupt Control Register 0000

X-Peripheral Control Register 0401

Constant Value 0’s Register (read only) 0000

Value

Data Sheet 47 V2.2, 2001-08

C167CS-4R

Absolute Maximum Ratings

Table 8 Absolute Maximum Rating Parameters

Parameter Symbol Limit Values Unit Notes

min. max.

C167CS-L

Storage temperature

Junction temperature

Voltage on respect to ground (

pins with

Voltage on any pin with respect to ground (

Input current on any pin

)

– -10 10 mA –

-65 150 °C –

-40 150 °C under bias

-0.5 6.5 V –

-0.5 VDD + 0.5 V –

during overload condition

Absolute sum of all input

–– |100| mA – currents during overload condition

Power dissipation

DISS

– 1.5 W –

Note: Stresses above those listed under “Absolute Maximum Ratings” may cause

permanent damage to the device. This is a stress rating only and functional operation of the device at these or any other conditions above those indicated in the operational sections of this specification is not implied. Exposure to absolute maximum rating conditions for extended periods may affect device reliability. During absolute maximum rating overload conditions ( voltage on

pins with respect to ground (VSS) must not exceed the values

> VDD or VIN< VSS) the

defined by the absolute maximum ratings.

Data Sheet 48 V2.2, 2001-08

C167CS-4R

C167CS-L

Operating Conditions

The following operating conditions must not be exceeded in order to ensure correct operation of the C167CS. All parameters specified in the following sections refer to these operating conditions, unless otherwise noticed.

Table 9 Operating Condition Parameters

Parameter Symbol Limit Values Unit Notes

min. max.

Digital supply voltage

Digital ground voltage

Overload current

Absolute sum of overload

Σ|I

4.5 5.5 V Active mode,

2.5

5.5 V PowerDown mode

0 V Reference voltage

– ±5mAPer pin

| – 50 mA

CPUmax

= 40 MHz

2)3)

currents

External Load Capacitance

Ambient temperature T

Output voltages and output currents will be reduced when VDD leaves the range defined for active mode.

Overload conditions occur if the standard operating conditions are exceeded, i.e. the voltage on any pin exceeds the specified range (i.e. currents on all pins may not exceed 50 mA. The supply voltage must remain within the specified limits. Proper operation is not guaranteed if overload conditions occur on functional pins line XTAL1, RD

Not 100% tested, guaranteed by design and characterization.

The timing is valid for pin drivers in high current or dynamic current mode. The reduced static output current in dynamic current mode must be respected when designing the system.

– 50 pF Pin drivers in

fast edge mode

> VDD+0.5V or VOV< VSS- 0.5 V). The absolute sum of input overload

070°C SAB-C167CS …

-40 85

-40 125

°C SAF-C167CS …

°C SAK-C167CS …

, WR, etc.

Data Sheet 49 V2.2, 2001-08

C167CS-4R

C167CS-L

Parameter Interpretation

The parameters listed in the following partly represent the characteristics of the C167CS and partly its demands on the system. To aid in interpreting the parameters right, when evaluating them for a design, they are marked in column “Symbol”:

CC (Controller Characteristics): The logic of the C167CS will provide signals with the respective characteristics.

SR (System Requirement): The external system must provide signals with the respective characteristics to the C167CS.

DC Characteristics

(Operating Conditions apply)

Parameter Symbol Limit Values Unit Test Condition

Input low voltage (TTL, all except XTAL1)

Input low voltage XTAL1

Input low voltage (Special Threshold)

Input high voltage (TTL, all except RSTIN

and XTAL1)

Input high voltage RSTIN (when operated as input)

Input high voltage XTAL1

Input high voltage (Special Threshold)

Input Hysteresis (Special Threshold)

Output low voltage

Output high voltage

min. max.

SR -0.5 0.2 V

V –

- 0.1

SR -0.5 0.3 V

IL2

SR -0.5 2.0 V –

ILS

SR 0.2 V

+ 0.9

SR 0.6 V

IH1

DDVDD

0.5

V –

0.5

IH2

SR 0.7 V

DDVDD

V –

0.5

IHS

SR 0.8 V

- 0.2

0.5

V –

HYS 400 – mV Series

resistance = 0

CC – 1.0 V IOL ≤ I

– 0.45 V IOL ≤ I

CC VDD -

– V IOH ≥ I

1.0

– V IOH ≥ I

0.45

Ω

OLmax

3)4)

OLnom

OHmax

3)4)

OHnom

Input leakage current (Port 5) I

Data Sheet 50 V2.2, 2001-08

CC – ±200 nA 0 V < VIN < V

OZ1

C167CS-4R

C167CS-L

DC Characteristics (cont’d)

(Operating Conditions apply)

Parameter Symbol Limit Values Unit Test Condition

min. max.

Input leakage current (all other) I

10)

RSTIN inactive current

RSTIN active current

READY/RD/WR inact. current

READY

/RD/WR active current

ALE inactive current

ALE active current

Port 6 inactive current

Port 6 active current

PORT0 configuration current

XTAL1 input current I

Pin capacitance (digital inputs/outputs)

Keeping signal levels within the levels specified in this table, ensures operation without overload conditions. For signal levels outside these specifications also refer to the specification of the overload current

For pin RSTIN this specification is only valid in bidirectional reset mode.

The maximum deliverable output current of a port driver depends on the selected output driver mode, see

Table 10, Current Limits for Port Output Drivers. The limit for pin groups must be respected.

As a rule, with decreasing output current the output levels approach the respective supply level (V

→ V

This specification is not valid for outputs which are switched to open drain mode. In this case the respective output will float and the voltage results from the external circuitry.

These parameters describe the RSTIN pullup, which equals a resistance of ca. 50 to 250 kΩ.

The maximum current may be drawn while the respective signal line remains inactive.

The minimum current must be drawn in order to drive the respective signal line active.

This specification is valid during Reset and during Hold-mode or Adapt-mode. During Hold-mode Port 6 pins are only affected, if they are used (configured) for CS READY

10)

This specification is valid during Reset and during Adapt-mode.

11)

Not 100% tested, guaranteed by design and characterization.

-pullup is always active, except for Powerdown mode.

11)

). However, only the levels for nominal output currents are guaranteed.

CC – ±500 nA 0.45 V < V

OZ2

< V

RSTH

RSTL

RWH

RWL

ALEL

ALEH

P6H

P6L

P0H

P0L

– -10 µA VIN = V

-100 – µA VIN = V

– -40 µA V

-500 – µA V

– 40 µA V

500 – µA V

– -40 µA V

-500 – µA V

– -10 µA VIN = V

-100 – µA VIN = V

CC – ±20 µA0 V < VIN < V

CC – 10 pF f = 1 MHz

output and the open drain function is not enabled. The

= 2.4 V

OUT

= V

OUT

= V

OUT

= 2.4 V

OUT

= 2.4 V

OUT

= V

OUT

= 25 °C

IH1

OLmax

OL1max

IHmin

ILmax

→ V

Data Sheet 51 V2.2, 2001-08

Table 10 Current Limits for Port Output Drivers

C167CS-4R

C167CS-L

Port Output Driver Maximum Output Current

(

OLmax

, -I

OHmax

)

Nominal Output Current

(

OLnom

, -I

OHnom

)

P2.7 - P2.0 10 mA 2.5 mA

(PORT0, PORT1, Port 4, ALE, RD

, CLKOUT,

BHE RSTOUT

, RSTIN2))

, WR,

----- 2.5 mA

All other outputs ----- 1.6 mA

An output current above |I For any group of 16 neighboring port output pins the total output current in each direction (Σ must remain below 50 mA.

Valid for VOL in bidirectional reset mode only.

| may be drawn from up to three pins (P2.7-P2.0 only) at the same time.

OXnom

and/or Σ-IOH)

Power Consumption C167CS

(Operating Conditions apply)

Parameter Symbol Limit Values Unit Test Condition

min. max.

Power supply current (active) with all peripherals active

Idle mode supply current with all peripherals active

Idle mode supply current with all peripherals deactivated,

DD5

IDX5

IDO

3)2)

– 20 +

3.2

× f

– 15 +

× f

1.4

– 800 +

× f

CPU

OSC

mA RSTIN = V

in [MHz]

CPU

mA RSTIN = V

in [MHz]

CPU

µARSTIN = V

in [MHz]

OSC

PLL off, SDD factor = 32

Sleep and Power-down mode supply current with RTC running

Sleep and Power-down mode

PDR

PDO

3)2)

– 800 +

× f

OSC

µA V

OSC

= V

in [MHz]

– 50 µA VDD = V

DDmax

supply current with RTC disabled

The supply current is a function of the operating frequency. This dependency is illustrated in Figure 10. These parameters are tested at

or VIH.

These values are not 100% tested but verified by means of system characterization.

This parameter is determined mainly by the current consumed by the oscillator (see Figure 9). This current, however, is influenced by the external oscillator circuitry (crystal, capacitors). The values given refer to a typical circuitry and may change in case of a not optimized external oscillator circuitry (see also application notes AP2420: Crystal Oscillator, AP2424: Ceramic Resonator Oscillator).

This parameter is tested including leakage currents. All inputs (including pins configured as inputs) at 0 V to

0.1 V or at

- 0.1 V to VDD, V

REF

and maximum CPU clock with all outputs disconnected and all inputs

DDmax

= 0 V, all outputs (including pins configured as outputs) disconnected.

IH1

Data Sheet 52 V2.2, 2001-08

I [µA]

3000

2000

C167CS-4R

C167CS-L

IDOmax

IDOtyp

PDRmax

1000

PDOmax

10 20 30 40

OSC

[MHz]

Figure 9 Idle and Power Down Supply Current as a Function of Oscillator

Frequency

Data Sheet 53 V2.2, 2001-08

C167CS-4R

C167CS-L

I [mA]

140

120

100

DD5max

DD5typ

IDX5max

IDX5typ

10 20 30 40

CPU

Figure 10 Supply/Idle Current as a Function of Operating Frequency

[MHz]

Data Sheet 54 V2.2, 2001-08

AC Characteristics Definition of Internal Timing

C167CS-4R

C167CS-L

The internal operation of the C167CS is controlled by the internal CPU clock

CPU

. Both edges of the CPU clock can trigger internal (e.g. pipeline) or external (e.g. bus cycles) operations.

The specification of the external timing (AC Characteristics) therefore depends on the time between two consecutive edges of the CPU clock, called “TCL” (see Figure 11).

Phase Locked Loop Operation

OSC

TCL

CPU

TCL

Direct Clock Drive

OSC

TCL

CPU

TCL

Prescaler Operation

OSC

TCL

CPU

TCL

MCT04338

Figure 11 Generation Mechanisms for the CPU Clock

The CPU clock signal

can be generated from the oscillator clock signal f

CPU

OSC

via different mechanisms. The duration of TCLs and their variation (and also the derived external timing) depends on the used mechanism to generate

. This influence must

CPU

be regarded when calculating the timings for the C167CS.

Note: The example for PLL operation shown in Figure 11 refers to a PLL factor of 4.

The used mechanism to generate the basic CPU clock is selected by bitfield CLKCFG in register RP0H.7-5. Upon a long hardware reset register RP0H is loaded with the logic levels present on the upper half of PORT0 (P0H), i.e. bitfield CLKCFG represents the logic levels on pins

Data Sheet 55 V2.2, 2001-08

C167CS-4R

C167CS-L

P0.15-13 (P0H.7-5). Register RP0H can be loaded from the upper half of register RSTCON under software control.

Table 11 associates the combinations of these three bits with the respective clock

generation mode.

Table 11 C167CS Clock Generation Modes

CLKCFG (RP0H.7-5)

11 1

110

101

100

011

010 f

001

000

The external clock input range refers to a CPU clock range of 10 … 40 MHz.

The maximum frequency depends on the duty cycle of the external clock signal.

In prescaler mode the full CPU clock range cannot be used.

CPU Frequency

= f

CPU

× 4 2.5 to 10 MHz Default configuration

OSC

× 3 3.33 to 13.33 MHz –

OSC

× 2 5 to 20 MHz –

OSC

× 5 2 to 8 MHz –

OSC

× 1 1 to 40 MHz Direct drive

OSC

× 1.5 6.66 to 26.66 MHz –

OSC

/ 2 2 to 50 MHz

OSC

× 2.5 4 to 16 MHz –

OSC

× F

External Clock Input Range

Notes

CPU clock via prescaler

Prescaler Operation

When prescaler operation is configured (CLKCFG = 001

) the CPU clock is derived from

the internal oscillator (input clock signal) by a 2:1 prescaler.

The frequency of

is half the frequency of f

CPU

the duration of an individual TCL) is defined by the period of the input clock

and the high and low time of f

OSC

CPU

(i.e.

The timings listed in the AC Characteristics that refer to TCLs therefore can be calculated using the period of

for any TCL.

OSC

Phase Locked Loop

When PLL operation is configured (via CLKCFG) the on-chip phase locked loop is enabled and provides the CPU clock (see Table 11). The PLL multiplies the input frequency by the factor F which is selected via the combination of pins P0.15-13 (i.e.

CPU

= f

× F). With every F’th transition of f

OSC

the PLL circuit synchronizes the CPU

OSC

clock to the input clock. This synchronization is done smoothly, i.e. the CPU clock frequency does not change abruptly.

Data Sheet 56 V2.2, 2001-08

C167CS-4R

C167CS-L

Due to this adaptation to the input clock the frequency of f

it is locked to

. The slight variation causes a jitter of f

OSC

is constantly adjusted so

CPU

which also effects the

CPU

duration of individual TCLs.

The timings listed in the AC Characteristics that refer to TCLs therefore must be calculated using the minimum TCL that is possible under the respective circumstances.

The actual minimum value for TCL depends on the jitter of the PLL. As the PLL is constantly adjusting its output frequency so it corresponds to the applied input frequency (crystal or oscillator) the relative deviation for periods of more than one TCL is lower than for one single TCL (see formula and Figure 12). For a period of deviation D

N × TCL)

(

where

N = number of consecutive TCLs and 1 ≤ N ≤ 40.

So for a period of 3 TCLs @ 25 MHz (i.e. and (3TCL)

min

N × TCL the minimum value is computed using the corresponding

= N × TCL

min

= 3TCL

- 1.288 ns = 58.7 ns (@ f

NOM

- DN; DN [ns] = ±(13.3 + N × 6.3) / f

NOM

N = 3): D

= (13.3 + 3 × 6.3) / 25 = 1.288 ns,

= 25 MHz).

CPU

[MHz],

This is especially important for bus cycles using waitstates and e.g. for the operation of timers, serial interfaces, etc. For all slower operations and longer periods (e.g. pulse train generation or measurement, lower baudrates, etc.) the deviation caused by the PLL jitter is neglectible.

Note: For all periods longer than 40 TCL the N = 40 value can be used (see Figure 12).

40 and 10 MHz

CPU

40 MHz.

10 MHz

16 MHz

20 MHz

25 MHz

33 MHz

40 MHz

MCD04413B

±30

±26.5

±20

±10

±1

Max. jitter

This approximated formula is valid for 1

1 5 10 20

Figure 12 Approximated Maximum Accumulated PLL Jitter

Data Sheet 57 V2.2, 2001-08

Direct Drive

C167CS-4R

C167CS-L

When direct drive is configured (CLKCFG = 011

) the on-chip phase locked loop is

disabled and the CPU clock is directly driven from the internal oscillator with the input clock signal. The frequency of

(i.e. the duration of an individual TCL) is defined by the duty cycle of the input clock

CPU

OSC

directly follows the frequency of f

CPU

so the high and low time of

OSC

The timings listed below that refer to TCLs therefore must be calculated using the minimum TCL that is possible under the respective circumstances. This minimum value can be calculated via the following formula:

TCL

For two consecutive TCLs the deviation caused by the duty cycle of so the duration of 2TCL is always 1/

min

= 1/f

OSC

× DC

min

(DC = duty cycle)

. The minimum value TCL

OSC

is compensated

OSC

therefore has to

min

be used only once for timings that require an odd number of TCLs (1, 3, …). Timings that require an even number of TCLs (2, 4, …) may use the formula 2TCL = 1/

OSC

Data Sheet 58 V2.2, 2001-08

AC Characteristics External Clock Drive XTAL1

(Operating Conditions apply)

Table 12 External Clock Drive Characteristics

C167CS-4R

C167CS-L

Parameter Symbol Direct Drive

1:1

Prescaler

2:1

PLL

1:N

min. max. min. max. min. max.

Oscillator period

High time

Low time

Rise time

Fall time

The minimum and maximum oscillator periods for PLL operation depend on the selected CPU clock generation mode. Please see respective table above.

The clock input signal must reach the defined levels V

The minimum high and low time refers to a duty cycle of 50%. The maximum operating frequency (f direct drive mode depends on the duty cycle of the clock input signal.

OSC

SR 25 – 20 – 37

SR 12

– 5 – 10 – ns

SR – 8 – 5 – 10 ns

and V

IL2

IH2

500

Unit

CPU

) in

VDD0.5

OSC

IH2

MCT02534

Figure 13 External Clock Drive XTAL1

Note: If the on-chip oscillator is used together with a crystal, the oscillator frequency is

limited to a range of 4 MHz to 40 MHz. It is strongly recommended to measure the oscillation allowance (or margin) in the final target system (layout) to determine the optimum parameters for the oscillator operation. Please refer to the limits specified by the crystal supplier. When driven by an external clock signal it will accept the specified frequency range. Operation at lower input frequencies is possible but is guaranteed by design only (not 100% tested).

Data Sheet 59 V2.2, 2001-08

C167CS-4R

C167CS-L

A/D Converter Characteristics

(Operating Conditions apply)

Table 13 A/D Converter Characteristics

Parameter Symbol Limit Values Unit Test

Condition

Analog reference supply

AREF

min. max.

SR 4.0 VDD + 0.1 V

Analog reference ground V

Analog input voltage range

Basic clock frequency f

Conversion time t

Calibration time after reset t

CAL

SR VSS - 0.1 VSS + 0.2 V –

AGND

AIN

SR V

AGND

AREF

0.5 6.25 MHz

CC – 40 tBC + tS

+ 2

CPU

CC – 3328 t

–

CPU

= 1/f

Total unadjusted error TUE CC1)– ±2 LSB Channels

0 … 15

–

±10 LSB Channels

16 … 23

Internal resistance of

reference voltage source

Internal resistance of

analog source

ADC input capacitance C

TUE is tested at V within the defined voltage range. If the analog reference supply voltage exceeds the power supply voltage by up to 0.2 V

(i.e. The specified TUE is guaranteed only if the absolute sum of input overload currents on Port 5 pins and P1H pins (see During the reset calibration sequence the maximum TUE may be ±4 LSB (±12 LSB for channels 16 … 23).

AIN

these cases will be X000

The limit values for f

This parameter includes the sample time tS, the time for determining the digital result and the time to load the result register with the conversion result. Values for the basic clock This parameter depends on the ADC control logic. It is not a real maximum value, but rather a fixum.

= VDD = +0.2 V) the maximum TUE is increased to ±3/11 LSB. This range is not 100% tested.

AREF

specification) does not exceed 10 mA.

may exceed V

= 5.0 V, V

AREF

or V

AGND

or X3FFH, respectively.

must not be exceeded when selecting the CPU frequency and the ADCTC setting.

AGND

up to the absolute maximum ratings. However, the conversion result in

AREF

depend on programming and can be taken from Table 14.

SR – tBC/60

AREF

kΩ tBC in [ns]

- 0.25

SR – tS/450

ASRC

kΩ tS in [ns]

- 0.25

CC – 33 pF

AIN

= 0 V, VDD = 4.9 V. It is guaranteed by design for all other voltages

CPU

6)7)

7)8)

Data Sheet 60 V2.2, 2001-08

C167CS-4R

C167CS-L

As the default basic clock after reset is fBC = f a valid factor as early as possible. A timeframe of approx. 6000 CPU clock cycles is sufficient to ensure a proper reset calibration. This corresponds to minimum 300 instructions (worst case: external MUX bus with maximum waitstates). This is required for During the reset calibration conversions can be executed (with the current accuracy). The time required for these conversions is added to the total reset calibration time.

During the conversion the ADC’s capacitance must be repeatedly charged or discharged. The internal resistance of the reference voltage source must allow the capacitance to reach its respective voltage level within each conversion step. The maximum internal resistance results from the programmed conversion timing.

Not 100% tested, guaranteed by design and characterization.

During the sample time the input capacitance C internal resistance of the analog source must allow the capacitance to reach its final voltage level within

After the end of the sample time Values for the sample time

, changes of the analog input voltage have no effect on the conversion result.

depend on programming and can be taken from Table 14.

/ 4 the ADC’s prescaler (ADCTC) must be programmed to

CPU

> 33 MHz and is recommended for f

CPU

can be charged/discharged by the external source. The

AIN

> 25 MHz.

CPU

Sample time and conversion time of the C167CS’s A/D Converter are programmable.

Table 14 should be used to calculate the above timings.

The limit values for

must not be exceeded when selecting ADCTC.

Table 14 A/D Converter Computation Table

ADCON.15|14 (ADCTC)

00 f

A/D Converter Basic Clock

/ 4 00 tBC × 8

CPU

/ 2 01 tBC × 16

CPU

/ 16 10 tBC × 32

CPU

/ 8 11 tBC × 64

CPU

ADCON.13|12 (ADSTC)

Sample time

Converter Timing Example:

Assumptions:

Basic clock Sample time Conversion time

CPU

= 25 MHz (i.e. t

= f

/ 4 = 6.25 MHz, i.e. tBC = 160 ns.

CPU

= tBC × 8 = 1280 ns. = tS + 40 tBC + 2 t

CPU

= 40 ns), ADCTC = ‘00’, ADSTC = ‘00’.

= (1280 + 6400 + 80) ns = 7.8 µs.

Data Sheet 61 V2.2, 2001-08

Testing Waveforms

C167CS-4R

C167CS-L

2.4 V

1.8 V

0.8 V

0.45 V

AC inputs during testing are driven at 2.4 V for a logic ’1’ and 0.45 V for a logic ’0’.

Timing measurements are made at

min for a logic ’1’ and

Figure 14 Input Output Waveforms

+ 0.1 V

Load

- 0.1 V

Load

Test Points

Timing

Reference

Points

1.8 V

0.8 V

max for a logic ’0’.

MCA04414

- 0.1 V

+ 0.1 V

For timing purposes a port pin is no longer floating when a 100 mV change from load voltage occurs,

but begins to float when a 100 mV change from the loaded

level occurs (

/ = 20 mA).

OH OL

MCA00763

Figure 15 Float Waveforms

Data Sheet 62 V2.2, 2001-08

C167CS-4R

C167CS-L

AC Characteristics

Table 15 CLKOUT Reference Signal

Parameter Symbol Limits Unit

min. max.

CLKOUT cycle time

CLKOUT high time

CLKOUT low time

CLKOUT rise time

CLKOUT fall time

The CLKOUT cycle time is influenced by the PLL jitter (given values apply to f For a single CLKOUT cycle (2 TCL) the deviation caused by the PLL jitter is below 1 ns (for For longer periods the relative deviation decreases (see PLL deviation formula).

CC 40/30/25

CC 8 – ns

CC 6 – ns

CC – 4ns

= 25/33/40 MHz).

CPU

> 25 MHz).

MCT04415

CLKOUT

Figure 16 CLKOUT Signal Timing

Variable Memory Cycles

The bus timing shown below is programmable via the BUSCONx registers. The duration of ALE and two types of waitstates can be selected. This table summarizes the possible bus cycle durations.

Table 16 Variable Memory Cycles

Bus Cycle Type Bus Cycle Duration Unit 25/33/40 MHz, 0 Waitstates

Demultiplexed bus cycle with normal ALE

Demultiplexed bus cycle with extended ALE

4 + 2 + 2

6 + 2 + 2

× (15 - <MCTC>)

× (1 - <MTTC>)

× (15 - <MCTC>)

× (1 - <MTTC>)

TCL 80 ns / 60.6 ns / 50 ns

TCL 120 ns / 90.9 ns / 75 ns

Multiplexed bus cycle with normal ALE

Multiplexed bus cycle with extended ALE

Data Sheet 63 V2.2, 2001-08

6 + 2 + 2

8 + 2 + 2

× (15 - <MCTC>)

× (1 - <MTTC>)

× (15 - <MCTC>)

× (1 - <MTTC>)

TCL 120 ns / 90.9 ns / 75 ns

TCL 160 ns / 121.2 ns / 100 ns

C167CS-4R

C167CS-L

Table 17 External Bus Cycle Timing (Operating Conditions apply)

Parameter Symbol Limits Unit

min. max.

Output delay from CLKOUT falling edge Valid for: address (MUX on PORT0), write data out

Output delay from CLKOUT edge Valid for: latched CS

, ALE (normal)

Output delay from CLKOUT edge Valid for: WR

, WRL, WRH, WrCS

Output delay from CLKOUT edge Valid for: RD

, RdCS

Input setup time to CLKOUT falling edge Valid for: read data in

Input hold time after CLKOUT falling edge Valid for: read data in

Output delay from CLKOUT falling edge Valid for: address (on PORT1 and/or P4), BHE

Output hold time after CLKOUT falling edge Valid for: address, BHE

Output hold time after CLKOUT edge

Valid for: write data out

CC 0 14 ns

CC -3 6 ns

CC -4 7 ns

CC -2 7 ns

SR 10 – ns

SR 0 – ns

CC 0 9

CC -2 8 ns

CC -1 – ns

Output delay from CLKOUT falling edge

CC -4 4 ns

Valid for: ALE (extended), early CS

Turn off delay after CLKOUT edge

CC – 7ns

Valid for: write data out

Turn on delay after CLKOUT falling edge

CC -5 – ns

Valid for: write data out

Output hold time after CLKOUT edge

CC -6 4 ns

Valid for: early CS

Read data are latched with the same (internal) clock edge that triggers the address change and the rising edge

. Therefore address changes before the end of RD have no impact on (demultiplexed) read cycles.

of RD

If the capacitive load on the respective output pins is limited to 30 pF the maximum output delay tc16 can be reduced to 8 ns.

Due to comparable propagation delays the address does not change before WR goes high. The minimum

output delay (

Not 100% tested, guaranteed by design and characterization.

) is therefore the actual value of tc12.

17min

Data Sheet 64 V2.2, 2001-08

C167CS-4R

C167CS-L

The bandwidth of a parameter (minimum and maximum value) covers the whole operating range (temperature, voltage) as well as process variations. Within a given device, however, this bandwidth is smaller than the specified range. This is also due to interdependencies between certain parameters. Some of these interdependencies are described as relative timing (see below) or in additional notes (see standard timing).

Table 18 External Bus Relative Timing (Operating Conditions apply)

Parameter Symbol Limits Unit

min. max.

Output hold time after WR

rising edge

CC 0 – ns

Valid for: address, write data out

Input hold time after RD

rising edge

SR – 0ns

Valid for: read data in

Not 100% tested, guaranteed by design and characterization.

General Notes For The Following Bus Timing Figures

These standard notes apply to all subsequent timing figures. Additional individual notes are placed at the respective figure.

The falling edge of signals RD and WR/WRH/WRL/WrCS is controlled by the Read/Write delay feature (bit BUSCON.RWDCx).

The rising edge of signal WR/WRH/WRL/WrCS is controlled by the early write feature (bit BUSCON.EWENx).

A bus cycle is extended here, if MCTC waitstates are selected or if the READY input is sampled inactive.

A bus cycle is extended here, if an MTTC waitstate is selected.

Data Sheet 65 V2.2, 2001-08

CLKOUT

Normal ALE

Extended ALE

Normal ALE Cycle

Extended ALE Cycle

C167CS-4R

C167CS-L

CSxE, CSxL

tc tc

A23-A0, BHE

WRL, WRH, WR, WrCS

D15-D0

Note: Write data is deactivated 1 TCL earlier

if early write is enabled (same timing).

Valid

MCTC

Data OUT

MTTC

MCT04435

Figure 17 Demultiplexed Bus, Write Access

Data Sheet 66 V2.2, 2001-08

CLKOUT

Normal ALE

Extended ALE

Normal ALE Cycle

Extended ALE Cycle

C167CS-4R

C167CS-L

CSxE, CSxL

A23-A0, BHE

RD, RdCS

D15-D0

tc tc

Valid

MCTC

Data IN

MTTC

MCT04436

Figure 18 Demultiplexed Bus, Read Access

Data Sheet 67 V2.2, 2001-08

CLKOUT

Normal ALE

Extended ALE

Extended ALE Cycle

C167CS-4R

C167CS-L

Normal ALE Cycle

CSxE, CSxL

A23-A16, BHE

WRL, WRH, WR, WrCS

AD15-AD0 (Normal ALE)

AD15-AD0 (Extended ALE)

tc tc

Low Address

Valid

12 12

Data OUT

MCTC

Note: Write data is deactivated 2 TCL earlier if early write is enabled (same timing).

MTTC

MCT04437

Figure 19 Multiplexed Bus, Write Access

Data Sheet 68 V2.2, 2001-08

CLKOUT

Normal ALE

Extended ALE

Extended ALE Cycle

C167CS-4R

C167CS-L

Normal ALE Cycle

CSxE, CSxL

A23-A16, BHE

RD, RdCS

AD15-AD0 (Normal ALE)

AD15-AD0 (Extended ALE)

tc tc

Low Address

Valid

1721

Data IN

MCTC

MTTC

MCT04438

Figure 20 Multiplexed Bus, Read Access

Data Sheet 69 V2.2, 2001-08

C167CS-4R

C167CS-L

Bus Cycle Control via READY Input

The duration of an external bus cycle can be controlled by the external circuitry via the READY

input signal.

Synchronous READY

permits the shortest possible bus cycle but requires the input

signal to be synchronous to the reference signal CLKOUT.

Asynchronous READY

puts no timing constraints on the input signal but incurs one

waitstate minimum due to the additional synchronization stage.

Table 19 READY Timing (Operating Conditions apply)

Parameter Symbol Limit Values Unit

min. max.

Input setup time to CLKOUT rising edge Valid for: READY

input

Input hold time after CLKOUT rising edge Valid for: READY

Asynchronous READY

Notes (Valid for Table 19 and Figure 21)

Cycle as programmed, including MCTC waitstates (Example shows 0 MCTC WS).

Multiplexed bus modes have a MUX waitstate added after a bus cycle, and an additional MTTC waitstate may be inserted here. For a multiplexed bus with MTTC waitstate this delay is 2 CLKOUT cycles, for a demultiplexed bus without MTTC waitstate this delay is zero.

These timings are given for test purposes only, in order to assure recognition at a specific clock edge. If the Asynchronous READY it must fulfill Proper deactivation of READY of the corresponding command (RD

READY sampled HIGH at this sampling point generates a READY controlled waitstate, READY

If the next following bus cycle is READY controlled, an active READY signal must be disabled before the first valid sample point for the next bus cycle. This sample point depends on the MTTC waitstate of the current cycle, and on the MCTC waitstates and the ALE mode of the next following cycle. If the current cycle uses a multiplexed bus the intrinsic MUX waitstate adds another CLKOUT cycle to the READY

sampled LOW at this sampling point terminates the currently running bus cycle.

input

input low time

signal does not fulfill the indicated setup and hold times with respect to CLKOUT,

in order to be safely synchronized.

is guaranteed if READY is deactivated in response to the trailing (rising) edge

or WR).

CC 12 – ns

CC 0 – ns

CC tc5 + tc

– ns

deactivation time.

Data Sheet 70 V2.2, 2001-08

C167CS-4R

C167CS-L

Running Cycle

READY WS MUX/MTTC

CLKOUT

D15-D0 Data IN

D15-D0 Data OUT

Command (RD, WR)

Synchronous READY

Asynchronous READY

4) 4)

The next external bus cycle may start here.

MCT04820

Figure 21 READY Timing

Data Sheet 71 V2.2, 2001-08

C167CS-4R

C167CS-L

External Bus Arbitration

Table 20 Bus Arbitration Timing (Operating Conditions apply)

Parameter Symbol Limit Values Unit

min. max.

HOLD

CLKOUT to BREQ

CLKOUT to HLDA

CSx

Other signals release

Other signals drive

input setup time to CLKOUT falling edge tc

delay tc

release

drive tc

Not 100% tested, guaranteed by design and characterization.

SR 14 – ns

CC -3 6 ns

CC -2 6 ns

CC 0 10 ns

CC -3 4 ns

CC 0 10 ns

CC 0 6 ns

Data Sheet 72 V2.2, 2001-08

CLKOUT

HOLD

HLDA

C167CS-4R

C167CS-L

BREQ

Other Signals

MCT04421

Figure 22 External Bus Arbitration, Releasing the Bus

Notes

The C167CS will complete the currently running bus cycle before granting bus access.

This is the first possibility for BREQ to get active.

The CS outputs will be resistive high (pullup) after t33. Latched CS outputs are driven high for 1 TCL before the output drivers are switched off.

Data Sheet 73 V2.2, 2001-08

C167CS-4R

C167CS-L

CLKOUT

HOLD

HLDA

BREQ

Other Signals

MCT04422

Figure 23 External Bus Arbitration, (Regaining the Bus)

Notes

This is the last chance for BREQ to trigger the indicated regain-sequence. Even if BREQ Please note that HOLD

The next C167CS driven bus cycle may start here.

is activated earlier, the regain-sequence is initiated by HOLD going high.

may also be deactivated without the C167CS requesting the bus.

Data Sheet 74 V2.2, 2001-08

C167CS-4R

C167CS-L

External XRAM Access

If XPER-Share mode is enabled the on-chip XRAM of the C167CS can be accessed (during hold states) by an external master like an asynchronous SRAM.

Table 21 XRAM Access Timing (Operating Conditions apply)

Parameter Symbol Limit Values Unit

min. max.

Address setup time before RD

Address hold time after RD

Data turn on delay after RD

/WR falling edge t

/WR rising edge t

falling edge

Data output valid delay after address latched

Data turn off delay after RD

Write data setup time before WR

Write data hold time after WR

pulse width t

signal recovery time t

Address

Command (RD, WR)

rising edge t

rising edge

rising edge t

SR 4 – ns

SR 0 – ns

CC 2 – ns

CC – 37 ns

Read

CC 0 10 ns

SR 10 – ns

SR 1 – ns

Write

SR 18 – ns

SR t

– ns

Write Data

Read Data

MCT04423

Figure 24 External Access to the XRAM

Data Sheet 75 V2.2, 2001-08

Package Outlines

P-MQFP-144-6

(Plastic Metric Quad Flat Package)

C167CS-4R

C167CS-L

Sorts of Packing

Package outlines for tubes, trays etc. are contained in our Data Book “Package Information”.

SMD = Surface Mounted Device

Data Sheet 76 V2.2, 2001-08

Dimensions in mm

GPM09391

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Published by Infineon Technologies AG

INFINEON C167CS-4R, C167CS-L User Manual

Specifications and Main Features

Frequently Asked Questions

User Manual

Ordering Information

Introduction

Pin Configuration

Functional Description

Memory Organization

External Bus Controller

Central Processing Unit (CPU)

Interrupt System

Capture/Compare (CAPCOM) Units

PWM Module

General Purpose Timer (GPT) Unit

Real Time Clock

A/D Converter

Serial Channels

CAN-Modules

Watchdog Timer

Parallel Ports

Oscillator Watchdog

Power Management

Instruction Set Summary

Special Function Registers Overview

Absolute Maximum Ratings

Operating Conditions

Parameter Interpretation

DC Characteristics

Power Consumption C167CS

AC Characteristics Definition of Internal Timing

Prescaler Operation

Phase Locked Loop

Direct Drive

AC Characteristics External Clock Drive XTAL1

A/D Converter Characteristics

Converter Timing Example:

Testing Waveforms

AC Characteristics

Variable Memory Cycles

General Notes For The Following Bus Timing Figures

Bus Cycle Control via READY Input

External Bus Arbitration

External XRAM Access

Package Outlines