Datasheet C167CR, C167SR Datasheet (INFINEON)

Data Sheet, V3.3, Feb. 2005

C167CR
C167SR

16-Bit Single-Chip Microcontroller

Microcontrollers

Never stop thinking.

Edition 2005-02

Published by Infineon Technologies AG,
St.-Martin-Strasse 53,
81669 München, Germany

© Infineon Technologies AG 2005.

All Rights Reserved.

Attention please!

The information herein is given to describe certain components and shall not be considered as a guarantee of
characteristics.

Terms of delivery and rights to technical change reserved.
We hereby disclaim any and all warranties, including but not limited to warranties of non-infringement, regarding

circuits, descriptions and charts stated herein.

Information

For further information on technology, delivery terms and conditions and prices please contact your nearest
Infineon Technologies Office (www.infineon.com).

Warnings

Due to technical requirements components may contain dangerous substances. For information on the types in
question please contact your nearest Infineon Technologies Office.

Infineon Technologies Components may only be used in life-support devices or systems with the express written
approval of Infineon Technologies, if a failure of such components can reasonably be expected to cause the failure
of that life-support device or system, or to affect the safety or effectiveness of that device or system. Life support
devices or systems are intended to be implanted in the human body, or to support and/or maintain and sustain
and/or protect human life. If they fail, it is reasonable to assume that the health of the user or other persons may
be endangered.

Data Sheet, V3.3, Feb. 2005

C167CR
C167SR

16-Bit Single-Chip Microcontroller

Microcontrollers

Never stop thinking.

C167CR, C167SR

Revision History: 2005-02 V3.3

Previous Version: V3.2, 2001-07

V3.1, 2000-04
V3.0, 2000-02
1999-10 (Introduction of clock-related timing)
1999-06
1999-03 (Summarizes and replaces all older docs)
1998-03 (C167SR/CR, 25 MHz Addendum)

07.97 / 12.96 (C167CR-4RM)

12.96 (C167CR-16RM)

06.95 (C167CR, C167SR)

06.94 / 05.93 (C167)

Page Subjects (major changes since last revision)

all The layout of several graphics and text structures has been adapted to

company documentation rules, obvious typographical errors have been
corrected.

all The contents of this document have been re-arranged into numbered

sections and a table of contents has been added.

6 BGA-type added to product list

8 Pin designation corrected (pin 78)

9 Input threshold control added to Port 6

17

…

25 Pin diagram and pin description for BGA package added

45 Port 6 added to input-threshold controlled ports

85 Mechanical package drawing corrected (P-MQFP-144-8)

86 Mechanical package drawing added (P-BGA-176-2)

We Listen to Your Comments

Any information within this document that you feel is wrong, unclear or missing at all?
Your feedback will help us to continuously improve the quality of this document.
Please send your proposal (including a reference to this document) to:

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Template: mc_a5_ds_tmplt.fm / 4 / 2004-09-15

C167CR

C167SR

Table of Contents

Table of Contents

Table of Contents . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3

1 Summary of Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4

2 General Device Information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7

2.1 Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7

2.2 Pin Configuration and Definition for P-MQFP-144-8 . . . . . . . . . . . . . . . . . . 8

2.3 Pin Configuration and Definition for P-BGA-176-2 . . . . . . . . . . . . . . . . . . 17

3 Functional Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26

3.1 Memory Organization . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 27

3.2 External Bus Controller . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 28

3.3 Central Processing Unit (CPU) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 30

3.4 Interrupt System . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 32

3.5 Capture/Compare (CAPCOM) Units . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 36

3.6 PWM Module . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 38

3.7 General Purpose Timer (GPT) Unit . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 39

3.8 A/D Converter . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 42

3.9 Serial Channels . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 43

3.10 CAN-Module . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 44

3.11 Watchdog Timer . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 44

3.12 Parallel Ports . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 45

3.13 Oscillator Watchdog . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 46

3.14 Instruction Set Summary . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 47

3.15 Special Function Registers Overview . . . . . . . . . . . . . . . . . . . . . . . . . . . . 50

4 Electrical Parameters . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 58

4.1 General Parameters . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 58

4.2 DC Parameters . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 60

4.3 Analog/Digital Converter Parameters . . . . . . . . . . . . . . . . . . . . . . . . . . . . 64

4.4 AC Parameters . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 66

4.4.1 Definition of Internal Timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 66

4.4.2 External Clock Drive XTAL1 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 70

4.4.3 Testing Waveforms . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 71

4.4.4 External Bus Timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 72

5 Package Outlines . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 85

Data Sheet 3 V3.3, 2005-02

C167CR/C167SR16-Bit Single-Chip Microcontroller

C166 Family

1 Summary of Features

• High Performance 16-bit CPU with 4-Stage Pipeline
– 80/60 ns Instruction Cycle Time at 25/33 MHz CPU Clock
– 400/303 ns Multiplication (16 × 16 bits), 800/606 ns Division (32 / 16 bits)
– Enhanced Boolean Bit Manipulation Facilities
– Additional Instructions to Support HLL and Operating Systems
– Register-Based Design with Multiple Variable Register Banks
– Single-Cycle Context Switching Support
– 16 Mbytes Total Linear Address Space for Code and Data
– 1024 Bytes On-Chip Special Function Register Area

• 16-Priority-Level Interrupt System with 56 Sources, Sample-Rate down to 40/30 ns

• 8-Channel Interrupt-Driven Single-Cycle Data Transfer Facilities via
Peripheral Event Controller (PEC)

• Clock Generation via on-chip PLL (factors 1:1.5/2/2.5/3/4/5),
via prescaler or via direct clock input

• On-Chip Memory Modules
– 2 Kbytes On-Chip Internal RAM (IRAM)
– 2 Kbytes On-Chip Extension RAM (XRAM)
– 128/32 Kbytes On-Chip Mask ROM

• On-Chip Peripheral Modules
– 16-Channel 10-bit A/D Converter with Programmable Conversion Time

down to 7.8 µs
– Two 16-Channel Capture/Compare Units
– 4-Channel PWM Unit
– Two Multi-Functional General Purpose Timer Units with 5 Timers
– Two Serial Channels (Synchronous/Asynchronous and

High-Speed-Synchronous)
– On-Chip CAN Interface (Rev. 2.0B active) with 15 Message Objects

(Full CAN / Basic CAN)

• Up to 16 Mbytes External Address Space for Code and Data
– Programmable External Bus Characteristics for Different Address Ranges
– Multiplexed or Demultiplexed External Address/Data Buses with 8-Bit or 16-Bit

Data Bus Width
– Five Programmable Chip-Select Signals
– Hold- and Hold-Acknowledge Bus Arbitration Support

• Idle and Power Down Modes

• Programmable Watchdog Timer and Oscillator Watchdog

Data Sheet 4 V3.3, 2005-02

C167CR

C167SR

Summary of Features

• Up to 111 General Purpose I/O Lines,
partly with Selectable Input Thresholds and Hysteresis

• Supported by a Large Range of Development Tools like C-Compilers,
Macro-Assembler Packages, Emulators, Evaluation Boards, HLL-Debuggers,
Simulators, Logic Analyzer Disassemblers, Programming Boards

• On-Chip Bootstrap Loader

• 144-Pin MQFP Package

• 176-Pin BGA Package

Ordering Information

The ordering code for Infineon microcontrollers provides an exact reference to the
required product. This ordering code identifies:

• the derivative itself, i.e. its function set, the temperature range, and the supply voltage

• the package and the type of delivery.

1)

For the available ordering codes for the C167CR please refer to the “Product Catalog
Microcontrollers”, which summarizes all available microcontroller variants.

Note: The ordering codes for Mask-ROM versions are defined for each product after

verification of the respective ROM code.

This document describes several derivatives of the C167 group. Table 1 enumerates
these derivatives and summarizes the differences. As this document refers to all of these
derivatives, some descriptions may not apply to a specific product.

For simplicity all versions are referred to by the term C167CR throughout this document.

1) The external connections of the C167CR in P-BGA-176-2 are referred to as pins throughout this document,

although they are mechanically realized as solder balls.

Data Sheet 5 V3.3, 2005-02

Table 1 C167CR Derivative Synopsis

Derivative

1)

Program

XRAM Size Operating

ROM Size

C167CR

C167SR

Summary of Features

Package

Frequency

SAK-C167SR-LM

– 2 Kbytes 25 MHz P-MQFP-144-8

SAB-C167SR-LM

SAK-C167SR-L33M

– 2 Kbytes 33 MHz P-MQFP-144-8

SAB-C167SR-L33M

SAK-C167CR-LM

– 2 Kbytes 25 MHz P-MQFP-144-8
SAF-C167CR-LM
SAB-C167CR-LM

SAK-C167CR-L33M

– 2 Kbytes 33 MHz P-MQFP-144-8
SAB-C167CR-L33M

SAK-C167CR-4RM

32 Kbytes 2 Kbytes 25 MHz P-MQFP-144-8
SAB-C167CR-4RM

SAK-C167CR-4R33M

32 Kbytes 2 Kbytes 33 MHz P-MQFP-144-8
SAB-C167CR-4R33M

SAK-C167CR-16RM 128 Kbytes 2 Kbytes 25 MHz P-MQFP-144-8

SAK-C167CR-16R33M 128 Kbytes 2 Kbytes 33 MHz P-MQFP-144-8

SAK-C167CR-LE – 2 Kbytes 25 MHz P-BGA-176-2

1) This Data Sheet is valid for devices manufactured in 0.5 µm technology, i.e. devices starting with and including

design step GA(-T)6.

Data Sheet 6 V3.3, 2005-02

C167CR

C167SR

General Device Information

2 General Device Information

2.1 Introduction

The C167CR derivatives are high performance derivatives of the Infineon C166 Family
of full featured single-chip CMOS microcontrollers. They combine high CPU
performance (up to 16.5 million instructions per second) with high peripheral functionality
and enhanced IO-capabilities. They also provide clock generation via PLL and various
on-chip memory modules such as program ROM, internal RAM, and extension RAM.

V

V

AREF AGND

V

DDVSS

XTAL1
XTAL2

RSTIN
RSTOUT

NMI

EA

READY

ALE
RD
WR/WRL

Port 5
16 Bit

Figure 1 Logic Symbol

C167CR

Port 0
16 Bit

Port 1
16 Bit

Port 2
16 Bit

Port 3
15 Bit

Port 4
8 Bit

Port 6
8 Bit

Port 7
8 Bit

Port 8
8 Bit

MCL04411

Data Sheet 7 V3.3, 2005-02

C167CR

C167SR

General Device Information

2.2 Pin Configuration and Definition for P-MQFP-144-8

The pins of the C167CR are described in detail in Table 2, including all their alternate
functions. Figure 2 summarizes all pins in a condensed way, showing their location on
the 4 sides of the package.

Note: The P-BGA-176-2 is described in Table 3 and Figure 3.

P6.0/CS0
P6.1/CS1
P6.2/CS2
P6.3/CS3
P6.4/CS4

P6.5/HOLD

P6.6/HLDA

P6.7/BREQ
P8.0/CC16IO
P8.1/CC17IO
P8.2/CC18IO
P8.3/CC19IO
P8.4/CC20IO
P8.5/CC21IO
P8.6/CC22IO
P8.7/CC23IO

V
V

P7.0/POUT0
P7.1/POUT1
P7.2/POUT2

P7.3/POUT3
P7.4/CC28IO
P7.5/CC29IO
P7.6/CC30IO
P7.7/CC31IO

P5.0/AN0
P5.1/AN1
P5.2/AN2
P5.3/AN3
P5.4/AN4
P5.5/AN5
P5.6/AN6
P5.7/AN7
P5.8/AN8
P5.9/AN9

SS

VDDV

144

143

1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17

DD

18

SS

19
20
21
22
23
24
25
26
27
28
29
30
31
32
33
34
35
36

373839

AREF

AGND

V

V

SS

RSTIN

RSTOUT

NMI

142

141

404142

P5.11/AN11/T5EUD

P5.10/AN10/T6EUD

XTAL2

V

XTAL1

139

140

138

137

434445

P5.13/AN13/T5IN

P5.12/AN12/T6IN

P5.15/AN15/T2EUD

P5.14/AN14/T4EUD

DD

V

136

SS

V

P1H.4/A12/CC24IO

P1H.5/A13/CC25IO

P1H.6/A14/CC26IO

P1H.7/A15/CC27IO

133

135

134

132

464748

495051

DD

V

P2.2/CC2IO

P2.1/CC1IO

P2.0/CC0IO

P1H.0/A8

P1H.1/A9

P1H.2/A10

P1H.3/A11

130

131

129

128

C167CR

525354

P2.6/CC6IO

P2.5/CC5IO

P2.4/CC4IO

P2.3/CC3IO

DD

P1L.6/A6

VSSV

P1L.7/A7

127

124

126

125

555657

SS

DD

V

V

P2.7/CC7IO

P2.8/CC8IO/EX0IN

P1L.0/A0

P1L.1/A1

P1L.2/A2

P1L.3/A3

P1L.4/A4

P1L.5/A5

121

123

122

585960

P2.9/CC9IO/EX1IN

P2.10/CC10IO/EX2IN

118

120

119

616263

P2.14/CC14IO/EX6IN

P2.13/CC13IO/EX5IN

P2.12/CC12IO/EX4IN

P2.11/CC11IO/EX3IN

P0H.7/AD15

115

117

116

114

646566

676869

P3.0/T0IN

P3.2/CAPIN

P3.1/T6OUT

P2.15/CC15IO/EX7IN/T7IN

VSSV

112

113

111

110

707172

SS

V

P3.5/T4IN

P3.4/T3EUD

P3.3/T3OUT

109

108
107
106
105
104
103
102
101
100

V

P0H.1/AD9

P0H.2/AD10

P0H.3/AD11

P0H.4/AD12

P0H.5/AD13

P0H.6/AD14

DD

P0H.0/AD8
P0L.7/AD7
P0L.6/AD6
P0L.5/AD5
P0L.4/AD4
P0L.3/AD3
P0L.2/AD2
P0L.1/AD1
P0L.0/AD0
EA

99

ALE

98

READY

97
96

WR/WRL

95

RD

94

V

SS

93

V

DD

92

P4.7/A23
P4.6/A22/CAN1_TxD

91
90

P4.5/A21/CAN1_RxD

89

P4.4/A20

88

P4.3/A19
P4.2/A18

87

P4.1/A17

86

P4.0/A16

85

OWE

84
83

V

SS

82

V

DD

81

P3.15/CLKOUT

80

P3.13/SCLK

79

P3.12/BHE/WRH

78

P3.11/RxD0

77

P3.10/TxD0
P3.9/MTSR

76

P3.8/MRST

75

P3.7/T2IN

74

P3.6/T3IN

73

DD

MCP04410

Figure 2 Pin Configuration P-MQFP-144-8 (top view)

Data Sheet 8 V3.3, 2005-02

General Device Information

Table 2 Pin Definitions and Functions P-MQFP-144-8

C167CR

C167SR

Symbol Pin

No.

P6

P6.0
P6.1
P6.2
P6.3
P6.4
P6.5
P6.6

P6.7

1
2
3
4
5
6
7

8

P8

P8.0
P8.1
P8.2
P8.3
P8.4
P8.5
P8.6
P8.7

9
10
11
12
13
14
15
16

Input
Outp.

IO

O
O
O
O
O
I
I/O

O

IO

I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O

Function

Port 6 is an 8-bit bidirectional I/O port. It is bit-wise
programmable for input or output via direction bits. For a pin
configured as input, the output driver is put into high­impedance state. Port 6 outputs can be configured as
push/pull or open drain drivers. The input threshold of Port 6
is selectable (TTL or special).
The Port 6 pins also serve for alternate functions:
CS0
CS1
CS2
CS3
CS4
HOLD
HLDA

Chip Select 0 Output
Chip Select 1 Output
Chip Select 2 Output
Chip Select 3 Output
Chip Select 4 Output
External Master Hold Request Input
Hold Acknowledge Output (master mode) or
Input (slave mode)

BREQ

Bus Request Output

Port 8 is an 8-bit bidirectional I/O port. It is bit-wise
programmable for input or output via direction bits. For a pin
configured as input, the output driver is put into high­impedance state. Port 8 outputs can be configured as
push/pull or open drain drivers. The input threshold of Port 8
is selectable (TTL or special).
The following Port 8 pins also serve for alternate functions:
CC16IO CAPCOM2: CC16 Capture Inp./Compare Outp.
CC17IO CAPCOM2: CC17 Capture Inp./Compare Outp.
CC18IO CAPCOM2: CC18 Capture Inp./Compare Outp.
CC19IO CAPCOM2: CC19 Capture Inp./Compare Outp.
CC20IO CAPCOM2: CC20 Capture Inp./Compare Outp.
CC21IO CAPCOM2: CC21 Capture Inp./Compare Outp.
CC22IO CAPCOM2: CC22 Capture Inp./Compare Outp.
CC23IO CAPCOM2: CC23 Capture Inp./Compare Outp.

Data Sheet 9 V3.3, 2005-02

General Device Information

Table 2 Pin Definitions and Functions P-MQFP-144-8 (cont’d)

C167CR

C167SR

Symbol Pin

No.

P7

P7.0
P7.1
P7.2
P7.3
P7.4
P7.5
P7.6
P7.7

19
20
21
22
23
24
25
26

P5

P5.0
P5.1
P5.2
P5.3
P5.4
P5.5
P5.6
P5.7
P5.8
P5.9
P5.10
P5.11
P5.12
P5.13
P5.14
P5.15

27
28
29
30
31
32
33
34
35
36
39
40
41
42
43
44

Input
Outp.

IO

O
O
O
O
I/O
I/O
I/O
I/O

I

I
I
I
I
I
I
I
I
I
I
I
I
I
I
I
I

Function

Port 7 is an 8-bit bidirectional I/O port. It is bit-wise
programmable for input or output via direction bits. For a pin
configured as input, the output driver is put into high­impedance state. Port 7 outputs can be configured as
push/pull or open drain drivers. The input threshold of Port 7
is selectable (TTL or special).
The following Port 7 pins also serve for alternate functions:
POUT0 PWM Channel 0 Output
POUT1 PWM Channel 1 Output
POUT2 PWM Channel 2 Output
POUT3 PWM Channel 3 Output
CC28IO CAPCOM2: CC28 Capture Inp./Compare Outp.
CC29IO CAPCOM2: CC29 Capture Inp./Compare Outp.
CC30IO CAPCOM2: CC30 Capture Inp./Compare Outp.
CC31IO CAPCOM2: CC31 Capture Inp./Compare Outp.

Port 5 is a 16-bit input-only port with Schmitt-Trigger
characteristic.
The pins of Port 5 also serve as analog input channels for the
A/D converter, or they serve as timer inputs:
AN0
AN1
AN2
AN3
AN4
AN5
AN6
AN7
AN8
AN9
AN10, T6EUD GPT2 Timer T6 Ext. Up/Down Ctrl. Inp.
AN11, T5EUD GPT2 Timer T5 Ext. Up/Down Ctrl. Inp.
AN12, T6IN GPT2 Timer T6 Count Inp.
AN13, T5IN GPT2 Timer T5 Count Inp.
AN14, T4EUD GPT1 Timer T4 Ext. Up/Down Ctrl. Inp.
AN15, T2EUD GPT1 Timer T5 Ext. Up/Down Ctrl. Inp.

Data Sheet 10 V3.3, 2005-02

General Device Information

Table 2 Pin Definitions and Functions P-MQFP-144-8 (cont’d)

C167CR

C167SR

Symbol Pin

No.

P2

P2.0
P2.1
P2.2
P2.3
P2.4
P2.5
P2.6
P2.7
P2.8

P2.9

P2.10

P2.11

P2.12

P2.13

P2.14

P2.15

47
48
49
50
51
52
53
54
57

58

59

60

61

62

63

64

Input
Outp.

IO

I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I
I/O
I
I/O
I
I/O
I
I/O
I
I/O
I
I/O
I
I/O
I
I

Function

Port 2 is a 16-bit bidirectional I/O port. It is bit-wise
programmable for input or output via direction bits. For a pin
configured as input, the output driver is put into high­impedance state. Port 2 outputs can be configured as
push/pull or open drain drivers. The input threshold of Port 2
is selectable (TTL or special).
The following Port 2 pins also serve for alternate functions:
CC0IO CAPCOM1: CC0 Capture Inp./Compare Output
CC1IO CAPCOM1: CC1 Capture Inp./Compare Output
CC2IO CAPCOM1: CC2 Capture Inp./Compare Output
CC3IO CAPCOM1: CC3 Capture Inp./Compare Output
CC4IO CAPCOM1: CC4 Capture Inp./Compare Output
CC5IO CAPCOM1: CC5 Capture Inp./Compare Output
CC6IO CAPCOM1: CC6 Capture Inp./Compare Output
CC7IO CAPCOM1: CC7 Capture Inp./Compare Output
CC8IO CAPCOM1: CC8 Capture Inp./Compare Output,
EX0IN Fast External Interrupt 0 Input
CC9IO CAPCOM1: CC9 Capture Inp./Compare Output,
EX1IN Fast External Interrupt 1 Input
CC10IO CAPCOM1: CC10 Capture Inp./Compare Outp.,
EX2IN Fast External Interrupt 2 Input
CC11IO CAPCOM1: CC11 Capture Inp./Compare Outp.,
EX3IN Fast External Interrupt 3 Input
CC12IO CAPCOM1: CC12 Capture Inp./Compare Outp.,
EX4IN Fast External Interrupt 4 Input
CC13IO CAPCOM1: CC13 Capture Inp./Compare Outp.,
EX5IN Fast External Interrupt 5 Input
CC14IO CAPCOM1: CC14 Capture Inp./Compare Outp.,
EX6IN Fast External Interrupt 6 Input
CC15IO CAPCOM1: CC15 Capture Inp./Compare Outp.,
EX7IN Fast External Interrupt 7 Input,
T7IN CAPCOM2: Timer T7 Count Input

Data Sheet 11 V3.3, 2005-02

General Device Information

Table 2 Pin Definitions and Functions P-MQFP-144-8 (cont’d)

C167CR

C167SR

Symbol Pin

No.

P3

P3.0
P3.1
P3.2
P3.3
P3.4
P3.5
P3.6
P3.7
P3.8
P3.9
P3.10
P3.11
P3.12

P3.13
P3.15

65
66
67
68
69
70
73
74
75
76
77
78
79

80
81

Input
Outp.

IO

I
O
I
O
I
I
I
I
I/O
I/O
O
I/O
O
O
I/O
O

Function

Port 3 is a 15-bit bidirectional I/O port. It is bit-wise
programmable for input or output via direction bits. For a pin
configured as input, the output driver is put into high­impedance state. Port 3 outputs can be configured as
push/pull or open drain drivers. The input threshold of Port 3
is selectable (TTL or special).
The following Port 3 pins also serve for alternate functions:
T0IN CAPCOM1 Timer T0 Count Input
T6OUT GPT2 Timer T6 Toggle Latch Output
CAPIN GPT2 Register CAPREL Capture Input
T3OUT GPT1 Timer T3 Toggle Latch Output
T3EUD GPT1 Timer T3 External Up/Down Control Input
T4IN GPT1 Timer T4 Count/Gate/Reload/Capture Inp.
T3IN GPT1 Timer T3 Count/Gate Input
T2IN GPT1 Timer T2 Count/Gate/Reload/Capture Inp.
MRST SSC Master-Receive/Slave-Transmit Inp./Outp.
MTSR SSC Master-Transmit/Slave-Receive Outp./Inp.
TxD0 ASC0 Clock/Data Output (Async./Sync.)
RxD0 ASC0 Data Input (Async.) or Inp./Outp. (Sync.)
BHE
WRH

External Memory High Byte Enable Signal,

External Memory High Byte Write Strobe
SCLK SSC Master Clock Output / Slave Clock Input.
CLKOUT System Clock Output (= CPU Clock)

OWE
(

V

PP

)

84 I Oscillator Watchdog Enable. This input enables the oscillator

watchdog when high or disables it when low e.g. for testing
purposes. An internal pull-up device holds this input high if
nothing is driving it.
For normal operation pin OWE should be high or not
connected.
In order to drive pin OWE low draw a current of at least
200 µA.

Data Sheet 12 V3.3, 2005-02

General Device Information

Table 2 Pin Definitions and Functions P-MQFP-144-8 (cont’d)

C167CR

C167SR

Symbol Pin

No.

P4

Input
Outp.

IO

Function

Port 4 is an 8-bit bidirectional I/O port. It is bit-wise
programmable for input or output via direction bits. For a pin
configured as input, the output driver is put into high­impedance state.
Port 4 can be used to output the segment address lines and
for serial bus interfaces:

P4.0
P4.1
P4.2
P4.3
P4.4
P4.5

P4.6

P4.7

85
86
87
88
89
90

91

92

O
O
O
O
O
O
I
O
O
O

A16 Least Significant Segment Address Line
A17 Segment Address Line
A18 Segment Address Line
A19 Segment Address Line
A20 Segment Address Line
A21 Segment Address Line,
CAN1_RxD CAN 1 Receive Data Input
A22 Segment Address Line,
CAN1_TxD CAN 1 Transmit Data Output
A23 Most Significant Segment Address Line

RD 95 O External Memory Read Strobe. RD

external instruction or data read access.

is activated for every

WR

/

WRL

96 O External Memory Write Strobe. In WR-mode this pin is

activated for every external data write access. In WRL

-mode
this pin is activated for low byte data write accesses on a
16-bit bus, and for every data write access on an 8-bit bus.
See WRCFG in register SYSCON for mode selection.

READY

97 I Ready Input. When the Ready function is enabled, a high

level at this pin during an external memory access will force
the insertion of memory cycle time waitstates until the pin
returns to a low level.
An internal pull-up device will hold this pin high when nothing
is driving it.

ALE 98 O Address Latch Enable Output. Can be used for latching the

address into external memory or an address latch in the
multiplexed bus modes.

EA

99 I External Access Enable pin. A low level at this pin during and

after Reset forces the C167CR to begin instruction execution
out of external memory. A high level forces execution out of
the internal program memory.
“ROMless” versions must have this pin tied to ‘0’.

Data Sheet 13 V3.3, 2005-02

General Device Information

Table 2 Pin Definitions and Functions P-MQFP-144-8 (cont’d)

C167CR

C167SR

Symbol Pin

No.

PORT0

P0L.0-7

100­107

P0H.0-7

108,
111­117

PORT1

P1L.0-7

118­125

P1H.0-7

128­135

P1H.4
P1H.5
P1H.6
P1H.7

132
133
134
135

Input

Function

Outp.

IO PORT0 consists of the two 8-bit bidirectional I/O ports P0L

and P0H. It is bit-wise programmable for input or output via
direction bits. For a pin configured as input, the output driver
is put into high-impedance state.
In case of an external bus configuration, PORT0 serves as
the address (A) and address/data (AD) bus in multiplexed
bus modes and as the data (D) bus in demultiplexed bus
modes.

Demultiplexed bus modes:

8-bit data bus: P0H = I/O, P0L = D7 - D0
16-bit data bus: P0H = D15 - D8, P0L = D7 - D0

Multiplexed bus modes:

8-bit data bus: P0H = A15 - A8, P0L = AD7 - AD0
16-bit data bus: P0H = AD15 - AD8, P0L = AD7 - AD0

IO

PORT1 consists of the two 8-bit bidirectional I/O ports P1L
and P1H. It is bit-wise programmable for input or output via
direction bits. For a pin configured as input, the output driver
is put into high-impedance state. PORT1 is used as the 16-bit
address bus (A) in demultiplexed bus modes and also after
switching from a demultiplexed bus mode to a multiplexed
bus mode.
The following PORT1 pins also serve for alternate functions:

I
I
I
I

CC24IO CAPCOM2: CC24 Capture Input
CC25IO CAPCOM2: CC25 Capture Input
CC26IO CAPCOM2: CC26 Capture Input
CC27IO CAPCOM2: CC27 Capture Input

XTAL2
XTAL1

137
138

O
I

XTAL2: Output of the oscillator amplifier circuit.
XTAL1: Input to the oscillator amplifier and input to the

internal clock generator
To clock the device from an external source, drive XTAL1,
while leaving XTAL2 unconnected. Minimum and maximum
high/low and rise/fall times specified in the AC
Characteristics must be observed.

Data Sheet 14 V3.3, 2005-02

General Device Information

Table 2 Pin Definitions and Functions P-MQFP-144-8 (cont’d)

C167CR

C167SR

Symbol Pin

No.

Input
Outp.

Function

RSTIN 140 I/O Reset Input with Schmitt-Trigger characteristics. A low level

at this pin while the oscillator is running resets the C167CR.
An internal pull-up resistor permits power-on reset using only
a capacitor connected to

V

SS

.
A spike filter suppresses input pulses < 10 ns. Input pulses
> 100 ns safely pass the filter. The minimum duration for a
safe recognition should be 100 ns + 2 CPU clock cycles.
In bidirectional reset mode (enabled by setting bit BDRSTEN
in register SYSCON) the RSTIN

line is internally pulled low
for the duration of the internal reset sequence upon any reset
(HW, SW, WDT). See note below this table.

Note: To let the reset configuration of PORT0 settle and to let

the PLL lock a reset duration of ca. 1 ms is
recommended.

RST
OUT

141 O Internal Reset Indication Output. This pin is set to a low level

when the part is executing either a hardware-, a software- or
a watchdog timer reset. RSTOUT

remains low until the EINIT

(end of initialization) instruction is executed.

NMI

V

AREF

V

AGND

142 I Non-Maskable Interrupt Input. A high to low transition at this

pin causes the CPU to vector to the NMI trap routine. When
the PWRDN (power down) instruction is executed, the NMI
pin must be low in order to force the C167CR to go into power
down mode. If NMI

is high, when PWRDN is executed, the
part will continue to run in normal mode.
If not used, pin NMI

should be pulled high externally.

37 – Reference voltage for the A/D converter.

38 – Reference ground for the A/D converter.

Data Sheet 15 V3.3, 2005-02

General Device Information

Table 2 Pin Definitions and Functions P-MQFP-144-8 (cont’d)

C167CR

C167SR

Symbol Pin

No.

V

DD

17, 46,
56, 72,
82, 93,

Input

Function

Outp.

– Digital Supply Voltage:

+ 5 V during normal operation and idle mode.
≥ 2.5 V during power down mode.

109,
126,
136,
144

V

SS

18, 45,

– Digital Ground.
55, 71,
83, 94,
110,
127,
139,
143

Note: The following behavioural differences must be observed when the bidirectional

reset is active:

• Bit BDRSTEN in register SYSCON cannot be changed after EINIT and is cleared
automatically after a reset.

• The reset indication flags always indicate a long hardware reset.

• The PORT0 configuration is treated as if it were a hardware reset. In particular, the
bootstrap loader may be activated when P0L.4 is low.

•Pin RSTIN

may only be connected to external reset devices with an open drain output

driver.

• A short hardware reset is extended to the duration of the internal reset sequence.

Data Sheet 16 V3.3, 2005-02

C167CR

C167SR

General Device Information

2.3 Pin Configuration and Definition for P-BGA-176-2

The pins1) of the C167CR are described in detail in Table 3, including all their alternate
functions. Figure 3 summarizes all pins in a condensed way, showing their location on
the bottom of the package.

Note: The P-MQFP-144-8 is described in Table 2 and Figure 2.

1 2 3 4 5 6 7 8 9 1011121314

A

B

C

D

E

F

G

H

J

K

L

V

AREF

P5.11

V

AGND

P5.13

P5.12

V

SS

P2.1

V

DD

P2.7

V

P2.9 P2.10 P2.12

P2.13

P2.14

P2.15

P3.2 P3.12

SS

P5.0 P7.7

P5.2P5.5 P7.3

P5.4

P5.6P5.9

P5.3 P7.1

P5.1

P5.7P5.10

P5.14P5.15

P2.0 P2.2

P2.3

P2.4P2.6 P2.5

P2.8

V

DD

P2.11

P3.1

V

DD

V

SS

V

SS

P7.6

P7.5

P7.4

P4.2

V

P8.5

SS

V

P7.2

P7.0

P4.6

DD

P8.7

P8.6

RD P0.12 P0.11

P8.4P5.8

P8.2

P0.1

P8.0

P6.6

P6.2

P0.8

P6.4P6.7P8.1

P6.1

P6.5

V

P6.3P8.3

V

RST

P1.9 P1.12P1.10

P1.7

P1.4 P1.5

P0.14

P0.9

V

IN

SS

SS

DD

RST
OUT

V

SS

V

SS

P0.15

P0.13

P0.10

P6.0

XTAL2

P1.15

P1.8

P1.6

P1.2

NMIXTAL1

V

DD

P1.14

P1.13

P1.11

V

DD

P1.3

P1.1P1.0

A

B

C

D

E

F

G

H

J

K

L

M

N

P3.4 P3.7 P3.8 P3.10 P4.7

P

1 2 3 4 5 6 7 8 9 1011121314

P3.6

P3.11P3.3P3.0

P3.13

V

DD

P3.15

P4.1

OWE

P4.0P3.9P3.5

P4.5

P4.3

P4.4

V

EA

SS

WR P0.0 P0.4

REA

V

DD

DY

P0.3

ALE

P0.5

P0.2

V

DD

P0.7

P0.6

M

N

P

Not connected or thermal ground

mc_c167crle_pindiagram.vsd

Figure 3 Pin Configuration P-BGA-176-2 (top view)

1) The external connections of the C167CR in P-BGA-176-2 are referred to as pins throughout this document,

although they are mechanically realized as solder balls.

Data Sheet 17 V3.3, 2005-02

General Device Information

Table 3 Pin Definitions and Functions P-BGA-176-2

C167CR

C167SR

Symbol Pin

Num.

P5

P5.0
P5.1
P5.2
P5.3
P5.4
P5.5
P5.6
P5.7
P5.8
P5.9
P5.10
P5.11
P5.12
P5.13
P5.14
P5.15

A5
D5
A4
C5
B4
A3
C4
D4
B3
C3
D3
C1
D1
D2
E3
E2

Input
Outp.

I

I
I
I
I
I
I
I
I
I
I
I
I
I
I
I
I

Function

Port 5 is a 16-bit input-only port with Schmitt-Trigger
characteristic.
The pins of Port 5 also serve as analog input channels for the
A/D converter, or they serve as timer inputs:
AN0
AN1
AN2
AN3
AN4
AN5
AN6
AN7
AN8
AN9
AN10, T6EUD GPT2 Timer T6 Ext. Up/Down Ctrl. Inp.
AN11, T5EUD GPT2 Timer T5 Ext. Up/Down Ctrl. Inp.
AN12, T6IN GPT2 Timer T6 Count Inp.
AN13, T5IN GPT2 Timer T5 Count Inp.
AN14, T4EUD GPT1 Timer T4 Ext. Up/Down Ctrl. Inp.
AN15, T2EUD GPT1 Timer T5 Ext. Up/Down Ctrl. Inp.

P7

P7.0
P7.1
P7.2
P7.3
P7.4
P7.5
P7.6
P7.7

D7
C7
B7
A7
D6
C6
B6
A6

IO

O
O
O
O
I/O
I/O
I/O
I/O

Port 7 is an 8-bit bidirectional I/O port. It is bit-wise
programmable for input or output via direction bits. For a pin
configured as input, the output driver is put into high­impedance state. Port 7 outputs can be configured as
push/pull or open drain drivers. The input threshold of Port 7
is selectable (TTL or special).
The following Port 7 pins also serve for alternate functions:
POUT0 PWM Channel 0 Output
POUT1 PWM Channel 1 Output
POUT2 PWM Channel 2 Output
POUT3 PWM Channel 3 Output
CC28IO CAPCOM2: CC28 Capture Inp./Compare Outp.
CC29IO CAPCOM2: CC29 Capture Inp./Compare Outp.
CC30IO CAPCOM2: CC30 Capture Inp./Compare Outp.
CC31IO CAPCOM2: CC31 Capture Inp./Compare Outp.

Data Sheet 18 V3.3, 2005-02

General Device Information

Table 3 Pin Definitions and Functions P-BGA-176-2 (cont’d)

C167CR

C167SR

Symbol Pin

Num.

P8

P8.0
P8.1
P8.2
P8.3
P8.4
P8.5
P8.6
P8.7

B10
A10
D9
C9
B9
A9
D8
C8

P6

P6.0
P6.1
P6.2
P6.3
P6.4
P6.5
P6.6

P6.7

A13
B12
D10
C11
A12
B11
C10

A11

Input
Outp.

IO

I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O

IO

O
O
O
O
O
I
I/O

O

Function

Port 8 is an 8-bit bidirectional I/O port. It is bit-wise
programmable for input or output via direction bits. For a pin
configured as input, the output driver is put into high­impedance state. Port 8 outputs can be configured as
push/pull or open drain drivers. The input threshold of Port 8
is selectable (TTL or special).
The following Port 8 pins also serve for alternate functions:
CC16IO CAPCOM2: CC16 Capture Inp./Compare Outp.
CC17IO CAPCOM2: CC17 Capture Inp./Compare Outp.
CC18IO CAPCOM2: CC18 Capture Inp./Compare Outp.
CC19IO CAPCOM2: CC19 Capture Inp./Compare Outp.
CC20IO CAPCOM2: CC20 Capture Inp./Compare Outp.
CC21IO CAPCOM2: CC21 Capture Inp./Compare Outp.
CC22IO CAPCOM2: CC22 Capture Inp./Compare Outp.
CC23IO CAPCOM2: CC23 Capture Inp./Compare Outp.

Port 6 is an 8-bit bidirectional I/O port. It is bit-wise
programmable for input or output via direction bits. For a pin
configured as input, the output driver is put into high­impedance state. Port 6 outputs can be configured as
push/pull or open drain drivers. The input threshold of Port 6
is selectable (TTL or special).
The Port 6 pins also serve for alternate functions:
CS0
CS1
CS2
CS3
CS4
HOLD
HLDA

Chip Select 0 Output
Chip Select 1 Output
Chip Select 2 Output
Chip Select 3 Output
Chip Select 4 Output
External Master Hold Request Input
Hold Acknowledge Output (master mode) or
Input (slave mode)

BREQ

Bus Request Output

NMI

C14 I Non-Maskable Interrupt Input. A high to low transition at this

pin causes the CPU to vector to the NMI trap routine. When
the PWRDN (power down) instruction is executed, the NMI
pin must be low in order to force the C167CR to go into power
down mode. If NMI

is high, when PWRDN is executed, the
part will continue to run in normal mode.
If not used, pin NMI

Data Sheet 19 V3.3, 2005-02

should be pulled high externally.

General Device Information

Table 3 Pin Definitions and Functions P-BGA-176-2 (cont’d)

C167CR

C167SR

Symbol Pin

Num.

XTAL2
XTAL1

RST

D13
C13

D12 O Internal Reset Indication Output. This pin is set to a low level

OUT

RSTIN

E11 I/O Reset Input with Schmitt-Trigger characteristics. A low level

Input
Outp.

O
I

Function

XTAL2: Output of the oscillator amplifier circuit.
XTAL1: Input to the oscillator amplifier and input to the

internal clock generator.
To clock the device from an external source, drive XTAL1,
while leaving XTAL2 unconnected. Minimum and maximum
high/low and rise/fall times specified in the AC
Characteristics must be observed.

when the part is executing either a hardware-, a software- or
a watchdog timer reset. RSTOUT

remains low until the EINIT

(end of initialization) instruction is executed.

at this pin while the oscillator is running resets the C167CR.
An internal pull-up resistor permits power-on reset using only
a capacitor connected to

V

SS

.
A spike filter suppresses input pulses < 10 ns. Input pulses
> 100 ns safely pass the filter. The minimum duration for a
safe recognition should be 100 ns + 2 CPU clock cycles.
In bidirectional reset mode (enabled by setting bit BDRSTEN
in register SYSCON) the RSTIN

line is internally pulled low
for the duration of the internal reset sequence upon any reset
(HW, SW, WDT). See note below this table.

Note: To let the reset configuration of PORT0 settle and to let

the PLL lock a reset duration of ca. 1 ms is
recommended.

Data Sheet 20 V3.3, 2005-02

General Device Information

Table 3 Pin Definitions and Functions P-BGA-176-2 (cont’d)

C167CR

C167SR

Symbol Pin

Num.

PORT1

P1L.0-7

K13,
K14,
J13,
J14,
H11,
H12,
H13,
G11

P1H.0-3

G13,
F11,
F12,

G14
P1H.4
P1H.5
P1H.6
P1H.7

F13

F14

E14

E13

Input
Outp.

IO

I
I
I
I

Function

PORT1 consists of the two 8-bit bidirectional I/O ports P1L
and P1H. It is bit-wise programmable for input or output via
direction bits. For a pin configured as input, the output driver
is put into high-impedance state. PORT1 is used as the 16-bit
address bus (A) in demultiplexed bus modes and also after
switching from a demultiplexed bus mode to a multiplexed
bus mode.

The following PORT1 pins also serve for alternate functions:
CC24IO CAPCOM2: CC24 Capture Input
CC25IO CAPCOM2: CC25 Capture Input
CC26IO CAPCOM2: CC26 Capture Input
CC27IO CAPCOM2: CC27 Capture Input

PORT0

P0L.0-7

P0H.0-7

RD

IO PORT0 consists of the two 8-bit bidirectional I/O ports P0L
N10,
L9,
P11,
M10,
N11,
M11,
P12,
N12
L10,
K11,
L12,
L14,
L13,

and P0H. It is bit-wise programmable for input or output via
direction bits. For a pin configured as input, the output driver
is put into high-impedance state.
In case of an external bus configuration, PORT0 serves as
the address (A) and address/data (AD) bus in multiplexed
bus modes and as the data (D) bus in demultiplexed bus
modes.

Demultiplexed bus modes:

8-bit data bus: P0H = I/O, P0L = D7 - D0
16-bit data bus: P0H = D15 - D8, P0L = D7 - D0

Multiplexed bus modes:

8-bit data bus: P0H = A15 - A8, P0L = AD7 - AD0

16-bit data bus: P0H = AD15 - AD8, P0L = AD7 - AD0
K12,
J11,
J12

L8 O External Memory Read Strobe. RD is activated for every

external instruction or data read access.

Data Sheet 21 V3.3, 2005-02

General Device Information

Table 3 Pin Definitions and Functions P-BGA-176-2 (cont’d)

C167CR

C167SR

Symbol Pin

Num.

Input
Outp.

Function

EA M9 I External Access Enable pin. A low level at this pin during and

after Reset forces the C167CR to begin instruction execution

out of external memory. A high level forces execution out of

the internal program memory.

“ROMless” versions must have this pin tied to ‘0’.

WR

/

WRL

N9 O External Memory Write Strobe. In WR-mode this pin is

activated for every external data write access. In WRL

-mode
this pin is activated for low byte data write accesses on a
16-bit bus, and for every data write access on an 8-bit bus.
See WRCFG in register SYSCON for mode selection.

READY

P9 I Ready Input. When the Ready function is enabled, a high

level at this pin during an external memory access will force
the insertion of memory cycle time waitstates until the pin
returns to a low level.
An internal pull-up device will hold this pin high when nothing
is driving it.

ALE P10 O Address Latch Enable Output. Can be used for latching the

address into external memory or an address latch in the
multiplexed bus modes.

P4

IO

Port 4 is an 8-bit bidirectional I/O port. It is bit-wise
programmable for input or output via direction bits. For a pin
configured as input, the output driver is put into high­impedance state.
Port 4 can be used to output the segment address lines and
for serial bus interfaces:

P4.0
P4.1
P4.2
P4.3
P4.4
P4.5

P4.6

P4.7

P6
M6
L6
N7
P7
M7

L7

N8

O
O
O
O
O
O
I
O
O
O

A16 Least Significant Segment Address Line
A17 Segment Address Line
A18 Segment Address Line
A19 Segment Address Line
A20 Segment Address Line
A21 Segment Address Line,
CAN1_RxD CAN 1 Receive Data Input
A22 Segment Address Line,
CAN1_TxD CAN 1 Transmit Data Output
A23 Most Significant Segment Address Line

Data Sheet 22 V3.3, 2005-02

General Device Information

Table 3 Pin Definitions and Functions P-BGA-176-2 (cont’d)

C167CR

C167SR

Symbol Pin

Num.

OWE
(

V

PP

)

N6 I Oscillator Watchdog Enable. This input enables the oscillator

P3

P3.0
P3.1
P3.2
P3.3
P3.4
P3.5
P3.6
P3.7
P3.8
P3.9
P3.10
P3.11
P3.12

P3.13
P3.15

M1
K3
L2
M2
N1
P2
M3
N2
N3
P3
N4
M4
L4

P4
N5

Input
Outp.

IO

I
O
I
O
I
I
I
I
I/O
I/O
O
I/O
O
O
I/O
O

Function

watchdog when high or disables it when low e.g. for testing
purposes. An internal pull-up device holds this input high if
nothing is driving it.
For normal operation pin OWE should be high or not
connected.
In order to drive pin OWE low draw a current of at least
200 µA.

Port 3 is a 15-bit bidirectional I/O port. It is bit-wise
programmable for input or output via direction bits. For a pin
configured as input, the output driver is put into high­impedance state. Port 3 outputs can be configured as
push/pull or open drain drivers. The input threshold of Port 3
is selectable (TTL or special).
The following Port 3 pins also serve for alternate functions:
T0IN CAPCOM1 Timer T0 Count Input
T6OUT GPT2 Timer T6 Toggle Latch Output
CAPIN GPT2 Register CAPREL Capture Input
T3OUT GPT1 Timer T3 Toggle Latch Output
T3EUD GPT1 Timer T3 External Up/Down Control Input
T4IN GPT1 Timer T4 Count/Gate/Reload/Capture Inp.
T3IN GPT1 Timer T3 Count/Gate Input
T2IN GPT1 Timer T2 Count/Gate/Reload/Capture Inp.
MRST SSC Master-Receive/Slave-Transmit Inp./Outp.
MTSR SSC Master-Transmit/Slave-Receive Outp./Inp.
TxD0 ASC0 Clock/Data Output (Async./Sync.)
RxD0 ASC0 Data Input (Async.) or Inp./Outp. (Sync.)
BHE
WRH

External Memory High Byte Enable Signal,

External Memory High Byte Write Strobe
SCLK SSC Master Clock Output / Slave Clock Input.
CLKOUT System Clock Output (= CPU Clock)

Data Sheet 23 V3.3, 2005-02

General Device Information

Table 3 Pin Definitions and Functions P-BGA-176-2 (cont’d)

C167CR

C167SR

Symbol Pin

Num.

P2

P2.0
P2.1
P2.2
P2.3
P2.4
P2.5
P2.6
P2.7
P2.8

P2.9

P2.10

P2.11

P2.12

P2.13

P2.14

P2.15

F3
F2
F4
G4
G3
G2
G1
H1
H4

J1

J2

J4

J3

K1

K2

L1

Input
Outp.

IO

I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I
I/O
I
I/O
I
I/O
I
I/O
I
I/O
I
I/O
I
I/O
I
I

Function

Port 2 is a 16-bit bidirectional I/O port. It is bit-wise
programmable for input or output via direction bits. For a pin
configured as input, the output driver is put into high­impedance state. Port 2 outputs can be configured as
push/pull or open drain drivers. The input threshold of Port 2
is selectable (TTL or special).
The following Port 2 pins also serve for alternate functions:
CC0IO CAPCOM1: CC0 Capture Inp./Compare Output
CC1IO CAPCOM1: CC1 Capture Inp./Compare Output
CC2IO CAPCOM1: CC2 Capture Inp./Compare Output
CC3IO CAPCOM1: CC3 Capture Inp./Compare Output
CC4IO CAPCOM1: CC4 Capture Inp./Compare Output
CC5IO CAPCOM1: CC5 Capture Inp./Compare Output
CC6IO CAPCOM1: CC6 Capture Inp./Compare Output
CC7IO CAPCOM1: CC7 Capture Inp./Compare Output
CC8IO CAPCOM1: CC8 Capture Inp./Compare Output,
EX0IN Fast External Interrupt 0 Input
CC9IO CAPCOM1: CC9 Capture Inp./Compare Output,
EX1IN Fast External Interrupt 1 Input
CC10IO CAPCOM1: CC10 Capture Inp./Compare Outp.,
EX2IN Fast External Interrupt 2 Input
CC11IO CAPCOM1: CC11 Capture Inp./Compare Outp.,
EX3IN Fast External Interrupt 3 Input
CC12IO CAPCOM1: CC12 Capture Inp./Compare Outp.,
EX4IN Fast External Interrupt 4 Input
CC13IO CAPCOM1: CC13 Capture Inp./Compare Outp.,
EX5IN Fast External Interrupt 5 Input
CC14IO CAPCOM1: CC14 Capture Inp./Compare Outp.,
EX6IN Fast External Interrupt 6 Input
CC15IO CAPCOM1: CC15 Capture Inp./Compare Outp.,
EX7IN Fast External Interrupt 7 Input,
T7IN CAPCOM2: Timer T7 Count Input

V

AREF

V

AGND

Data Sheet 24 V3.3, 2005-02

B2 – Reference voltage for the A/D converter.

C2 – Reference ground for the A/D converter.

General Device Information

Table 3 Pin Definitions and Functions P-BGA-176-2 (cont’d)

C167CR

C167SR

Symbol Pin

Num.

V

DD

B8,
C12,
D14,
F1,
H3,
H14,
K4,
M5,
M12,
P8

V

SS

A8,
D11,
E1,
E12,
G12,
H2,
L3,
L5,
L11,
M8

Input

Function

Outp.

– Digital Supply Voltage:

+ 5 V during normal operation and idle mode.
≥ 2.5 V during power down mode.

– Digital Ground.

Note: The following behavioural differences must be observed when the bidirectional

reset is active:

• Bit BDRSTEN in register SYSCON cannot be changed after EINIT and is cleared
automatically after a reset.

• The reset indication flags always indicate a long hardware reset.

• The PORT0 configuration is treated as if it were a hardware reset. In particular, the
bootstrap loader may be activated when P0L.4 is low.

•Pin RSTIN

may only be connected to external reset devices with an open drain output

driver.

• A short hardware reset is extended to the duration of the internal reset sequence.

Data Sheet 25 V3.3, 2005-02

C167CR

C167SR

Functional Description

3 Functional Description

The architecture of the C167CR combines advantages of both RISC and CISC
processors and of advanced peripheral subsystems in a very well-balanced way. In
addition the on-chip memory blocks allow the design of compact systems with maximum
performance.
The following block diagram gives an overview of the different on-chip components and
of the advanced, high bandwidth internal bus structure of the C167CR.

Note: All time specifications refer to a CPU clock of 33 MHz

(see definition in the AC Characteristics section).

8

8

ProgMem

ROM

128/32

KByte

XRAM

2 KByte

CAN

Rev 2.0B active

EBC

XBUS Control

Port 4

External Bus

Control

Port 6

Port 0

16

32

Instr. / Data

16

16

On-Chip XBUS (16-Bit Demux)

Port 1

16

External Instr. / Data

Interrupt Controller

ADC

10-Bit

Channels

ASC0

(USART)

16

BRGen

Port 5 Port 3

16

C166-Core

CPU

SSC

(SPI)

BRGen

PEC

16-Level

Priority

GPT

15

Data

Data

16

Interrupt Bus

Peripheral Data Bus

PWM CCOM1

T2
T3
T4

T5
T6

CCOM2

Port 7

8

16

16

T7
T8

IRAM

Internal

RAM

Dual Port

2 KByte

Osc / PLL

WDT

T0
T1

Port 8

8

XTAL

16

Port 2

Figure 4 Block Diagram

The program memory, the internal RAM (IRAM) and the set of generic peripherals are
connected to the CPU via separate buses. A fourth bus, the XBUS, connects external
resources as well as additional on-chip resources, the X-Peripherals (see Figure 4).

Data Sheet 26 V3.3, 2005-02

C167CR

C167SR

Functional Description

3.1 Memory Organization

The memory space of the C167CR is configured in a Von Neumann architecture which
means that code memory, data memory, registers and I/O ports are organized within the
same linear address space which includes 16 Mbytes. The entire memory space can be
accessed bytewise or wordwise. Particular portions of the on-chip memory have
additionally been made directly bitaddressable.

The C167CR incorporates 128/32 Kbytes (depending on the derivative) of on-chip mask­programmable ROM for code or constant data. The lower 32 Kbytes of the on-chip ROM
can be mapped either to segment 0 or segment 1.

2 Kbytes of on-chip Internal RAM (IRAM) are provided as a storage for user defined
variables, for the system stack, general purpose register banks and even for code. A
register bank can consist of up to 16 wordwide (R0 to R15) and/or bytewide (RL0, RH0,
…, RL7, RH7) so-called General Purpose Registers (GPRs).

1024 bytes (2 × 512 bytes) of the address space are reserved for the Special Function
Register areas (SFR space and ESFR space). SFRs are wordwide registers which are
used for controlling and monitoring functions of the different on-chip units. Unused SFR
addresses are reserved for future members of the C166 Family.

2 Kbytes of on-chip Extension RAM (XRAM) are provided to store user data, user stacks,
or code. The XRAM is accessed like external memory and therefore cannot be used for
the system stack or for register banks and is not bitaddressable. The XRAM permits
16-bit accesses with maximum speed.

In order to meet the needs of designs where more memory is required than is provided
on chip, up to 16 Mbytes of external RAM and/or ROM can be connected to the
microcontroller.

Data Sheet 27 V3.3, 2005-02

C167CR

C167SR

Functional Description

3.2 External Bus Controller

All of the external memory accesses are performed by a particular on-chip External Bus
Controller (EBC). It can be programmed either to Single Chip Mode when no external
memory is required, or to one of four different external memory access modes, which are
as follows:

• 16-/18-/20-/24-bit Addresses, 16-bit Data, Demultiplexed

• 16-/18-/20-/24-bit Addresses, 16-bit Data, Multiplexed

• 16-/18-/20-/24-bit Addresses, 8-bit Data, Multiplexed

• 16-/18-/20-/24-bit Addresses, 8-bit Data, Demultiplexed

In the demultiplexed bus modes, addresses are output on PORT1 and data is
input/output on PORT0 or P0L, respectively. In the multiplexed bus modes both
addresses and data use PORT0 for input/output.

Important timing characteristics of the external bus interface (Memory Cycle Time,
Memory Tri-State Time, Length of ALE and Read Write Delay) have been made
programmable to allow the user the adaption of a wide range of different types of
memories and external peripherals.
In addition, up to 4 independent address windows may be defined (via register pairs
ADDRSELx / BUSCONx) which control the access to different resources with different
bus characteristics. These address windows are arranged hierarchically where
BUSCON4 overrides BUSCON3 and BUSCON2 overrides BUSCON1. All accesses to
locations not covered by these 4 address windows are controlled by BUSCON0.

Up to 5 external CS
external glue logic. The C167CR offers the possibility to switch the CS
unlatched mode. In this mode the internal filter logic is switched off and the CS
are directly generated from the address. The unlatched CS
CSCFG (SYSCON.6).

Access to very slow memories or memories with varying access times is supported via
a particular ‘Ready’ function.

A HOLD
resources with other bus masters. The bus arbitration is enabled by setting bit HLDEN
in register PSW. After setting HLDEN once, pins P6.7 … P6.5 (BREQ
are automatically controlled by the EBC. In Master Mode (default after reset) the HLDA
pin is an output. By setting bit DP6.7 to ‘1’ the Slave Mode is selected where pin HLDA
is switched to input. This allows to directly connect the slave controller to another master
controller without glue logic.

For applications which require less than 16 Mbytes of external memory space, this
address space can be restricted to 1 Mbyte, 256 Kbyte, or to 64 Kbyte. In this case Port 4
outputs four, two, or no address lines at all. It outputs all 8 address lines, if an address
space of 16 Mbytes is used.

/HLDA protocol is available for bus arbitration and allows to share external

signals (4 windows plus default) can be generated in order to save

outputs to an

signals

mode is enabled by setting

, HLDA, HOLD)

Data Sheet 28 V3.3, 2005-02

C167CR

C167SR

Functional Description

Note: When the on-chip CAN Module is to be used the segment address output on

Port 4 must be limited to 4 bits (i.e. A19 … A16) in order to enable the alternate
function of the CAN interface pins. CS
amount of addressable external memory.

lines can be used to increase the total

Data Sheet 29 V3.3, 2005-02

C167CR

C167SR

Functional Description

3.3 Central Processing Unit (CPU)

The main core of the CPU consists of a 4-stage instruction pipeline, a 16-bit arithmetic
and logic unit (ALU) and dedicated SFRs. Additional hardware has been spent for a
separate multiply and divide unit, a bit-mask generator and a barrel shifter.

Based on these hardware provisions, most of the C167CR’s instructions can be
executed in just one machine cycle which requires 60 ns at 33 MHz CPU clock. For
example, shift and rotate instructions are always processed during one machine cycle
independent of the number of bits to be shifted. All multiple-cycle instructions have been
optimized so that they can be executed very fast as well: branches in 2 cycles, a
16 × 16 bit multiplication in 5 cycles and a 32-/16-bit division in 10 cycles. Another
pipeline optimization, the so-called ‘Jump Cache’, allows reducing the execution time of
repeatedly performed jumps in a loop from 2 cycles to 1 cycle.

Figure 5 CPU Block Diagram

Data Sheet 30 V3.3, 2005-02

C167CR

C167SR

Functional Description

The CPU has a register context consisting of up to 16 wordwide GPRs at its disposal.
These 16 GPRs are physically allocated within the on-chip RAM area. A Context Pointer
(CP) register determines the base address of the active register bank to be accessed by
the CPU at any time. The number of register banks is only restricted by the available
internal RAM space. For easy parameter passing, a register bank may overlap others.

A system stack of up to 1024 words is provided as a storage for temporary data. The
system stack is allocated in the on-chip RAM area, and it is accessed by the CPU via the
stack pointer (SP) register. Two separate SFRs, STKOV and STKUN, are implicitly
compared against the stack pointer value upon each stack access for the detection of a
stack overflow or underflow.

The high performance offered by the hardware implementation of the CPU can efficiently
be utilized by a programmer via the highly efficient C167CR instruction set which
includes the following instruction classes:

• Arithmetic Instructions

• Logical Instructions

• Boolean Bit Manipulation Instructions

• Compare and Loop Control Instructions

• Shift and Rotate Instructions

• Prioritize Instruction

• Data Movement Instructions

• System Stack Instructions

• Jump and Call Instructions

• Return Instructions

• System Control Instructions

• Miscellaneous Instructions

The basic instruction length is either 2 or 4 bytes. Possible operand types are bits, bytes
and words. A variety of direct, indirect or immediate addressing modes are provided to
specify the required operands.

Data Sheet 31 V3.3, 2005-02

C167CR

C167SR

Functional Description

3.4 Interrupt System

With an interrupt response time within a range from just 5 to 12 CPU clocks (in case of
internal program execution), the C167CR is capable of reacting very fast to the
occurrence of non-deterministic events.

The architecture of the C167CR supports several mechanisms for fast and flexible
response to service requests that can be generated from various sources internal or
external to the microcontroller. Any of these interrupt requests can be programmed to
being serviced by the Interrupt Controller or by the Peripheral Event Controller (PEC).

In contrast to a standard interrupt service where the current program execution is
suspended and a branch to the interrupt vector table is performed, just one cycle is
‘stolen’ from the current CPU activity to perform a PEC service. A PEC service implies a
single byte or word data transfer between any two memory locations with an additional
increment of either the PEC source or the destination pointer. An individual PEC transfer
counter is implicity decremented for each PEC service except when performing in the
continuous transfer mode. When this counter reaches zero, a standard interrupt is
performed to the corresponding source related vector location. PEC services are very
well suited, for example, for supporting the transmission or reception of blocks of data.
The C167CR has 8 PEC channels each of which offers such fast interrupt-driven data
transfer capabilities.

A separate control register which contains an interrupt request flag, an interrupt enable
flag and an interrupt priority bitfield exists for each of the possible interrupt sources. Via
its related register, each source can be programmed to one of sixteen interrupt priority
levels. Once having been accepted by the CPU, an interrupt service can only be
interrupted by a higher prioritized service request. For the standard interrupt processing,
each of the possible interrupt sources has a dedicated vector location.

Fast external interrupt inputs are provided to service external interrupts with high
precision requirements. These fast interrupt inputs feature programmable edge
detection (rising edge, falling edge or both edges).

Software interrupts are supported by means of the ‘TRAP’ instruction in combination with
an individual trap (interrupt) number.

Table 4 shows all of the possible C167CR interrupt sources and the corresponding

hardware-related interrupt flags, vectors, vector locations and trap (interrupt) numbers.

Note: Interrupt nodes which are not used by associated peripherals, may be used to

generate software controlled interrupt requests by setting the respective interrupt
request bit (xIR).

Data Sheet 32 V3.3, 2005-02

Table 4 C167CR Interrupt Nodes

C167CR

C167SR

Functional Description

Source of Interrupt or
PEC Service Request

Request
Flag

Enable
Flag

Interrupt
Vector

Vector
Location

CAPCOM Register 0 CC0IR CC0IE CC0INT 00’0040

CAPCOM Register 1 CC1IR CC1IE CC1INT 00’0044

CAPCOM Register 2 CC2IR CC2IE CC2INT 00’0048

CAPCOM Register 3 CC3IR CC3IE CC3INT 00’004C

CAPCOM Register 4 CC4IR CC4IE CC4INT 00’0050

CAPCOM Register 5 CC5IR CC5IE CC5INT 00’0054

CAPCOM Register 6 CC6IR CC6IE CC6INT 00’0058

CAPCOM Register 7 CC7IR CC7IE CC7INT 00’005C

CAPCOM Register 8 CC8IR CC8IE CC8INT 00’0060

CAPCOM Register 9 CC9IR CC9IE CC9INT 00’0064

CAPCOM Register 10 CC10IR CC10IE CC10INT 00’0068

CAPCOM Register 11 CC11IR CC11IE CC11INT 00’006C

CAPCOM Register 12 CC12IR CC12IE CC12INT 00’0070

H

H

H

H

H

H

H

H

H

H

H

H

H

Trap
Number

10

H

11

H

12

H

13

H

14

H

15

H

16

H

17

H

18

H

19

H

1A

H

1B

H

1C

H

CAPCOM Register 13 CC13IR CC13IE CC13INT 00’0074

CAPCOM Register 14 CC14IR CC14IE CC14INT 00’0078

CAPCOM Register 15 CC15IR CC15IE CC15INT 00’007C

CAPCOM Register 16 CC16IR CC16IE CC16INT 00’00C0

CAPCOM Register 17 CC17IR CC17IE CC17INT 00’00C4

CAPCOM Register 18 CC18IR CC18IE CC18INT 00’00C8

CAPCOM Register 19 CC19IR CC19IE CC19INT 00’00CC

CAPCOM Register 20 CC20IR CC20IE CC20INT 00’00D0

CAPCOM Register 21 CC21IR CC21IE CC21INT 00’00D4

CAPCOM Register 22 CC22IR CC22IE CC22INT 00’00D8

CAPCOM Register 23 CC23IR CC23IE CC23INT 00’00DC

CAPCOM Register 24 CC24IR CC24IE CC24INT 00’00E0

CAPCOM Register 25 CC25IR CC25IE CC25INT 00’00E4

CAPCOM Register 26 CC26IR CC26IE CC26INT 00’00E8

CAPCOM Register 27 CC27IR CC27IE CC27INT 00’00EC

1D

H

H

H

H

H

H

H

H

H

H

H

H

H

H

H

1E

1F

30

31

32

33

34

35

36

37

38

39

3A

3B

H

H

H

H

H

H

H

H

H

H

H

H

H

H

H

CAPCOM Register 28 CC28IR CC28IE CC28INT 00’00E0

CAPCOM Register 29 CC29IR CC29IE CC29INT 00’0110

3C

H

H

44

H

H

Data Sheet 33 V3.3, 2005-02

Table 4 C167CR Interrupt Nodes (cont’d)

C167CR

C167SR

Functional Description

Source of Interrupt or
PEC Service Request

Request
Flag

Enable
Flag

Interrupt
Vector

Vector
Location

CAPCOM Register 30 CC30IR CC30IE CC30INT 00’0114

CAPCOM Register 31 CC31IR CC31IE CC31INT 00’0118

CAPCOM Timer 0 T0IR T0IE T0INT 00’0080

CAPCOM Timer 1 T1IR T1IE T1INT 00’0084

CAPCOM Timer 7 T7IR T7IE T7INT 00’00F4

CAPCOM Timer 8 T8IR T8IE T8INT 00’00F8

GPT1 Timer 2 T2IR T2IE T2INT 00’0088

GPT1 Timer 3 T3IR T3IE T3INT 00’008C

GPT1 Timer 4 T4IR T4IE T4INT 00’0090

GPT2 Timer 5 T5IR T5IE T5INT 00’0094

GPT2 Timer 6 T6IR T6IE T6INT 00’0098

GPT2 CAPREL Reg. CRIR CRIE CRINT 00’009C

A/D Conversion

ADCIR ADCIE ADCINT 00’00A0

Complete

H

H

H

H

H

H

H

H

H

H

H

H

H

Trap
Number

45

H

46

H

20

H

21

H

3D

H

3E

H

22

H

23

H

24

H

25

H

26

H

27

H

28

H

A/D Overrun Error ADEIR ADEIE ADEINT 00’00A4

ASC0 Transmit S0TIR S0TIE S0TINT 00’00A8

ASC0 Transmit Buffer S0TBIR S0TBIE S0TBINT 00’011C

ASC0 Receive S0RIR S0RIE S0RINT 00’00AC

ASC0 Error S0EIR S0EIE S0EINT 00’00B0

SSC Transmit SCTIR SCTIE SCTINT 00’00B4

SSC Receive SCRIR SCRIE SCRINT 00’00B8

SSC Error SCEIR SCEIE SCEINT 00’00BC

PWM Channel 0 … 3 PWMIR PWMIE PWMINT 00’00FC

CAN Interface 1 XP0IR XP0IE XP0INT 00’0100

Unassigned node XP1IR XP1IE XP1INT 00’0104

Unassigned node XP2IR XP2IE XP2INT 00’0108

PLL/OWD XP3IR XP3IE XP3INT 00’010C

29

H

H

H

H

H

H

H

H

H

H

H

H

H

2A

47

2B

2C

2D

2E

2F

3F

40

41

42

43

H

H

H

H

H

H

H

H

H

H

H

H

H

Data Sheet 34 V3.3, 2005-02

C167CR

C167SR

Functional Description

The C167CR also provides an excellent mechanism to identify and to process
exceptions or error conditions that arise during run-time, so-called ‘Hardware Traps’.
Hardware traps cause immediate non-maskable system reaction which is similar to a
standard interrupt service (branching to a dedicated vector table location). The
occurrence of a hardware trap is additionally signified by an individual bit in the trap flag
register (TFR). Except when another higher prioritized trap service is in progress, a
hardware trap will interrupt any actual program execution. In turn, hardware trap services
can normally not be interrupted by standard or PEC interrupts.

Table 5 shows all of the possible exceptions or error conditions that can arise during run-

time:

Table 5 Hardware Trap Summary

Exception Condition Trap

Flag

Reset Functions:

–

• Hardware Reset

• Software Reset

• W-dog Timer Overflow

Class A Hardware Traps:

• Non-Maskable Interrupt

• Stack Overflow

• Stack Underflow

NMI
STKOF
STKUF

Class B Hardware Traps:

• Undefined Opcode

• Protected Instruction

UNDOPC
PRTFLT

Fault

• Illegal Word Operand

ILLOPA

Access

• Illegal Instruction

ILLINA

Access

• Illegal External Bus

ILLBUS

Access

Trap
Vector

RESET
RESET
RESET

NMITRAP
STOTRAP
STUTRAP

BTRAP
BTRAP

BTRAP

BTRAP

BTRAP

Vector
Location

00’0000
00’0000
00’0000

00’0008
00’0010
00’0018

00’0028
00’0028

00’0028

00’0028

00’0028

H

H

H

H

H

H

H

H

H

H

H

Trap
Number

00

H

00

H

00

H

02

H

04

H

06

H

0A

H

0A

H

0A

H

0A

H

0A

H

Trap
Priority

III
III
III

II
II
II

I
I

I

I

I

Reserved – – [2C

Software Traps

–– Any

• TRAP Instruction

- 3CH][0BH - 0FH]–

H

Any
[00’0000
00’01FC

[00

-

H

]

H

- 7FH]

H

Current
CPU

Priority
in steps of
4

H

Data Sheet 35 V3.3, 2005-02

C167CR

C167SR

Functional Description

3.5 Capture/Compare (CAPCOM) Units

The CAPCOM units support generation and control of timing sequences on up to
32 channels with a maximum resolution of 16 TCL. The CAPCOM units are typically
used to handle high speed I/O tasks such as pulse and waveform generation, pulse
width modulation (PMW), Digital to Analog (D/A) conversion, software timing, or time
recording relative to external events.

Four 16-bit timers (T0/T1, T7/T8) with reload registers provide two independent time
bases for the capture/compare register array.

The input clock for the timers is programmable to several prescaled values of the internal
system clock, or may be derived from an overflow/underflow of timer T6 in module GPT2.
This provides a wide range of variation for the timer period and resolution and allows
precise adjustments to the application specific requirements. In addition, external count
inputs for CAPCOM timers T0 and T7 allow event scheduling for the capture/compare
registers relative to external events.

Both of the two capture/compare register arrays contain 16 dual purpose
capture/compare registers, each of which may be individually allocated to either
CAPCOM timer T0 or T1 (T7 or T8, respectively), and programmed for capture or
compare function. Each register has one port pin associated with it which serves as an
input pin for triggering the capture function, or as an output pin (except for
CC24 … CC27) to indicate the occurrence of a compare event.

When a capture/compare register has been selected for capture mode, the current
contents of the allocated timer will be latched (‘captured’) into the capture/compare
register in response to an external event at the port pin which is associated with this
register. In addition, a specific interrupt request for this capture/compare register is
generated. Either a positive, a negative, or both a positive and a negative external signal
transition at the pin can be selected as the triggering event. The contents of all registers
which have been selected for one of the five compare modes are continuously compared
with the contents of the allocated timers. When a match occurs between the timer value
and the value in a capture/compare register, specific actions will be taken based on the
selected compare mode.

Data Sheet 36 V3.3, 2005-02

C167CR

C167SR

Functional Description

Table 6 Compare Modes (CAPCOM)

Compare Modes Function

Mode 0 Interrupt-only compare mode;

several compare interrupts per timer period are possible

Mode 1 Pin toggles on each compare match;

several compare events per timer period are possible

Mode 2 Interrupt-only compare mode;

only one compare interrupt per timer period is generated

Mode 3 Pin set ‘1’ on match; pin reset ‘0’ on compare time overflow;

only one compare event per timer period is generated

Double
Register Mode

Two registers operate on one pin;
pin toggles on each compare match;
several compare events per timer period are possible.

Data Sheet 37 V3.3, 2005-02

Reload Reg. TxREL

C167CR

C167SR

Functional Description

CPU

TxIN

GPT2 Timer T6

Over/Underflow

CCxIO

16 Capture Inputs

16 Compare Outputs

CCxIO

CPU

GPT2 Timer T6

Over/Underflow

2n : 1f

2n : 1f

Tx

Input

Control

Mode

Control

(Capture

or

Compare)

Ty

Input

Control

CAPCOM Timer Tx

16-Bit

Capture/
Compare
Registers

CAPCOM Timer Ty

Interrupt
Request
(TxIR)

16 Capture/Compare

Interrupt Request

Interrupt
Request
(TyIR)

Reload Reg. TyREL

MCB02143B

x = 0, 7
y = 1, 8
n = 3 … 10

Figure 6 CAPCOM Unit Block Diagram

3.6 PWM Module

The Pulse Width Modulation Module can generate up to four PWM output signals using
edge-aligned or center-aligned PWM. In addition the PWM module can generate PWM
burst signals and single shot outputs. The frequency range of the PWM signals covers
4 Hz to 16.5 MHz (referred to a CPU clock of 33 MHz), depending on the resolution of
the PWM output signal. The level of the output signals is selectable and the PWM
module can generate interrupt requests.

Data Sheet 38 V3.3, 2005-02

C167CR

C167SR

Functional Description

3.7 General Purpose Timer (GPT) Unit

The GPT unit represents a very flexible multifunctional timer/counter structure which
may be used for many different time related tasks such as event timing and counting,
pulse width and duty cycle measurements, pulse generation, or pulse multiplication.

The GPT unit incorporates five 16-bit timers which are organized in two separate
modules, GPT1 and GPT2. Each timer in each module may operate independently in a
number of different modes, or may be concatenated with another timer of the same
module.

Each of the three timers T2, T3, T4 of module GPT1 can be configured individually for
one of four basic modes of operation, which are Timer, Gated Timer, Counter, and
Incremental Interface Mode. In Timer Mode, the input clock for a timer is derived from
the CPU clock, divided by a programmable prescaler, while Counter Mode allows a timer
to be clocked in reference to external events.
Pulse width or duty cycle measurement is supported in Gated Timer Mode, where the
operation of a timer is controlled by the ‘gate’ level on an external input pin. For these
purposes, each timer has one associated port pin (TxIN) which serves as gate or clock
input. The maximum resolution of the timers in module GPT1 is 16 TCL.

The count direction (up/down) for each timer is programmable by software or may
additionally be altered dynamically by an external signal on a port pin (TxEUD) to
facilitate e.g. position tracking.

In Incremental Interface Mode the GPT1 timers (T2, T3, T4) can be directly connected
to the incremental position sensor signals A and B via their respective inputs TxIN and
TxEUD. Direction and count signals are internally derived from these two input signals,
so the contents of the respective timer Tx corresponds to the sensor position. The third
position sensor signal TOP0 can be connected to an interrupt input.

Timer T3 has an output toggle latch (T3OTL) which changes its state on each timer over­flow/underflow. The state of this latch may be output on pin T3OUT e.g. for time out
monitoring of external hardware components, or may be used internally to clock timers
T2 and T4 for measuring long time periods with high resolution.

In addition to their basic operating modes, timers T2 and T4 may be configured as reload
or capture registers for timer T3. When used as capture or reload registers, timers T2
and T4 are stopped. The contents of timer T3 is captured into T2 or T4 in response to a
signal at their associated input pins (TxIN). Timer T3 is reloaded with the contents of T2
or T4 triggered either by an external signal or by a selectable state transition of its toggle
latch T3OTL. When both T2 and T4 are configured to alternately reload T3 on opposite
state transitions of T3OTL with the low and high times of a PWM signal, this signal can
be constantly generated without software intervention.

Data Sheet 39 V3.3, 2005-02

C167CR

C167SR

Functional Description

T2EUD

T2IN

T3IN

T3EUD

T4IN

CPU

CPU

CPU

U/D

2n : 1f

2n : 1f

2n : 1f

T2

Mode

Control

T3

Mode

Control

T4

Mode

Control

GPT1 Timer T2

Reload

Capture

Toggle FF

GPT1 Timer T3 T3OTL

U/D

Capture

Reload

GPT1 Timer T4

Interrupt
Request

Interrupt
Request

T3OUT

Other
Timers

Interrupt
Request

T4EUD

U/D

MCT02141

n = 3 … 10

Figure 7 Block Diagram of GPT1

With its maximum resolution of 8 TCL, the GPT2 module provides precise event control
and time measurement. It includes two timers (T5, T6) and a capture/reload register
(CAPREL). Both timers can be clocked with an input clock which is derived from the CPU
clock via a programmable prescaler or with external signals. The count direction
(up/down) for each timer is programmable by software or may additionally be altered
dynamically by an external signal on a port pin (TxEUD). Concatenation of the timers is
supported via the output toggle latch (T6OTL) of timer T6, which changes its state on
each timer overflow/underflow.

The state of this latch may be used to clock timer T5, and/or it may be output on pin
T6OUT. The overflows/underflows of timer T6 can additionally be used to clock the
CAPCOM timers T0 or T1, and to cause a reload from the CAPREL register. The
CAPREL register may capture the contents of timer T5 based on an external signal
transition on the corresponding port pin (CAPIN), and timer T5 may optionally be cleared
after the capture procedure. This allows the C167CR to measure absolute time
differences or to perform pulse multiplication without software overhead.

Data Sheet 40 V3.3, 2005-02

C167CR

C167SR

Functional Description

The capture trigger (timer T5 to CAPREL) may also be generated upon transitions of
GPT1 timer T3’s inputs T3IN and/or T3EUD. This is especially advantageous when T3
operates in Incremental Interface Mode.

T5EUD

T5IN

CAPIN

T6IN

CPU

T3

CPU

2n : 1f

2n : 1f

T5

Mode

Control

MUX

CT3

T6

Mode

Control

Clear

Capture

U/D

GPT2 Timer T5

GPT2 CAPREL

GPT2 Timer T6

U/D

T6OTL

Interrupt
Request

Interrupt
Request

Interrupt
Request

T6OUT

Other
Timers

T6EUD

MCB03999

n = 2 … 9

Figure 8 Block Diagram of GPT2

Data Sheet 41 V3.3, 2005-02

C167CR

C167SR

Functional Description

3.8 A/D Converter

For analog signal measurement, a 10-bit A/D converter with 16 multiplexed input
channels and a sample and hold circuit has been integrated on-chip. It uses the method
of successive approximation. The sample time (for loading the capacitors) and the
conversion time is programmable and can so be adjusted to the external circuitry.

Overrun error detection/protection is provided for the conversion result register
(ADDAT): either an interrupt request will be generated when the result of a previous
conversion has not been read from the result register at the time the next conversion is
complete, or the next conversion is suspended in such a case until the previous result
has been read.

For applications which require less than 16 analog input channels, the remaining
channel inputs can be used as digital input port pins.

The A/D converter of the C167CR supports four different conversion modes. In the
standard Single Channel conversion mode, the analog level on a specified channel is
sampled once and converted to a digital result. In the Single Channel Continuous mode,
the analog level on a specified channel is repeatedly sampled and converted without
software intervention. In the Auto Scan mode, the analog levels on a prespecified
number of channels are sequentially sampled and converted. In the Auto Scan
Continuous mode, the number of prespecified channels is repeatedly sampled and
converted. In addition, the conversion of a specific channel can be inserted (injected) into
a running sequence without disturbing this sequence. This is called Channel Injection
Mode.

The Peripheral Event Controller (PEC) may be used to automatically store the
conversion results into a table in memory for later evaluation, without requiring the
overhead of entering and exiting interrupt routines for each data transfer.

After each reset and also during normal operation the ADC automatically performs
calibration cycles. This automatic self-calibration constantly adjusts the converter to
changing operating conditions (e.g. temperature) and compensates process variations.

These calibration cycles are part of the conversion cycle, so they do not affect the normal
operation of the A/D converter.

In order to decouple analog inputs from digital noise and to avoid input trigger noise
those pins used for analog input can be disconnected from the digital IO or input stages
under software control. This can be selected for each pin separately via register P5DIDIS
(Port 5 Digital Input Disable).

Data Sheet 42 V3.3, 2005-02

C167CR

C167SR

Functional Description

3.9 Serial Channels

Serial communication with other microcontrollers, processors, terminals or external
peripheral components is provided by two serial interfaces with different functionality, an
Asynchronous/Synchronous Serial Channel (ASC0) and a High-Speed Synchronous
Serial Channel (SSC).

The ASC0 is upward compatible with the serial ports of the Infineon 8-bit microcontroller
families and supports full-duplex asynchronous communication at up to
781 kbit/s/1.03 Mbit/s and half-duplex synchronous communication at up to

3.1/4.1 Mbit/s (@ 25/33 MHz CPU clock).
A dedicated baud rate generator allows to set up all standard baud rates without
oscillator tuning. For transmission, reception and error handling 4 separate interrupt
vectors are provided. In asynchronous mode, 8- or 9-bit data frames are transmitted or
received, preceded by a start bit and terminated by one or two stop bits. For
multiprocessor communication, a mechanism to distinguish address from data bytes has
been included (8-bit data plus wake up bit mode).
In synchronous mode, the ASC0 transmits or receives bytes (8 bits) synchronously to a
shift clock which is generated by the ASC0. The ASC0 always shifts the LSB first. A loop
back option is available for testing purposes.
A number of optional hardware error detection capabilities has been included to increase
the reliability of data transfers. A parity bit can automatically be generated on
transmission or be checked on reception. Framing error detection allows to recognize
data frames with missing stop bits. An overrun error will be generated, if the last
character received has not been read out of the receive buffer register at the time the
reception of a new character is complete.

The SSC supports full-duplex synchronous communication at up to 6.25/8.25 Mbit/s
(@ 25/33 MHz CPU clock). It may be configured so it interfaces with serially linked
peripheral components. A dedicated baud rate generator allows to set up all standard
baud rates without oscillator tuning. For transmission, reception, and error handling three
separate interrupt vectors are provided.
The SSC transmits or receives characters of 2 … 16 bits length synchronously to a shift
clock which can be generated by the SSC (master mode) or by an external master (slave
mode). The SSC can start shifting with the LSB or with the MSB and allows the selection
of shifting and latching clock edges as well as the clock polarity.
A number of optional hardware error detection capabilities has been included to increase
the reliability of data transfers. Transmit and receive error supervise the correct handling
of the data buffer. Phase and baudrate error detect incorrect serial data.

Data Sheet 43 V3.3, 2005-02

C167CR

C167SR

Functional Description

3.10 CAN-Module

The integrated CAN-Module handles the completely autonomous transmission and
reception of CAN frames in accordance with the CAN specification V2.0 part B (active),
i.e. the on-chip CAN-Module can receive and transmit standard frames with 11-bit
identifiers as well as extended frames with 29-bit identifiers.

The module provides Full CAN functionality on up to 15 message objects. Message
object 15 may be configured for Basic CAN functionality. Both modes provide separate
masks for acceptance filtering which allows to accept a number of identifiers in Full CAN
mode and also allows to disregard a number of identifiers in Basic CAN mode. All
message objects can be updated independent from the other objects and are equipped
for the maximum message length of 8 bytes.

The bit timing is derived from the XCLK and is programmable up to a data rate of
1 Mbit/s. The CAN-Module uses two pins of Port 4 to interface to an external bus
transceiver.

Note: When the CAN interface is to be used the segment address output on Port 4 must

be limited to 4 bits, i.e. A19 … A16. This is necessary to enable the alternate
function of the CAN interface pins.

3.11 Watchdog Timer

The Watchdog Timer represents one of the fail-safe mechanisms which have been
implemented to prevent the controller from malfunctioning for longer periods of time.

The Watchdog Timer is always enabled after a reset of the chip, and can only be
disabled in the time interval until the EINIT (end of initialization) instruction has been
executed. Thus, the chip’s start-up procedure is always monitored. The software has to
be designed to service the Watchdog Timer before it overflows. If, due to hardware or
software related failures, the software fails to do so, the Watchdog Timer overflows and
generates an internal hardware reset and pulls the RSTOUT
external hardware components to be reset.

The Watchdog Timer is a 16-bit timer, clocked with the system clock divided either by 2
or by 128. The high byte of the Watchdog Timer register can be set to a prespecified
reload value (stored in WDTREL) in order to allow further variation of the monitored time
interval. Each time it is serviced by the application software, the high byte of the
Watchdog Timer is reloaded. Thus, time intervals between 15.5 µs and 254 ms can be
monitored (@ 33 MHz).
The default Watchdog Timer interval after reset is 3.97 ms (@ 33 MHz).

pin low in order to allow

Data Sheet 44 V3.3, 2005-02

C167CR

C167SR

Functional Description

3.12 Parallel Ports

The C167CR provides up to 111 I/O lines which are organized into eight input/output
ports and one input port. All port lines are bit-addressable, and all input/output lines are
individually (bit-wise) programmable as inputs or outputs via direction registers. The I/O
ports are true bidirectional ports which are switched to high impedance state when
configured as inputs. The output drivers of five I/O ports can be configured (pin by pin)
for push/pull operation or open-drain operation via control registers. During the internal
reset, all port pins are configured as inputs.

The input threshold of Port 2, Port 3, Port 6, Port 7, and Port 8 is selectable (TTL or
CMOS like), where the special CMOS like input threshold reduces noise sensitivity due
to the input hysteresis. The input threshold may be selected individually for each byte of
the respective ports.

All port lines have programmable alternate input or output functions associated with
them. All port lines that are not used for these alternate functions may be used as general
purpose IO lines.

PORT0 and PORT1 may be used as address and data lines when accessing external
memory, while Port 4 outputs the additional segment address bits A23/19/17 … A16 in
systems where segmentation is enabled to access more than 64 Kbytes of memory.
Port 2, Port 8 and Port 7 (and parts of PORT1) are associated with the capture inputs or
compare outputs of the CAPCOM units and/or with the outputs of the PWM module.
Port 6 provides optional bus arbitration signals (BREQ
signals.
Port 3 includes alternate functions of timers, serial interfaces, the optional bus control
signal BHE
Port 5 is used for the analog input channels to the A/D converter or timer control signals.

The edge characteristics (transition time) of the C167CR’s port drivers can be selected
via the Port Driver Control Register (PDCR). Two bits select fast edges (‘0’) or reduced
edges (‘1’) for bus interface pins and non-bus pins separately.
PDCR.0 = BIPEC controls PORT0, PORT1, Port 4, RD
PDCR.4 = NBPEC controls Port 3, Port 8, RSTOUT

/WRH, and the system clock output (CLKOUT).

, HLDA, HOLD) and chip select

, WR, ALE, CLKOUT, BHE/WRH.

, RSTIN (bidir. reset mode).

Data Sheet 45 V3.3, 2005-02

C167CR

C167SR

Functional Description

3.13 Oscillator Watchdog

The Oscillator Watchdog (OWD) monitors the clock signal generated by the on-chip
oscillator (either with a crystal or via external clock drive). For this operation the PLL
provides a clock signal which is used to supervise transitions on the oscillator clock. This
PLL clock is independent from the XTAL1 clock. When the expected oscillator clock
transitions are missing the OWD activates the PLL Unlock / OWD interrupt node and
supplies the CPU with the PLL clock signal. Under these circumstances the PLL will
oscillate with its basic frequency.

In direct drive mode the PLL base frequency is used directly (
In prescaler mode the PLL base frequency is divided by 2 (

f

= 2 … 5 MHz).

CPU

f

= 1 … 2.5 MHz).

CPU

Note: The CPU clock source is only switched back to the oscillator clock after a

hardware reset.

The oscillator watchdog can be disabled via hardware by (externally) pulling low pin
OWE (internal pull-up provides high level if not connected). In this case (OWE = ‘0’) the
PLL remains idle and provides no clock signal, while the CPU clock signal is derived
directly from the oscillator clock or via prescaler. Also no interrupt request will be
generated in case of a missing oscillator clock.

Data Sheet 46 V3.3, 2005-02

C167CR

C167SR

Functional Description

3.14 Instruction Set Summary

Table 7 lists the instructions of the C167CR in a condensed way.

The various addressing modes that can be used with a specific instruction, the operation
of the instructions, parameters for conditional execution of instructions, and the opcodes
for each instruction can be found in the “C166 Family Instruction Set Manual”.

This document also provides a detailed description of each instruction.

Table 7 Instruction Set Summary

Mnemonic Description Bytes

ADD(B) Add word (byte) operands 2 / 4

ADDC(B) Add word (byte) operands with Carry 2 / 4

SUB(B) Subtract word (byte) operands 2 / 4

SUBC(B) Subtract word (byte) operands with Carry 2 / 4

MUL(U) (Un)Signed multiply direct GPR by direct GPR

(16 × 16 bits)

DIV(U) (Un)Signed divide register MDL by direct GPR

(16 / 16 bits)

DIVL(U) (Un)Signed long divide reg. MD by direct GPR

(32 / 16 bits)

CPL(B) Complement direct word (byte) GPR 2

NEG(B) Negate direct word (byte) GPR 2

AND(B) Bitwise AND, (word/byte operands) 2 / 4

OR(B) Bitwise OR, (word/byte operands) 2 / 4

XOR(B) Bitwise XOR, (word/byte operands) 2 / 4

BCLR Clear direct bit 2

BSET Set direct bit 2

BMOV(N) Move (negated) direct bit to direct bit 4

BAND, BOR,
BXOR

AND/OR/XOR direct bit with direct bit 4

2

2

2

BCMP Compare direct bit to direct bit 4

BFLDH/L Bitwise modify masked high/low byte of bit-addressable

direct word memory with immediate data

CMP(B) Compare word (byte) operands 2 / 4

CMPD1/2 Compare word data to GPR and decrement GPR by 1/2 2 / 4

CMPI1/2 Compare word data to GPR and increment GPR by 1/2 2 / 4

Data Sheet 47 V3.3, 2005-02

4

C167CR

C167SR

Functional Description

Table 7 Instruction Set Summary (cont’d)

Mnemonic Description Bytes

PRIOR Determine number of shift cycles to normalize direct

2

word GPR and store result in direct word GPR

SHL / SHR Shift left/right direct word GPR 2

ROL / ROR Rotate left/right direct word GPR 2

ASHR Arithmetic (sign bit) shift right direct word GPR 2

MOV(B) Move word (byte) data 2 / 4

MOVBS Move byte operand to word operand with sign extension 2 / 4

MOVBZ Move byte operand to word operand. with zero extension 2 / 4

JMPA, JMPI,

Jump absolute/indirect/relative if condition is met 4

JMPR

JMPS Jump absolute to a code segment 4

J(N)B Jump relative if direct bit is (not) set 4

JBC Jump relative and clear bit if direct bit is set 4

JNBS Jump relative and set bit if direct bit is not set 4

CALLA, CALLI,

Call absolute/indirect/relative subroutine if condition is met 4

CALLR

CALLS Call absolute subroutine in any code segment 4

PCALL Push direct word register onto system stack and call

absolute subroutine

TRAP Call interrupt service routine via immediate trap number 2

PUSH, POP Push/pop direct word register onto/from system stack 2

SCXT Push direct word register onto system stack and update

register with word operand

RET Return from intra-segment subroutine 2

RETS Return from inter-segment subroutine 2

RETP Return from intra-segment subroutine and pop direct

word register from system stack

RETI Return from interrupt service subroutine 2

SRST Software Reset 4

IDLE Enter Idle Mode 4

PWRDN Enter Power Down Mode (supposes NMI

-pin being low) 4

SRVWDT Service Watchdog Timer 4

4

4

2

Data Sheet 48 V3.3, 2005-02

C167CR

C167SR

Functional Description

Table 7 Instruction Set Summary (cont’d)

Mnemonic Description Bytes

DISWDT Disable Watchdog Timer 4

EINIT Signify End-of-Initialization on RSTOUT

-pin 4

ATOMIC Begin ATOMIC sequence 2

EXTR Begin EXTended Register sequence 2

EXTP(R) Begin EXTended Page (and Register) sequence 2 / 4

EXTS(R) Begin EXTended Segment (and Register) sequence 2 / 4

NOP Null operation 2

Data Sheet 49 V3.3, 2005-02

C167CR

C167SR

Functional Description

3.15 Special Function Registers Overview

The following table lists all SFRs which are implemented in the C167CR in alphabetical
order.

Bit-addressable SFRs are marked with the letter “b” in column “Name”. SFRs within the
Extended SFR-Space (ESFRs) are marked with the letter “E” in column “Physical

Address”. Registers within on-chip X-peripherals are marked with the letter “X” in column
“Physical Address”.

An SFR can be specified via its individual mnemonic name. Depending on the selected
addressing mode, an SFR can be accessed via its physical address (using the Data
Page Pointers), or via its short 8-bit address (without using the Data Page Pointers).

Note: Registers within device specific interface modules (CAN) are only present in the

corresponding device, of course.

Table 8 C167CR Registers, Ordered by Name

Name Physical

Address

ADCIC b FF98

ADCON b FFA0

ADDAT FEA0

H

H

H

8-Bit
Addr.

CC

D0

50

ADDAT2 F0A0HE 50

ADDRSEL1 FE18

ADDRSEL2 FE1A

ADDRSEL3 FE1C

ADDRSEL4 FE1E

ADEIC b FF9A

BUSCON0 b FF0C

BUSCON1 b FF14

BUSCON2 b FF16

H

H

H

H

H

H

H

H

0C

0D

0E

0F

CD

86

8A

8B

Description Reset

A/D Converter End of Conversion

H

Interrupt Control Register

A/D Converter Control Register 0000

H

A/D Converter Result Register 0000

H

A/D Converter 2 Result Register 0000

H

Address Select Register 1 0000

H

Address Select Register 2 0000

H

Address Select Register 3 0000

H

Address Select Register 4 0000

H

A/D Converter Overrun Error Interrupt

H

Control Register

Bus Configuration Register 0 0XX0

H

Bus Configuration Register 1 0000

H

Bus Configuration Register 2 0000

H

Value

0000

0000

H

H

H

H

H

H

H

H

H

H

H

H

BUSCON3 b FF18

BUSCON4 b FF1A

H

H

C1BTR EF04HX – CAN1 Bit Timing Register UUUU

C1CSR EF00HX – CAN1 Control / Status Register XX01

C1GMS EF06HX – CAN1 Global Mask Short UFUU

8C

8D

Bus Configuration Register 3 0000

H

Bus Configuration Register 4 0000

H

H

H

H

H

H

Data Sheet 50 V3.3, 2005-02

Table 8 C167CR Registers, Ordered by Name (cont’d)

C167CR

C167SR

Functional Description

Name Physical

Address

8-Bit
Addr.

Description Reset

Value

C1IR EF02HX – CAN1 Interrupt Register XX

C1LGML EF0AHX – CAN1 Lower Global Mask Long UUUU

C1LMLM EF0EHX – CAN1 Lower Mask of Last Message UUUU

C1UAR EFn2HX – CAN1 Upper Arbitration Register

UUUU

(message n)

C1UGML EF08HX – CAN1 Upper Global Mask Long UUUU

C1UMLM EF0CHX – CAN1 Upper Mask of Last Message UUUU

CAPREL FE4A

CC0 FE80

CC0IC b FF78

CC1 FE82

CC10 FE94

CC10IC b FF8C

H

H

H

H

H

H

25

40

BC

41

4A

C6

GPT2 Capture/Reload Register 0000

H

CAPCOM Register 0 0000

H

CAPCOM Register 0 Interrupt Ctrl. Reg. 0000

H

CAPCOM Register 1 0000

H

CAPCOM Register 10 0000

H

CAPCOM Reg. 10 Interrupt Ctrl. Reg. 0000

H

H

H

H

H

H

H

H

H

H

H

H

H

CC11 FE96

CC11IC b FF8E

CC12 FE98

CC12IC b FF90

CC13 FE9A

CC13IC b FF92

CC14 FE9C

CC14IC b FF94

CC15 FE9E

CC15IC b FF96

CC16 FE60

CC16IC b F160

CC17 FE62

CC17IC b F162

CC18 FE64

H

H

H

H

H

H

H

H

H

H

H

H

H

H

H

4B

C7

4C

C8

4D

C9

4E

CA

4F

CB

30

E B0

31

E B1

32

CAPCOM Register 11 0000

H

CAPCOM Reg. 11 Interrupt Ctrl. Reg. 0000

H

CAPCOM Register 12 0000

H

CAPCOM Reg. 12 Interrupt Ctrl. Reg. 0000

H

CAPCOM Register 13 0000

H

CAPCOM Reg. 13 Interrupt Ctrl. Reg. 0000

H

CAPCOM Register 14 0000

H

CAPCOM Reg. 14 Interrupt Ctrl. Reg. 0000

H

CAPCOM Register 15 0000

H

CAPCOM Reg. 15 Interrupt Ctrl. Reg. 0000

H

CAPCOM Register 16 0000

H

CAPCOM Reg. 16 Interrupt Ctrl. Reg. 0000

H

CAPCOM Register 17 0000

H

CAPCOM Reg. 17 Interrupt Ctrl. Reg. 0000

H

CAPCOM Register 18 0000

H

H

H

H

H

H

H

H

H

H

H

H

H

H

H

H

CC18IC b F164

CC19 FE66

H

H

E B2

33

CAPCOM Reg. 18 Interrupt Ctrl. Reg. 0000

H

CAPCOM Register 19 0000

H

H

H

Data Sheet 51 V3.3, 2005-02

Table 8 C167CR Registers, Ordered by Name (cont’d)

C167CR

C167SR

Functional Description

Name Physical

Address

CC19IC b F166

CC1IC b FF7A

CC2 FE84

CC20 FE68

CC20IC b F168

CC21 FE6A

H

H

H

H

H

H

8-Bit
Addr.

E B3

BD

42

34

E B4

35

CC21IC b F16AHE B5

CC22 FE6C

H

36

CC22IC b F16CHE B6

CC23 FE6E

H

37

CC23IC b F16EHE B7

CC24 FE70

CC24IC b F170

H

H

38

E B8

Description Reset

CAPCOM Reg. 19 Interrupt Ctrl. Reg. 0000

H

CAPCOM Reg. 1 Interrupt Ctrl. Reg. 0000

H

CAPCOM Register 2 0000

H

CAPCOM Register 20 0000

H

CAPCOM Reg. 20 Interrupt Ctrl. Reg. 0000

H

CAPCOM Register 21 0000

H

CAPCOM Reg. 21 Interrupt Ctrl. Reg. 0000

H

CAPCOM Register 22 0000

H

CAPCOM Reg. 22 Interrupt Ctrl. Reg. 0000

H

CAPCOM Register 23 0000

H

CAPCOM Reg. 23 Interrupt Ctrl. Reg. 0000

H

CAPCOM Register 24 0000

H

CAPCOM Reg. 24 Interrupt Ctrl. Reg. 0000

H

Value

H

H

H

H

H

H

H

H

H

H

H

H

H

CC25 FE72

CC25IC b F172

CC26 FE74

CC26IC b F174

CC27 FE76

CC27IC b F176

CC28 FE78

CC28IC b F178

CC29 FE7A

CC29IC b F184

CC2IC b FF7C

CC3 FE86

CC30 FE7C

H

H

H

H

H

H

H

H

H

H

H

H

H

39

E B9

3A

E BA

3B

E BB

3C

E BC

3D

E C2

BE

43

3E

CC30IC b F18CHE C6

CC31 FE7E

H

3F

CAPCOM Register 25 0000

H

CAPCOM Reg. 25 Interrupt Ctrl. Reg. 0000

H

CAPCOM Register 26 0000

H

CAPCOM Reg. 26 Interrupt Ctrl. Reg. 0000

H

CAPCOM Register 27 0000

H

CAPCOM Reg. 27 Interrupt Ctrl. Reg. 0000

H

CAPCOM Register 28 0000

H

CAPCOM Reg. 28 Interrupt Ctrl. Reg. 0000

H

CAPCOM Register 29 0000

H

CAPCOM Reg. 29 Interrupt Ctrl. Reg. 0000

H

CAPCOM Reg. 2 Interrupt Ctrl. Reg. 0000

H

CAPCOM Register 3 0000

H

CAPCOM Register 30 0000

H

CAPCOM Reg. 30 Interrupt Ctrl. Reg. 0000

H

CAPCOM Register 31 0000

H

H

H

H

H

H

H

H

H

H

H

H

H

H

H

H

CC31IC b F194

CC3IC b FF7E

H

H

E CA

BF

CAPCOM Reg. 31 Interrupt Ctrl. Reg. 0000

H

CAPCOM Reg. 3 Interrupt Ctrl. Reg. 0000

H

H

H

Data Sheet 52 V3.3, 2005-02

Table 8 C167CR Registers, Ordered by Name (cont’d)

C167CR

C167SR

Functional Description

Name Physical

Address

CC4 FE88

CC4IC b FF80

CC5 FE8A

CC5IC b FF82

CC6 FE8C

CC6IC b FF84

CC7 FE8E

CC7IC b FF86

CC8 FE90

CC8IC b FF88

CC9 FE92

CC9IC b FF8A

CCM0 b FF52

H

H

H

H

H

H

H

H

H

H

H

H

H

8-Bit
Addr.

44

H

C0

H

45

H

C1

H

46

H

C2

H

47

H

C3

H

48

H

C4

H

49

H

C5

H

A9

H

Description Reset

Value

CAPCOM Register 4 0000

CAPCOM Reg. 4 Interrupt Ctrl. Reg. 0000

CAPCOM Register 5 0000

CAPCOM Register 5 Interrupt Ctrl. Reg. 0000

CAPCOM Register 6 0000

CAPCOM Reg. 6 Interrupt Ctrl. Reg. 0000

CAPCOM Register 7 0000

CAPCOM Reg. 7 Interrupt Ctrl. Reg. 0000

CAPCOM Register 8 0000

CAPCOM Reg. 8 Interrupt Ctrl. Reg. 0000

CAPCOM Register 9 0000

CAPCOM Reg. 9 Interrupt Ctrl. Reg. 0000

CAPCOM Mode Control Register 0 0000

H

H

H

H

H

H

H

H

H

H

H

H

H

CCM1 b FF54

CCM2 b FF56

CCM3 b FF58

CCM4 b FF22

CCM5 b FF24

CCM6 b FF26

CCM7 b FF28

CP FE10

CRIC b FF6A

CSP FE08

DP0L b F100

DP0H b F102

DP1L b F104

DP1H b F106

H

H

H

H

H

H

H

H

H

H

H

H

H

H

AA

AB

AC

91

92

93

94

08

B5

04

E 80

E 81

E 82

E 83

CAPCOM Mode Control Register 1 0000

H

CAPCOM Mode Control Register 2 0000

H

CAPCOM Mode Control Register 3 0000

H

CAPCOM Mode Control Register 4 0000

H

CAPCOM Mode Control Register 5 0000

H

CAPCOM Mode Control Register 6 0000

H

CAPCOM Mode Control Register 7 0000

H

CPU Context Pointer Register FC00

H

GPT2 CAPREL Interrupt Ctrl. Register 0000

H

CPU Code Segment Pointer Register

H

(read only)

P0L Direction Control Register 00

H

P0H Direction Control Register 00

H

P1L Direction Control Register 00

H

P1H Direction Control Register 00

H

0000

H

H

H

H

H

H

H

H

H

H

H

H

H

H

DP2 b FFC2

DP3 b FFC6

H

H

E1

E3

Port 2 Direction Control Register 0000

H

Port 3 Direction Control Register 0000

H

H

H

Data Sheet 53 V3.3, 2005-02

Table 8 C167CR Registers, Ordered by Name (cont’d)

C167CR

C167SR

Functional Description

Name Physical

Address

DP4 b FFCA

DP6 b FFCE

DP7 b FFD2

DP8 b FFD6

DPP0 FE00

DPP1 FE02

DPP2 FE04

DPP3 FE06

H

H

H

H

H

H

H

H

8-Bit
Addr.

E5

E7

E9

EB

00

01

02

03

EXICON b F1C0HE E0

MDC b FF0E

MDH FE0C

MDL FE0E

H

H

H

87

06

07

ODP2 b F1C2HE E1

Description Reset

Port 4 Direction Control Register 00

H

Port 6 Direction Control Register 00

H

Port 7 Direction Control Register 00

H

Port 8 Direction Control Register 00

H

CPU Data Page Pointer 0 Reg. (10 bits) 0000

H

CPU Data Page Pointer 1 Reg. (10 bits) 0001

H

CPU Data Page Pointer 2 Reg. (10 bits) 0002

H

CPU Data Page Pointer 3 Reg. (10 bits) 0003

H

External Interrupt Control Register 0000

H

CPU Multiply Divide Control Register 0000

H

CPU Multiply Divide Reg. – High Word 0000

H

CPU Multiply Divide Reg. – Low Word 0000

H

Port 2 Open Drain Control Register 0000

H

Value

H

H

H

H

H

H

H

H

H

H

H

H

H

ODP3 b F1C6HE E3

ODP6 b F1CEHE E7

ODP7 b F1D2HE E9

ODP8 b F1D6HE EB

ONES FF1E

P0H b FF02

P0L b FF00

P1H b FF06

P1L b FF04

P2 b FFC0

P3 b FFC4

P4 b FFC8

P5 b FFA2

P5DIDIS b FFA4

P6 b FFCC

H

H

H

H

H

H

H

H

H

H

H

8F

81

80

83

82

E0

E2

E4

D1

D2

E6

Port 3 Open Drain Control Register 0000

H

Port 6 Open Drain Control Register 00

H

Port 7 Open Drain Control Register 00

H

Port 8 Open Drain Control Register 00

H

Constant Value 1’s Register (read only) FFFF

H

Port 0 High Reg. (Upper half of PORT0) 00

H

Port 0 Low Reg. (Lower half of PORT0) 00

H

Port 1 High Reg. (Upper half of PORT1) 00

H

Port 1 Low Reg. (Lower half of PORT1) 00

H

Port 2 Register 0000

H

Port 3 Register 0000

H

Port 4 Register (8 bits) 00

H

Port 5 Register (read only) XXXX

H

Port 5 Digital Input Disable Register 0000

H

Port 6 Register (8 bits) 00

H

H

H

H

H

H

H

H

H

H

H

H

H

H

H

H

P7 b FFD0

P8 b FFD4

H

H

E8

EA

Port 7 Register (8 bits) 00

H

Port 8 Register (8 bits) 00

H

H

H

Data Sheet 54 V3.3, 2005-02

Table 8 C167CR Registers, Ordered by Name (cont’d)

C167CR

C167SR

Functional Description

Name Physical

Address

PECC0 FEC0

PECC1 FEC2

PECC2 FEC4

PECC3 FEC6

PECC4 FEC8

PECC5 FECA

PECC6 FECC

PECC7 FECE

H

H

H

H

H

H

H

H

8-Bit
Addr.

60

61

62

63

64

65

66

67

PICON b F1C4HE E2

PDCR F0AAHE 55

PP0 F038

H

E 1C

PP1 F03AHE 1D

PP2 F03CHE 1E

Description Reset

PEC Channel 0 Control Register 0000

H

PEC Channel 1 Control Register 0000

H

PEC Channel 2 Control Register 0000

H

PEC Channel 3 Control Register 0000

H

PEC Channel 4 Control Register 0000

H

PEC Channel 5 Control Register 0000

H

PEC Channel 6 Control Register 0000

H

PEC Channel 7 Control Register 0000

H

Port Input Threshold Control Register 0000

H

Pin Driver Control Register 0000

H

PWM Module Period Register 0 0000

H

PWM Module Period Register 1 0000

H

PWM Module Period Register 2 0000

H

Value

H

H

H

H

H

H

H

H

H

H

H

H

H

PP3 F03EHE 1F

PSW b FF10

PT0 F030

PT1 F032

PT2 F034

PT3 F036

PW0 FE30

PW1 FE32

PW2 FE34

PW3 FE36

PWMCON0 b FF30

PWMCON1 b FF32

H

H

H

H

H

H

H

H

H

H

H

88

E 18

E 19

E 1A

E 1B

18

19

1A

1B

98

99

PWMIC b F17EHE BF

RP0H b F108

S0BG FEB4

H

H

E 84

5A

PWM Module Period Register 3 0000

H

CPU Program Status Word 0000

H

PWM Module Up/Down Counter 0 0000

H

PWM Module Up/Down Counter 1 0000

H

PWM Module Up/Down Counter 2 0000

H

PWM Module Up/Down Counter 3 0000

H

PWM Module Pulse Width Register 0 0000

H

PWM Module Pulse Width Register 1 0000

H

PWM Module Pulse Width Register 2 0000

H

PWM Module Pulse Width Register 3 0000

H

PWM Module Control Register 0 0000

H

PWM Module Control Register 1 0000

H

PWM Module Interrupt Control Register 0000

H

System Start-up Config. Reg. (Rd. only) XX

H

Serial Channel 0 Baudrate Generator

H

Reload Register

0000

H

H

H

H

H

H

H

H

H

H

H

H

H

H

H

S0CON b FFB0

H

D8

Serial Channel 0 Control Register 0000

H

H

Data Sheet 55 V3.3, 2005-02

Table 8 C167CR Registers, Ordered by Name (cont’d)

C167CR

C167SR

Functional Description

Name Physical

Address

S0EIC b FF70

S0RBUF FEB2

S0RIC b FF6E

H

H

H

8-Bit
Addr.

B8

59

B7

S0TBIC b F19CHE CE

S0TBUF FEB0

S0TIC b FF6C

SP FE12

H

H

H

58

B6

09

SSCBR F0B4HE 5A

SSCCON b FFB2

H

D9

Description Reset

Serial Chan. 0 Error Interrupt Ctrl. Reg. 0000

H

Serial Channel 0 Receive Buffer Reg.

H

(read only)

Serial Channel 0 Receive Interrupt

H

Control Register

Serial Channel 0 Transmit Buffer

H

Interrupt Control Register

Serial Channel 0 Transmit Buffer Reg.

H

(write only)

Serial Channel 0 Transmit Interrupt

H

Control Register

CPU System Stack Pointer Register FC00

H

SSC Baudrate Register 0000

H

SSC Control Register 0000

H

Value

XX

0000

0000

00

0000

H

H

H

H

H

H

H

H

H

SSCEIC b FF76

H

BB

SSCRB F0B2HE 59

SSCRIC b FF74

H

BA

SSCTB F0B0HE 58

SSCTIC b FF72

STKOV FE14

STKUN FE16

SYSCON b FF12

T0 FE50

T01CON b FF50

T0IC b FF9C

T0REL FE54

T1 FE52

T1IC b FF9E

T1REL FE56

H

H

H

H

H

H

H

H

H

H

H

B9

0A

0B

89

28

A8

CE

2A

29

CF

2B

SSC Error Interrupt Control Register 0000

H

SSC Receive Buffer XXXX

H

SSC Receive Interrupt Control Register 0000

H

SSC Transmit Buffer 0000

H

SSC Transmit Interrupt Control Register 0000

H

CPU Stack Overflow Pointer Register FA00

H

CPU Stack Underflow Pointer Register FC00

H

CPU System Configuration Register

H

CAPCOM Timer 0 Register 0000

H

CAPCOM Timer 0 and Timer 1 Ctrl. Reg. 0000

H

CAPCOM Timer 0 Interrupt Ctrl. Reg. 0000

H

CAPCOM Timer 0 Reload Register 0000

H

CAPCOM Timer 1 Register 0000

H

CAPCOM Timer 1 Interrupt Ctrl. Reg. 0000

H

CAPCOM Timer 1 Reload Register 0000

H

1)

0xx0

H

H

H

H

H

H

H

H

H

H

H

H

H

H

H

T2 FE40

T2CON b FF40

H

H

20

A0

GPT1 Timer 2 Register 0000

H

GPT1 Timer 2 Control Register 0000

H

H

H

Data Sheet 56 V3.3, 2005-02

Table 8 C167CR Registers, Ordered by Name (cont’d)

C167CR

C167SR

Functional Description

Name Physical

Address

T2IC b FF60

T3 FE42

T3CON b FF42

T3IC b FF62

T4 FE44

T4CON b FF44

T4IC b FF64

T5 FE46

T5CON b FF46

T5IC b FF66

T6 FE48

T6CON b FF48

T6IC b FF68

H

H

H

H

H

H

H

H

H

H

H

H

H

8-Bit
Addr.

B0

H

21

H

A1

H

B1

H

22

H

A2

H

B2

H

23

H

A3

H

B3

H

24

H

A4

H

B4

H

Description Reset

Value

GPT1 Timer 2 Interrupt Control Register 0000

GPT1 Timer 3 Register 0000

GPT1 Timer 3 Control Register 0000

GPT1 Timer 3 Interrupt Control Register 0000

GPT1 Timer 4 Register 0000

GPT1 Timer 4 Control Register 0000

GPT1 Timer 4 Interrupt Control Register 0000

GPT2 Timer 5 Register 0000

GPT2 Timer 5 Control Register 0000

GPT2 Timer 5 Interrupt Control Register 0000

GPT2 Timer 6 Register 0000

GPT2 Timer 6 Control Register 0000

GPT2 Timer 6 Interrupt Control Register 0000

H

H

H

H

H

H

H

H

H

H

H

H

H

T7 F050

T78CON b FF20

T7IC b F17AHE BE

T7REL F054

T8 F052

T8IC b F17CHE BF

T8REL F056

TFR b FFAC

WDT FEAE

WDTCON FFAE

XP0IC b F186

XP1IC b F18EHE C7

XP2IC b F196

XP3IC b F19EHE CF

ZEROS b FF1C

1) The system configuration is selected during reset.

2) The reset value depends on the indicated reset source.

H

H

H

H

H

H

H

H

H

H

H

E 28

90

E 2A

E 29

E 2B

D6

57

D7

E C3

E CB

8E

CAPCOM Timer 7 Register 0000

H

CAPCOM Timer 7 and 8 Ctrl. Reg. 0000

H

CAPCOM Timer 7 Interrupt Ctrl. Reg. 0000

H

CAPCOM Timer 7 Reload Register 0000

H

CAPCOM Timer 8 Register 0000

H

CAPCOM Timer 8 Interrupt Ctrl. Reg. 0000

H

CAPCOM Timer 8 Reload Register 0000

H

Trap Flag Register 0000

H

Watchdog Timer Register (read only) 0000

H

Watchdog Timer Control Register

H

CAN1 Module Interrupt Control Register 0000

H

Unassigned Interrupt Control Register 0000

H

Unassigned Interrupt Control Register 0000

H

PLL/OWD Interrupt Control Register 0000

H

Constant Value 0’s Register (read only) 0000

H

2)

00XX

H

H

H

H

H

H

H

H

H

H

H

H

H

H

H

Data Sheet 57 V3.3, 2005-02

Electrical Parameters

4 Electrical Parameters

4.1 General Parameters

Table 9 Absolute Maximum Rating Parameters

Parameter Symbol Limit Values Unit Notes

Min. Max.

C167CR

C167SR

Storage temperature

Junction temperature

Voltage on
respect to ground (

V

pins with

DD

V

SS

Voltage on any pin with
respect to ground (

V

SS

Input current on any pin

T

T

V

ST

J

DD

-65 150 °C–

-40 150 °C under bias

-0.5 6.5 V –

)

V

IN

-0.5 VDD + 0.5 V –

)

–-1010mA–

during overload condition

Absolute sum of all input

–– |100|mA–
currents during overload
condition

Power dissipation

P

DISS

–1.5W–

Note: Stresses above those listed under “Absolute Maximum Ratings” may cause

permanent damage to the device. This is a stress rating only and functional
operation of the device at these or any other conditions above those indicated in
the operational sections of this specification is not implied. Exposure to absolute
maximum rating conditions for extended periods may affect device reliability.
During absolute maximum rating overload conditions (
voltage on

V

pins with respect to ground (VSS) must not exceed the values

DD

V

> VDD or VIN < VSS) the

IN

defined by the absolute maximum ratings.

Data Sheet 58 V3.3, 2005-02

C167CR

C167SR

Electrical Parameters

Operating Conditions

The following operating conditions must not be exceeded in order to ensure correct
operation of the C167CR. All parameters specified in the following sections refer to these
operating conditions, unless otherwise noticed.

Table 10 Operating Condition Parameters

Parameter Symbol Limit Values Unit Notes

Min. Max.

Digital supply voltage

Digital ground voltage

Overload current

Absolute sum of overload

V

V

I

Σ|IOV|– 50 mA

currents

External Load Capacitance C

Ambient temperature T

DD

SS

OV

A

4.5 5.5 V Active mode,

2.5

f

CPUmax

1)

5.5 V Power Down mode

= 33 MHz

0 V Reference voltage

– ±5mAPer pin

3)

L

– 50 pF Pin drivers in

2)3)

fast edge mode
(PDCR.BIPEC = ‘0’)

– 30 pF Pin drivers in

reduced edge mode
(PDCR.BIPEC = ‘1’)

3)

– 100 pF Pin drivers in

fast edge mode,

f

CPUmax

= 25 MHz

4)

070°C SAB-C167CR …

-40 85 °C SAF-C167CR …

-40 125 °C SAK-C167CR …

1) Output voltages and output currents will be reduced when VDD leaves the range defined for active mode.

2) Overload conditions occur if the standard operating conditions are exceeded, i.e. the voltage on any pin

exceeds the specified range (i.e.
currents on all pins may not exceed 50 mA. The supply voltage must remain within the specified limits.
Proper operation is not guaranteed if overload conditions occur on functional pins like XTAL1, RD

3) Not subject to production test - verified by design/characterization.

4) The increased capacitive load is valid for the 25 MHz-derivatives up to a CPU clock frequency of 25 MHz.

Under these circumstances the timing parameters as specified in the “C167CR Data Sheet 1999-06” are valid.

Data Sheet 59 V3.3, 2005-02

V

> VDD + 0.5 V or VOV < VSS - 0.5 V). The absolute sum of input overload

OV

, WR, etc.

C167CR

C167SR

Electrical Parameters

Parameter Interpretation

The parameters listed in the following partly represent the characteristics of the C167CR
and partly its demands on the system. To aid in interpreting the parameters right, when
evaluating them for a design, they are marked in column “Symbol”:

CC (Controller Characteristics):
The logic of the C167CR will provide signals with the respective timing characteristics.

SR (System Requirement):
The external system must provide signals with the respective timing characteristics to
the C167CR.

4.2 DC Parameters

Table 11 DC Characteristics (Operating Conditions apply)

1)

Parameter Symbol Limit Values Unit Test Condition

Min. Max.

Input low voltage (TTL,
all except XTAL1)

Input low voltage XTAL1

Input low voltage

V

V

V

SR -0.5 0.2 VDD

IL

- 0.1

SR -0.5 0.3 V

IL2

SR -0.5 2.0 V –

ILS

DD

V–

V–

(Special Threshold)

Input high voltage (TTL,
all except RSTIN

and XTAL1)

Input high voltage RSTIN
(when operated as input)

Input high voltage XTAL1

V

V

V

SR 0.2 VDD

IH

SR 0.6 V

IH1

SR 0.7 V

IH2

+ 0.9

V

DD

0.5

DDVDD

0.5

DDVDD

+

+

+

V–

V–

V–

0.5

Input high voltage
(Special Threshold)

V

SR 0.8 VDD

IHS

- 0.2

V

DD

0.5

+

V–

Input Hysteresis
(Special Threshold)

Output low voltage

HYS 400 – mV Series

resistance = 0 Ω

V

CC – 0.45 V IOL = 2.4 mA

OL

(PORT0, PORT1, Port 4, ALE,
RD

, WR, BHE, CLKOUT,

RSTOUT

Output low voltage

, RSTIN2))

V

CC – 0.45 V IOL = 1.6 mA

OL1

(all other outputs)

Data Sheet 60 V3.3, 2005-02

C167CR

C167SR

Electrical Parameters

Table 11 DC Characteristics (Operating Conditions apply)1) (cont’d)

Parameter Symbol Limit Values Unit Test Condition

Min. Max.

Output high voltage
(PORT0, PORT1, Port 4, ALE,
RD

, WR, BHE, CLKOUT,

RSTOUT

)

Output high voltage
(all other outputs)

3)

3)

V

V

CC 2.4 – V IOH = -2.4 mA

OH

0.9

V

CC 2.4 – V IOH = -1.6 mA

OH1

0.9

V

–VIOH = -0.5 mA

DD

–VIOH = -0.5 mA

DD

Input leakage current (Port 5)

Input leakage current
(all other)

RSTIN inactive current

RSTIN active current

4)

5)

5)

READY/RD/WR inact. current

READY

ALE inactive current

ALE active current

Port 6 inactive current

Port 6 active current

/RD/WR active current

8)

8)

8)

8)

PORT0 configuration current

XTAL1 input current I

Pin capacitance

10)

(digital inputs/outputs)

1) Keeping signal levels within the levels specified in this table, ensures operation without overload conditions.

For signal levels outside these specifications also refer to the specification of the overload current

2) Valid in bidirectional reset mode only.

3) This specification is not valid for outputs which are switched to open drain mode. In this case the respective

output will float and the voltage results from the external circuitry.

4) This parameter is not valid for pins READY

5) These parameters describe the RSTIN

6) The maximum current may be drawn while the respective signal line remains inactive.

7) The minimum current must be drawn in order to drive the respective signal line active.

8) This specification is valid during Reset and during Hold-mode or Adapt-mode. During Hold-mode Port 6 pins

are only affected, if they are used (configured) for CS
READY

-pull-up is always active, except for Power-down mode.

I

I

I

I

8)

I

8)

I

I

I

I

I

9)

I

I

C

pull-up, which equals a resistance of ca. 50 to 250 kΩ.

CC – ±200 nA 0 V < VIN < V

OZ1

CC – ±500 nA 0.45 V < VIN <

OZ2

6)

RSTH

7)

RSTL

6)

RWH

7)

RWL

6)

ALEL

7)

ALEH

6)

P6H

7)

P6L

6)

P0H

7)

P0L

IL

IO

, ALE, RD, and WR while the respective pull device is on.

–-10µA VIN = V

-100 – µA VIN = V

–-40µA V

-500 – µA V

–40µA V

500 – µA V

–-40µA V

-500 – µA V

–-10µA VIN = V

-100 – µA VIN = V

CC – ±20 µA0 V < VIN < V

CC – 10 pF f = 1 MHz;

output and the open drain function is not enabled. The

V

DD

OUT

OUT

OUT

OUT

OUT

OUT

T

= 25 °C

A

IH1

IL

= 2.4 V

= V

OLmax

= V

OLmax

= 2.4 V

= 2.4 V

= V

OL1max

IHmin

ILmax

I

OV

DD

DD

.

Data Sheet 61 V3.3, 2005-02

C167CR

C167SR

Electrical Parameters

9) This specification is valid during Reset and during Adapt-mode.

10) Not subject to production test - verified by design/characterization.

Table 12 Power Consumption C167CR (Operating Conditions apply)

Parameter Symbol Limit Values Unit Test Condition

Min. Max.

Power supply current (active)
with all peripherals active

Idle mode supply current I

Power-down mode supply

I

DD

ID

I

PD

–15 + 2.5

×

f

CPU

–10 + 1.0

×

f

CPU

mA RSTIN = V

f

in [MHz]

CPU

mA RSTIN = V

f

in [MHz]

CPU

–50 µA VDD = V

IL

IH1

DDmax

1)

1)

2)

current

1) The supply current is a function of the operating frequency. This dependency is illustrated in Figure 9.

These parameters are tested at
at

V

or VIH.

IL

2) This parameter is tested including leakage currents. All inputs (including pins configured as inputs) at 0 V to

0.1 V or at

V

- 0.1 V to VDD, all outputs (including pins configured as outputs) disconnected.

DD

V

and maximum CPU clock with all outputs disconnected and all inputs

DDmax

Data Sheet 62 V3.3, 2005-02

I [mA]

140

120

100

C167CR

C167SR

Electrical Parameters

I

DDmax

I

DDtyp

80

60

40

20

10 20 30 40

f

CPU

I

IDmax

I

IDtyp

[MHz]

Figure 9 Supply/Idle Current as a Function of Operating Frequency

Data Sheet 63 V3.3, 2005-02

Electrical Parameters

4.3 Analog/Digital Converter Parameters

Table 13 A/D Converter Characteristics (Operating Conditions apply)

Parameter Symbol Limit Values Unit Test

Condition

1)

Analog reference supply

V

Min. Max.

SR 4.0 VDD + 0.1 V

AREF

C167CR

C167SR

Analog reference ground V

Analog input voltage range

Basic clock frequency f

Conversion time t

Calibration time after reset t

V

BC

C

CAL

Total unadjusted error TUE CC – ±2LSB

Internal resistance of

R

reference voltage source

Internal resistance of

R

analog source

ADC input capacitance C

1) TUE is tested at V

the defined voltage range.
If the analog reference supply voltage exceeds the power supply voltage by up to 0.2 V
(i.e.

V

= VDD + 0.2 V) the maximum TUE is increased to ±3 LSB. This range is not 100% tested.

AREF

The specified TUE is guaranteed only if the absolute sum of input overload currents on Port 5 pins (see
specification) does not exceed 10 mA.
During the reset calibration sequence the maximum TUE may be ±4 LSB.

2) V

3) The limit values for fBC must not be exceeded when selecting the CPU frequency and the ADCTC setting.

4) This parameter includes the sample time

5) During the reset calibration conversions can be executed (with the current accuracy). The time required for

6) During the conversion the ADC’s capacitance must be repeatedly charged or discharged. The internal

7) Not subject to production test - verified by design/characterization.

may exceed V

AIN

cases will be X000

result register with the conversion result.
Values for the basic clock
This parameter depends on the ADC control logic. It is not a real maximum value, but rather a fixum.

these conversions is added to the total reset calibration time.

resistance of the reference voltage source must allow the capacitance to reach its respective voltage level
within each conversion step. The maximum internal resistance results from the programmed conversion
timing.

= 5.0 V, V

AREF

or V

AGND

or X3FFH, respectively.

H

AGND

up to the absolute maximum ratings. However, the conversion result in these

AREF

t

depend on programming and can be taken from Table 14.

BC

SR VSS - 0.1 VSS + 0.2 V –

AGND

AIN

SR V

AGND

V

0.5 6.25 MHz

CC – 40 tBC + tS

+ 2

CC – 3328 t

SR – tBC / 60

AREF

AREF

t

CPU

BC

V

–

–

kΩ tBC in [ns]

2)

3)

4)

t

CPU

5)

1)

= 1/f

CPU

6)7)

- 0.25

SR – tS / 450

ASRC

kΩ tS in [ns]

7)8)

- 0.25

CC – 33 pF

AIN

= 0 V, VDD = 4.9 V. It is guaranteed by design for all other voltages within

, the time for determining the digital result and the time to load the

t

S

7)

I

OV

Data Sheet 64 V3.3, 2005-02

C167CR

C167SR

Electrical Parameters

8) During the sample time the input capacitance C

internal resistance of the analog source must allow the capacitance to reach its final voltage level within
After the end of the sample time
result.
Values for the sample time

t

, changes of the analog input voltage have no effect on the conversion

S

t

depend on programming and can be taken from Table 14.

S

can be charged/discharged by the external source. The

AIN

t

Sample time and conversion time of the C167CR’s A/D Converter are programmable.

Table 14 should be used to calculate the above timings.

The limit values for

f

must not be exceeded when selecting ADCTC.

BC

Table 14 A/D Converter Computation Table

ADCON.15|14
(ADCTC)

00 f

01

10

11

A/D Converter
Basic clock

/ 4 00 tBC × 8

CPU

f

/ 2 01 tBC × 16

CPU

f

/ 16 10 tBC × 32

CPU

f

/ 8 11 tBC × 64

CPU

f

BC

ADCON.13|12
(ADSTC)

Sample time

t

S

.

S

Converter Timing Example:

Assumptions:

Basic clock

Sample time

Conversion

f

CPU

f

BC

t

S

t

C

= 25 MHz (i.e. t

= f

CPU

= tBC × 8 = 1280 ns

= tS + 40 tBC + 2 t

time

= 40 ns), ADCTC = ‘00’, ADSTC = ‘00’

CPU

/ 4 = 6.25 MHz, i.e. tBC = 160 ns

= (1280 + 6400 + 80) ns = 7.8 µs

CPU

Data Sheet 65 V3.3, 2005-02

4.4 AC Parameters

4.4.1 Definition of Internal Timing

C167CR

C167SR

Electrical Parameters

The internal operation of the C167CR is controlled by the internal CPU clock f

CPU

. Both
edges of the CPU clock can trigger internal (e.g. pipeline) or external (e.g. bus cycles)
operations.

The specification of the external timing (AC Characteristics) therefore depends on the
time between two consecutive edges of the CPU clock, called “TCL” (see Figure 10).

Phase Locked Loop Operation

f

OSC

TCL

f

CPU

TCL

Direct Clock Drive

f

OSC

TCL

f

CPU

TCL

Prescaler Operation

f

OSC

TCL

f

CPU

TCL

MCT04338

Figure 10 Generation Mechanisms for the CPU Clock

The CPU clock signal

f

can be generated from the oscillator clock signal f

CPU

OSC

via
different mechanisms. The duration of TCLs and their variation (and also the derived
external timing) depends on the used mechanism to generate

f

. This influence must

CPU

be regarded when calculating the timings for the C167CR.

Note: The example for PLL operation shown in the fig. above refers to a PLL factor of 4.

The used mechanism to generate the basic CPU clock is selected by bitfield CLKCFG
in register RP0H.7-5.
Upon a long hardware reset register RP0H is loaded with the logic levels present on the

Data Sheet 66 V3.3, 2005-02

C167CR

C167SR

Electrical Parameters

upper half of PORT0 (P0H), i.e. bitfield CLKCFG represents the logic levels on pins
P0.15-13 (P0H.7-5).

Table 15 associates the combinations of these three bits with the respective clock

generation mode.

Table 15 C167CR Clock Generation Modes

CLKCFG
(P0H.7-5)

1 1 1

1 1 0

1 0 1

1 0 0

0 1 1

0 1 0 f

0 0 1

0 0 0

1) The external clock input range refers to a CPU clock range of 10 … 33 MHz (PLL operation).

2) The maximum frequency depends on the duty cycle of the external clock signal.

CPU Frequency

f

= f

CPU

f

× 4 2.5 to 8.25 MHz Default configuration

OSC

f

× 3 3.33 to 11 MHz –

OSC

f

× 2 5 to 16.5 MHz –

OSC

f

× 5 2 to 6.6 MHz –

OSC

f

× 1 1 to 33 MHz Direct drive

OSC

× 1.5 6.66 to 22 MHz –

OSC

f

/ 2 2 to 66 MHz CPU clock via prescaler

OSC

f

× 2.5 4 to 13.2 MHz –

OSC

OSC

× F

External Clock
Input Range

1)

Notes

2)

Prescaler Operation

When prescaler operation is configured (CLKCFG = 001

) the CPU clock is derived from

B

the internal oscillator (input clock signal) by a 2:1 prescaler.
The frequency of
the duration of an individual TCL) is defined by the period of the input clock

f

is half the frequency of f

CPU

and the high and low time of f

OSC

f

OSC

CPU

.

(i.e.

The timings listed in the AC Characteristics that refer to TCLs therefore can be

f

calculated using the period of

for any TCL.

OSC

Phase Locked Loop

When PLL operation is configured (via CLKCFG) the on-chip phase locked loop is
enabled and provides the CPU clock (see table above). The PLL multiplies the input
frequency by the factor F which is selected via the combination of pins P0.15-13 (i.e.
= f

× F). With every F’th transition of f

OSC

the PLL circuit synchronizes the CPU clock

OSC

f

CPU

to the input clock. This synchronization is done smoothly, i.e. the CPU clock frequency
does not change abruptly.

Due to this adaptation to the input clock the frequency of
it is locked to

f

. The slight variation causes a jitter of f

OSC

f

is constantly adjusted so

CPU

which also effects the

CPU

duration of individual TCLs.

Data Sheet 67 V3.3, 2005-02

C167CR

C167SR

Electrical Parameters

The timings listed in the AC Characteristics that refer to TCLs therefore must be
calculated using the minimum TCL that is possible under the respective circumstances.

The actual minimum value for TCL depends on the jitter of the PLL. As the PLL is
constantly adjusting its output frequency so it corresponds to the applied input frequency
(crystal or oscillator) the relative deviation for periods of more than one TCL is lower than
for one single TCL (see formula and Figure 11).
For a period of N × TCL the minimum value is computed using the corresponding
deviation D

:

N

(N × TCL)

= N × TCL

min

- DN, DN [ns] = ±(13.3 + N × 6.3) / f

NOM

[MHz], (1)

CPU

where N = number of consecutive TCLs and 1 ≤ N ≤ 40.

So for a period of 3 TCLs @ 25 MHz (i.e. N = 3): D
and (3TCL)

= 3TCL

min

- 1.288 ns = 58.7 ns (@ f

NOM

= (13.3 + 3 × 6.3) / 25 = 1.288 ns,

3

= 25 MHz).

CPU

This is especially important for bus cycles using waitstates and e.g. for the operation of
timers, serial interfaces, etc. For all slower operations and longer periods (e.g. pulse train
generation or measurement, lower baudrates, etc.) the deviation caused by the PLL jitter
is negligible.

Note: For all periods longer than 40 TCL the N = 40 value can be used (see Figure 11).

D

N

40 and 10 MHz

f

CPU

10 MHz

16 MHz

±30

±26.5

ns

±20

Max. jitter

This approximated formula is valid for
1 N 33 MHz.

20 MHz

25 MHz

±10

±1

1 5 10 20

40

33 MHz

N

MCD04413

Figure 11 Approximated Maximum Accumulated PLL Jitter

Data Sheet 68 V3.3, 2005-02

Direct Drive

C167CR

C167SR

Electrical Parameters

When direct drive is configured (CLKCFG = 011

) the on-chip phase locked loop is

B

disabled and the CPU clock is directly driven from the internal oscillator with the input
clock signal.
The frequency of

f

(i.e. the duration of an individual TCL) is defined by the duty cycle of the input clock

CPU

f

.

OSC

f

directly follows the frequency of f

CPU

so the high and low time of

OSC

The timings listed below that refer to TCLs therefore must be calculated using the
minimum TCL that is possible under the respective circumstances. This minimum value
can be calculated via the following formula:

TCL

For two consecutive TCLs the deviation caused by the duty cycle of
so the duration of 2TCL is always 1/

min

= 1/f

OSC

× DC

(DC = duty cycle) (2)

min

f

is compensated

OSC

f

. The minimum value TCL

OSC

therefore has to be

min

used only once for timings that require an odd number of TCLs (1, 3, …). Timings that

f

require an even number of TCLs (2, 4, …) may use the formula 2TCL = 1/

OSC

.

Data Sheet 69 V3.3, 2005-02

C167CR

C167SR

Electrical Parameters

4.4.2 External Clock Drive XTAL1

Table 16 External Clock Drive Characteristics (Operating Conditions apply)

Parameter Symbol Direct Drive

1:1

Prescaler

2:1

PLL

1:N

Unit

Min. Max. Min. Max. Min. Max.

Oscillator period

High time

Low time

Rise time

Fall time

1) The minimum and maximum oscillator periods for PLL operation depend on the selected CPU clock

generation mode. Please see respective table above.

2) The clock input signal must reach the defined levels V

3) The minimum high and low time refers to a duty cycle of 50%. The maximum operating frequency (f

direct drive mode depends on the duty cycle of the clock input signal.

2)

2)

2)

2)

t

OSC

t

1

t

2

t

3

t

4

SR 30 – 15 – 45

SR 15

SR 15

3)

3)

–5–10–ns

–5–10–ns

SR–8–5–10ns

SR–8–5–10ns

and V

IL2

t

1

.

IH2

t

3

1)

t

4

500

1)

ns

) in

CPU

V

VDD0.5

t

2

t

OSC

IH2

V

IL

MCT02534

Figure 12 External Clock Drive XTAL1

Note: If the on-chip oscillator is used together with a crystal, the oscillator frequency is

limited to a range of 4 MHz to 40 MHz.
It is strongly recommended to measure the oscillation allowance (or margin) in the
final target system (layout) to determine the optimum parameters for the oscillator
operation. Please refer to the limits specified by the crystal supplier.
When driven by an external clock signal it will accept the specified frequency
range. Operation at lower input frequencies is possible but is guaranteed by
design only (not 100% tested).

Data Sheet 70 V3.3, 2005-02

4.4.3 Testing Waveforms

C167CR

C167SR

Electrical Parameters

2.4 V

1.8 V

0.8 V

0.45 V

AC inputs during testing are driven at 2.4 V for a logic ’1’ and 0.45 V for a logic ’0’.

V

Timing measurements are made at

min for a logic ’1’ and

IH

Figure 13 Input Output Waveforms

+ 0.1 V

V

Load

- 0.1 V

V

Load

Test Points

Timing

Reference

Points

1.8 V

0.8 V

V

max for a logic ’0’.

IL

V

OH

V

OL

MCA04414

- 0.1 V

+ 0.1 V

For timing purposes a port pin is no longer floating when a 100 mV change from load voltage occurs,
but begins to float when a 100 mV change from the loaded

V

/

V

OH

level occurs (

OL

I

I

/ = 20 mA).

OH OL

MCA00763

Figure 14 Float Waveforms

Data Sheet 71 V3.3, 2005-02

C167CR

C167SR

Electrical Parameters

4.4.4 External Bus Timing

Table 17 CLKOUT Reference Signal

Parameter Symbol Limits Unit

Min. Max.

CLKOUT cycle time

tc

CC 30

5

1)

ns

CLKOUT high time

CLKOUT low time

CLKOUT rise time

CLKOUT fall time

1) The CLKOUT cycle time is influenced by the PLL jitter.

For a single CLKOUT cycle (2 TCL) the deviation caused by the PLL jitter is below 1 ns (for
For longer periods the relative deviation decreases (see PLL deviation formula).

tc

tc

tc

tc

CC 8 – ns

6

CC 6 – ns

7

CC – 4 ns

8

CC – 4 ns

9

tc

tc

CLKOUT

tc

7

5

tc

6

tc

8

Figure 15 CLKOUT Signal Timing

Variable Memory Cycles

f

> 25 MHz).

CPU

9

MCT04415

The bus timing shown below is programmable via the BUSCONx registers. The duration
of ALE and two types of waitstates can be selected. This table summarizes the possible
bus cycle durations.

Table 18 Variable Memory Cycles

Bus Cycle Type Bus Cycle Duration Unit 25/33 MHz, 0 Waitstates

Demultiplexed bus cycle
with normal ALE

Demultiplexed bus cycle
with extended ALE

Multiplexed bus cycle with
normal ALE

Multiplexed bus cycle with
extended ALE

Data Sheet 72 V3.3, 2005-02

4 + 2 × (15 - <MCTC>)
+ 2 × (1 - <MTTC>)

6 + 2 × (15 - <MCTC>)
+ 2 × (1 - <MTTC>)

6 + 2 × (15 - <MCTC>)
+ 2 × (1 - <MTTC>)

8 + 2 × (15 - <MCTC>)
+ 2 × (1 - <MTTC>)

TCL 80 ns/60.6 ns

TCL 120 ns/90.9 ns

TCL 120 ns/90.9 ns

TCL 160 ns/121.2 ns

C167CR

C167SR

Electrical Parameters

Table 19 External Bus Cycle Timing (Operating Conditions apply)

Parameter Symbol Limits Unit

Min. Max.

Output delay from CLKOUT falling edge
Valid for: address, BHE

, early CS, write data out, ALE

Output delay from CLKOUT rising edge
Valid for: latched CS

, ALE low

Output delay from CLKOUT rising edge
Valid for: WR

low (no RW delay), RD low (no RW

delay)

Output delay from CLKOUT falling edge
Valid for: RD

/WR low (with RW delay), RD high (with

RW delay)

Input setup time to CLKOUT falling edge
Valid for: read data in

Input hold time after CLKOUT falling edge
Valid for: read data in

1)

Output hold time after CLKOUT falling edge
Valid for: address, BHE

, early CS

Output hold time after CLKOUT edge

2)

3)

Valid for: write data out

tc

tc

tc

tc

tc

tc

tc

tc

CC -2 11 ns

10

CC -2 6 ns

11

CC -2 8 ns

12

CC -2 6 ns

13

SR 14 – ns

14

SR 0 – ns

15

CC -2 6 ns

17

CC -2 – ns

18

Output delay from CLKOUT falling edge
Valid for: WR

Turn off delay after CLKOUT edge

high

3)

tc

tc

CC -2 4 ns

19

CC – 7 ns

20

Valid for: write data out

Turn on delay after CLKOUT falling edge

3)

tc

CC -5 – ns

21

Valid for: write data out

1) Read data are latched with the same (internal) clock edge that triggers the address change and the rising edge

of RD

. Therefore the read data may be removed immediately after the rising edge of RD. Address changes

before the end of RD

2) Due to comparable propagation delays (at comparable capacitive loads) the address does not change before

WR

goes high. The minimum output delay (tc

3) Not subject to production test - verified by design/characterization.

have also no impact on (demultiplexed) read cycles.

) is therefore the actual value of tc19.

17min

Data Sheet 73 V3.3, 2005-02

C167CR

C167SR

Electrical Parameters

General Notes for the Following Timing Figures

These standard notes apply to all subsequent timing figures. Additional individual notes
are placed at the respective figure.

1. The falling edge of signals RD

and WR/WRH/WRL/WrCS is controlled by the

Read/Write delay feature (bit BUSCON.RWDCx).

2. A bus cycle is extended here, if MCTC waitstates are selected or if the READY

is sampled inactive.

3. A bus cycle is extended here, if an MTTC waitstate is selected.

input

Data Sheet 74 V3.3, 2005-02

CLKOUT

Normal ALE

Extended ALE

tc

10

tc

11

Normal ALE Cycle

tc

11

tc

10

Extended ALE Cycle

tc

10

tc

11

C167CR

C167SR

Electrical Parameters

tc

11

CSxL

A23-A0
BHE, CSxE

WRL, WRH,
WR, WrCS

D15-D0

tc

10

tc

10

tc

12

1)

tc

21

Valid

tc

13

tc

10

2)

MCTC

tc

tc

19

Data OUT

MTTC

17

3)

tc

18

tc

20

MCT04416

Figure 16 Demultiplexed Bus, Write Access

Data Sheet 75 V3.3, 2005-02

CLKOUT

Normal ALE

Extended ALE

tc

10

tc

11

Normal ALE Cycle

tc

11

tc

10

Extended ALE Cycle

tc

10

tc

11

C167CR

C167SR

Electrical Parameters

tc

11

CSxL

A23-A0,
BHE, CSxE

RD,
RdCS

D15-D0

tc tc

10

10

tc

12

1)

Valid

tc

13

2)

MCTC

tc

13

tc

tc

14

Data IN

tc

17

15

3)

MTTC

MCT04417

Figure 17 Demultiplexed Bus, Read Access

Data Sheet 76 V3.3, 2005-02

CLKOUT

C167CR

C167SR

Electrical Parameters

Normal ALE

Extended ALE

CSxL

A23-A16
BHE, CSxE

tc

tc

10

10

tc

11

tc

tc

10

10

tc

11

Extended ALE Cycle

tc

10

tc

11

tc

12

Normal ALE Cycle

Valid

tc

13

tc

19

tc

17

WRL, WRH,
WR, WrCS

AD15-AD0
(Normal ALE)

AD15-AD0
(Extended ALE)

tc

21

tc

10

tc

10

tc

21

Low Address

Low Address

1)

tc

tc

Figure 18 Multiplexed Bus, Write Access

17

17

tc

tc

10

10

2)

MCTC

Data OUT

Data OUT

3)

MTTC

tc

tc

18

18

tc

20

tc

20

MCT04418

Data Sheet 77 V3.3, 2005-02

CLKOUT

C167CR

C167SR

Electrical Parameters

Normal ALE

Extended ALE

CSxL

A23-A16
BHE, CSxE

tc

tc

10

10

tc

11

tc

tc

10

10

tc

11

Extended ALE Cycle

tc

10

tc

11

tc

12

Normal ALE Cycle

Valid

tc

13

tc

13

tc

17

RD,
RdCS

tc

10

tc

21

AD15-AD0
(Normal ALE)

AD15-AD0
(Extended ALE)

tc

21

tc

10

Low Address

Low Address

Figure 19 Multiplexed Bus, Read Access

1)

tc

tc

17

17

tc

tc

20

20

2)

MCTC

tc

tc

14

Data IN

tc

tc

14

Data IN

15

15

3)

MTTC

MCT04419

Data Sheet 78 V3.3, 2005-02

C167CR

C167SR

Electrical Parameters

Bus Cycle Control via READY Input

The duration of an external bus cycle can be controlled by the external circuitry via the
READY

input signal.

Synchronous READY

permits the shortest possible bus cycle but requires the input

signal to be synchronous to the reference signal CLKOUT.

Asynchronous READY

puts no timing constraints on the input signal but incurs one

waitstate minimum due to the additional synchronization stage.

Table 20 READY

Timing (Operating Conditions apply)

Parameter Symbol Limits Unit

Min. Max.

Input setup time to CLKOUT rising edge
Valid for: READY

input

Input hold time after CLKOUT rising edge
Valid for: READY

Asynchronous READY

input

input low time

6)

tc

tc

tc

CC 12 – ns

25

CC0–ns

26

CC tc5 + tc

27

–ns

25

Notes (Valid also for Figure 20)

4. Cycle as programmed, including MCTC waitstates (Example shows 0 MCTC WS).

5. READY

waitstate, READY

sampled HIGH at this sampling point generates a READY controlled

sampled LOW at this sampling point terminates the currently

running bus cycle.

6. These timings are given for test purposes only, in order to assure recognition at a

specific clock edge. If the Asynchronous READY
setup and hold times with respect to CLKOUT, it must fulfill
synchronized. Proper deactivation of READY
in response to the trailing (rising) edge of the corresponding command (RD

signal does not fulfill the indicated

tc

in order to be safely

27

is guaranteed if READY is deactivated

or WR).

7. Multiplexed bus modes have a MUX waitstate added after a bus cycle, and an

additional MTTC waitstate may be inserted here. For a multiplexed bus with MTTC
waitstate this delay is 2 CLKOUT cycles, for a demultiplexed bus without MTTC
waitstate this delay is zero.

8. If the next following bus cycle is READY

controlled, an active READY signal must be
disabled before the first valid sample point for the next bus cycle. This sample point
depends on the MTTC waitstate of the current cycle, and on the MCTC waitstates
and the ALE mode of the next following cycle. If the current cycle uses a multiplexed
bus the intrinsic MUX waitstate adds another CLKOUT cycle to the READY
deactivation time.

Data Sheet 79 V3.3, 2005-02

C167CR

C167SR

Electrical Parameters

Running Cycle

CLKOUT

4)

READY WS MUX/MTTC

tc

tc

14

D15-D0 Data IN

tc

10

tc

21

D15-D0 Data OUT

tc

13

Command
(RD, WR)

Synchronous
READY

Asynchronous
READY

tc

25

5)

tc

tc

26

12

1)

tc

26

tc

25

5) 5)

tc

27

tc

26

tc

25

5)

tc

tc

25

tc

26

13

15

6)

7)

tc

20

tc

18

tc

/

19

The next external bus cycle may start here.

8)

MCT04420

Figure 20 READY Timings

Data Sheet 80 V3.3, 2005-02

External Bus Arbitration

C167CR

C167SR

Electrical Parameters

Table 21 Bus Arbitration Timing

(Operating Conditions apply)

Parameter Symbol Limits Unit

Min. Max.

HOLD

CLKOUT to BREQ

CLKOUT to HLDA

CSx

CSx

Other signals release

Other signals drive

1) Not subject to production test - verified by design/characterization.

input setup time to CLKOUT falling edge tc

delay tc

delay tc

release

1)

tc

drive tc

1)

1)

tc

tc

SR 18 – ns

28

CC -4 6 ns

29

CC -4 6 ns

30

CC 0 10 ns

31

CC -2 6 ns

32

CC 0 10 ns

33

CC06ns

34

Data Sheet 81 V3.3, 2005-02

CLKOUT

HOLD

HLDA

tc

28

1)

tc

30

tc

C167CR

C167SR

Electrical Parameters

29

BREQ

CS

Other
Signals

tc

33

tc

2)

31

3)

MCT04421

Figure 21 External Bus Arbitration, Releasing the Bus

Notes

1. The C167CR will complete the currently running bus cycle before granting bus
access.

2. This is the first possibility for BREQ

3. The CS

outputs will be resistive high (pull-up) after t33. Latched CS outputs are driven

to get active.

high for 1 TCL before the output drivers are switched off.

Data Sheet 82 V3.3, 2005-02

C167CR

C167SR

Electrical Parameters

CLKOUT

HOLD

HLDA

BREQ

CS

Other
Signals

tc

29

tc

28

tc

29

4)

tc

30

tc

tc

5)

29

34

tc

32

MCT04422

Figure 22 External Bus Arbitration, Regaining the Bus

Notes

4. This is the last chance for BREQ
BREQ
Please note that HOLD

is activated earlier, the regain-sequence is initiated by HOLD going high.

may also be deactivated without the C167CR requesting the

to trigger the indicated regain-sequence. Even if

bus.

5. The next C167CR driven bus cycle may start here.

Data Sheet 83 V3.3, 2005-02

C167CR

C167SR

Electrical Parameters

External XRAM Access

If XPER-Share mode is enabled the on-chip XRAM of the C167CR can be accessed
(during hold states) by an external master like an asynchronous SRAM.

Table 22 XRAM Access Timing (Operating Conditions apply)

1)

Parameter Symbol Limits Unit

Min. Max.

Address setup time before RD

Address hold time after RD

Data turn on delay after RD

Data output valid delay after address latched

/WR falling edge t

/WR rising edge t

falling edge

40

41

t

42

t

43

SR 4 – ns

SR 0 – ns

CC 1 – ns

CC – 40 ns

Read

Data turn off delay after RD

Write data setup time before WR

Write data hold time after WR

WR

pulse width t

WR

signal recovery time t

1) The minimum access cycle time is 60 ns.

rising edge t

rising edge

rising edge t

Write

44

t

45

46

47

48

CC 1 14 ns

SR 10 – ns

SR 2 – ns

SR 20 – ns

SR t

40

–ns

t

40

Address

Command
(RD, WR)

Write Data

t

43

t

42

Read Data

Figure 23 External Access to the XRAM

t

41

t

47

t

45

t

48

t

46

t

44

MCT04423

Data Sheet 84 V3.3, 2005-02

5 Package Outlines

C167CR

C167SR

Package Outlines

144

0.3

A

0.65

±0.08

144x

M

A-B

0.12

D C

35 x 0.65 = 22.75

31.2

1)

28

D

-0.1

2.4

0.25 MIN.

0.2

0.2

0.1

A-B
A-B

C

H

2.75 MAX.

±0.15

0.88

4x

D
D

4xH

-0.02

+0.08

0.15

7˚ MAX.

B

1)

28

31.2

1 x 45˚

1

Index Marking

1)

Does not include plastic or metal protrusion of 0.25 max. per side

GPM05248

Figure 24 P-MQFP-144-8 (Plastic Metric Quad Flat Package)

You can find all of our packages, sorts of packing and others in our
Infineon Internet Page “Products”: http://www.infineon.com/products.

Data Sheet 85 V3.3, 2005-02

Dimensions in mm

C167CR

C167SR

Package Outlines

(0.8)

A14

±0.1

(0.56)

0.4

13 x 1 = 13

13 x 1 = 13

1

ø0.5

+0.14

-0.16

176x

ø0.3
ø0.1

1

P1

M
M

±1

A1

13

2 MAX.

A

B

0.2

C

C

C

A

±0.2

15

±0.5

1.5
Index Marking

4x

±1

13

15

±0.2

Index Marking
(sharp edge)

B

Figure 25 P-BGA-176-2 (Plastic Ball Grid Array Package)

You can find all of our packages, sorts of packing and others in our
Infineon Internet Page “Products”: http://www.infineon.com/products.

GPA09430

Dimensions in mm

Data Sheet 86 V3.3, 2005-02

www.infineon.com

Published by Infineon Technologies AG