Infineon C166S V1 SubSystem User Manual

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User’s Manual, V 1.6, August 2001

C166S V1 SubSystem

C166S V1 SubS R1

Microcontrollers

Never stop thinking.

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Edition 2001-08 Published by Infineon Technologies AG,

St.-Martin-Strasse 53, D-81541 München, German y

Attention please!

The information herein is given to describe certain components and shall not be considered as warranted characteristics.

Terms of delivery and rights to technical change reserved. We hereby disclaim any and all warranties, including but not limited to warranties of non-infringement, regarding

circuits, descriptions and charts stated herein. Infineon Technologies is an appr oved CECC manufacturer.

Information

For further information on technology, delivery terms and conditions and prices please contact your nearest Infineon Technologies Office in Germany o r our Infineon Technologies Representatives worldwide (see addre ss list).

Warnings

Due to technical require ments components may contain dangerous substances. For information on the types in question please contact your nearest Infineon Technologies Office.

Infineon T echnologies Components may only be used in life-support devices or systems with the express written approval of Infineon T echnologies, if a failure of such components can reasonably be expected to cause the failure of that life-support device or system, or to affect the safety or effectiveness of that device or system. Life support devices or systems are intended to be implanted in the human body, or to support and/or maintain and sustain and/or protect human life. If they fail, it is reasonable to assume that the health of the user or other persons may be endangered.

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User’s Manual, V 1.6, August 2001

C166S V1 SubSystem

C166S V1 SubS R1

Microcontrollers

Never stop thinking.

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C166S V1 SubS R1 Revision History: 2001-08 V1.6

Previous Version: V 1.5 Page Subjects ( 2-12 Periodic Wake up from Idle or Sleep Mode 2-14 Clock Generation Unit, On-chip Bootstrap Loader 3-80..3-86 Particular Pipeline Effects 6-21 CALLA Instruction description 6-38 EINIT Instruction description 6-52 JMPA Instruction description 6-78 RETI Instruction description 6-91 SRVWDT Instruction description 6-96 TRAP Instruction description 8-1...8-29 RP0H Register 8-1, 8-34 DP3, P3, ODP4, ODP6 Registers 8-22 CLKEN System Clock Enable bit 8-31 External Bus Arbitration

major changes since last revision

)

We Listen to Your Comments

Any information within this document that you feel is wrong, unclear or missing at all? Your feedback will help us to continuously improve the quality of this document. Please send your proposal (including a reference to this document) to:

ce.cmd@infineon.com

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User’s Manual

C166S V1 SubSystem

Table of Contents Page

1 Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1-1

1.1 The Members of the 16-bit Microcontroller Family . . . . . . . . . . . . . . . . . 1-2

1.2 Summary of Basic Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1-3

2 System Overview . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-1

2.1 Basic CPU Concepts and Mega Core . . . . . . . . . . . . . . . . . . . . . . . . . . 2-2

2.1.1 High Instruction Bandwidth / Fast Execution . . . . . . . . . . . . . . . . . . . . 2-2

2.1.2 High Function 8-bit and 16-bit Arithmetic and Logic Unit . . . . . . . . . . . 2-3

2.1.3 Extended Bit Processing and Peripheral Control . . . . . . . . . . . . . . . . . 2-4

2.1.4 Consistent and Optimized Instruction Formats . . . . . . . . . . . . . . . . . . 2-5

2.1.5 Programmable Multiple Priority Interrupt and PEC System . . . . . . . . . 2-6

2.2 The C166S System Resources . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-7

2.2.1 Memory Areas . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-7

2.2.2 External Bus Interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-8

2.2.3 The On-chip Peripheral Blocks . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-8

2.2.3.1 Asynchronous / Synchronous Serial Channel (ASC0) . . . . . . . . . . . 2-9

2.2.3.2 High Speed Synchronous Serial Channel (SSC0) . . . . . . . . . . . . . 2-10

2.2.3.3 General Purpose Timer Unit (GPT12E) . . . . . . . . . . . . . . . . . . . . . 2-10

2.2.4 Parallel Ports (PPorts) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-11

2.2.5 Periodic Wakeup from Idle or Sleep Mode . . . . . . . . . . . . . . . . . . . . 2-12

2.2.6 OCDS and JTAG . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-12

2.2.7 Core Control Block (CCB) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-12

2.2.8 Clock Generation Unit (CGU) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-14

2.2.9 On-chip Bootstrap Loader. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-14

3 Central Processing Unit . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-1

3.1 Register Description Format . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-3

3.2 CPU Special-Function Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-5

3.3 Instruction Fetch and Program Flow Control . . . . . . . . . . . . . . . . . . . . . . 3-7

3.3.1 Branch Target Addressing Modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-7

3.3.2 Sequential and Non-Sequential Instruction Flow . . . . . . . . . . . . . . . . 3-9

3.3.3 ATOMIC and EXTended Instructions . . . . . . . . . . . . . . . . . . . . . . . . 3-13

3.3.4 Code Addressing via Code Segment and Instruction Pointer . . . . . . 3-14

3.3.5 The CPU/System Configuration Register SYSCON . . . . . . . . . . . . . 3-17

3.4 Interrupt and Exception Execution . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-18

3.4.1 Interrupt System Structure . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-19

3.4.2 Interrupt Arbitration . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-19

3.4.3 Interrupt Vector Table . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-22

3.4.4 Interrupt Control Functions in the Processor Status Word . . . . . . . 3-22

3.4.4.1 Saving the Status during Interrupt Service . . . . . . . . . . . . . . . . . . 3-24

3.4.4.2 Context Switching . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-24

3.4.5 Traps . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-26

3.4.5.1 Software Traps . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-26

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3.4.5.2 Hardware Traps . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-26

3.4.6 Peripheral Event Controller . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-32

3.4.6.1 The PEC Source and Destination Pointers . . . . . . . . . . . . . . . . . . 3-33

3.4.6.2 PEC Control Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-36

3.4.6.3 Short Transfer Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-38

3.4.6.4 Long Transfer Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-39

3.4.6.5 Channel Link Mode for Data Chaining . . . . . . . . . . . . . . . . . . . . . . 3-41

3.4.6.6 PEC Channels Assignment and Arbitration . . . . . . . . . . . . . . . . . . 3-43

3.4.6.7 Programmable End of PEC Interrupt Level . . . . . . . . . . . . . . . . . . 3-44

3.5 Using General-Purpose Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-46

3.5.1 Context Switch . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-50

3.6 Data Addressing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-52

3.6.1 Short Addressing Modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-52

3.6.2 Long and Indirect Addressing Modes . . . . . . . . . . . . . . . . . . . . . . . . 3-54

3.6.2.1 Addressing via Data Page Pointer . . . . . . . . . . . . . . . . . . . . . . . . . 3-55

3.6.2.2 DPP Override Mechanism in the C166S . . . . . . . . . . . . . . . . . . . . 3-57

3.6.2.3 Long Addressing Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-58

3.6.2.4 Indirect Addressing Modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-59

3.6.3 The System Stack . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-61

3.6.3.1 Stack Overflow and Underflow . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-62

3.6.3.2 Linear Stack . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-64

3.6.3.3 Circular (Virtual) Stack . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-65

3.7 Data Processing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-68

3.7.1 Data Types . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-68

3.7.2 Constants . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-70

3.7.3 The 16-bit Adder/Subtracter, Barrel Shifter and the 16-bit Logic Unit 3-70

3.7.4 Bit-manipulation Unit . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-70

3.7.5 Multiply and Divide Unit . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-72

3.7.6 The Processor Status Word Register (PSW) . . . . . . . . . . . . . . . . . . 3-76

3.8 Instruction Pipeline . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-80

3.8.1 Particular Pipeline Effects . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-80

3.8.1.1 General considerations . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-81

3.8.1.2 Specific cases with core registers . . . . . . . . . . . . . . . . . . . . . . . . . 3-81

3.8.1.3 Common portable solution . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-86

3.8.2 Instruction State Times . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-87

3.9 Dedicated CSFRs . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-89

3.10 Summary of CPU Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-91

3.10.1 General Purpose Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-91

3.10.2 Core Special Function Registers Ordered by Name . . . . . . . . . . . . . 3-93

3.10.3 Core Special Function Registers ordered by Address . . . . . . . . . . . 3-94

3.10.4 Register Overview C166S Interrupt and Peripheral Event Controller 3-95

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4 Memory Organization . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4-1

4.1 Data Organization in Memory . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4-3

4.2 Internal Local Memory Area . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4-4

4.3 DPRAM and SFR-Area . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4-5

4.3.1 Data Memories . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4-5

4.3.2 Special Function Register Areas . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4-5

4.3.3 PEC Source and Destination Pointers . . . . . . . . . . . . . . . . . . . . . . . . . 4-7

4.4 External Memory Space . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4-8

4.4.1 External data accesses . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4-8

4.5 Crossing Memory Boundaries . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4-9

4.6 System Stack . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4-10

4.6.1 Data Organization in General Purpose Registers . . . . . . . . . . . . . . . 4-10

4.7 SFR / ESFR Table . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4-12

4.8 Interrupt Vector Table . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4-43

5 Instruction Set . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5-1

5.1 Short Instruction Summary . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5-1

5.2 Instruction Set Summary . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5-3

5.3 Instruction Opcodes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5-16

5.4 Instruction Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5-21

6 Detailed Instruction Set . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6-1

7 Parallel Ports . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7-1

7.1 Alternate Port Functions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7-2

7.2 PORT0 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7-3

7.3 PORT1 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7-7

7.4 Port 4 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7-10

7.5 Port 6 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7-13

8 The External Bus Interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8-1

8.1 Single-chip Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8-2

8.2 External Bus Modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8-2

8.2.1 Multiplexed Bus Modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8-3

8.2.2 Demultiplexed Bus Modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8-6

8.2.3 Switching Among the Bus Modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8-9

8.3 Programmable Bus Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . 8-16

8.3.1 ALE Length Control . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8-16

8.3.2 Programmable Memory Cycle Time . . . . . . . . . . . . . . . . . . . . . . . . . 8-17

8.3.3 Programmable Memory Tri-State Time . . . . . . . . . . . . . . . . . . . . . . 8-17

8.3.4 Read/Write Signal Delay . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8-18

8.3.5 Early WR . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8-18

8.3.6 READY Controlled Bus Cycles . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8-18

8.4 Controlling the External Bus Controller . . . . . . . . . . . . . . . . . . . . . . . . . 8-21

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8.5 EBC Idle State . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8-30

8.6 External Bus Arbitration . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8-31

8.7 The XBUS Interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8-35

8.7.1 XBUS Access Control . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8-37

9 Watchdog Timer . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9-1

9.1 Operation of the Watchdog Timer . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9-2

10 Asynchronous/Synchronous Serial Interface (ASC) . . . . . . . . . . . . 10-1

10.1 Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10-1

10.2 Operational Overview . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10-4

10.3 General Operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10-5

10.3.1 Asynchronous Operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10-9

10.3.1.1 Asynchronous Data Frames . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10-10

10.3.1.2 Asynchronous Transmission . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10-11

10.3.1.3 Asynchronous Reception . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10-12

10.3.2 Synchronous Operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10-14

10.3.2.1 Synchronous Transmission . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10-15

10.3.2.2 Synchronous Reception . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10-15

10.3.2.3 Synchronous Timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10-15

10.3.3 Baudrate Generation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10-17

10.3.3.1 Baudrate in Asynchronous Mode . . . . . . . . . . . . . . . . . . . . . . . . . 10-17

10.3.3.2 Baudrate in Synchronous Mode . . . . . . . . . . . . . . . . . . . . . . . . . 10-21

10.3.4 Hardware Error Detection Capabilities . . . . . . . . . . . . . . . . . . . . . . 10-23

10.3.5 Interrupts . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10-23

11 High-Speed Synchronous Serial Interface (SSC) . . . . . . . . . . . . . . . 11-1

11.1 Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11-1

11.2 General Operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11-3

11.2.1 Operating Mode Selection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11-5

11.2.2 Full-Duplex Operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11-10

11.2.3 Half-Duplex Operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11-13

11.2.4 Continuous Transfers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11-14

11.2.5 Baudrate Generation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11-15

11.2.6 Error Detection Mechanisms . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11-17

12 General Purpose Timer Unit . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12-1

12.1 Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12-1

12.2 Functional Description of Timer Block 1 . . . . . . . . . . . . . . . . . . . . . . . . 12-3

12.2.1 Core Timer T3 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12-5

12.2.2 Auxiliary Timers T2 and T4 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12-16

12.2.3 Timer Concatenation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12-21

12.3 Functional Description of Timer Block 2 . . . . . . . . . . . . . . . . . . . . . . . 12-26

12.3.1 Core Timer T6 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12-28

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Table of Contents Page

12.3.2 Auxiliary Timer T5 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12-34

12.3.3 Timer Concatenation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12-38

13 Instruction Index . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13-1

14 Keyword Index . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14-1

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Introduction

1 Introduction

The rapidly growing area of embedded control applications is representing one of the most time-critical operating environments for today’s microcontrollers. Complex control algorithms have to be processed based on a large number of digital as well as analog input signals, and the appropriate output signals must be generated within a defined maximum response time. Embedded control applications also are often sensitive to board space, power consumption, and overall system cost.

Embedded control applications therefore require microcontrollers, which...

• offer a high level of system integration

• eliminate the need for addition al peripheral devices and the associ ated software overhead

• provide system security and fail-safe mechanisms

• provide effective means to control (and reduce) the device’s power consumption.

About this Manual

This manual describes the functionality of the 16-bit microcontroller-subsystem C166S_R1 of the Infineon C166 Family, the C166S-class.

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Introduction

1.1 The Members of the 16-bit Micro controller Family

The microcontroller-subsystem of the Infineon 16-bit family has been designed to meet the high performance requirements of real-time embedded control applications. The architecture of this family has been optimized for high instruction throughput and minimum response time to external stimuli (interrupts). Intelligent peripheral subsystems have been integrated to re duce the nee d for CPU (Centr al Processing Unit) inter vention to a minimum extent. This also minimizes the need for communication via the external bus interface. The high flexibility of this architecture allows to serve the diverse and varying needs of different application areas such as automotive, industrial control, or data communications.

The core of the 16-bit family has bee n developed with a m odular famil y concept in mind. All family members execute an efficient control-optimized instruction set (additional instructions for members of the second generation). This allows an easy and quick implementation of new family members with different internal memory sizes and technologies, different sets of on-chip peripherals an d/or different numbers of I/O ( Input/ Output ) pins.

The Internal Bus Interface (IBI) concept op ens a straight for ward path f or t he integrati on of application specific per ipheral modul es in additi on to the standard on-chi p peripher als in order to build application specific derivatives.

As programs for embedded control app lications become larger, favoured by programmers, because high level lang uage programs are easi er to write, to debug and to maintain.

The 80C166-type microcontrollers were the first generation of the 16-bit controller family. These devices have established the C166 architecture.

The C165-type and C167-type devices are members of the second generation of this family. This second generation is even more powerful due to additional instructions for HLL support, an increased address space, increased internal RAM (Random Access Memory) and highly efficient management of various resources on the external bus.

The C166S-type devices are members of the third generation of this family. This third generation is the synthesizable version of the second generation.

Enhanced derivatives of this second/third generation provide additional features like additional internal high-speed RAM, an integrated CAN-Module (Controller Area Network), an on-chip PLL (Phase Locked Loop), etc.

high level languages are

Utilizing integration to design efficient systems may require the integration of application specific peripherals to boost system performance, while minimizing the part count. These efforts are supported by the so-called Internal Bus Interface, defined for the Infineon 16-bit microcontroll ers (XBus second generation). Thi s Internal Bus Interface i s an internal representation of the External Bus Interface that opens and simplifies the integration of peripherals by standardizing the required interface.

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Introduction

1.2 Summary of Basic Features

The C166S is an improved representative of the Infineon family of full featured 16-bit single-chip CMOS (Complementary Metal Oxide Silicon) microcontrollers. It combines high CPU performance with high peripheral functionality. Several key features contribute to the high performance of th e C166S bases subsystem (the indicated timings refer to a CPU clock of 50 MHz).

High Performance 16-Bit CPU With Four-Stage Pipeline

• 40 ns minimum instruction cycle time, with most instructions executed in 1 cycle

• 200 ns multiplication (16-bit *16-bit), 400 ns division (32-bit/16-bit)

• Multiple high bandwidth internal data buses

• Register based design with multiple variable register banks

• Single cycle context switching support

• 16 MBytes linear address space for code and data (von Neumann architecture)

• System stack cache support with automatic stack overflow/underflow detection

Control Oriented Instruction Set with High Efficiency

• Bit, byte, and word data types

• Flexible and efficient addressing modes for high code density

• Enhanced boolean bit manipulation with direct addressability of 6 Kbits

for peripheral control and user defined flags

• Hardware traps to identify exception conditions during runtime

• HLL support for semaphore operations and efficient data access

External Bus Interface

• Multiplexed or demultiplexed bus configurations

• Segmentation capability and chip slect signal generation

• 8-bit or 16-bit data bus

• Bus cycle characteristics selectable for five programmable address areas

16-Priority-Level Interrupt System

• Up to 112 interrupt nodes with separate interrupt vectors

• 16 priority levels and 4(8) group levels

Up to 16-Channel Peripheral Event Controller (PEC)

• Interrupt driven single cycle data transfer

• Transfer count option (std. CPU interrupt after programmable number of PEC transfers)

• Long Transfer Counter

• Channel Linking

• Eliminates overhead of saving and restoring system state for interrupt r equ ests

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Intelligent On-chip Peripherals

• General Purpose Timer Unit Timer Block 1:

–f

PDBUS+/4

maximum resolution – 3 independent timers/counters – Timer/counters can be concatenated – 4 operation modes (timer, gated timer, counter, incremental) – Seperate interrupt lines

• General Purpose Timer Unit Timer Block 2: –f

PDBUS+/2

maximum resolution – 2 independent timers/counters – Timer/counters can be concatenated – 3 operation modes (timer, gated timer, counter) – Extendend capture/reload functions – Seperate interrupt lines

• Asynchronous/Sychronous Serial Channel (ASC0) with baud rate generator, parity, framing, and overrun error detection

• High Speed Synchronous Serial Cannel (SSC0) with baud rate generator, programmable data length and shift direction

• Watchdog Timer with programmable timer events

Introduction

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Complete Development Support

For the development tool support of its microcontrollers, Infineon follows a clear third party concept. Currently around 120 tool suppliers world-wide, ranging from local niche manufacturers to multinational companies with broad product portfolios, offer powerful development tools for the Infineon C166/ C166S microcontr oller fam ilies, guar anteeing a remarkable variety of price-performance classes as well as early availability of high quality key tools such as compilers, assemblers, simulators, debuggers or in-circuit emulators.

Infineon incorporates its strategic tool partners very early into the product development process, making sure embedded system developers get reliable, well-tuned tool solutions, which help them unleash the power of Infineon microcontrollers in the most effective way and with the shortest possible learning curve.

The tool environment for t he Infineon 16-bit microcon trollers includes th e following tools:

• Compilers (C, MODULA2, FORTH)

• Macro-Assemblers, Linkers, Locaters, Library Managers, Format-Converters

• Architectural Simulators

• HLL debuggers

• Real-Time operating systems

• VERILOG chip models

• In-Circuit Emulators (based on bondout or standard chips)

• Plug-In emulators

• Emulation and Clip-Over adapters, production sockets

• Logic Analyzer disassemblers

• Starter Kits

• Evaluation Boards with monitor programs

Introduction

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Introduction

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System Overview

2 System Overview

The architecture of the C166S combines the advantages of both RISC (Reduced Instruction Set Computing) and CISC (Complex Instruction Set Computing) processors in a very well-balanced way. The sum of the features which are combined results in a high performance microcontroller, which is the right choice not only for today’s applications, but also for future engineering challenges. C166S based derivatives does not only integrate a powerful CPU ( Central Proce ssing Unit) core and a set of per ipheral units into one chip, but also connects the units in a very efficient way. One of the four buses used concurrently on the C166S is the Internal Bus Interface, an internal representation of the externa l bus interface. This bus pr ovides a standardized method of integrating application-specific peripherals to produce derivatives of the standard C166S. This manual specially describes the C166S Subsystem consists of the CPU, Interrupt Controller (ITC), Bus Controller (BC), On-Chip Debug Support (OCDS) and other system specific peripherals and modules. The following figure shows the principles of a C166S based system.

Local Memory Bu s

Local

Memory

Inte rru p t/

PEC

Interrupt

Controller

GPT12E

C166S Subsystem

up to 3 kByte

DPRAM

DPRAM Interface

CPU

Break

Inte rfa c e

SSC0

External

Trace

Inte rfa c e

OCDS/

JTAG

ASC0

PORT and ded icated Pins

0/1/4/6

P o r

Bus

Bus Interface

External

RESET

CONFIG

&&%

CEG

PSC

WDT

Config.

Block

Inte rn a l

JTAG

&6 6\VWHP

PLL

Clock

Generation

Unit

PDBUS+

Peripheral

....

PORT

P o r

NMI

OSC

Peripheral

....

Memory

PORT

P o r

Internal Bus Interface

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System Overview

2.1 Basic CPU Concepts and Mega Core

The main core of the CPU consists of a 4-stage instruction pipeline, a 16-bit arithmetic and logic unit (ALU) and dedicated Special Function Registers (SFRs). Additional hardware is provided for a separ ate m ul ti ply a nd di vide unit, a bit-mask generator a nd a barrel shifter.

To meet the demand for greater perform ance and flexibility, a number of are as has been optimized in the processor core. Functional blocks in the CPU core are controlled by signals from the instruction decode logic. These are summarized below, and described in detail in the following sections:

1) High Instruction Bandwidth / Fast Execution

2) High Function 8-bit and 16-bit Arithmetic and Logic Unit

3) Extended Bit Processing and Peripheral Control

4) High Performance Branch-, Call-, and Loop Processing

5) Consistent and Optimized Instruction Formats

6) Programmable Multiple Priority Interrupt Structure

2.1.1 High Instruction Bandwidth / Fast Execution

Based on the hardware provi sio ns, m ost of the C16 6S’s instruction s can be e xecu ted i n just one machine cycle, which requires 2 CPU clock cycles T1 and T2 (2 * 1/ 4 TCL). For example, shift and rotate instructions are always processed within one machine cycle, independent of the number of bits to be shifted.

Branch-, multiply- and divide instructions normally take more than one machine cycle. These instructions, however, have also been optimized.

A 32-bit / 16-bit division takes 20 CPU clock cycles, a 16- bit 10 CPU clock cycles.

The instruction cycle time has been dramatically reduced through the use of instruction pipelining. This technique allo ws the core CPU to process portions of multiple sequentia l instruction stages in parallel. The following four stage pipeline provides the optimum balancing for the CPU core:

FETCH: In this stage, an instruction is fetched from the internal ROM (Read Only Memory) or RAM (Random Access Me mory) or from the external memory, ba sed on the current Instruction Pointer (IP) value.

DECODE: In this stage, the previously fetched instruction is decoded and the required operands are fetched.

16-bit multipli ca tion takes

CPU

EXECUTE: In this stage, the specified oper ati on is perfo rm ed on the previousl y fetched operands.

WRITE BACK: In this stage, the result is written to the specified location.

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If this technique were not used, each instruction would require four machine cycles. This increased performance a llows a greater number of tasks and interrupts t o be processed.

Instruction Decoder

Instruction decoding is primarily generated from PLA (Programmable Logic Array) outputs based on the selected opcode. No microcode is used and each pipeline stage receives control signals staged in control re gisters from the decode stage PLAs. Pipeline holds are primarily caused by waitstates for external memory accesses and cause the holding of signals in the control registers. Multiple-cycle instructions are performed through instruction injection and simple internal state machines which modify required control signals.

System Overview

2.1.2 High Function 8-bit and 16-bit Arithmetic and Logic Unit

All standard arithmetic and logical operations are perfor med in a 16-bit ALU. In addition, for byte operations, signals are provided from bits six and seven of the ALU result to correctly set the condition flags. Multiple precision arithmetic is provided through a ’CARRY-IN’ signal to the ALU from previously calculated portions of the desired operation.

Most internal execution blocks have been optimized to perform operations on either 8bit or 16-bit quantities. Once the pipe line has been filled, one instruction i s completed per machine cycle, except for multiply and divide. An advanced Booth algorithm has been incorporated to allow four bits to be multiplied and two bits to be divided per machine cycle. Thus, these operations use two coupled 16-bit registers, MDL (Multiply Divide Low Word) and MDH (Multiply Divide High Word), and require four and nine machine cycles, respectively, to perform a 16-bit by 16-bit (or 32-bit by 16-bit) cal culation plus one machine cycle to setup and adjust the operands and the result. Even these longer multiply and divide instr uctions can be interr upted during their execution to allow for very fast interrupt response. Instructions have also been provided to allow byte packing in memory while providing sign extension of byte s for word wide arithmetic operatio ns. The internal bus structure also all ows transfers of bytes or words to or from peripherals based on the peripheral requirements.

A set of consistent flags is automatically updated in the PSW (Program Status Word) after each arithmetic, lo gical , shift, or movement operatio n. These fl ags a llow br anching on specific conditions. Support for both signed and unsigned arithmetic is provided through user-specifiable branch tests. These flags are also preserved automatically by the CPU upon entry into an interrupt or trap routine. All targets for branch calculations are also computed in the central ALU.

A 16-bit barrel shifter p rovides multipl e bit sh ifts in a single cycle. Rotat es and arithmeti c shifts are also supported.

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System Overview

2.1.3 Extended Bit Processing and Peripheral Control

A large number of instructions has been dedicated to bit processing. These instructions provide efficient control and testing of peripherals while enhancing data manipulation. Unlike other microcontrollers, these instructions provide direct access to two operands in the bit-addressable space without requiring to move them into temporary flags.

The same logical instructions available for words and bytes are also supported for bits. This allows the user to compare and modify a control bit for a peripheral in one instruction. Multiple-bit shift instructions have been included to avoid long instruction streams of single-bit shift operations. These are also performed in a single machine cycle.

In addition, bit field instructions have been provided, which allow the modification of multiple bits from one operand in a single instruction.

High Performance Branch-, Call-, and Loop Processing

Due to the high percentage of branching in controller applications, branch instructions have been optimized to require one extra machine cycle only when a branch is taken. This is implemented by precal culat ing the tar get addr ess while decodi ng the in struction. To decrease loop execution overhead, three enhancements have been provided:

• The first solution provides two cycle branch execution after the first iteration of a loop.

Thus, only one addition al machine cycle is lost dur ing the execution of the ent ire loop. In loops which fall through upon completion, no additional machine cycles is lost when exiting the loop. No special instructions are required to perform loops, and loops are automatically detected during execution of branch instructions.

• The second loop enhancement allows the detection of the end of a table and avoids

the use of two compare instructions embedded in loops. One simply places the lowest negative number at the end of the specific table, and specifies branching if neither this value nor the compared value have been found. Otherwise the l oop is terminated if e ither condition has been met. The terminating condition can then be tested.

• The third loop enhancement provides a more flexib le soluti on th an the Decrement and

Skip on Zero instruction which is found in other microcontrollers. Through the use of Compare and Increment or Decrement instructions, the user can make comparisons to any value. This allows loop counters to cover any range. This is particularly advantageous in table searching.

Saving of system state is automatically performe d on the internal system stack avoiding the use of instructions to preserve state upon entry and exit of interrupt or trap routines. Call instructions push the value of the IP on the system stack, and require the same execution time as branch instructions.

Instructions have also been provided to support indirect branch and call instructions. This supports implementation of multiple CASE statement branching in assembler macros and high level languages.

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System Overview

2.1.4 Consistent and Optimized Instruction Formats

To obtain optimum performance in a pipelined design, an instruction set has been designed which incorporates concepts from Reduced I nstruction Set Computing (RISC). These concepts primarily allow fast decoding of the instructions and operands while reducing pipeline holds. These concepts, however, do not preclude the use of complex instructions, which are require d by microcont roller users. The followi ng goals w ere used to design the instruction set:

1. Provide powerful instructions to perform operations which currently require sequences of instructions and are frequently used. Avoid transfer into and out of temporary registers such as accumulators and carry bits. Perform tasks in parallel such as saving state upon entry into interrupt routines or subroutines.

2. Avoid complex encoding schemes by placing operands in consistent fields for each instruction. Also avoid complex addressing modes wh ich are not frequently used. This decreases the instruction decode time while also simplifying the development of compilers and assemblers.

3. Provide most frequently used instru ction s wi th one- word instr ucti on for ma ts. All oth er instructions are placed into two-word formats. This allow s all instructions to be placed on word boundaries, which alleviates the need for complex alignment hardware. It also has the benefit of increasing the range for relative branching instructions.

The high performance offered by the hardware implementation of the C PU can efficiently be utilized by a programmer via the highly functional C166S instruction set which includes the following instruction classes:

• Arithmetic Instructions

• Logical Instructions

• Boolean Bit Manipulation Instructions

• Compare and Loop Control Instructions

• Shift and Rotate Instructions

• Prioritize Instruction

• Data Movement Instructions

• System Stack Instructions

• Jump and Call Instructions

• Return Instructions

• System Control Instructions

• Miscellaneous Instructions

Possible operand types are bits, bytes and words. Specific instruction support the conversion (extension) of bytes to words. A variety of direct, indirect or immediate addressing modes are provided to specify the required operands.

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System Overview

2.1.5 Programmable Multiple Priority Interrupt and PEC System

The following enhanceme nts have been incl ude d to al lo w pr ocessin g of a l arg e number of interrupt sources:

1. Peripheral Event Controller (PEC): This processor is used to off-load many interrupt requests from the CPU. It avoids the overhead of ente ring and exiting i nterrupt o r trap routines by performing single-cycle interrupt-driven byte or word data transfers between any two locations wit h an optional increm ent of eith er the PEC sou rce or the destination pointer. Just one cycle is ’stolen’ from the current CPU activity to perform a PEC service.

2. Multiple Priority Interrupt Controller (ITC): This controller allows all interrupts to be placed at any specified priority. Interrupts may also be grouped, which provides the user with the ability to prevent similar priority tasks from interrupting each other. For each of the possible interrupt sources there is a separate control register, which contains an interrupt request flag, an interrupt enable flag and an interrupt priority bitfield. Once having been accepted by the CPU, an interrupt service can only be interrupted by a higher prioritized service request. For standard interrupt processing, each of the possible interrupt sources has a dedicated vector location.

3. Multiple Register Banks: This feature allows the user to specify up to sixteen general purpose registers located anywhe re in the i nternal DPRAM ( Dual Port RAM). A single one-machine-cycle instruction allows to switch register banks from one task to another.

4. Interruptible Multiple Cycle Instructions: Reduced interrupt latency is provided by allowing multiple-cycle instructions (multiply, divide) to be interruptible.

5. Hardware Traps: The C166S also provide s an excellent me chanism to identi fy and to process exceptions or error condit ions that arise dur ing r un-time, so called ’Hardware Traps’. Hardware traps cause an immediate non-maskable system reaction which is similar to a standard i nterrupt service ( branching to a dedicated vector table loca tion). The occurrence of a hardware trap is additionally signified by an individual bit in the Trap Flag Register (TFR). Except for another higher prioritized trap service being in progress, a hardware trap will interrupt any current program execution. In turn, hardware trap services can normally not be interr upted by standard or PEC interrupts.

6. Software Traps: Software interr upts are suppo rted by mean s of the ’ T RAP’ instruction in combination with an individual trap (interrupt) number.

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System Overview

2.2 The C166S System Resources

The C166S based subsystem provides a number of powerful system resources designed around the CPU. The combination of CPU and these resources results in the high performance of the members of this controller family.

2.2.1 Memory Areas

The memory space of the C166S is configured in a Von Neumann architecture which means that code memory, data memory, re gisters and I/O ports are organized within the same linear address space whi ch covers up to 16 MBytes. The entire memory space can be accessed bytewise or wordwise. Particular portions of the on-chip memory have additionally been made directly bit addressable.

An up to 3 KByte 16-bit wide internal DPRAM provides fast access to General Purpose Registers (GPRs), user data (variables) and system stack. The DPRAM may also be used for code. A unique decoding scheme provides flexible user register banks in the internal memory while optimizing the remaining RAM for user data.

The CPU has an actual register context consistin g of up to 16 wordwide and /or bytewide GPRs at its disposal, which are physically located within the on-chip RAM area. A Context Pointer (CP) register determi nes the base address of the active register bank to be accessed by the CPU at a time. The number of register banks is only restricted by the available DPRAM space. For easy parameter passing, a register bank may overlap others.

A system stack is provided as a storage for temporary data. The system stack is also located within the on-chip RAM area, and it i s accessed by the CPU via the stack pointer (SP) register. Two separate SFRs, STacK OVerflow (STKOV) and STacK UNderflow (STKUN), are implicitly compared against the stack pointer value upon each stack access for the detection of a stack overflow or underflow.

Hardware detection of the selected memory space is placed at the internal memory decoders and allows the user to specify any address directly or indire ctly and obtai n the desired data without using temporary registers or special instructions.

For Special Function Registers 1024 Bytes of the address space are reserved. The standard Special Function Register area (SFR) uses 512 bytes, while the Extended Special Function Register area (ESFR) uses the other 512 bytes. (E)SFRs ar e wordwide registers which are used for controlling and monitoring functions of the different on-chip units. Unused (E)SFR addresses are reserved for future members of the C166 family with enhanced functionality.

An optional Local Memory is provided for both code and data storage. This memory area is connected to the CPU via a 32-bit-wide local memory bus. Program execution from Local Memory is the fastest of all possible alternatives.

The type of the on-chip Local Memory (Flash/ROM/SR AM/DRAM/none) depends on the chosen derivative.

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System Overview

2.2.2 External Bus Interface

In order to meet the needs of designs where more memory is required than is provided on chip, up to 16 MBytes of external RAM and/or ROM can be connected to the microcontroller via its external bus interface. The integrated Bus Controller (BC) allows to access external memory and/or peripheral resources in a very flexible way.

It can be programmed either to Single Chip Mode when no exter nal memory is required, or to one of four different external memory access modes, which are as follows:

– 16-/18-/20-/24-bit Addresses, 16-bit Data, Demultiplexed – 16-/18-/20-/24-bit Addresses, 16-bit Data, Multiplexed – 16-/18-/20-/24-bit Addresses, 8-bit Data, Multiplexed – 16-/18-/20-/24-bit Addresses, 8-bit Data, Demultiplexed

In the demultiplexed bus modes, addresses are output on PORT1 and data is input/ output on PORT0. In the multiplexed bus modes both addresses and data use PORT0 for input/output.

Important timing characteristics of the external bus interface (Memory Cycle Time, Memory Tri-State Time, Length of ALE, Read Wri te Delay CS programmable to allow the user the adaptation of a wide range of different types of memories. In addition, different address ranges may be accessed with different bus characteristics. Up to 5 external CS glue logic. Access to very slow memories is supported via a particular ‘Ready’ function.

signals can be generated in order to save external

and WR) have been made

For applications which require less than 16 MBytes of external memory space, this address space can be restricted to 1MByte, 256 kByte or 64 kByte. In this case Port4 outputs four, two or no address (segment) lines at all. It outputs all 8 address, if an address space of 16 MByte is used.

The on-chip Internal Bus Interface is an internal rep resentation of the external bus and allows to access integrated applicatio n-specific periph erals/modules in the same w ay as external components. It provides a defined interface for these customized peripherals.

2.2.3 The On-chip Peripheral Blocks

The C166 Family clearly separate s periphe rals from the core. This structure per mits the maximum number of operations to be performed i n parallel and allows per ipheral s to be added or deleted from family members without modifications to the core. These built in peripherals either allow the CPU to interface with the external world, or provide functions on-chip that otherwise were to be added externally in the respective system. Each functional block processes data independently and communicates information over common buses. Individually selected clock signals are generated for each peripheral.

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System Overview

Peripheral Interfaces

The on-chip peripherals generally have two different types of interfaces, an interface to the CPU and an interface to external hardware. Communication between CPU and peripherals is performed through Special Function Registers (SFRs) and interrupts.

Each peripheral contains a set of Special Function Registers (SFRs), which control the functionality of the peripheral and temporarily store intermediate data results. These SFRs are located either within the standard SFR area (00’FE00 the extended ESFR area (00’F000

-00’F1FFH). Each peripheral has an associated set

-00’FFFFH) or within

of status flags. Interrupt requests are generated by the peripherals based on specific events which

occur during their operation (e.g. operation complete, error, etc.). For interfacing with e xte rna l har dwar e, sp ecifi c pins of the parallel ports a re used, w hen

an input or output function has been selected for a peripheral. During this time, the port pins are controlled by the per ipheral (when used a s outputs) or by the external hardware which controls the peripheral (when used as inputs). This is called the 'alternate (input or output) function' of a port pin, in contrast to its function as a general purpose IO pin.

Peripheral Timing

Internal operation of CPU and peripherals is based on the CPU clock (

). The on-chip

CPU

oscillator derives the CPU clock from the crystal or from the external clock signal. The clock signal (

PDBUS+

) which is gated to the peripherals is independent from the clock signal which feeds the CPU. During Idle mode the CPU’s clock is stopped while the peripherals continue their operation. Peripheral SFRs may be accessed by the CPU once per state. When an SFR is w ritten to by so ftwar e in the sam e state where it is also to be modified by the peripheral, the software write operation has priority.

2.2.3.1 Asynchronous / Synchronous Serial Channel (ASC0)

Serial communication with other microcontrollers, processors, terminals or external peripheral components is provided by a Asynchronous / Synchronous Serial Channel. The ASC0 supports full-duplex asynchronous communication up to 3.125 MBaud and half-duplex synchronous communication up to 6.25 MBaud (r eferred to a PDBUS+ cl ock of 50 MHz).

A versatile baud rate generator allows to set up all standard baud rates without subsystem clock tuning. For transmission, reception, and erroneous reception three separate interrupt requests are provided.

In asynchronous mode, 8- or 9-bit data fr ames are transm itted or received , prece ded by a start bit and terminated by one or two stop bits. For multiprocessor communication, a mechanism to distinguish address from data bytes has been incl uded (8-bit da ta + wake up bit mode).

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In synchronous mode, the ASC0 transmits or receives bytes (8 bits) synchronously to a shift clock which is generated by the ASC0.

A loop back option is available for testing purposes. A number of optional hardwar e error detection capabil ities has been included to increase

the reliability of data transfers. A parity bit can automatically be generated on transmission or be checked on reception. Framing error detection allows to recognize data frames with missing stop bits. An overrun error will be generated, if the last character received has not been read out of the receive buffer register at the time the reception of a new character is complete.

System Overview

2.2.3.2 High Speed Synchronous Serial Channel (SSC0)

Serial communication with other microcontrollers, processors, terminals or external peripheral components is provided by a High-Speed Synchronous Serial Channel.

The SSC0 allows full duplex synchronous communication up to 25 MBaud in master mode and 12.5 MBaud in slave mode (referred to a PDBUS+ clock of 50 MHz).

A dedicated baud rate generator allows to set up all standard baud rates without subsystem clock tuning. For transmission, reception, and erroneous reception three separate interrupt requests are provided.

The SSC0 transmits or receives characters of 2...16 bits length synchronously to a shift clock which can be generated by the SSC0 (master mode) or by an external master (slave mode). The SSC0 can start shifting with LSB or with MSB. Fully SPI functionality is supported. A loop back option is available for testing purposes.

A number of optional hardwar e error detection capabil ities has been included to increase the reliability of data transfers. A parity bit can automatically be generated on transmission or be checked on reception. Framing error detection allows to recognize data frames with missing stop bits. An overrun error will be generated, if the last character received has not been read out of the receive buffer register at the time the reception of a new character is complete.

2.2.3.3 General Purpose Timer Unit (GPT12E)

The General Purpose Time r Unit (GPT12E) represent s very flexible multifun ctional timer structures which may be used for timing, event counting, pulse width measurement, pulse generation, frequency multiplication, and other purposes. They incorporate five 16-bit timers that are grouped into the two timer blocks GPT1 and GPT2. Each timer in each block may operate independently in a number of different modes such as gated timer or counter mode, or may be concatenated with another timer of the same block.

Block 1 contains 3 timers/counters with a maxi mum resolution of f timers of GPT1 may optionally be configured as reload or capture registers for the core timer.

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PDBUS+

/4. The auxiliary

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Block 2 contains 2 timers/counters with a maximum resolution of f

System Overview

PDBUS+

/2. An additional CAPREL register supports capture and reload operation with extended functionality.

The following enumeration summarizes all features to be supported:

• Timer Block 1:

–f

PDBUS+

/4 maximum resolution – 3 independent timers/counters. – Timers/counters can be concatenated. – 4 operating modes (timer, gated timer, counter, incremental). – Separate interrupt request lines.

• Timer Block 2: –f

PDBUS+

/2 maximum resolution – 2 independent timers/counters. – Timers/counters can be concatenated. – 3 operating modes (timer, gated timer, counter). – Extended capture/reload functions via 16-bit Capture/Reload register CAPREL. – Separate interrupt request lines.

2.2.4 Parallel Ports (PPorts)

The C166S V1 SubS R1 provides up to 48 I/O lines which are organized into four input/ output ports. All port lines are bit-addressable and individually (bit-wise) programmable as inputs or outputs via direction r egisters. The outpu t driver is disabled when an I/O line is configured as input. This allows true bidirectional ports which are switched to high impedance state when configured as inputs.

Further features like output driver control, input characteristic selection, temperature compensation and output mode selection (open drain or push/pull mode) are not supported by the subsystem´s port module. However, these features can be easily added by the product logic, because they are controlling the PADs directly and have no influence on the port module.

The output drivers´ enable signal s are switched asynchronously to inactive l evel as soon as a subsystem reset occurs. In this case all pins are configured as inputs.

Most port lines have programmable alternate input or output functions associated with them.

PORT0 and PORT1 may be used as address and data lines when accessing external memory, while Port 4 outputs the additional segment address bits A23/19/17...A16 in applications where segmentation i s enabled to access more than 64 kBytes of mem ory.

Port 6 provides optional bus arbitration signals and chip select signals. All port lines that are not used for these alternate functions may be used as general

purpose IO lines.

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System Overview

2.2.5 Periodic Wakeup from Idle or Sleep Mode

Periodic wakeup from Idle mode or from Sleep mode combines the drastically reduced power consumption in Idle/Sleep mode (in conjunction with the additional power management features) with a high level of system availability. External signals and events can be scanned (at a lo wer r ate) by pe ri odical ly acti vating the CPU and selected peripherals which then return to po wersave mode after a short time. This greatl y reduces the system’s average power consumption. Idle/Sleep mode can also be terminated by external interrupt signals.

2.2.6 OCDS and JTAG

The On-Chip Debug Support (OCDS) provides facilities to the debugger in order to emulate resources and assists in application program debug. The main features are:

– real time emulation – extended trigger capability including: instruction pointer events, data events on

address and/or value, external inputs, counters, chaining of events, timers, etc....

– software break support – break and “break before make” (on IP events only) – simple monitor mode or JTAG based debugging through instruction injection

The C166S OCDS is controlled by the debugger from the JTAG interface. The OCDS also recei ves informations (such as IP, data, status) from the core for monitoring the activity and generating triggers. Finally, the OCDS interacts with the core through a break interface to suspend program execution, and an injection interface to allow execution of OCDS generated instructions.

through a set of registers accessible

2.2.7 Core Control Block (CCB)

The Core Control Block supports all central control tasks and all subsystem specific features. The following typical sub-modules are implemented in this unit:

Reset Control (RC)

The reset function is controlled by the reset control unit. The reset block resets the subsystem itself and provides three reset outputs to reset the complete c166S based system according to the reset source.

• Hardware Reset: The system enters the reset state immediately (asynchronous to its clock).

• Software Reset (synchronous to the CPU clock)

• Watchdog Timer Reset (synchronous to the CPU clock)

Debugger refers to the tool connected to the emu lator, and more specifically to the OCDS via the JTAG and which manages the emula tion/debugging task.

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Power Saving Control (PSC)

The idle mode, and the power down mode mode are supported by the power saving control block. Periodic wakeup from Idle mode combines the drastically reduced power consumption in Idle mode (in conjunction with the additional power management features) with a high level of system availability. External signals and events can be scanned (at a lower rate) by periodically activating the CPU and selected peripherals which then return to powersave mode after a short time. This greatly reduces the system’s average power consumption.

Clock Enable Generator (CEG)

The clock enable generator module generates the clock enable signals used by the different clock gates of the subsystem. These clock gates are used for the diffe rent clock domains:

• CPU Clock

• Negative CPU Clock

• Peripheral Clock (PDBUS+ clock)

System Overview

The CPU clock and the negative CPU clock shows the same frequency. However, both clocks have a phase shift of 180°. This behavior is used for running the EBC protocol state machine on two clock edges. Also the pr otocol of the local memor y bus LM66-Bu s is based on two clock edges and needs this two clock domains.

The peripheral bus clock is limited to 50 MHz. For not limiting the core to this frequency the peripherals are decoupled from the CPU by their own clock domain. The frequency of the peripheral clock domain is either equal to or half of the CPU clock domain.

For generating all this enable signals, the clock enable generator needs to be supplied by the double frequency of the CPU.

Watchdog Timer (WDT)

The watchdog timer represents one of the fail-safe mechanisms which have been implemented to prevent the controller from malfuncti oning. However, the watchdog timer can only detect long term malfunctioning.

The watchdog timer is enabled automatically by setting its enable control line. It is recommended that any product enables the watchdog timer after internal chip initialization. The watchdog timer can only be disabled by software in the time interval until the EINIT (end of initia lization) i nstruction has b een executed. Thus, t he application startup code is always monitored. The software has to be designed to service the watchdog timer before it overflows. If, due to hardware or software related failures, the software fails to do so, the watchdog timer overflows and generates either an internal subsystem reset, which is indicated on the subsystem boundary (general signals interface) for further product related actions, or triggers an interrupt. Which action will be triggered depends on a new control bit within the WDTCON register.

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The Watchdog Timer is a 16-bi t timer, which count s the PDBUS+ clock divided either by 2, 4, 128 or 256. The high byte of the Watchdog Timer register can be set to a predefined reload value (stored in WDTREL) in order to all ow further variation of the moni tored time interval. Each time it is serviced by the application software, the high byte of the Watchdog Timer is reloaded. Thus, time intervals between 10 µs and 336 ms (default after reset) can be monitored (referred to a PDBUS+ clock of 50 MHz).

System Overview

2.2.8 Clock Generation Unit (CGU)

The C166S clock g eneration unit gener ates the system clock based on an osc illator or crystal input. A programmable on-chip PLL adds a high flexibility on clock generation to the C166S.

2.2.9 On-chip Bootstrap Loader.

An on-chip bootstrap loader allow s to move the start code into int ernal memor ies via the serial or other interfaces.

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Central Processing Unit

3 Central Processing Unit

The C166S Central Processing Unit (CPU) represents the synthesizable generation of the well-known C166 core family. It has many powerful enhancements while remaining compatible with the C166 family. The new architecture offers a high-performance CPU; fast and efficient access to different kinds of memories; and efficient integration with peripheral units.

CSP

Division Unit Multiply Unit

MDC PSW

Zeros

Instruction Fe tch and Injection/Ex ception Handler

Bit-Mask-Gen.

Barrel-Shifter

+/-

MDLMDH

Ones

TFR

DPP0 DPP1 DPP2 DPP3

+/-

SPSEG

SP STKOV STKUN

4-Stage

Pipeline

R15 R14

GPRs

DPRAM up to 3KByte

address

R15 R14

GPRs

R1 R0

data in

data out

CPU

ALU

ADU

R1 R0

Figure 3-1 CPU architecture

The new core architecture of the C166S results in higher CPU clock frequencies compared to the C166 full custom cores.

C166S has 5 main units that are listed below. All these units have been optimized to achieve maximum performance and flexibility.

• High Performance Instruction Fetch Unit (IFU) – High bandwidth fetch interface – Instruction FIFO (First In First Out Buffer) – High-performance branch-, call-, and loop-processing with instruction flow

prediction

• Injection/Exception Handler – Handling of interrupt requests – Handling of hardware failures

• Instruction PIPeline (IPIP)

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– 4-stage execution pipeline

7. Address and Data Unit (ADU) – 16-bit arithmetic unit for address generation

8. Arithmetic and Logic Unit (ALU) – 8-bit and 16-bit arithmetic unit – 16-bit barrel shifter – Multiplication and division unit – 8-bit and 16-bit logic unit – Bit-manipulation unit

Central Processing Unit

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3.1 Register Description Form at

The C166S contains a set of Special-Function Registers (S FRs) and Extended Special Function Registers (ESFRs) that are described in the respecti ve chapter of this manua l. The example below shows how to interpret the format and notation that are used to describe SFRs and ESFRs.

A word register looks like this:

REG_NAME Short Description SFR/ESFR(A16

1514131211109876543210

000000

rrrrrr

bitfield

A byte register looks like this:

,A8H) Reset value: *****

rwh r r rw rw rwh

bitCbitBbit

REG_NAME Short Description SFR/ESFR(A16

76543210

bitfield

rwh r rw rw rwh

,A8H) Reset value: **

bit

Field Bits Type Description bitfieldX [m:n] type Description

value Function off(Default) value Enable F unction 1

... ...

bitX [n] type Description

0 Function off(Default) 1 Enable Function

Elements:

REG_NAME Name of this register bitX Name of bit bitfieldX Name of bitfield A16 / A8 Long 16-bit address / Short 8-bit address SFR/ESFR Register space (SFR or ESFR Register)

(* *) * * Register contents after reset

0/1 : defined value

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U : unchanged [undefined (X) after power up] Y : defined by reset configuration

[n] n : bit number of bit [m:n] n : bit number of first bit of the bitfield

m : bit number of last bit of the bitfield

type r : readable by software

w : writable by software h : writable by hardware

value 0/1 : defined value,

X : undefined,

: reserved for future purpose, read access delivers ’0’, must not be set to 1

Central Processing Unit

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3.2 CPU Special-Function Registers

The core CPU requires a set of CPU Special-Function Registers (CSFRs) to maintain the system state information, to control system and bus configuration, and to manage code memory segmentation and data memory paging. The CPU also uses CSFRs to access the General-Purpose Regi sters (GPRs) and the System Stack, to supply the ALU with register-addressable constants, and to suppor t multipl y and divide ALU operati ons.

The access mechanism for these CSFRs in the CPU core is identical to the access mechanism for any other SFR. Since all SFRs can be controlled by any instruction that is capable of addressing the SFR/CSFR memory space, there is no need for special system control instructions.

However, to ensure proper processor opera tions, certain restrictions on the user access to some CSFRs must be applied. For example, the Instruction Pointer (IP) and Code Segment Pointer (CSP) registers cannot be accessed directly at all. They can only be changed indirectly via branch instructions.

The Program Status Word (PSW), Stack Pointer (SP), and Multiply/Divide Control Register (MDC) registers can be modi fied explicitl y by the programmer, and i mplicitly by the CPU during normal instruction processing.

Note: Note that any explicit write request (via software) to a (C)SFR supersedes a

simultaneous modification by hardware of the same register.

Note: All (C)SFRs may be accessed word-wise, or byte-wise (some of them even

bitwise). Reading bytes from word (C)SFRs is a non-critical operation. Any write operation to a single byte of an ( C)SFR clears the non -addre ssed complementary byte within the specified (C)SFR. Non-implemented (reserved) (C)SFR-Bits cannot be modified, and will always supply a read value of 0. Non-implemented (C)SFR will always supply a read value of FFFF

Programming Hints Access to SFRs

All SFRs reside in dedicated page of the memory space. The following addressing mechanisms allow to access the (C)SFRs:

• indirect or direct addressing with 16-bit (mem) addresses must guarantee that the used data page pointer (DPP0...DPP3) selects data page 3.

• accesses via the Peripheral Event Controller (PEC) use the SRCPx and DSTPx pointers instead of the data page pointers.

• short 8-bit (reg) addresses to the standard SFR area do not use the data page pointers but directly access the registers within this 512 Byte area.

• short 8-bit (reg) addresses to the extend ed ESFR area require switching to the 512 Byte extended SFR area. This is done via the EXTension instructions EXTR, EXTP(R), EXTS(R).

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Byte write operations to word wide SFRs via indirect or direct 16- bit (mem) addressing

or byte transfers via the PEC force zeros in the non-addressed byte. Byte write operations via short 8-bit (reg) addressing can only access the low byte of an SFR and force zeros in the high byte. It is ther efore recomm ended, to use the bi t field i nstruction s (BFLDL and BFLDH) to write to any number of bits in either byte of an SFR without disturbing the non-addressed byte and the unselected bits.

Reserved Bits

Some of the bits which are contained in the C166S’s SFRs are marked as Reserved. User software should never write 1s to reserved bits. These bits are currently not implemented and may be used in future products to invoke new functions. In this case, the active state for these functions will be 1, and the inactive state will be 0. Therefore writing only 0s to rese rved lo ca tio ns pr ovide s por tabi l ity o f the curr ent so ftware to future devices. After read accesses reserved bits should be ignored or masked out.

Central Processing Unit

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3.3 Instruction Fetch and Program Flow Control

The C166S can fetch on average one 32-bit or two 16-bit instructi ons via the 32-bit wide Local Memory Bus (LM-Bus) every machine cycle (which equals two clock cycles T1 and T2) to provide a continuous instruction flow. The instructions can be fetched via this new internal LM-Bus from the internal local memories (ROM, FLASH, OTP, SRAM, DRAM) every clock cycle. A waitstate mechanism allows the CPU to adapt to different kind of memories. For example, this mechanism can be used to:

• Access slower memories

• Generate a power ramp up phase for flash modules

• Stall a DRAM access during the refresh cycles.

Note: Additionally, the LM-Bus provides 16-bit read and write data accesses with and

without waitstates to the internal local memory. Furthermore, read protection is provided by the CPU to protect the internal local memories against illegal data accesses.

3.3.1 Branch Target Addressing Modes

The target address and the segment of jump or call instructions can be specified by several addressing modes. The IP register may be updated using relative, absolute, or indirect modes. The CSP register can be updated only by using an absolute value. A special mode is provided to address the interrupt and trap jump vector table, which resides in the lowest portion of the code segment 0.

Table 3-1 Branch Target Addressing Modes Mnemonic Target Address Target Segment Valid Address Range

...7F

...FFFE

H H

caddr (IP) = caddr - caddr= 0000 rel (IP) = (IP) + 2*rel

(IP) = (IP) + 2*(rel

[Rw] seg #trap7

(IP) = (Rw) - Rw w = 0...15

- (CSP) = seg seg = 0...255(3) (IP) = 0000H + 4*trap7 (CSP) = 0000

+1)

rel = 00 rel = 80H...FF

trap7 = 00H...7F

caddr: Specifies an absolute 16-bit code address within the current segment.

Branches MAY NOT be taken to odd code addresses. Therefore, the least significant bit of caddr must always contain a 0 or a hardware trap will occur.

rel: This mnemonic represents an 8-bit signed word offset address relative to the

current IP contents, which point to the instruction after the branch instruction. Depending on the offset address range, both forward (rel= 00 backward (rel= 80 itself is repeatedly executed, when rel = -1 (FF

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to FFH) branches are possible. The branch instruction

) for a word-sized branch

to 7FH) and

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instruction, or rel = -2 (FEH) for a double-word-sized branch instruction.

[Rw]: In this case, the 16-bit branch target instruction address is determined indi-

rectly by the contents of a word GPR. In contrast to indirect data addresses, indirectly-specified code addresses are NOT calculated via additional pointer registers (eg. DPP registers). Branches MAY NOT be taken to odd code addresses. Therefore, the least significant bit of the address pointer GPR must always contain a 0 or a hardware trap would occur.

seg: Specifies an absolute code segment number. The C166S supports 256 differ-

ent code segments, so only the 8 lower bits (r espectively) of the ’seg’ operand value are used to update the CSP register.

#trap7: Specifies a particular i nterrupt or tr ap number for branching to the correspon d-

ing interrupt or trap service routine via a jump vector table. Trap numb ers from 00

to 7FH can be specified to access any double-word code location within

the address range 00’0000

-00’01FCH in code segment 0 (i.e., the interrupt

jump vector table). For the association of trap numbers with the corresponding interrupt or trap sources, please refer to Section 3.4 “Interrupt and Trap Functions”.

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3.3.2 Sequential and Non-Sequential Instruction Flow

Since passing through one pipeline stage takes at least one machine cycle (which equals two clock cycles T1 and T2), any isolated instruction takes at least four machine cycles to be completed. Pipelining, however, allows parallel (i.e., simultaneous) processing of up to four instructions. Therefore, most instructions will seem to be processed during one machine cycle as soon as the pipeline has been filled once after reset.

Pipelining increases the average instruction throughput. In this manual, any execution time specification always refers to the average instruction execution time due to pipelined parallel processing.

The execution time of a sequential and non- sequential instruction flow is mainly given by the instruction fetch from different kind of memories (number of waitstates).

The following pipeline diagram (Table 3-2) shows the continuous execution of instruction under the assumption of a fast Local Memory (0/1 waitstate).

Table 3-2 Sequential instruction execution (local memory, 0/1 waitstate)

Clock Cycle FETCH DECODE EXECUTE WRITE BACK Machine Cycle

I I I I

n-1

n-2

n-3

I I I I

n+1

n-1

n-2

m+1

n+2

n+1

n-1

m+2

n+3

In+2 I In+1 I I

m+3

n+4

n+3

n+2

n+1

m+4

n+6

n+4

n+3

n+2

m+5

The fetch stage fetches instructions from the Local Mem ory (LM) via the 32-bi t LM -Bus. If 16-bit instructions are fetched from the LM-Bus, instructions can be buffered in the 3word FIFO. The fetch stage always prefetches instructions. If the buffer is filled with instructions, LM-Bus accesses are stopped unti l the fetched i nstructions can be loaded into the buffer again.

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Table 3-3 shows the standard unconditional branch (branch taken) instruction pipeline,

assuming a fast local memory (0/1 waitstates)..

Table 3-3

Clock Cycle LM-Address LM-Data 32bit

FETCH DECODE EXECUTE WRITE BACK Machine Cycle

Unconditional branches (LM-Bus, 0/1 waitstate)

n-1

n-2

n-3

branch

n+1==

n-1

n-2

m+1

n+1==

branch

n-1

m+2

I I

a_t

d_t

-ItI

n+1==

branch

m+3

-I

branch

n+1==

m+4

t+1

t+2

m+5

In case of a branch to a 32-bi t target instru ction, w hich is not aligned to a 32- bit addre ss, one additional machine cycle (T1,T2) is required.

Table 3-4 shows a standard conditional branch (branch taken) instruction pipeline,

assuming a fast local memory (0/1 waitstates).

Table 3-4 Conditional branches (LM-Bus, 0/1 waitstate)

Clock Cycle Address Data 32bit

FETCH DECODE EXECUTE WRITE BACK Machine Cycle

n-1

n-2

n-3

n-1

n-2

m+1

n+1==

branch

n+1==

branch

n-1

m+2

n+2

n+1==

branch

n+1==

branch

m+3

I I

a_t

d_t

-I

n+1==

branch

n+1==

branch

m+4

n+1==

branch

m+5

t+1

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Cache Jump Instruction Processing

The C166S incorporates a jump cache to optimize conditional jumps, which are processed repeatedly within a loop. Whenever a jump on cache is taken, the extra time to fetch the branch target instruction can be saved and thus the corresponding cache jump instruction in most cases takes only one (unconditi onal branch) or two (conditiona l branch) machine cycles.

This performance is achieved by the following mechanism: Whenever a cache jump instruction passes through the de code stage of the pi peline for th e first time (and pr ovided that the jump condition is met), the jump target instruction is fetched as usual, causing a time delay of one machine cycle. In con trast to standard branch instructions, however, the target instruction of a cache jump instruction (JMPA, JMPR, JB, JBC, JNB, JNBS) is additionally stored in the cach e after having been fetched.

After each subsequent execution of the same cache jump instruction, the jump target instruction is not fetched from program memory but taken from the cache and immediately injected into the fetch/decode stage of the pipeline (see table below

Table 3-5).

A time-saving jump on cache is always taken after the second and any subsequent occurrences of the same cache jump instruction, unless an instruction that has the fundamental capability of changing the CSP register contents (JMPS, CALLS, RETS, TRAP, RETI), or any standard interrupt has been processed during the period of time between two following occurrences of the same cache jump instruction.

Table 3-5 shows a standard unconditional branch (branch taken and target cached)

instruction pipeline, assuming a fast local memory (0/1 waitstates). .

Table 3-5 Unconditional cached branches (LM-Bus, 0/1 waitstate)

Clock Cycle LM-Address LM-Data 32bit

FETCH DECODE EXECUTE WRITE BACK Machine Cycle

n-1

n-2

n-3

branch

n+1==

n-1

n-2

m+1

n+1==

branch

n-1

m+2

I I

a_t+1

d_t+1Id_t+1

It I

n+1==

branch

m+3

t+1

n+1==

branch

m+4

t+2

t+1

m+5

t+3

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Table 3-6 shows a standard conditional branch (branch taken and target cached)

instruction pipeline, assuming a fast local memory (0/1 waitstates).

Table 3-6 Conditional cached branches (LM-Bus, 0/1 waitstate)

Clock Cycle Address Data 32bit

FETCH DECODE EXECUTE WRITE BACK Machine Cycle

n-1

n-2

n-3

n-1

n-2

m+1

n+1==

branch

n+1==

branch

n-1

m+2

I I

n+2

n+1==

branch

n+1==

branch

m+3

a_t+1

d_t+1Id_t+1

n+1==

branch

n+1==

branch

m+4

t+1

n+1==

branch

m+5

t+2

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3.3.3 ATOMIC and EXTended Instructions

ATOMIC and EXTended instructions (ATOMIC, EXTR, EXTP, EXTS, EXTPR, EXTSR) disable the standard and PEC interru pts and class A traps until the completion of the next sequence of instructions. The number of instructions in the sequence may vary from 1 to 4. The instruction number is code d in the 2-bi t constant field #irang2 and takes values from 0 to 3. The EXTended instructions additionally change the addressing mechanism during this sequence (see instruction description).

ATOMIC and EXTended instructions become active immediate ly, so no additi on al NOP instructions are required. All instructions requiring multiple cycles or hold states for execution are considered as one instruction. ATOMIC and EXTended instructions can be used with any instruction type.

Note: If a class B trap interrupt occurs during an ATOMIC or EXTende d sequence, then

the sequence is terminated, an interrupt lock is removed, and the standard condition is restored before the trap routine is executed. The remaining instructions of the terminated sequence that ar e executed after retur ning fro m the trap routine will run under standard conditio ns.

Note: Certain precautions are required when using nested ATOMIC and EXTended

instructions. There is only one counter to control the length of the sequence, i.e., issuing an ATOMIC or EXTended instruction within a sequence will reload the counter with the value of the new instruction.

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3.3.4 Code Addressing via Code Segment and Instruction Pointer

The C166S provides a total addressable memory space of 16 MBytes. This address space is arranged as 256 segments of 64 KBytes each. A dedicated 24-bit code address pointer is used to access the memories for instruction fetches. This pointer has two parts: An 8-bit Code Segment Pointer (CSP), and a 16-bit offset Instruction Pointer (IP). The concatenation of the CSP and IP results directly in a correct 24-bit physical memory address.

Memory organized in segments

255 254

1 0

FF’0000 FE’0000

01’0000 00’0000

CSP 015 IP

segment offset

0157

1516

023

Figure 3-2 Addressing via the Code Segment- and Instruction Pointers

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The Instruction Pointer IP

This register determines the 16-bit intra-segment address of the currently fetched instruction within the code segment selected by the CSP register. The IP register is not mapped into the C166S’s address space, and thus it is not directly accessible by the programmer. The IP can be modified indirectly by return instructions via the stack. The IP register is updated impli citly by the C166S f or branch instru ctions and after in struction fetch operations.

IP Instruction Pointer (----

1514131211109876543210

(r)(w)h r

,--H) Reset value: 0000

IP 0

Field Bits Type Description IP [15:1] rwh Specifies the intra-segment offset from which the

current instruction is to be fetched; IP refers to the current segment <SEGNR>.

0 [0] r IP is always word-aligned

The Code Segment Pointer CSP

This non-bit-addressable register selects the code segment being used at run-time to access instructions. The lower 8 bits of register CSP select one of up 256 segments of 64 KBytes each, while the higher 8 bits are reserved for future use.

CSP Code Segment Pointer SFR(FE08

1514131211109876543210

00000000 SEGNR

rrrrrrrr r(w)h

The reset value of th e bitfield segnr[1: 0] is product-specific. With a n alternate boot mo de feature, the code execution can be started at different segments afte r reset .

,04H) Reset value: 000x

1) H

Field Bits Type Description SEGNR [7:0] rwh Specifies the code segment from which the current

instruction is to be fetched

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The actual code memory address is generated by di rect extension of the 16-bi t contents of the IP register by the lower byte of the CSP register, as shown in Figure 3-2.

There are two modes: Segmented and non-segmented. The mode is selected with the

SGTDIS bit in the SYSCON register. After reset, the segmented mode is selected.

SYSCON System Control Register SFR (FF12

1514131211109876543210

STKSZ

rw rw rw

ROMS1SGT

ROMENSYS

DIS

CON9

rwh rwh rwh rwh rwh rwh rwh rwh rwh rwh rwh

SYS

CON8

/ 89H) (Reset value: 0xx0H)

SYS

CON7

SYS

CON6

SYS

CON5

SYS

CON4

SYS

CON3

SYS

CON2

SYS

CON1

SYS

CON0

Field Bits Type Description SGTDIS 11 rw Segmentation Disable/Enable Control

0 Segmentation enabled (CSP is saved/restored

during interrupt entry/exit)

1 Segmentation disabled (Only IP is saved/restored)

Note:

For summary of the SYSCON register please refer to Section 3.3.5.

Segmented Mode

The CSP register can be o nly re ad and may no t be w ritten by da ta oper ations. The CSP is modified either directly by the JMPS and CALLS instructions, or i ndirectly via the stack by the RETS and RETI instructions. Upon the accep tance of an interrupt or the execution of a software TRAP instruction, the CSP register is automatically loaded with the segment address of the vector location.

Non-Segmented Mode

In the non-segmented mode, the CSP is fixed to segment 0. It is no longer possible to modify the CSP either directly by the JMPS or CALLS instructions, or indirectly via the stack by the RETS (RETI) instruction. For non-segmented memory mode, the contents of this register are not significant, because all code acce sses are restricted automatically to segment 0.

Note: When segmentation is disabled, the IP valu e is used directly as the 16-bit a ddress.

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3.3.5 The CPU/System Configuration Register SYSCON

This register is used to configure the C166S. It is bit-addressable and provides general system configuration and control functions. The reset value of register SYSCON depends on the state of the configuration inputs during reset.

SYSCON System Control Register SFR (FF12

1514131211109876543210

STKSZ

rw rw rw

ROMS1SGTDISROMENSYS

CON9

rwh rwh rwh rwh rwh rwh rwh rwh rwh rwh rwh

SYS

CON8

Field Bits Type Description

SYSCON0

.....

SYSCON9

....

rwh SYStem CONfiguration

/ 89H) (Reset value: 0xx0H)

SYS

CON7

SYS

CON6

SYS

CON5

SYS

CON4

SYS

CON3

SYS

CON2

SYS

CON1

SYS

CON0

ROMEN 10 rwh Internal ROM ENable (Set according to pin EA during

reset) 0 Internal local memory disabled: Accesses to the Local memory area use the external bus 1 Internal local memory enabled

SGTDIS 11 rw SeGmenTation DISable/enable control

0 Segmentation enabled (CSP is saved/restored

during interrupt entry/exit)

1 Segmentation disabled (Only IP is saved/restored)

ROMS1 12 rw Internal local memory mapping

0 Internal local memory area mapped to segment 0

(00’0000

...00’7FFFH)

1 Internal Local Memory area mapped to segment 1

(01’0000H...01’7FFFH)

STKSZ [15:13] rw System STacK SiZe

Selects the size of the system stack (in the internal DPRAM) from 32 to 1536 words

Note: The CPU SYSCON bits cannot be changed after execution of the EINIT

instruction.

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3.4 Interrupt and Exception Execution

An Interrupt and Exception Handler is responsible for managing all system and core exceptions. There are four different kinds of exceptions that are executed in a similar way:

• Interrupts generated by the InTerrupt Controller (ITC)

• DMA transfers issued by the Peripheral Event Controller (PEC).

• Software traps caused by the TRAP instruction

• Hardware traps issued by faults or specific system states

Normal Interrupt Processing

The CPU temporarily suspends the current program execution and branches to an Interrupt Service Routine (ISR) in order to service an interrupt-requesting device. The current program status [Instruction Pointer (IP), Processor Status Word (PSW), and in segmentation mode, the Code Segment Pointer (CSP)] is saved on the internal system stack. A prioritization scheme with 16 priority levels and with 4/8 sub-levels (4/8 group levels) specifies the order of multiple interrupt-request handling. The maximum number of interrupt requests is 112 (configured in steps of 16), wherein the lowest priority level is reserved for the CPU and cannot be used for interrupts.

Software and Hardware Traps

Trap functions are activated in response to special conditions that occur during the execution of instructions. A trap can also be caused externally by the Non-Maskable Interrupt (N conditions and exceptions that arise during the program execution. Hardware traps always have highest priority and cause immediate system reaction. The software trap function is invoked by the TRAP instruction, which generates a software interrupt for a specified interrupt vector. For all types of traps, the current program status is saved in the system stack.

Interrupt Processing via the Peripheral Event Controller

A faster alternative to normal interrupt processing is servicing an interrupt requesting device by the C166S's integrated PEC. Triggered by an interrupt request, the PEC performs a single-word or byte d ata transfer between any tw o memory locatio ns through one of up to 16 programmabl e PEC service channels. Du ring a PEC transfer, the normal program execution of the CPU is halted. No internal program status information needs to be saved. The same prioritization scheme is used for PEC service as for normal interrupt processing.

MI) pin. Several hardware trap functions are provide d for handling erroneou s

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3.4.1 Interrupt System Structure

The C166S provides up to 112 separate interrupt nodes that may be assigned to 128 arbitration priority levels with 16 interrupt priority groups and 4/8 priorities inside each group. In order to support modular and consistent software design techniques, most sources of an interrupt or PEC request are supplied with a separate interrupt control register and interrupt vector. The control register contains an interrupt request flag, Interrupt Enable (IE) bit, and interrupt priority of the associated source. Each source request is activated by one specific event, dependi ng on the selected oper ating mode of the respective device. In some cases, the multi-source interrupt nodes are incorpor ated for efficient use of system resources. These nodes can be activated by several source requests.

The C166S provides a vectored interrupt system. This system reserves specific vector locations in the memory space for the reset, trap, and interrupt service functions. Whenever a request occurs, the CPU branches to the location that is associated w ith the respective interrupt source. The reserved vector locations build a jump table in the C166S’s address space.

The arbitration winner is sent to the CPU together with its priority level and action request. The CPU triggers the corresponding action, which depends on the required functionality (normal interrupt, PEC etc.) of the arbitration winner.

An action request will be accepted by the CPU if the requesting source has a higher priority than the current CPU priority level, and if interrupts are globally enabled. If the requesting source has a lower (or equal) interrupt level priority, then the requested interrupt stays pending.

3.4.2 Interrupt Arbitration

The C166S interrupt arbitration system can handle interrupt requests from up to 112 sources. Interrupt requests may be triggered either by the C166S peripherals or by external inputs. The “End of PEC” in terrupt for suppor ting enhanced PEC functionality i s connected internally to one of the interrupt request lines.

The arbitration process starts by an enabled interrupt request and stays active for as long as interrupt request is pending. If nothing is pending then the arbitration logic switches to the idle state to save power.

Each interrupt request line is controlled by its interrupt control register xxIC (here and below, ’xx’ stands for the mnemonic of the respective interrupt source). An interrupt request event sets the interrupt request flag to 1 in the corresponding interrupt control register (bit xxIC.xxIR). The interrupt requ est can also be triggered by the softw are if the program sets the respective interrupt request bit. This feature is used by operating systems.

If the request bit has been set and this interrupt request is enabled by the IE bit of the same control register (bit xxIC.xxIE), then an arbitration cycle starts on the next clock

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cycle. However, if an arbitration cycle is currently in progress, the new interrupt request will be delayed till the next arbitration cycle. If an interrupt request (or PEC request) is accepted by the core, the respective interrupt request flag is cleared automatically.

All interrupt requests that are pending at the beginning of a new arbitration cycle are considered simultaneously. Within the arbitration cycle, the arbitration is independent of the actual request time.

C166S uses a two-stage interrupt prioritization scheme for interrupt arbitration, as shown in Figure 3-3.

Interrupt Request

Lines

Arbitration

Control

(Interrupt

Control

Registers)

irq0IC irq1IC

irq112IC

EOPIC

irq0

irq1

irq2

irq112



End of PEC Interrupt (EOPINT) is connected to one of the interrupt request lines. Therefore, only up to 111 interrupt lines are available for peripheral request handling.

Arbitration

Arbitr.

Winner

EOP

irqxirq111

INT

SRCP15



SRCP0 SRCP1

PEC Poin ter

DSTP0 DSTP1

DSTP15

eripheral

(

vent

ontroller (PEC)

Internal Priorization

Internal Interrupt/PEC Handler

C166S CPU

PECSN0 PECSN1

PECSN15

PEC

Control

(PEC

Control

Registers)

PECC0 PECC1

PECC15

PECISNC

ILVL

TRAP

IEN

EPEC

Figure 3-3 Interrupt Arbitration

The first arbitration stage compares up to 128 priority levels of interrupt request lines. The priority level of each request consists of Interrupt priority LeVeL (ILVL) and Group priority LeVeL (GLVL). An interrupt priority level is programmed for each interrupt request line by the 4-bit bitfield ILVL of the respective xxIC register. The group priority level is programmed for each interrupt request line by the 2-bit bitfield GLVL and the group extension bit xxGP of the register xxIC.

Note: All interrupt request sources that are enabled and programmed to the same ILVL

must have different group priority levels. Otherwise, an incorrect interrupt vector may be generated.

In the second arbitration stage, the priority level of the first-stage winner is compared with the priority of the current CPU task. An action request will be accepted by the CPU if the requesting sour ce has a higher priori ty level than t he current CPU priority l evel (bits ILVL of the PSW register), and if interrupts are enabled globally by the globa l IEN flag in

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PSW. The CPU denies all requests in case of a cleared IEN flag. If the requester has a lower or equal priority level than current CPU task, the request stays pending.

Note: Priority level 0000B is the default level of the CPU. Therefore, a request on ILVL

0000

will be arbitrated, but the CPU will never accept an action request on this

level. However, every enabled interrupt request (including all denied interrupt requests - also priority level 0000

requests) triggers a CPU wake-up from idle

state independent of the setting of the global interrupt enable bit PSW.IEN.

Note: The first 16 trap numbers are reserved for the CPU traps. The first usable interr upt

trap number starts with 10

. Therefore, the number of interr upt nodes is limited to

112.

All interrupt control registers are organized identically. The lower 8 bits of an interrupt control register contain the complete interrupt control and status information of the associated source, which is required during one round of prioritization (arbitration cycle). The upper 8 bits of the respective register are reserved. Al l interrupt control registe rs are bit-addressable, and al l bits can be read or wri tten via software. Therefore, each interrupt source can be programmed or modified with just one instruction. When reading the interrupt control registers with instructions that operate with word data types, the upper 8 bits (15...8) will return zeros. Zeros should always be written to these bit positions. The layout of the interrupt control registers shown below is applicable to all xxIC registers.

xxIC Interrupt Control Register bSFR(xxxx

1514131211109876543210

0000000xxGPxxIRxxIE ILVL GLVL

rrrrrrr

rw rwh rw rw

,xxH) Reset value: 0000

Field Bits Type Description xxGP [8] rw Group Priority Extension

Defines the value of high-order group level bit

xxIR

[7] rwh Interrupt Request Flag

0 No request pending 1 This source has raised an interrupt request

xxIE [6] rw Interrupt Enable Control Bit

(individually enables/disables a specific source) 0 Interrupt request is disabled 1 Interrupt request is enabled

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Field Bits Type Description ILVL [5:2] rw Interrupt Priority Level

Highest priority level

... ...

Lowest priority level

GLVL [1:0] rw Group Priority Level

Defines the internal order for simultaneous requests of the same priority.

Bit xxIR supports bit-protection

The arbitration scheme allo ws nesti ng of u p to 15 ISRs of differ ent pr iori ty levels ( level 0 cannot be used; see note above).

Note: When no interrupt request is active, arbitration is stopped to reduce power

consumption.

3.4.3 Interrupt Vector Table

The C166S has a vectored interrupt system. This system reserves the specifi c vector locations in the memory space for the reset, trap, and interrupt service functions. Whenever a request occurs, the CPU branches to the location that is associated w ith the respective interrupt source. This vector position directly identifies the source t hat caused the request.

Note: The Class B hardware traps all share the same interrupt vector. The status flags

in the Trap Flag Register (TFR) are used to determi ne which exception caused the trap. For details, see Section 3.4.5.2 “Hardware Traps”.

The reserved vector locations are assembled into a jump table that is located in the C166S’s address space. The jump table contains the appropriate jump instructions that transfer control to the interrupt or trap service routines. These routines may be located anywhere within the address space. The vector table i s located at the bottom in segment 0 of the address space. Each entry occupies 2 words to provide space for long jumps, except for the reset vector and the hardware trap vectors, which occupy 4 or 8 words.

Each vector location has an offset address to the segment base address (00’0000

) of the vector table. The offset address can be calculated easily. The offset is the trap number shifted by 2.

3.4.4 Interrupt Control Functions in the Processor Status Word

The PSW is divided functionally into 2 parts. The lower byte of the PSW represents the arithmetic status of the CPU ; t he up per byte of the PSW controls th e i nter rupt system of the C166S.

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PSW Processor Status Word SFR(FF10

1514131211109876543210

ILVL IEN

rwh rw rwh

PSW

0 0 0 USR0

rrrrw

,88H) Reset value: 0000

MUL

rwh rwh rwh rwh rwh rwh

EZVCN

Field Bits Type Description ILVL [15:12] rwh CPU Priority Level

Lowest Priority

... ...

Highest Priority

IEN [11] rw Interrupt/PEC Enable Flag (globally)

0 Interrupt/PEC requests are disable d 1 Interrupt/PEC requests are enabled

Note: For a summary of the PSW register, please refer to Section 3.7.6

CPU Priority ILVL defines the current level for the CPU operation, i.e., this bit field reflects the priority level of the routine currently being executed. When the CPU enters an ISR, this bitfield is set to the priority level of the request that is being serviced. The previous PSW is saved in the system stack before ente ring the I SR. To be service d, any interrupt request must have a higher priori ty level than the current CPU priority level. Any request of the same or a lower level will not be acknowledged. The current CPU priority level may be adjusted via software to select interrupt request sources that can be serviced.

PEC transfers do not really interrupt the CPU, but rather “steal” some CPU cycles, so PEC services do not influence the ILVL field in the PSW.

Hardware traps set the CPU level to the maximum priority (i.e., 15). Therefore, no interrupt or PEC requests will be acknowledged while an exception trap service routine is executed.

The TRAP instruction does not change the CPU level, so software trap service routines may be interrupted by higher-level requests.

Interrupt ENable flag IEN globally enables or disables interrupts and PEC operations. When IEN is cleared, no n ew interrupt requests are accepted by the CPU after IEN was set to 0. However, the re quests that have alre ady entered the pipel ine will be completed. If IEN is set to 1, all interrupt sources are globally enabled.

Note: To generate requests, interrupt sources must be also enabled by the IEN bits in

their associated control registers.

Note: Traps are non-maskable and, therefore, they are not controlled by the IEN bit.

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3.4.4.1 Saving the Status during Interrupt Service

Before an operating system or ITC can actuall y service a task switch request or interrupt, the CPU must save the current task status. The C166S saves the CPU status (PSW) along with the return address in the system stack. The return address defines the point where the execution of the interrupted task is to be resumed after returning from the service routine. This return address is specified by the IP and, in the case of a segmented memory mode, also by the CSP. Bit SGTDIS in the SYSCON register defines which mode is used and, therefore, controls how the return address is stored.

In the case of non-segmented mode, the system stack stores the PSW first and then the IP. In the segmented mode, PSW is followed by CSP and the IP. This order optimizes the use of the system stack if segmentation is disabled.

The CPU priority field (ILVL in PSW) is updated with the priority of the interrupt request that is to be serviced, so the CPU now executes on the new level.

Status of

Interrupted Task

PSW

CSP

1. System Stack before Interrupt Entry

2. System Stack after Interrupt Entry (Unsegmented)

3. System Stack after Interrupt Entry (Segmented)

Figure 3-4 Task Status saved on the System Stack

After accepting an interrupt request, the C166S sends an acknowledgement to the ITC that the requested interrupt i s being serviced. The vector associa ted wi th the requesti ng source is loaded into the IP and CSP, and the first instruction of the service routine is fetched. All other CPU resources such as data pa ge pointers and the context po inter are not affected.

When the CPU returns from the ISR [RETurn from Interrupt (RETI) is executed], the status information is “popped” from the system stack in reverse order. The status information contents depend on the SGTDIS bit value.

3.4.4.2 Context Switching

An ISR usually saves all the registers it uses on the stack, and restores them before returning. The more registers a routine uses, the more time is wasted by saving and restoring.

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The C166S makes it possible to switch the complete register bank of CPU registers (GPRs) with a single instruction, so the service routine executes with in its own separate context. The instruction “SCXT CP, #New_Bank” pushes the contents of the Context Pointer (CP) into the system stack and loads the CP with the immediate value “New_Bank”. The new CP value sets a new register bank. The service routine may now use its own registers. This register bank is preserved when the service routine is terminated, i.e., its contents are available for the next call. Before returning (RETI), the previous CP is simply popped from the system stack, which returns the registers to the original register bank.

Central Processing Unit

Note: Resources that are used by the interrupting program must eventually be saved

Pointers (DPP) and the registers of the multiply and divide unit.

Note: The first instruction following the SCXT CP,... instruction must not use a GPR.

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3.4.5 Traps

3.4.5.1 Software Traps

The TRAP instruction is used to cause a software call to an ISR. The trap number that is specified in the operand field of the trap instruction determines which vector location of the vector table will be used.

The TRAP instruction’s eff ect is similar to that of an interru pt request that uses the same vector. PSW, CSP (in segmentation mode), and IP are pushed into the system stack and then a jump is taken to the specified vector location. When a software trap is executed, the CSP for the trap service routine is loaded with segment address 0. No Interrupt Request flags are affected by the TRAP instruction. The ISR called by a TRAP instruction must be terminated with a RETI instruction to ensure correct operation.

Note: The CPU priority level is not modified by the TRAP instruction, so the service

routine is executed with the same pr iority level as the interrupt task. Ther efore, the service routine entered by the TRAP instruction can be interrupted by other traps or by higher priority interrupts, othe r than when triggered by a real hardware event.

3.4.5.2 Hardware Traps

Hardware traps are issued by faults or specific system states that occur during runtime (not identified at assembly time). The C 166S d isti nguishes ei ght diff ere nt har dwa re tr ap functions. When a hardware trap con ditio n has been de tected, the CP U branche s to the trap vector location for the re spective trap con dition . The instruction that caused t he trap event is either completed or canceled before the trap-handling routine is entered.

Hardware traps are not-maskable and always have a higher priori ty than any other CPU task. If several hardware trap conditions are detected w ithin the same machine cycle, the highest-priority trap is serviced. In the case of a hardware trap, the injection unit injects a TRAP instruction into the pipeline. The TRAP instruction performs the following actions:

• Push PSW, CSP (in segmented mode) and IP onto the system stack

• Set CPU level in the PSW register to the highest possible priority level, which disables all interrupts and DMA transfers

• Branch to the trap vector location specified by the trap number of the trap condition

The eight hardware functions of the C166S are divided in two Classes. Class A traps are: – External NMIs

– Stack overflow – Stack underflow

These traps share the same trap priority, but have an individual vector address. Class B traps are:

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– Undefined opcode – Protection fault – Illegal word operand access – Illegal instruction access – Illegal external bus access

The Class B traps share the same interrupt node and interrupt vector. The bitaddressable Trap Flag Register (TFR) allows a trap service routine to identify the trap that caused the exception.

The Trap Flag Register TFR

Each trap function is indicated by a separate request flag. Wh en a hardware trap occurs, the corresponding request flag in register TFR is set to 1.

TFR Trap Flag Register SFR(FFAC

1514131211109876543210

,D6H) Reset value: 0000

NMI

rwh rwh rwhrrrr

STKOFSTK

00000

UND OPC

rwh

Field Bits Type Description NMI

[15] rwh Non-Maskable Interrupt flag

0 No non-maskable interrupt detected 1 Non-maskable interrupt detected

STKOF

[14] rwh STacK OverFlow flag

0 No stack overflow event detected 1 Stack overflow event detected

STKUF

[13] rwh STacK UnderFlow flag

0 No stack underflow event detected 1 Stack underflow event detected

UNDOPC

[7] rw h UNDefined OPCode

0 No undefined opcode event detected 1 Undefined opcode event detected

PRTFLT

[3] rwh PRoTection FauLT

0 No protection fault event detected 1 Protection fault event detected

000

rrr

PRT FLT

rwh rwh rwh rwh

ILL

OPA

ILL

INA

ILL

BUS

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Field Bits Type Description ILLOPA

[2] rwh ILLegal word OPerand Access

0 No illegal word operand access event detected 1 Ilegal word operand access event detected

ILLINA

[1] rwh ILLegal INstruction Access

0 No illegal instruction access detected 1 A branch to an odd address has been attempt.

ILLBUS [0] rwh ILLegal External BUS Access

0 No illegal external bus access detected 1 An external access has been attempted wi th no bus defined.

This bit supports bi t protection

Note: The trap service routine must clear the respective trap flag. Otherwise, a new trap

will be requested after exiting the service routine. Setting a trap request flag by software causes the same effects as if it had been set by hardware.

The reset functions (hardware, software, watchdog) may be also regarded as a type of trap. Reset functions have the highest trap priority ( trap pr ior ity IV). The Debu g tr ap ha s the second-highest trap priority (trap priority III) , followed by the third-highest trap priority traps, Class A traps (trap priority II), and then by Class B traps (trap priority I). So the Debug trap can interrupt a Class A and B trap and a Class A trap can interrupt a Class B trap. The Debug trap is a special ki nd of interr upt-ser vice channel f or debug pu rpose s whose priority lies between the Class A trap and the reset function. This allows the debugger to interrupt hardware traps and hardware interrupts

Exception Condition Trap

Flag

Trap Vector

Trap Number

Trap Priority

Reset Functions:

Hardware Reset Software Reset Watchdog Timer Overflow

Debug Trap DEBUG DEBTRAP 08

RESET RESET RESET

00 00 00

H H H

IV IV IV

III

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Exception Condition Trap

Flag

Trap Vector

Central Processing Unit

Trap Number

Trap Priority

Class A Hardware Traps:

Non-Maskable Interrupt STacK OverFlow STacK UnderFlow SOFTware BReaK

NMI STKOF STKUF SOFTBRK

NMITRAP STOTRAP STUTRAP SBRKTRAP

02 04 06 08

H H H H

II.3 II.2 II.1 II.0

Class B Hardware Traps:

UNDefined OPCode PRoTection FauLT ILLegal word Operand Access ILLegal INstruction Access ILLegal external BUS access

UNDOPC PRTFLT ILLOPA ILLINA ILLBUS

BTRAP BTRAP BTRAP BTRAP BTRAP

0A 0A 0A 0A 0A

H H H H H

I I I I I

Class A Trap

Class A traps are generated by the high-priority system NMI or by special CPU events such as a software break, or a stack overflow or underflow event. Class A traps are not used to indicate hardware failures. After a Class A event, a dedicated service routine is called to react to the events. Each Class A trap has its own vector location in the vector table. After finishing the service routine, the remainder of the instruction flow must be executed correctly. This explains why Class A traps cannot interrupt atomic/extend sequences.

In case of an atomic/extend sequence, the execution continues until sequence completion. Upon completio n, the IP of the instruction foll owi ng th e l ast execute d one i s pushed onto the stack.

If more than one Class A trap occurs at a same time, they are prioritized internally. The NMI trap has the highest priority, and the stack underflow trap has the lowest.

Note: When two different Class A traps occur simultaneously, both trap flags are set.

The trap with the higher priority is executed. After return from the service routine, the IP is popped from the stack and immediately pushed again because of the other pending Class A trap (unless the second trap flag in TFR has been cleared by the first trap service routine).

External NMI Trap (NMI)

Whenever a high-to-low transition on the dedicated NMI

is detected, the NMI flag in register TFR is set , and the CPU will enter the NMI trap routin e. The IP value pushed on the system stack is the address of the instruction following the one after which normal processing was interrupted by the NMI trap.

Note: The NMI is sampled with every CPU clock cycle to detect transitions.

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STacK OverFlow Trap (STKOF)

Whenever the stack pointer SP is decremented to a value less than the value in the stack overflow register STKOV, the STKOF flag in register TFR is set and the CPU will enter the stack overflow trap routine. Which IP value will be pushed onto the system stack depends on which operation caused the decrement of the SP. When an implicit decrement of the SP is made through a push or call instruction, or upon interrup t or trap entry, the IP value pushed is the address of the following instruction. When the SP is decremented by a subtract instruction, the IP value pushed represents the address of the first or second instruction after the instruction following the subtract instruction.

For recovery from stack overflow, there must be enough excess space on the stack for saving the current system state (PSW; IP; and, in segmented mode, the CSP) twice. Otherwise, a system reset should be generated.

STacK UnderFlow Trap (STKUF)

Whenever the stack pointer is incremente d to a value greate r than the value i n the stack underflow register STKUN, the STKUF flag is se t in register TFR and the CPU wil l enter the stack underflow trap routine. Again, which IP value will be pushed onto the system stack depends on which operation caused the increment of the SP. When an implicit increment of the SP is made through a POP or return instruction , the IP value pushed i s the address of the following instruction. When the SP is incremented by an add instruction, the pushed IP val ue repr esents th e address of the first or second instructi on after the instruction following the add instruction.

Central Processing Unit

Class B Trap

Class B traps are generated by unrecoverable hardware failures. In case of hardware failure, the CPU must immediately start a failure service routine. Class B traps can interrupt an atomic/extend sequence. After finishing a Class B service routine, the

interrupted instruction flow cannot be restored.

Note: If a Class A trap and a Class B occur simultaneously, both trap flags are set. If

this occurs during execution of an atomic/extend sequence, then the presence of the Class B trap breaks the protection of atomi c/extend o perations, and the Class A trap will be executed immediately without waiting for the sequence completion. After return from the service routine, the IP is popped from the system stack and immediately pushed again because of the other pending Class B trap. In this situation, the interrupted instruction flow cannot be restored.

All Class B traps have the same trap prior ity (tra p pri ority I). When severa l Class B trap s are active at the same time, the corresponding flags in the TFR are set, and the trap service routine is entered. Since all Class B traps have the same vector, the priority of service of Class B that occur simultaneously is determined by the software in the trap service routine.

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During the execution of a Class A trap service routine, any Class B trap will not be serviced until the Class A trap service routine is exited with a RETI instruction. In this case, the Class B trap condition is stored in the TFR but the IP value of the instruction that caused this trap will be lost.

UNDefined OPCode Trap (UNDOPC)

When the instruction currently decoded by the CPU does not contain a valid C166S opcode, the UNDOPC flag is set in the TFR, and the CPU enters the undefined opcode trap routine. The IP value pushed onto the system stack is the address of the instruction that caused the trap.

This can be used to emulate unimplemented instructions. The trap service routine can examine the faulting instruction to decode operand s for unim pl eme nted opcodes based on the stacked IP. In order to resume processing, the stacked IP value must be

incremented by the size of the undefined instruction, which is determined by the user,

before a RETI instruction is executed.

Central Processing Unit

PRoTection FauLT Trap (PRTFLT)

DISWDT, EINIT, IDLE, PWRDN, SRST, and SRVWDT are protected instructions. Whenever one protected instruction is executed and the protection is broken, the PRTFLT flag in register TFR is set and the CPU enters the protection fault trap routine. The IP value pushed onto the system stack for th e protection fault t rap is the address of the instruction that caused the trap.

ILLegal word OPerand Access Trap (ILLOPA)

Whenever a word operand r ead or write access i s attempted to an odd byte address, the ILLOPA flag in register TFR is set, and the CPU enters the illegal word operand access trap routine. The IP value pushed onto the system stack is the address of the instruction following the one that caused the trap.

ILLegal INstruction Access Trap (ILLINA)

Whenever a branch is made to an odd byte address, the ILLINA flag in register TFR is set and the CPU enters the illegal instruction access trap routine. The IP value pushed onto the system stack is the illegal odd target address of the branch instruction.

ILLegal external BUS access Trap (ILLBUS)

Whenever the CPU requests an exter nal instructi on fetch or a data read or a data write, and no external bus configuration has been specified, the ILLBUS flag in register TFR i s set and the CPU enters the illegal bus access trap ro utine. The IP value pushe d onto the system stack is the address of the instruction following the one that caused the trap.

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3.4.6 Peripheral Event Controller

The Peripheral Event Controller (PEC) “decides” which CPU action is required to manage an interrupt request. It may be either normal interrupt service, or fast data transfer between two memory locations. The C166S PEC controls up to sixteen data transfer channels.

If a normal interrupt is requested, the CPU temporarily suspends the current program execution and branches to an Interrupt Service Routine (ISR). The current program status and context must be preserved.

If a PEC channel is se lected for servicin g an interrupt re quest, a single w ord or byte data transfer between any two memory locations is to be performed. During a PEC transfer, the normal program execution o f the CPU is halted for just 1 machine cycles. No internal program status information needs to be saved. The PEC transfer is the fastest possible interrupt response. In many cases, a PEC transfer is sufficient to service the peripheral request (serial channels, for example).

The PEC channels can perform the following actions:

• Byte or word transfer

• Continuous data transfer

• PEC channel-specific interrupt request upon data transfer completion; or for all

channels a common End of PEC (EOP) interrupt for enhanced handling

• Automatic increment of source or destination pointers

• Channel linking of two PEC channels

fast

Note: PEC transfer is executed if its priority level is h igher than current CPU priority le vel.

The number of PEC channels depends on the configuration of the product. Please refer to the product User Manual.

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3.4.6.1 The PEC Source and Destination Pointers

The PEC channels’ source an d destination pointers spe cify the locations betwe en which the data is to be moved. All pointers are 24 bits wide. The 24-bit source addr ess is stored in the internal DPRAM location SRCPx (lower 16 bits of address) and in the low byte of register PECSNx (highest 8 address bits).

PECSNx

SRCSNx DSTSNx

8 7

SRCPx

015

DSTPx

015

Source Pointer

23 0

Segment Address Segment Offset Segment Address Segment Offset

16 15 16 15

'DWD7UDQVIHU

Destination Pointer

x = 15...0, depending on PEC channel number

Figure 3-5 PEC Pointer Address Handling

The 24-bit destination address i s sto red in the D PRAM l ocati on DSTPx (l ow er 16 bi ts of address) and in the high byte of register PECSNx (highe st 8 address bits). Only the lower 16 bits of the PEC address pointers (segment offset) can be modified (incremented) by the PEC transfer mechanism. The highest 8 bits , w hich repr esent th e se gmen t numb er, are not modified by hardware. Therefore, the PEC pointers may be incremented within the address space of one segment and may not cross the segment border. If the offset address pointer has a value of FFFF

in the case of byte transfers (BWT = 1) or FFFE

in the case of word transfers (BW T = 0), the next i ncrem ent wil l l ead to an over fl ow. No explicit error event is generated by the system in case of address pointer(s) overflow; therefore, the user must prevent this condition from occurring.

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Note: If a word data transfer is selected for a specific PEC channel (i.e. BWT = 0), the

respective source and destination pointers must both conta in a valid word address that points to an even byte boundary. Otherwise, the Illegal Word Access trap will be invoked when this channel is used.

SRCPx PEC Source Pointer DPRAM(

1514131211109876543210

SRCPx

rwh

) Reset value: 0000

H,H

Field Bits Type Description SRCPx [15:0] rwh Source Pointer Address of Channel x

Source Address bits 15-0

DSTPx PEC Destination Pointer DPRAM(

1514131211109876543210

DSTPx

rwh

) Reset value: 0000

H,H

Field Bits Type Description DSTPx [15:0] rwh Destination Pointer Address of Channel x

Destination Address bits 15-0

Table 3-7 DPRAM Addresses of PEC Source and Destination Pointer

Pointer Address Pointer Address Pointer Address Pointer Address

DSTP7 00’FCFE DSTP6 00’FCFA DSTP5 00’FCF6 DSTP4 00’FCF2 DSTP3 00’FCEE DSTP2 00’FCEA DSTP1 00’FCE6 DSTP0 00’FCE2

H H H

SRCP7 00’FCFC SRCP6 00’FCF8 SRCP5 00’FCF4 SRCP4 00’FCF0 SRCP3 00’FCEC SRCP2 00’FCE8 SRCP1 00’FCE4 SRCP0 00’FCE0

H H H H

DSTP11 00’FCDE DSTP10 00’FCDA DSTP9 00’FCD6 DSTP8 00’FCD2 DSTP15 00’FCCE DSTP14 00’FCCA DSTP13 00’FCC6 DSTP12 00’FCC2

H H H

SRCP11 00’FCDC SRCP10 00’FCD8 SRCP9 00’FCD4 SRCP8 00’FCD0 SRCP15 00’FCCC SRCP14 00’FCC8 SRCP13 00’FCC4 SRCP12 00’FCC0

H H H H

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PECSNx PEC Segment Pointer SFR(

1514131211109876543210

DSTSNx SRCSNx

rw rw

) Reset value: 0000

H,H

Field Bits Type Description DSTSNx [15:8] rw Destination Pointer Segment Address of C hann el

x Destination Address bits 23-16

SRCSNx [7:0] rw Source Pointer Segment Address of Channel x

Source Address bits 23-16

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3.4.6.2 PEC Control Registers

Each PEC channel is controlled by the respective PEC channel Control register (PECCx) and a set of source and destination pointers (SRCPx, DSTPx and PECSNx), where “x” stands for the PEC channel numb er. Th e PECCx r egisters contr ol the arbitrati on prior ity level assigned to the PEC channels and specifies the action to be performed.

PECCx PEC Channel Control Register SFR(

1514131211109876543210

EOP

INT

rw rw rw rw rw rw rwh

PLEV CL INC BWT COUNT

Field Bits Type Description PT [15] rw Transfer Mode

0 Short Transfer Mode 1 Long Transfer Mode

EOPINT [14] rw End of PEC Interrupt Selection

0 EOP interrupt with the same level as the PEC transfer is triggered 1 EOP interrupt is serviced by a separate interrupt node with programmable interrupt level (EOPIC) and interrupt sharing control register (PECISNC)

PLEV [13:12] rw PEC Level Selection

This bitfield controls the PEC chann el assignment to an arbitration priority level. (see section below)

) Reset value: 0000

H,H

CL [11] rw Channel Link Control

0 PEC channels work independently 1 Pairs of channels are linked together

INC [10:9] rw Increment Control

(Modification of source and destination pointer after PEC transfer) 00 No modification 01 Increment of destination pointer DSTPx by 1 (BWT = 1) or by 2 (BWT = 0) 10 Increment of source pointer SRCPx by 1 (BWT = 1) or by 2 (BWT = 0) 11 Reserved

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Field Bits Type Description BWT [8] rw Byte / Word Transfer Selection

0 Transfer a word 1 Transfer a byte

COUNT [7:0] rwh PEC Transfer Count

Counts PEC transfers and influences the channel´s action

The long transfer m ode is an op tional mode. If the product does not supp ort the long tran sfer mode for this specific PEC channel, the PT-bit is hardwired to zero. See Section 3.4.6.3 and Section 3.4.6.4

See Section 3.4.6.7

See Section 3.4.6.6

See Section 3.4.6.3

The Byte/Word Transfer bit (BWT) of the PECCx register selects whether a byte or a word is to be moved during a PEC service cycle, and defines an increment step size for the pointer(s) to be modified.

The Increment Control Field (INC) of the PECCx register defines when either one or both of the PEC pointers have to be incremented after the PEC transfer. If the pointers are not to be modified (INC= 00

), the respective channel will alw ays move data from the

same source to the same destination.

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3.4.6.3 Short Transfer Mode

If the short transfer mode is enabled by the PT flag (PT = 0) in the PEC control register PECCx, the PEC Transfer Count Field (COUNT) of the PECCx controls directly the action of the respective PEC channel. The contents of the bitfield COUNT may specify a certain number of PEC transfers, unlimited transfers, or no PEC service at all.

a) If the PEC transfer counter (COUNT) value is set to 00

requests are processed instead of PEC data transfers, and the corresponding PEC channel remains idle.

b) Continuous data transfers are selected by setti ng the bitfield COUNT to FF

case, COUNT is not decremented by the transfers, and the respective PEC channel can serve unlimited number of PEC requests until it is modified by the program.

c) If the bitfield COUNT is set to service a specified number of requests by the

respective PEC channel, it is decremente d with each PEC transfer, and the request flag is cleared to indicate that the request has been serviced. When COUNT reaches 00

it activates the ISR that has the same priority level (EOPINT = 0), or

triggers the EOP ISR with a different priority level (EOPINT = 1). When COUNT is decremented from 01

to 00H after a data transfer, the request flag will be cleared

if EOPINT is set to 1. If EOPINT is 0, the request flag will not be cle ared and another interrupt request will be generated on the same priority level. The respective PEC channel remains idle, and the associated ISR is activated instead of PEC transfer, because COUNT contains the 00

value.

, the normal interrupt

. In this

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3.4.6.4 Long Transfer Mode

Central Processing Unit

If the long transfer mode is enabled by the PT flag (PT = 1) in the PEC control register PECCx, the PEC Transfer Count Field (COUNT2) of the PECXCx register directly controls the action of the respective PEC channel.

PEC Extended Count Register PECXC0/2/4/6 SFR (

1514131211109876543210

COUNT2

rwh

) (Reset value: 0000H)

H,H

Field Bits Type Description COUNT2 [15:0] rwh PEC Extended (Long) Transfer Count

PEC transfer count extension (see table below)

The long transfer mode is only available for PEC channels with an even PEC number.

Note: The channel link mode is indepe ndent of the long tr ansfer mode. Both mo des can

be combined.

Note: The PEC Transfer Count Field (COUNT) of the PECCx register must be set to

zero.

Note: Crossing of segment boundaries is not checked during data transfers with long

transfer count, and is not supported. A wrap around occurs when reaching the segment boundary .

The contents of the bitfield COUNT2 may specify a certain number of PEC transfers or no PEC service at all. The 16-bit transfer counter permits servicing up to 65536 byte transfers or up to 32768 word transfers.

a) If the PEC transfer counter COUNT2 value is set to 0000

, the normal interrupt

requests are processed instead of PEC data transfers, and the corresponding PEC channel remains idle.

b) If the bitfield COUNT2 is set to service a specified number of requests by the

respective PEC channel, it is decremented with each PEC tr ansfer and the request flag is cleared to indicate that the request has been serviced. When COUNT2 reaches 0000

, it activates the ISR that has the same priority level (EOPINT = 0),

or triggers the EOP ISR wit h a different prior ity level (EOPIN T = 1). When COUN T2 is decremented from 0001

to 0000H after a data transfer, the request flag will be

The long transfer mode is an optional mode for PEC channels with an even number. Please refer to the product User Manual.

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cleared if EOPINT is set to 1. If EOPINT is 0, the request flag will not be cleared and another interrupt request will be generated on the same priority level. The respective PEC channel remains idle and the associated interrupt servi ce routine is activated instead of PEC transfer, because COUNT2 contains the 0000

value.

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3.4.6.5 Channel Link Mode for Data Chaining

Channel linking, if enabled, links two channels together to serve the data transfer requests of one peripheral. The whole data transfer (for example a message) is divided into separately-controlled block tran sfers. The two PEC channels that are linked together handle chained block transfers alternately with one another. At the end of a data block transfer controlled by one PEC channel, the other (linked) PEC channel is started automatically to continue the t ransfer w i th th e next data b lo ck. Channel linking and data (block) chaining are supported within pairs of PEC channels (channels 0&1, 2&3, 4&5 etc.). Each data block is controlled by one PEC channel of the channel pair.

Channel linking is enabled if the Channel Link (CL) control bits of both PEC channels are set to 1 in their PECCx registers . The data transfer of linked channels must always be started always with the even numbered channel of the channel pair.

If in channel link mode the channel’s data block is completely transferred, the PEC service request processing is automatically switched to the other PEC channel of the pair. CL of the previously active PEC channel is then reset.

Every channel toggle is indicated to CPU by means of an EOP interrupt. This makes it possible to set up multiple buffers for PEC transfers by changing pointer and count values of one channel while the other channel is active. Inside the EOP interrupt, the Channel Link Control bit CL must be set again before the channel is reactivated or the channel link mode is finished.This EOP in terrupt is requested, indi cated, and enab led in the respective PEC Interrupt Subnode Control Register (PECISNC or PECXISNC).

Thus, all EOP interrupts are contr olled with the one EOP interrupt control register EOPIC and therefore with the same interrupt priority level. This service request node requests the CPU in case of one or more pending EOP interrupt requests if t he respective enable control bit(s) are set in the according subn ode control register and in the interrupt control register EOPIC.

If CL of the previous PEC channel is set to zero and the count field (COUNT=0 or COUNT2=0, dependent on the mode) of the active channel is zero as well, the whole data transfer is finished and the channel l ink inter rupt r epresents a term ination i nterr upt, the End of PEC interrupt.

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The channel link feature is supported for all PEC channels, including the new PEC channels 8-15. The following table shows the channels that can be linked together and the channel numbers required to start transfers via linked channels.

Table 3-8 PEC Channels That Can Be Linked Together

Linked PEC Channels Linked

PEC

Channel

channel 0 channel 1 channel 0 channel 8 channel 9 channel 8 channel 2 channel 3 channel 2 channel 10 channel 11 channel 10 channel 4 channel 5 channel 4 channel 12 channel 13 channel 12 channel 6 channel 7 channel 6 channel 14 channel 15 channel 14

The two PEC control registers of a pair are linked to one interrupt control register, whereby in this IC register only the even-numbered PEC channel is indicated with the priority/group bits.

PEC

Channel

PEC

Start

Channel

Linked PEC Channels Linked

PEC

Channel

Central Processing Unit

PEC

Start

Channel

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3.4.6.6 PEC Channels Assignment and A rbitration

The PEC channels can be assigned to arbitration priority levels. All requests with interrupt priority levels 8 to 15 can be associated wi th the PEC functionali ty (up to a total of sixteen PEC channels). The following formula shows how to program the bitfield PECCx.PLEV to set up a link to a certain i nterrupt priority l evel and a group prior ity level.

PEC channel: x = (x.3,x.2,x.1,x.0) linked to Interrupt priority level: (1, ~PLEV.1, ~PLEV.0, x.2) Group priority level: (x.3, x.1, x.0) [3-1]

The following table lists all possible combinations:

Table 3-9 PEC interrupt level control with PLEV bits in PECCx registers

Priority Level PEC Channel Selection (x)

Interrupt Level

ILVL3-0

Group Level

xxGP, GLVL1,0

PLEV[1,0]=00PLEV[1,0] =01PLEV[1,0] =10PLEV[1,0] =

15 7-4 15-12 - - 15 3-0 7-4 - - 14 7-4 11-8 - - 14 3-0 3-0 - - 13 7-4 - 15-12 - 13 3-0 - 7-4 - 12 7-4 - 11-8 - 12 3-0 - 3-0 - 11 7-4 - - 15-12 11 3-0 - - 7-4 10 7-4 - - 11-8 10 3-0 - - 3-0 -

9 7-4 - - - 15-12 93-0---7-4 87-4---11-8 83-0---3-0

All interrupt requests that are not assigned to a PEC channel go directly to the interrupt handler.

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3.4.6.7 Programmable End of PEC Interrupt Level

The programmable EOP interrupt supports PEC transfers, which need a high priority level for the transfer request, and which do not need the same priority level for the termination interrupt. One dedi cated service request node with a prog rammable interrupt level is shared among all PEC channels. This service request node is controlled by the EOPIC interrupt control register.

EOPIC Interrupt Control Register bSFR(xxxx

1514131211109876543210

0000000xxGP

rrrrrrr

The EOPIC register is assigned to one of the 64 interrupt control registers. The assignment is product specific.

ILVL GLVL

,xxH)

EOPIREOP

rw rwh rw rw

Reset value: 0000

Field Bits Type Description xxGP [8] rw Group Priority Extension

Defines the value of high order group level bit

EOPIR

[7] rwh Interrupt Request Flag

0 No request pending 1 his source has raised an interrupt request

EOPIE [6] rw Interrupt Enable Control Bit

0 Interrupt request is disabled 1 Interrupt request is enabled

ILVL [5:2] rw Interrupt Priority Level

Highest priority level

... ...

Lowest priority level

GLVL [1:0] rw Group Priority Level

Highest priority level

... ...

Bit xxIR supports bit-protection

Lowest priority leve

The Register PECISNC and PECXISN contain flags of the EOP interrupt node. This node is used when the en hanced End of PEC in terrupt feature i s invoked and con trol b it EOPINT is set to 1 in the corresponding PECCx.

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PECISNC PEC Interrupt Sub Node Control SFR(

1514131211109876543210

C7IR C7IE C6IR C6IE C5IR C5IE C4IR C4IE C3IR C3IE C2IR C2IE C1IR C1IE C0IR C0IE

rwh rw rwh rw rwh rw rwh rw rwh rw rwh rw rwh rw rwh rw

) Reset value: 0000

H,H

PECXISNC PEC Interrupt Sub Node Control SFR(

1514131211109876543210

C15IRC15IEC14IRC14IEC13IRC13IEC12IRC12IEC11IRC11IEC10IRC10IEC9IRC9IEC8IRC8

rwh rw rwh rw rwh rw rwh rw rwh rw rwh rw rwh rw rwh rw

) Reset value: 0000

H,H

Field Bits Type Description CxIR 15, 13,

11, 9, 7, 5, 3, 1

rwh Interrupt Sub Node Request Flag of PEC Channel

1) 2)

x 0 No special EOP interrupt request is pending for PEC channel x 1 PEC channel x has raised an EOP interrupt request

CxIE 14, 12,

10, 8, 6, 4, 2, 0

rw Interrupt Sub Node Enable Control Bit

of PEC Channel x

1) 3)

(individually enables/disables a specific source) 0 EOP interrupt request of PEC channel x is disabled 1 EOP interrupt request of PEC channel x is enabled

x = 15...0

NOTE: The EOP sub-node in terrupt re quest flags are n ot cle ared by hardw are when e ntering t he ISR (in terrupt h as been accepted by the CPU), unlike the interrupt request flags of the interrupt nodes (request flags xxIC.xxIR). The ISR has to check the request flags and to clear them before executing the RETI instructi on.

It is recommended that you clear an interrupt request flag (CxIR) before setting the respect ive enable flag (CxIE). Otherwise, pending former requests will immediately trigger an interrupt request after setting the enable bit.

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3.5 Using General-Purpose Registers

The C166S uses several banks of 16 dedicated General Purp ose Re gister s (GPRs) R0, R1, R2... R15 that can be accessed in one CPU cycle. The GPRs are the working

registers of the Arithmetic and Logic Units (ALU) and may also serve as address pointers in indirect addressing modes.

Several banks of GPRs are memory-mapped. The banks of these GPRs are located in the DPRAM. One bank uses a block of 16 consecutive words. A Context Pointer (CP) register determines the base address of the currently selected bank.

The C166S can switch the complete GPR bank with a single instruction for time-critical tasks. After switching, the new task is executed within its own separate context.

Internal DPRAM

(CP)+30 (CP)+28

16-Bit Context Pointer

…

(CP)+2 (CP)

Figure 3-6 Register Bank Selection via Register CP

There are 3 different ways to access the GPRs: Short 4-bit GPR addresses (mnemonic: Rw or Rb) specify an address relative to the

memory location pointed to by the contents of the CP register , i.e., the base of content s of the current register bank. Both byte- wise and wor d- wise G PR accesses are p ossible. The short 4-bit GPR address is logically added to the contents of register CP if a byte (Rb) GPR address is specified, or multipl ied by two and th en added to C P if a w ord (Rw) GPR address is specified (see Figure 3-7).

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Note: If GPRs are used as indirect address pointers, they are always accessed word-

wise.

For some instructions, only the first 4 GPRs (R0, R1, R2 and R3) ca n be used as indirect address pointers. These GPRs are specified via short 2-bit GPR addresses. The physical address calculation is identical to the one for the short 4-bit GPR addresses.

Short 8-bit register addresses (mnem onic: reg or bitoff) within a range from F0

to FF

interpret the four least-significant bits as a short 4-bit GPR address, while the four most significant bits are ignored. The physical GPR address is calculated in a similar fashion as the short 4-bit GPR addresses. For single -bit GPR accesses, the GPR’ s word address is calculated in the same way. The accessed bit position within the word is specified by a separate additional 4-bit value.

Specified by reg or bitoff

12-Bit Context Pointer

1 011

1111

4-Bit GPR Address

Internal

For byte GPR accesses

For word GPR

accesses

Must be within the internal CoreRAM area

Core-RAM

GPRs

Figure 3-7 Implicit CP Use by logical Short GPR Addressing Modes

24-Bit memory addresses within a range from (CP)+0 to (CP)+30 can be used to

access GPRs directly. Both byte and word GPR accesses are possible. The 24-bit memory address is generated according to the rules for long- and indirect-addressing modes (Section 3.6.2).

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Table 3-10 Addressing modes to Access Word-GPRs Name Physical

Address

R0 (CP)+0 F0 R1 (CP)+2 F1 R2 (CP)+4 F2 R3 (CP)+6 F3 R4 (CP)+8 F4 R5 (CP)+10 F5 R6 (CP)+12 F6 R7 (CP)+14 F7 R8 (CP)+16 F8

8-Bit Address

H H H H H H H H H

4-Bit Address

Description Reset

General-Purpose word Register R0 UUUU General-Purpose word Register R1 UUUU General-Purpose word Register R2 UUUU General-Purpose word Register R3 UUUU General-Purpose word Register R4 UUUU General-Purpose word Register R5 UUUU General-Purpose word Register R6 UUUU General-Purpose word Register R7 UUUU General-Purpose word Register R8 UUUU

Central Processing Unit

Value

H H H H H H H H H

R9 (CP)+18 F9 R10 (CP)+20 FA R11 (CP)+22 FB R12 (CP)+24 FC R13 (CP)+26 FD R14 (CP)+28 FE R15 (CP)+30 FF

H H

H H H

9 A B C D E F

H H

H H H

General-Purpose word Register R9 UUUU General-Purpose word Register R10 UUUU General-Purpose word Register R11 UUUU General-Purpose word Register R12 UUUU General-Purpose word Register R13 UUUU General-Purpose word Register R14 UUUU General-Purpose word Register R15 UUUU

Note: The first 8 GPRs (R7...R0) may also be accessed byte-wise. Note: Writing to a GPR byte does not affect the other byte of the same GPR.

H H H H H H H

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Each half of the byte-wise accessible r egisters has a special name (see table below ).

Table 3-11 Addressing modes to access Byte-GPRs Name Physical

Address

RL0 (CP)+0 F0 RH0 (CP)+1 F1 RL1 (CP)+2 F2 RH1 (CP)+3 F3 RL2 (CP)+4 F4 RH2 (CP)+5 F5 RL3 (CP)+6 F6 RH3 (CP)+7 F7 RL4 (CP)+8 F8

8-Bit Address

H H H H H H H H H

4-Bit Address

Description Reset

Value

General-Purpose byte Register RL0 UU General-Purpose byte Register RL1 UU General-Purpose byte Register RL2 UU General-Purpose byte Register RL3 UU General-Purpose byte Register RL4 UU General-Purpose byte Register RL5 UU General-Purpose byte Register RL6 UU General-Purpose byte Register RL7 UU General-Purpose byte Register RL8 UU

H H H H H H H H H

RH4 (CP)+9 F9 RL5 (CP)+10 FA RH5 (CP)+11 FB RL6 (CP)+12 FC RH6 (CP)+13 FD RL7 (CP)+14 FE RH7 (CP)+15 FF

H H

H H H

9 A B C D E F

H H

H H H

General-Purpose byte Register RL9 UU General-Purpose byte Register RL10 UU General-Purpose byte Register RL11 UU General-Purpose byte Register RL12 UU General-Purpose byte Register RL13 UU General-Purpose byte Register RL14 UU General-Purpose byte Register RL15 UU

H H H H H H H

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3.5.1 Context Switch

An Interrupt Service Routine (ISR) or a task scheduler of an operating system usually saves the contents of all used registers into the stack, and restores them before returning. The more registers a routine uses, the more time is wasted by saving and restoring.

The contents of the register bank are switched by changing the base address of the memory-mapped GPR bank. The base address is given by the contents of the Context Pointer (CP) register.

The Context Pointer

The CP register is not bit-addressable. It can be updated via any instruction capable of modifying SFRs.

CP Context Pointer SFR(FE10

1514131211109876543210

,08H) R eset value: FC00

1111 CP 0

rrrr rw r

Field Bits Type Description

1 [15:12] r CP always points in the DPRAM CP [11:1] rw Modifiable portion of register CP

Specifies the (word) base address of the current memory-mapped register bank.

Note: When writing a value to register CP with

bits CP[11:9] = 000, bits CP[11:10] are set to 11 by hardware.

0 [0] r CP is always word-aligned

Note: It is the user’s responsibility to ensure that the physical GPR address specified via

CP register plus short GPR address must always be an RAM location. If this condition is not met, unexpected results may occur. Do not set CP below the DPRAM start address.

Note: Due to the internal instruction pipeline, a new CP value cannot be used for GPR

address calculations for the instruction immediately following the instruction updating the CP register.

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The C166S switches the complete memor y-mapped GPR ban k with a singl e instruction. After switching, the service routine executes within its own separate context.

The instruction SCXT CP, #New_Bank pushes the value of the current context pointer (CP) into the system stack and loads CP with the immediate value New_Bank, which selects a new register bank. The service routine may now use its own registers. This memory register bank is preserved when the service routine termi nates, i.e. its contents are available on the next call. Before returning from the service routine (RETI), the previous CP is simply popped from the system stack, which returns the registers to the original bank.

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3.6 Data Addressing

The C166S provides a lot of powerful addressing modes for word-wise, byte-wise and bitwise data accesses (short, long, indirect). The different addressing modes use different formats and have different scopes.

The following major tasks are performed:

• Address generation using short-, long- and indirect-addressing modes

• Data paging or overwriting mechanism

• System stack handling

3.6.1 Short Addressing Modes

All of these addressing modes use an implicit base offset address to specify a 24-bit physical address. Short addressing modes allow access to the GPRs, SFRs, or bitaddressable memory space:

Physical Address = Base Address + ∆

Short Address

Note:∆ is 1 for byte-wise GPRs, ∆ is 2 for word-wise GPRs.

Table 3-12 Short addressing modes Mnemonic Physical Address Short Address

Scope of Access

Range

Rw (CP) + 2*Rw or local Rw = 0...15 GPRs (Word) Rb (CP) + 1*Rb or local Rb = 0...15 GPRs(Byte) reg 00’FE00

00’F000 (CP)+ 2*(r eg∧0F (CP)+ 1*(r eg∧0F

bitoff 00’FD00

00’FF00 00’F100 (CP) + 2*(bitoff∧0F

+ 2*reg

)

+ 2*bitoff

+ 2*(bitoff∧7FH)

)

bitaddr Word offset as with bitoff.

immediate bit position.

reg = 00 reg = 00H...EF reg = F0H...FF reg = F0H...FF

bitoff = 00 bitoff = 80H...EF bitoff = 80H...EF bitoff = F0H...FF

bitoff = 00 bitpos= 0...15

...EF

...7F

...FF

SFRs(Word, Low byte)

ESFRs(Word, Low byte)

GPRs(Word)

GPRs(Bytes)

DPRAMBit word offset

SFR Bit w ord offset

ESFRBit word offset

GPR Bit word offset

Any single bit

Rw, Rb: Specifies direct access to any GPR in the currently active context. Both Rw

and Rb require 4 bits in the instruction format. The base address o f the gl oba l register bank is determined by the contents of registe r CP. Rw specifies a 4-bit word GPR address relative to the base address (CP), while Rb specifies a 4bit byte GPR address relative to the base address (CP).

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reg: Specifies direct access to any (E)SFR or GPR in the currently active context.

The reg value requires 8 bits in the instruction format. Short reg addresses in the range from 00 equals 2, and the base address is 00’FE00 00’F000

for the extended ESFR area. The reg accesses to the ESFR area

to EFH always specify (E)SFRs. In that case, the factor ∆

for the standard SFR area or

require a preceding EXT*R instruction to switch the base address. De pending on the opcode, either the total word (for word operations) or the low byte (for byte operations) of an SFR can be addressed via reg. Note that the high byte of an SFR cannot be accessed via the reg addressing mode. Short reg addresses in the range from F0

to FFH always specify GPRs. In that case,

only the lower 4bits of r e g ar e si gnifican t for physi cal address generation and, therefore, the address calculation is identical to the address generation process described for the Rb and Rw addressing modes.

bitoff: Specifies direct access to any word in the bit -addressable memo ry space. The

bitoff value requires 8 bits in the instruction format. Depending on the specified bitoff range, different base addresses are used to generate physical addresses: Short bitoff add resses in the ran ge from 00

to 7FH use 00’FD00H

as a base address to specify the 128 highest DPRAM word locations in the range from 00’FD00

to EFH use base address 00’FF00H to specify the internal SFR word loca-

tions in the range from 00’FF00 specify the internal ESFR word locations in the range from 00’F100 00’F1DE

. The bitoff accesses to the ESFR area require a preceding EXT*R

instruction to switch the base address. For short bitoff addresses from F0 FF

, only the lowest four bits ar e used to gener ate the addr ess of the sele cted

h to 00’FDFEH. Short bitoff addresses in the range from

to 00’FFDEH or base address 00’F100H to

word GPR.

bitaddr: Any bit address is specified by a word address within the bit-addressable

memory space (see bitoff), and by a bit position (bitpos) within that word. Therefore, bitaddr requires 12 bits in the instruction format.

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3.6.2 Long and Indirect Addressing Modes

These addressing modes use one of th e 4 DPP registers to specify a 24-bit a ddress. Any word or byte data within the entire address space can be accessed with these modes. Any long or indirect 16-bi t addr ess contai ns tw o pa rts th at ha ve differ ent m eani ng s. Bit s 13-0 specify a 14-bit data page offset, while bits 15-14 specify the Data Page Pointer (DPP) (1 of 4) register, which is used to generate the full 24-bit address (see figure below).

The C166S also supports an override mechanism for the DPP addressing scheme [EXTP(R) and EXTS(R) instructions].

DPP0 DPP1 DPP2 DPP3

16-bit Long Address

15 14 13

14-bit page offset

1323

24-bit Physical Address

Figure 3-8 Interpretation of a 16-bit Long Address

Note: Word accesses on odd byte addresses are not executed. A hardware trap will be

triggered.

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3.6.2.1 Addressing via Data Page Pointer

The 4 non-bit-addressable DPP registers select up to 4 different data pages. The lower 10 bits of each DPP regi ster sele ct one of the 10 24 possible 1 6-KB yte data pages, whil e the upper 6 bits are reserved for the future use. The DPP reg isters provide access to the entire memory space in 1 6-KByte pages.

The DPP registers are used implicitly whenever data accesses to any memory location are made via indirect or direct long 16-bit addressing modes (except for override accesses via EXTended instructions and PEC data transfers).

Data paging is perfo rm ed b y concaten ati ng t he l ow er 14 bits of an indirect or direct long 16-bit address with the contents of the DDP register selected by the upper 2 bits of the 16-bit address. The contents of the selected DPP register specify one of the 1024 possible data pages. This data page base address together with the 14-bit page offset forms the physical 24-bit address.

16-Bit Data Address

015 14

Memory

255

254

FF’0000

FE’0000

01’0000

00’0000

selects DPP

DPP

Page

Segment Segment offset

DPP3 - 11 DPP2 - 10 DPP1 - 01 DPP0 - 00

023 15 14

Page offset

Figure 3-9 Addressing via the Data Page Pointer

After reset, the DPP registers select data pages 3-0 within segment 0. If the user does not want to use any data paging, no further action is required.

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DPP0 Data Page Pointer 0 SFR(FE00

1514131211109876543210

000000 DPP0PN

rrrrrr rw

,00H) Reset value: 0000

DPP1 Data Page Pointer 1 SFR(FE02

1514131211109876543210

000000 DPP1PN

rrrrrr rw

,01H) Reset value: 0001

DPP2 Data Page Pointer 2 SFR(FE04

,02H) Reset value: 0002

1514131211109876543210

000000 DPP2PN

rrrrrr rw

DPP3 Data Page Pointer 3 SFR(FE06

1514131211109876543210

000000 DPP3PN

rrrrrr rw

,03H) Reset value: 0003

Field Bits Type Description

DPPxPN [9:0] rw Data Page Number of DPP

Specifies the data page selected via DPP.

Note: In a non-segmented memory mode, the whole DPP register is still used for the

calculation of the physical 24-bit address.

A DPP register can be updated via any instruction that is capable of modifying an SFR.

Note: Due to the internal instruction pipeline, a new DPP value is not usable for the

operand address calculation of the instruction immediately following the instruction updating the DPPx register.

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3.6.2.2 DPP Override Mechanism in the C166S

The C166S provides an override mechanism to tempora rily bypass the DPP addre ssing scheme.

The EXTP(R) and EXTS(R) instructions over ride this addressing mechanism. Instructi on EXTP(R) replaces the contents of the DPP register, while instruction EXTS(R) concatenates the complete 16-bit long address with the specified segment base address. The overriding page or segmen t may be specified dir ectly as a constant (#pag, #seg) or via a word GPR (Rw).

EXTP(R):

#pag

24-bit Physical Address

16-bit Long Address

14 13

14-bit page offset

EXTS(R):

16-bit Long Address

#seg

24-bit Physical Address

Figure 3-10 Overriding the DPP Mechanism

16-bit segment offset

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3.6.2.3 Long Addressing Mode

The long addressing mode uses a 1 6-bit constant value encoded in the instruction format which specifies the data page offset and the DPP.

The long addressing mode is referred to by the mnemonic mem.

Table 3-13 Long addressing mode Mnemonic Physical Address Scope of Access

mem (DPP0)|| mem∧3FFF

(DPP1)|| mem∧3FFF (DPP2)|| mem∧3FFF (DPP3)|| mem∧3FFF

mem pag || mem∧3FFF

H H H H

mem seg || mem any word or byte

Note: The long addressing mode may be used with the DPP overriding mechanism

(EXTP(R) and EXTS(R)).

any word or b yte

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3.6.2.4 Indirect Addressing Modes

These addressing modes can be considered as a combination of short and long addressing modes. This means that a long 16-bit address is provided indirectly by the contents of a word GPR that is specified di rectly by a short 4- bit address ( Rw = 0 to 15). There are indirect addressing modes which add a constant value to the GPR contents before the long 16-bit address is calculated. Other indirect addressing modes can decrement or increment the indi rect address pointers (GPR contents) by 2 or 1 (referring to words or bytes).

In each case, one of the four DPP registers is used to spe cify physical 24-bit a ddresses. Any word or byte data within the entire memory space can be addressed indirectly.

Note: Indirect addressing may be used with the DPP overriding mechanism (EXTP(R)

and EXTS(R)).

Some instructions use only the lowest 4-word GPRs (R3-R0) as indirect address pointers, which are then specified via short 2-bit addresses.

Physical addresses are generated from indirect address pointers using the following algorithm:

1) Calculate the physical address of the word GPR, which is used as indirect address pointer, using the specified short address (Rw) and

GPR Address = (CP) + 2

2) If required, pre-decrement indirect address pointer (-Rw) by the data-type-

dependent value (∆=1 for byte ope rations, ∆=2 for word operatio ns) before the long 16-bit address is generated:

(GPR Address) = (GPR Address) - ∆ ; [optional step!]

3) Calculate the long 16-bit address by adding a constant value (Rw+const16 if

selected) to the contents of the indirect address pointer:

Long Address = (GPR Pointer) + Constant ; [+Constant is optional]

4) Calculate the physical 24-bit a ddress using the resulting l ong addr ess and the

corresponding DPP register contents (see long mem addressing modes).

Short Address

Physical Address = (DPPi) + Page offset

5) If required, post-in/decrement indirect address pointers (‘Rw±’) by the data-

type-dependent value (∆=1 for byte operations, ∆=2 for word operations).

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(GPR Pointer) = (GPR Pointer) ± ∆; [optional step!]

The following indirect addressing modes are provided:

Table 3-14 Indirect addressing modes Mnemonic Particularities

[Rw] Most instructions accept any GPR (R15...R0) as indirect address

pointer. Some instructions accept only the lower four GPRs (R3...R0).

[Rw+] The specified indirect address pointer is automatically p ost-incremented

by 2 or 1 (for word or byte data operations) after the access.

[-Rw] The specified indirect address pointe r is automatically pre-decremented

by 2 or 1 (for word or byte data operations) before the access.

[Rw+#data16] The specified 16-bit constant is added to the indirect address pointer

before the long address is calculated.

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3.6.3 The System Stack

A system stack is provided to store return vectors, segment pointers, and processor status for procedures and interrupt routines.

The internal system stack can also be used to store dat a temporarily, o r pass it between subroutines or tasks. Instructions are provided to push or pop registers on/from the system stack. However, in most cases, the register banking scheme provides the best performance for passing data between multiple tasks.

Note: The system stack allows the storage of words only. Bytes must either be

converted to words or the “unwanted” other byte must be disregarded. Register SP can be loaded only with even byte addresses (The LSB of SP is always 0).

The Stack Pointer (SP) addresses the stack within the DPRAM area.

The Stack Pointer Register

The non-bit-addressable Stack Pointer (SP) register is used to point to the Top Of the System (TOS) stack. The SP register is pre-decr emented whenever data is to be pushed onto the stack, and it is post-incremented whenever data is to be popped from the stack. Therefore, the system stack grows from higher toward lower memory locations.

Since the Least Significant Bit (LSB) of r egister SP i s tied to 0, and bits 15- 12 are tied to 1 by hardware, the SP register can contain values only from F000

to FFFEH. This

allows access to a physical stack within the DPRAM of the C166S. A virtual stack (usually bigger) can be implemented via software. This mechanism is supported by registers STKOV and STKUN (see descriptions below (Section 3.6.3.1).

The SP register can be updated via any instruction that is capable of modifying a 16-bit SFR.

Note: Due to the internal instruction pipeline, a POP or RETurn instruction must not

immediately follow an instruction updating the SP register.

SP Stack Pointer SFR(FE12

1514131211109876543210

,09H) R eset value: FC00

1111 SP 0

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Field Bits Type Description 1111 [15:12] r Fixed at 1111 SP [11:1] rwh Modifiable portion of register SP

Specifies the top of the system stack.

0 [0] r Fixed at 0

3.6.3.1 Stack Overflow and Underflow

Detection of stack overflow/underflow is supported by two registers, STKOV (STacK OVerflow pointer) and STKUN (STacK UNderflo w pointer) . Specific system traps (Stack Overflow trap, Stack Underflow trap) will be entered whenever the SP reaches either boundary specified in these registers.

In many cases, the user will place a Software ReSeT instruction (SRST) into the stack underflow and overflow trap service routines. This is an easy approach that does not require special programming. Ho wever, this approach assu mes that the defined int ernal stack is sufficient for the current software, and that exceeding its upper or lower boundary represents a fatal error (see Linear Stack).

It is also possible to use the stack underflow and stack overflow traps to cache portions of a larger external stack. Only the portion of the system stack currently being used is placed into the internal memory, thus allowing a greater portion of the internal RAM to be used for program, data, or register banking. This approach assumes no error but requires a set of control routines (see Circular Stack).

The STacK OVerflow Pointer Register STKOV

This non-bit-addressable STKOV pointer register is compared to the SP register after each operation that pushes data onto the system stack (e.g., PUSH and CALL instructions or interrupts), and after each substraction from the SP register. If the contents of the SP register is less than the contents of the STKOV pointer register, a stack overflow trap will occur.

STKOV STacK OVerflow Pointer SFR(FE14

1514131211109876543210

1111 STKOV 0

,0AH) Reset value: FA00

rrwr

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Field Bits Type Description 1111 [15:12] r Fixed at 1111 STKOV [11:1] rw Modifiable portion of register STKOV

Specifies the segment offset address of the lower limit of the system stack.

0 [0] r Fixed at ’0’ STKOV can be updated via any instruction that is capable of modifying an SFR.

Note: When a value is MOVED into the stack pointer, NO check against the overflow/

registers is performed.

• Fatal error indication treats the stack overflow as a system error and executes

associated trap service routine. Under these cir cumstances, da ta in the botto m of the stack may have been overwritten b y the status information stacked upon servicing the stack overflow trap.

• Automatic system stack flushing allows the system stack to be used as a “Stack

Cache” for a bigger external user stack. In this case, STKOV should be initialized to a value that represents the desired lowest Top Of Stack (TOS) address plus an offset based on the selected maximum stack size. This offset considers the wo rst case that will occur when a stack overflow condition i s detected j ust duri ng entry into an ISR, or during an ATOMIC/EXTend sequence. Under these conditi ons, addi tional stack word locations are required to push IP, PSW, and CSP for both the ISR and the hardware trap service routine.

The STacK UNderflow Pointer Register STKUN

STKUN is a non-bit-addressable register that is compared to the SP register after each operation that pops data from the system stack (e.g. POP and RET instructions), and after each addition to the SP register. If the content of the SP register is greater than the the content of STKUN, a stack underflow hardware trap will occur.

Since the LSB of STKUN is tied to 0 and bits 15 through 12 are tied to 1 by hardware, STKUN register can only contain values from F000

to FFFEH.

STKUN STacK UNderflow Pointer SFR(FE16

,0BH) Reset value: FC00

1514131211109876543210

1111 STKUN 0

rrwr

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Field Bits Type Description 1111 [15:12] r Fixed at 1111 STKUN [11:1] rw Modifiable portion of register STKUN

Specifies the segment offset address of the upper limit of the system stack.

0 [0] r Fixed at 0 STKUN can be updated via any instruction capable of modifying an SFR.

Note: When a value is MOVED into the stack pointer, NO check against the overflow/

registers is performed.

• Fatal error indication treats the stack underflow as a system error and executes

associated trap service routine.

• Automatic system stack refilling allows the system stack to be used as a “Stack

Cache” for a bigger external user stack. In this case, STKUN should be initialized to a value that represents the desired highest Bottom of Stack address.

Scope of Stack Limit Control

The stack limit control by the register pair STKOV and STKUN detects cases where SP is moved outside the defined st ack area ei ther by ADD or SUB i nstructions, or by PUSH or POP operations (explicit or implicit, e.g., CALL or RET instructions).

This control mechanism is not triggered and no stack trap is generated when:

• the stack pointer SP is directly updated via MOV instructions, or

• the limits of the stack area (STKOV, STKUN) are changed so that SP is outside the

new limits.

3.6.3.2 Linear Stack

The C166S offers a linear stack option (STKSZ = 111B) in which the system stack may use the complete DPRAM area. This provides a large system stack without requiring procedures to handle data transfers for a circular stack. However, this method also leaves less RAM space for variables or code. Th e DPR AM area that m ay be consu med by the system stack is defined via the STKUN and STKOV pointers. The underflow and overflow traps in this case serve for fatal error detection only.

For the linear stack option, all modifiable bits of register SP are used to access the physical stack. Although the stack pointer may cover addresses from 00’F000 00’FFFE may only use the address range 00’F600

, the (physical) system stack must be located within the DPRAM and therefo re

to 00’FDFEH. It is the user’s responsibility to

restrict the system stack to the DPRAM range.

up to

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Note: Stack accesses below the DPRAM area (ESFR space and reserved area) and

within address range 00’FE00

and 00’FFFEH (SFR space) will have

unpredictable results.

3.6.3.3 Circular (Virtual) Stack

This basic technique allows pushing until the overflow boundary of the internal stack is reached. At this point , a portion of the stacked data must be saved i nto external memory to create space for further stack pushes. This is called “ stack flushing” . Whe n executing a number of return or pop instructions, the upper boundary (since the stack empties upward to higher memory locations) is reached. The entries that have been previously saved in external memory must now be restored. This is called “stack filling”. Because procedure call instructions do not continue to nest infinitely and call and return instructions alternate, flushing and filling normally occurs very infrequently. If this is not true for a given program environme nt, this techni que shoul d not be used becau se of the overhead of flushing and filling.

The basic mechanism is the transformation of the addresses of a virtual stack area controlled via SP, STKOV, and STKUN to a defined physical stack area within the DPRAM via hardware. This virtual stack area covers all possible locations that SP can point to, i.e. 00’F000 address range. The size of the physical stack area within the DPRAM that is used for standard stack operations is defined via bitfie ld STKSZ in register SYSCON (see below).

through 00’FFFEH. STKOV and STKUN accept the same 4-K Byte

Table 3-15 Circular Stack Address Transformation STKSZ Stack Size

(Words)

0 0 0 0 0 1 0 1 0 0 1 1 1 0 0

256 00’FBFEH-00’FA00H (Default after Reset) SP.8-SP.0

128 00’FBFEH-00’FB00

64 00’FBFEH-00’FB80

32 00’FBFEH-00’FBC0

512 00’FBFEH-00’F800H (not for 1KByte

DPRAM Addresses (Words) of Physical Stack

H H

DPRAM) 1 0 1 1 1 0 1 1 1

--- Reserved. Do not use this combination. ---

1024 00’FDFEH-00’FX00H (Note: No circular stack)

00’FX00

represents the lower DPRAM limit,

i.e.

1 KB: 00’FA00

3 KB: 00’F200

, 2 KB: 00’F600H,

Significant Bits of Stack Ptr. SP

SP.7-SP.0 SP.6-SP.0 SP.5-SP.0 SP.9-SP.0

SP.11...SP.0

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The virtual stack addresses are transformed to physical stack addresses by concatenating the significant bits of SP (see table Table 3-15) with the complementary most significant bits of the upper limit of the physical stack area (00’FBFE

). This

transformation is done via hardware (see figure Figure 3-11). The reset values (STKOV=FA00

, STKUN=FC00H, SP=FC00H, STKSZ=000B) map the

virtual stack area directly to the physical stack area, and allow using the internal system stack without any changes, provided that the 256-word area is not exceeded.

FBFE

FB80

1 1 1 1 1 0 1 1 1 1 1 1 1 1 1 0

1 1 1 1 1 0 1 1 1 0 0 0 0 0 0 0

Phys.A.

<SP>

FBFE

FA00

F800

1 1 1 1 1 0 1 1 1 1 1 1 1 1 1 0

1 1 1 1 1 0 1 0 0 0 0 0 0 0 0 0

1 1 1 1 1 0 0 0 0 0 0 0 0 0 0 0

FBFE

FB7E

After PUSH 1 1 1 1 1 0 1 1 1 1 1 1 1 1 1 0

1 1 1 1 1 0 1 1 1 1 1 1 1 1 1 0

1 1 1 1 1 0 1 1 0 1 1 1 1 1 1 0

64 words 256 words

Phys.A.

<SP>

Stack Size

FBFE

F7FE

After PUSH 1 1 1 1 1 0 1 1 1 1 1 1 1 1 1 0

1 1 1 1 1 0 1 1 1 1 1 1 1 1 1 0

1 1 1 1 0 1 1 1 1 1 1 1 1 1 1 0

Figure 3-11 Physical Stack Address Generation

The following example demonstr ates the ci rcul ar stack mechanism that is also an effect of this virtual stack mapping: First, register R1 is pushed onto the lowest physical stack location according to the selected maximum stack size. The next instruction will push register R2 onto the highest physical stack location, although the SP is decr emen ted b y 2 as for the previous push operation.

MOV SP, #0F802H ;Set SP before last entry...

;...of physical stack of 256 words ... ;(SP)=F802H: Physical stack addr.=FA02H PUSH R1 ;(SP)=F800H: Physical stack addr.=FA00H PUSH R2 ;(SP)=F7FEH: Physical stack addr.=FBFEH

The effect of the address transformation is that the physical stack addresses wrap around from the end of the defined area to its beginning. When flushing and filling the

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internal stack, this circular stack mechanism only requires moving that portion of stack data that is to be re-used (i.e. the upper part of the defined stack area) instead of the whole stack area. Stack data that remain in the lower part of the interna l stack need not be moved by the distance of the space being flushed or filled, as the stack pointer automatically wraps around to the beginning of the freed part of the stack area.

Central Processing Unit

Note: This circular stack technique is applicable for stack sizes of 32 to 512 words

(STKSZ = 000

to 100B). It does not work with option STKSZ = 111B, which uses

the complete DPRAM for system stack; in this case, the address transformation mechanism is deactivated.

When a boundary is r eached, the stack u nder fl ow or over flow tr ap is enter ed . Inside the trap handler a prede termined portion of the internal stack is moved to or from the external stack. The amount of data transferred is determined by t he average stack space required by routines and the frequency of calls, traps, interrupts, and returns. In most cases, this will be approximately 1/4 to 1/10 the size of the internal stack. Once the transfer is complete, the boundary poin ters are updated to r eflect th e newly a llocated space on the internal stack. Thus, the user is free to write code without concern for the internal stack limits. Only the execution time required by the trap routines affects user programs.

The following procedure initializes the controller for usage of the circular stack mechanism:

1. Specify the size of the physical system stack area within the DPRAM (bitfield STKSZ

in register SYSCON).

2. Define two pointers that specify the upper and lower boundary of the external stack.

These values are then tested in the stack underflow and overflow trap routines when moving data.

3. Set STKOV to the limit of the defined internal stack area plus six words (for the

reserved space to store two interrupt entries).

The internal stack will now fill until the overflow pointer is reached. After entry into the overflow trap procedure, the top of the stack wi ll be copi ed to the externa l memory. The internal pointers will then be modified to reflect the newly-allocated space. After exiting the trap procedure, the internal stack will wrap around to the top of the internal stack, and continue to grow until the new value of the stack overflow pointer is reached.

When the underflow pointer is reached, while the stack is emptied, the bottom of stack is reloaded from the external memory, and the in ternal pointers are adjusted accordingly.

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Central Processing Unit

3.7 Data Processing

All standard arithmetic, shift, and logical operations are performed in the 16-bit Arithmetic and Logic Unit (ALU ). In addition to the standard ALU, the ALU of the C 166S includes bit manipulation, and a multiply-and-divide unit. Most internal execution blocks have been optimized to perform operations on either 8-bit or 16-bit numbers. Once the pipeline has been filled, most instructions are completed in one machine cycle.

The status flags are autom atically updated in the PSW register (see Section 3 .7.6) after each ALU operation. These flags allow branching upon specific conditions. Support of both signed and unsigned ari thmetic i s provided b y the user-selectabl e branch test. The status flags are also preserved automatically by the CPU upon entry into an interrupt or trap routine.

3.7.1 Data Types

The C166S supports operations on boolean/bit, bit string, character, and integer data types. Most instructions operate with specific data types, while others are useful for manipulating several data types.

The C166S data formats support all ANSI C data types. In addition, some C compilers support new types that allow the efficient use of the bit-manipulation instructions in embedded control applications.

The C166S directly supports the following data formats:

Table 3-16 CPU data formats CPU data format Size (bytes) Range

BIT 1 bit 0 or 1 BYTE 1 0 to 255U or

-128 to +127

WORD 2 0 to 65535U or

-32768 to +32767

Table 3-17 ANSI C data types ANSI C data types Size (bytes) Range CPU data format

bit 1bit 0 or 1 BIT sfrbit 1bi t 0 or 1 BIT esfrbit 1bit 0 or 1 BIT signed char 1 -128 to +127 BYTE unsigned char 1 0 to 255U BYTE

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Table 3-17 ANSI C data types ANSI C data types Size (bytes) Range CPU data format

sfr 1 0 to 65535U WORD esfr 1 0 to 65535U WORD signed short 2 -32768 to +32767 WORD unsigned short 2 0 to 65535U WORD bitword 2 0 to 65535U WORD or BIT signed int 2 -32768 to +32767 WORD unsigned int 2 0 to 65535U WORD signed long 4 -2147483648 to

+2147483647 unsigned long 4 0 to 4294967295UL Not directly supported float 4 +/-1,176E-38 to

+/-3,402E+38

Central Processing Unit

Not directly supported

double 8 +/- 2,225E-308 to

+/- 1,797E+308 long double 8 +/- 2,225E-308 to

+/- 1,797E+308 near pointer 2 16/14bits

depending on

memory model far pointer 4 14bits (16k) in any

page huge pointer 4 24bits (16M) Not directly supported shuge pointer 4 24bits (16M), but

arithmetic is done

16-bit wide

Not directly supported

WORD

Not directly supported

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Central Processing Unit

3.7.2 Constants

In addition to the powerful addressing modes the C166S instruction set also supports word-wide or byte-wi de imme diate con stants. For an op timum utilizati on of the ava ilable code storage, these constants are represented in the instruction formats by either 3, 4, 8 or 16 bits. The short constants are always zero-extended, while the long constants are truncated if necessary to match the data format requ ired for the pa rticular operati on (see table below):

Table 3-18 Constant formats Mnemonic Word Operation Byte Operation

#data3 0000 #data4 0000 #data8 0000 #data16 data16 data16 ∧ FF #mask 0000H + mask mask

+ data3 00H + data3

+ data4 00H + data4

+ data8 data8

Note: Immediate constants are always signified by a leading #.

3.7.3 The 16-bit Adder/Subtracter, Barrel Shift er

and the 16-bit Logic Unit

All standard arithmetic and logical operati ons are perform ed by a 16-bit ALU . In case of byte operations signals from bi ts six and seven of the ALU result are used to contr ol the condition flags. Multiple precision arithmetic is supported by a CARRY-IN signal to the ALU from previously calculated portions of the desired operation.

A 16-bit barrel shifter provides mult iple bit shifts in a single machine cycle. Rotations and arithmetic shifts are also supported.

3.7.4 Bit-manipulation Unit

The C166S offers a large number of instructions for bit processing. The special bitmanipulation unit was implemented for this purpose. The bit-manipulation instructions are for efficient control and testing of peripherals. Unlike other microcontrollers, the C166S has instructions that provide direct access to two operands in the bit -addressable space without requiring them to be moved into temporary locations.

The same logical instruction s that are available fo r words and bytes can al so be used for bits. The user can compare and modify a control bit for a peripheral in one instruction. Multiple-bit shift instructions have been included to avoid long instruction streams of single bit shift operation s. These instru ctions requ ire a sing le machine cycle. In addition, bit field instructions are able to modify multiple bits of one operand in a single instruction.

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Specifications and Main Features

Frequently Asked Questions

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