INFINEON C165 User Manual

Data Sheet, V2.0, Dec. 2000

C165

16-Bit Single-Chip Microcontroller

Microcontrollers

Never stop thinking.

Edition 2000-12 Published by Infineon Technologies AG,

St.-Martin-Strasse 53,

D-81541 München, Germa ny

Attention please!

The information herein is given to describe certain com ponents and shall not be consid ered as warranted characteristics.

Terms of delivery and rights to technical change reserved. We hereby disclaim any and all warranties, including but not limited to warranties of non-infringement, regarding

circuits, descriptions and charts stated her ein. Infineon Technologies is an approved CECC manufacturer.

Information

For further information on te ch nology, delivery terms and conditions and prices please contact your nearest Infineon Technologies Office in Germany or ou r Infineon Technologies Representatives worldwide.

Warnings

Due to technical requirements co mp onents may contain dangerous substan ce s. For information on the typ es in question please contact your nearest Infineon Technologies Office.

Infineon Technologies Components may only be used in life-support devices or systems with the express written approval of Infineon T echnologies, if a f ailure of such components can reasonably be expected to cause the failure of that life - su ppo rt de vi ce o r system, or to aff ec t th e sa fety or effectiveness of that devi ce o r system. Life supp ort devices or systems are intended to be implanted in the human body, or to support and/or maintain and sustain and/or protect human life. If they fail, it is reasonable to assume that the health of the user or other persons may be endangered.

Data Sheet, V2.0, Dec. 2000

C165

16-Bit Single-Chip Microcontroller

Microcontrollers

Never stop thinking.

C165 Revision History: 2000-12 V2.0

Previous Version: 1998-12 Update 0.5µ technology

01.96 3 Volt Addendum

07.95 25 MHz Addendum

09.94 Data Sheet

Page Subjects (major changes since last revision)

All Converted to Infineon layout

2 ROM derivatives removed, 25-MHz derivatives and 3 V derivatives

included

6ff Pin numbers for TQFP added 14 Address window arbitration and master/slave mode introduced 32 New standard layout for section “Absolute Maximum Ratings” 33 Section “Operating Condition s” added 34f Parameter “RSTIN

pullup” replaced by “RSTIN current”

36f DC Characteristics for reduced supply voltage added 38f Separate specification for power consumption with greatly improved values 40ff Description of clock generation improved 45, 55, 65 Timing adapted to 25 MHz 48, 58, 66 Timing for reduced supply voltage added

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C166 Family

C165

• High Performance 16-bit CPU with 4-Stage Pipeline – 80 ns Instruction Cycle Time at 25 MHz CPU Clock – 400 ns Multiplication (16 × 16 bit), 800 ns Division (32 / 16 bit) – Enhanced Boolean Bit Manipulation Facilities – Additional Instructions to Support HLL and Operating Systems – Register-Based Design with Multiple Variable Register Banks – Single-Cycle Context Switching Support – 16 MBytes Total Linear Address Space for Code and Data – 1024 Bytes On-Chip Special Function Register Area

• 16-Priority-Level Interrupt System with 28 Sources, Sample-Rate down to 40 ns

• 8-Channel Interrupt-Driven Single-Cycle Data Transfer Facilities via Peripheral Event Controller (PEC)

• Clock Generation via prescaler or via direct clock input

• On-Chip Memory Modules – 2 KBytes On-Chip Internal RAM (IRAM)

• On-Chip Peripheral Modules – Two Multi-Functional General Purpose Timer Units with 5 Timers – Two Serial Channels (Synchronous/Asynchronous and High-Speed-Synchronous)

• Up to 16 MBytes External Address Space for Code and Data – Programmable External Bus Characteristics for Different Address Ranges – Multiplexed or Demultiplexed External Address/Data Buses with 8-Bit or 16-Bit

Data Bus Width – Five Programmable Chip-Select Signals – Hold- and Hold-Acknowledge Bus Arbitration Support

• Idle and Power Down Modes

• Programmable Watchdog Timer

• Up to 77 General Purpose I/O Lines, partly with Selectable Input Thresholds and Hysteresis

• Power Supply: the C165 can operate from a 5 V or a 3 V power supply

• Supported by a Large Range of Development Tools like C-Compilers, Macro-Assembler Packages, Emulators, Evaluation Boards, HLL-Debuggers, Simulators, Logic Analyzer Disassemblers, Programming Boards

• On-Chip Bootstrap Loader

• 100-Pin MQFP Package (0.65 mm pitch)

• 100-Pin TQFP Package (0.5 mm pitch)

C16516-Bit Single-Chip Microcontroller

Data Sheet 1 V2.0, 2000-12

C165

This document describes several derivatives of the C165 grou p. Table 1 enumerates these derivatives and summarizes the differences. As this document refers to all of these derivatives, some descriptions may not apply to a specific product.

Table 1 C165 Derivative Synopsis Derivative

SAF-C165-LM 20 MHz 4.5 to 5.5 V MQFP-100 SAB-C165-LM 20 MHz 4.5 to 5.5 V MQFP-100 SAF-C165-L25M 25 MHz 4.5 to 5.5 V MQFP-100 SAB-C165-L25M 25 MHz 4.5 to 5.5 V MQFP-100 SAF-C165-LF 20 MHz 4.5 to 5.5 V TQFP-100

Max. Operating Frequency

Operating Voltage

Package

SAB-C165-LF 20 MHz 4.5 to 5.5 V TQFP-100 SAF-C165-L25F 25 MHz 4.5 to 5.5 V TQFP-100 SAB-C165-L25F 25 MHz 4.5 to 5.5 V TQFP-100 SAF-C165-LM3V 20 MHz 3.0 to 3.6 V MQFP-100 SAB-C165-LM3V 20 MHz 3.0 to 3.6 V MQFP-100 SAF-C165-LF3V 20 MHz 3.0 to 3.6 V TQFP-100 SAB-C165-LF3V 20 MHz 3.0 to 3.6 V TQFP-100

This Data Sheet is valid for devic es start ing with and including design st ep H A.

For simplicity all versions are referred to by the term C165 throughout this document.

Ordering Information

The ordering code for Infineon microcontrollers provides an exact reference to the required product. This ordering code identifies:

• the derivative itself, i.e. its function set, the temperature range, and the supply voltage

• the package and the type of delivery.

For the available ordering codes for the C165 please refer to the “Product Catalog Microcontrollers”, which summarizes all available microcontroller variants.

Note: The ordering codes for Mask-ROM versions are defined for each product after

verification of the respective ROM code.

Data Sheet 2 V2.0, 2000-12

C165

Introduction

The C165 is a derivativ e of the Infineon C1 66 Family of full featured si ngle -chi p CMOS microcontrollers. It combin es high CPU perfo rman ce (up to 12 .5 mi llion instructions per second) with peripheral functionality and enhanced IO-capabilities. The C165 is especially suited for cost sensitive applications.

XTAL1 XTAL2

RSTIN

RSTOUT NMI

EA READY

ALE RD

WR/WRL

Port 5 6 Bit

Figure 1 Logic Symbol

C165

Port 0 16 Bit

Port 1 16 Bit

Port 2 8 Bit

Port 3 15 Bit

Port 4 8 Bit

Port 6 8 Bit

MCL04824

Data Sheet 3 V2.0, 2000-12

Pin Configuration TQFP Package

(top view)

P5.12/T6IN

P5.10/T6EUD

P2.15/EX7IN

P2.14/EX6IN

P2.13/EX5IN

P5.11/T5EUD

P2.12/EX4IN

P2.11/EX3IN

P2.10/EX2IN

P2.9/EX1IN

P2.8/EX0IN

P6.7/BREQ

P6.6/HLDA

P6.5/HOLD

P6.4/CS4

P6.3/CS3

P6.2/CS2

P6.1/CS1

P6.0/CS0

NMI

RSTOUT

RSTIN

P1H.7/A15

C165

P5.13/T5IN P5.14/T4EUD P5.15/T2EUD

XTAL1

XTAL2

P3.0

P3.1/T6OUT

P3.2/CAPIN P3.3/T3OUT P3.4/T3EUD

P3.5/T4IN P3.6/T3IN P3.7/T2IN

P3.8/MRST

P3.9/MTSR

P3.10/TxD0

P3.11/RxD0

P3.12/BHE/WRH

P3.13/SCLK

P3.15/CLKOUT

P4.0/A16 P4.1/A17 P4.2/A18

2 3 4 5 6 7 8 9

11 12 13 14 15 16 17 18 19

100

828384858687888990919293949596979899

C165

2928

32 33 34 35 36 37 38 39 40

41 424344

45 464748 49

76777879

75 74 73 72

71 70 69 68 67 66 65 64 63 62

61 60 59 58 57 56 55 54 53 52

5031

P1H.6/A14 P1H.5/A13 P1H.4/A12 P1H.3/A11 P1H.2/A10

P1H.1/A9 P1H.0/A8 P1L.7/A7 P1L.6/A6 P1L.5/A5 P1L.4/A4 P1L.3/A3 P1L.2/A2 P1L.1/A1 P1L.0/A0 P0H.7/AD15 P0H.6/AD14 P0H.5/AD13 P0H.4/AD12 P0H.3/AD11 P0H.2/AD10 P0H.1/AD9 P0H.0/AD8

P4.3/A19

P4.5/A21

P4.6/A22

P4.4/A20

P4.7/A23

WR/WRL

ALE

READY

N.C.

P0L.2/AD2

P0L.0/AD0

P0L.1/AD1

P0L.3/AD3

P0L.6/AD6

P0L.5/AD5

P0L.4/AD4

P0L.7/AD7

MCP02216

Figure 2

Data Sheet 4 V2.0, 2000-12

Pin Configuration MQFP Package

(top view)

P2.15/EX7IN

P2.14/EX6IN

P2.13/EX5IN

P2.12/EX4IN

P2.11/EX3IN

P2.10/EX2IN

P2.9/EX1IN

P2.8/EX0IN

P6.7/BREQ

P6.6/HLDA

P6.5/HOLD

P6.4/CS4

P6.3/CS3

P6.2/CS2

P6.1/CS1

P6.0/CS0

NMI

RSTOUT

C165

RSTIN

99 98 97 96 95 94 93 92 91 90 89 88 87 86 85 84 83 82100

P5.11/T5EUD

P5.12/T6IN

P5.13/T5IN P5.14/T4EUD P5.15/T2EUD

XTAL1

XTAL2

P3.0

P3.1/T6OUT

P3.2/CAPIN P3.3/T3OUT P3.4/T3EUD

P3.5/T4IN P3.6/T3IN

P3.7/T2IN P3.8/MRST P3.9/MTSR

P3.10/TxD0 P1L.0/A0

P3.11/RxD0

P3.12/BHE/WRH

P3.13/SCLK

P3.15/CLKOUT

P4.0/A16 P4.1/A17 P4.2/A18 P4.3/A19

V V

SS DD

2 3 4 5 6 7 8 9

11 12 13 14 15 16 17 18 19

C165

403938373635343332

4645

4241

80 79 78 77 76 75 74 73 72

71 70 69 68 67 66 65 64 63 62

61 60 59 58 57 56 55 54 53 52

5031

4948

P1H.7/A15 P1H.6/A14 P1H.5/A13 P1H.4/A12 P1H.3/A11 P1H.2/A10

P1H.1/A9 P1H.0/A8 P1L.7/A7 P1L.6/A6 P1L.5/A5 P1L.4/A4 P1L.3/A3 P1L.2/A2 P1L.1/A1

P0H.7/AD15 P0H.6/AD14 P0H.5/AD13 P0H.4/AD12 P0H.3/AD11 P0H.2/AD10 P0H.1/AD9 P0H.0/AD8

ALE

READY

N.C.

P0L.2/AD2

P0L.0/AD0

P0L.1/AD1

P0L.5/AD5

P0L.3/AD3

P0L.4/AD4

P0L.6/AD6

P0L.7/AD7

MCP02144

P4.5/A21

P4.6/A22

P4.4/A20 P5.10/T6EUD

P4.7/A23

WR/WRL

Figure 3

Data Sheet 5 V2.0, 2000-12

Table 2 Pin Definitions and Functions

C165

Symbol Pin Nr

TQFP

XTAL1 XTAL256

P3.0 P3.1 P3.2 P3.3 P3.4 P3.5

P3.6 P3.7

P3.8 P3.9 P3.10

P3.11 P3.12

P3.13 P3.15

8 9 10 11 12 13

14 15

16 17 18

19 20

21 22

Pin Nr MQFP

7 8

10 11 12 13 14 15

16 17

18 19 20

21 22

23 24

Input Outp.

I O

O I O I I

I I

I/O I/O O

I/O O O I/O O

Function

XTAL1: Input to the oscillator amplifier and input

to the internal clock generator XTAL2: Output of the oscillator amplifier circuit. To clock the device from an external source, drive XTAL1, while leaving XTAL2 unconnected. Minimum and maximum high/low and rise/fall times specified in the AC Characteristics must be observed.

Port 3 is a 15-bit bidirectional I/O port. It is bit-wise programmable for input or output via direction bits. For a pin configured as input, the output driver is put into high-impedance state. Port 3 outputs can be configured as push/pull or open drain drivers. The Port 3 pins serve for following alternate functions:

T6OUT GPT2 Timer T6 Toggle Latch Output CAPIN GPT2 Register CAPREL Capture Input T3OUT GPT1 Timer T3 Toggle Latch Output T3EUD GPT1 Timer T3 Ext. Up/Down Ctrl Input T4IN GPT1 Timer T4

Count/Gate/Reload/Capture Input T3IN GPT1 Timer T3 Count/Gate Input T2IN GPT1 Timer T2

Count/Gate/Reload/Capture Input MRST SSC Master-Receive/Slave-Transmit

Input/Output MTSR SSC Master-Transmit/Slave-Receive

Output/Input TxD0 ASC0 Clock/Data Output (Asyn./Sync.) RxD0 ASC0 Data Inp. (Asyn.) or In/Out (Sync) BHE WRH

Ext. Memory High Byte Enable Signal,

Ext. Memory High Byte Write Strobe SCLK SSC Master Cl. Output / Slave Cl. Input CLKOUT System Clock Output (= CPU Clock)

Data Sheet 6 V2.0, 2000-12

Table 2 Pin Definitions and Functions (cont’d)

C165

Symbol Pin Nr

TQFP

P4.0 P4.1 P4.2 P4.3 P4.4 P4.5 P4.6 P4.7

23 24 25 26 29 30 31 32

33 35 O External Memory Read Strobe. RD is activated for

34 36 O External Memory Write Strobe. In WR-mode this pin

WRL

Pin Nr MQFP

25 26 27 28 31 32 33 34

Input Outp.

O O O O O O O O

Function

Port 4 is an 8-bit bidirectional I/O port. It is bit-wise programmable for input or output via direction bits. For a pin configured as input, the output driver is put into high-impedance state. Port 4 can be used to output the segment address lines: A16 Least Significant Segment Address Line A17 Segment Address Line A18 Segment Address Line A19 Segment Address Line A20 Segment Address Line A21 Segment Address Line A22 Segment Address Line A23 Most Significant Segment Address Line

every external instruction or data read access.

is activated for every external data write access. In

-mode this pin is activated for low byte data

WRL write accesses on a 16-bit bus, and for every data write access on an 8-bit bus. See WRCFG in register SYSCON for mode selection.

READY

35 37 I Ready Input. When the Ready function is enabled, a

high level at this pin during an external memory access will force the insertion of memory cycle waitstates until the pin returns to a low level. An internal pullup device holds this pin high when nothing is driving it.

ALE 36 38 O Address Latch Enable Output. Can be used for

latching the address into external memory or an address latch in the multiplexed bus modes.

37 39 I External Access Enable pin. A low level at this pin

during and after Reset forces the C165 to begin instruction execution out of external memory. A high level forces execution out of the internal program memory.

“ROMless” versions must have this pin tied to ‘0’.

Data Sheet 7 V2.0, 2000-12

Table 2 Pin Definitions and Functions (cont’d)

C165

Symbol Pin Nr

TQFP

Pin Nr MQFP

Input Outp.

Function

NC 40 42 – This pin is not connected in the C165.

No connection to the PCB is required.

PORT0

P0L.0-7

41-48

43-50

IO PORT0 consists of the two 8-bit bidirectional I/O

ports P0L and P0H. It is bit-wise programmable for input or output via direction bits. For a pin configured

P0H.0-7

51-58

53-60

as input, the output driver is put into high-impedance state. In case of an external bus configuration, PORT0 serves as the address (A) and address/data (AD) bus in multiplexed bus modes and as the data (D) bus in demultiplexed bus modes.

Demultiplexed bus modes:

Data Path Width: 8-bit 16-bit P0L.0 – P0L.7: D0 – D7 D0 – D7 P0H.0 – P0H.7: I/O D8 – D15

Multiplexed bus modes:

Data Path Width: 8-bit 16-bit P0L.0 – P0L.7: AD0 – AD7 AD0 – AD7 P0H.0 – P0H.7: A8 – A15 AD8 – AD15

PORT1

P1L.0-7 P1H.0-7

59-66 67,68,

71-76

61-68 69-70,

73-78

IO PORT1 consists of the two 8-bit bidirectional I/O

ports P1L and P1H. It is bit-wise programmable for input or output via direction bits. For a pin configured as input, the output driver is put into high-impedance state. PORT1 is used as the 16-bit address bus (A) in demultiplexed bus modes and also after switching from a demultiplexed bus mode to a multiplexed bus mode.

Data Sheet 8 V2.0, 2000-12

Table 2 Pin Definitions and Functions (cont’d)

C165

Symbol Pin Nr

TQFP

Pin Nr MQFP

Input Outp.

Function

RSTIN 79 81 I/O Reset Input with Schmitt-Trigger characteristics. A

low level at this pin while the oscillator is running resets the C165. An internal pullup resistor permits power-on reset using only a capacitor connected to

. A spike filter suppresses input pulses < 10 ns.

Input pulses >100 ns safely pass the filter. The minimum duration for a safe recognition should be 100 ns + 2 CPU clock cycles. In bidirectional reset mode (enabled by setting bit BDRSTEN in register SYSCON) the RSTIN

line is internally pulled low for the duration of the internal reset sequence upon any reset (HW, SW, WDT). See note below this table.

Note: To let the reset configuration of PORT0 settle

a reset duration of ca. 1 ms is recommended.

RST OUT

80 82 O Internal Reset Indication Output. This pin is set to a

low level when the part is executing either a hardware-, a software- or a watchdog timer reset. RSTOUT

remains low until the EINIT (end of

initialization) instruction is executed.

NMI

81 83 I N on-Maskable Interrupt Input. A high to low

transition at this pin causes the CPU to vector to the NMI trap routine. When the PWRDN (power down) instruction is executed, the NMI

pin must be low in order to force the C165 to go into power down mode. If NMI

is high, when PWRDN is exec uted, the part will continue to run in normal mode. If not used, pin NMI

should be pulled high externally.

Data Sheet 9 V2.0, 2000-12

Table 2 Pin Definitions and Functions (cont’d)

C165

Symbol Pin Nr

TQFP

P6.0 P6.1 P6.2 P6.3 P6.4 P6.5 P6.6

P6.7

82 83 84 85 86 87 88

P2.8 P2.9 P2.10 P2.11 P2.12 P2.13 P2.14 P2.15

90 91 92 93 94 95 96 97

Pin Nr MQFP

84 85 86 87 88 89 90

92 93 94 95 96 97 98 99

Input Outp.

O O O O O I I/O

O IO

I I I I I I I I

Function

Port 6 is an 8-bit bidirectional I/O port. It is bit-wise programmable for input or output via direction bits. For a pin configured as input, the output driver is put into high-impedance state. Port 6 outputs can be configured as push/pull or open drain drivers. The Port 6 pins also serve for alternate functions: CS0 CS1 CS2 CS3 CS4 HOLD HLDA

Chip Select 0 Output Chip Select 1 Output Chip Select 2 Output Chip Select 3 Output Chip Select 4 Output External Master Hold Request Input Hold Acknowledge Outp.(master mode) or Input (slave mode)

BREQ

Bus Request Output

Port 2 is an 8-bit bidirectional I/O port. It is bit-wise programmable for input or output via direction bits. For a pin configured as input, the output driver is put into high-impedance state. Port 2 outputs can be configured as push/pull or open drain drivers. The following Port 2 pins serve for alternate functions: EX0IN Fast External Interrupt 0 Input EX1IN Fast External Interrupt 1 Input EX2IN Fast External Interrupt 2 Input EX3IN Fast External Interrupt 3 Input EX4IN Fast External Interrupt 4 Input EX5IN Fast External Interrupt 5 Input EX6IN Fast External Interrupt 6 Input EX7IN Fast External Interrupt 7 Input

Port 5 is a 6-bit input-only port with Schmitt-Trigger char. The pins of Port 5 also serve as timer inputs:

P5.10 P5.11 P5.12 P5.13 P5.14 P5.15

Data Sheet 10 V2.0, 2000-12

98 99 100 1 2 3

100 1 2 3 4 5

I I I I I I

T6EUD GPT2 Timer T6 Ext. Up/Down Ctrl Input T5EUD GPT2 Timer T5 Ext. Up/Down Ctrl Input T6IN GPT2 Timer T6 Count Input T5IN GPT2 Timer T5 Count Input T4EUD GPT1 Timer T4 Ext. Up/Down Ctrl Input T2EUD GPT1 Timer T2 Ext. Up/Down Ctrl Input

Table 2 Pin Definitions and Functions (cont’d)

C165

Symbol Pin Nr

TQFP

7, 28, 38, 49, 69, 78

4, 27, 39, 50,

Pin Nr MQFP

9, 30, 40, 51, 71, 80

6, 29, 41, 52, 72, 79

Input

Function

Outp.

– Digital Supply Voltage:

+ 5 V or + 3 V during normal operation and idle mode.

2.5 V during power down mode.

≥

– Digital Ground.

70, 77

Note: The following behavioural differences must be observed when the bidirectional

reset is active:

• Bit BDRSTEN in register SYSCON cannot be changed after EINIT and is cleared automatically after a reset.

• The reset indication flags always indicate a long hardware reset.

• The PORT0 c onfig uration is tr eated l ike on a hardw are res et. Espe ciall y the bo otstra p loader may be activated when P0L.4 is low.

•Pin RSTIN

may only be connected to external reset devices with an open drain output

driver.

• A short hardware reset is extended to the duration of the internal reset sequence.

Data Sheet 11 V2.0, 2000-12

C165

Functional Description

The architecture of the C165 combines advantages of both RISC and CISC processors and of advanced peripheral subsystems in a very well-balanced way. In addition the on-chip memory blocks allow the design of compact systems with maximum performance. The following block diagram gives an overview of the different on-chip components and of the advanced, high bandwidth internal bus structure of the C165.

Note: All time specifications refer to a CPU clock of 25 MHz

(see definition in the AC Characteristics section).

ProgMem

Internal

ROM

Area

XBUS Control

Port 4

External Bus

Control

Port 6

Port 0

EBC

Instr. / Data

On-Chip XBUS (16-Bit Demux)

Port 1

External Instr. / Data

Interrupt Controller

ASC0

(USART)

BRGen

C166-Core

CPU

SSC

(SPI)

BRGen

PEC

16-Level

Priority

GPT

T2 T3 T4

T5 T6

Interrupt Bus

Peripheral Data Bus

Data

IRAM

Internal

Dual Port

2 KByte

Osc

RAM

XTAL

WDT

Port 2

Port 5Port 3

Figure 4 Block Diagram

The program memory, the internal R AM (IRAM) and the set of generic peripherals are connected to the CPU via separate buses. A fourt h bus, the XBUS, connects ext ernal resources as well as additional on-chip resoures, the X-Peripherals (see Figure 4).

Data Sheet 12 V2.0, 2000-12

C165

Memory Organization

The memory space of the C165 is configured in a Von Neumann architecture which means that code memory, data memory, registers and I/O ports are organized within the same linear address space which includes 16 MBytes. The entire memory space can be accessed bytewise or wordwise. Particular portions of the on-chip memory have additionally been made directly bitaddressable.

The C165 is prepared to incorporate on-chip program memory (not in the ROM-less derivatives, of course) for code or constant data. The internal ROM area can be mapped either to segment 0 or segment 1.

2 KBytes of on-chip Internal RAM (IRAM) are provided as a storage for user defined variables, for th e system stack, general purpo se register banks and even for code. A register bank can consist of up to 16 wordwide (R0 to R15) and/or bytewide (RL0, RH0,

…, RL7, RH7) so-called General Purpose Registers (GPRs). 1024 bytes (2×512 bytes) of the address space are reserved for the Special Func tion

Register areas (SFR space and ESFR sp ace). SFRs are w ordwide registers which are used for controlling and monitoring functions of the different on-chip units. Unused SFR addresses are reserved for future members of the C166 Family.

In order to meet the n eed s of d esi gns w he re m ore m emo ry is required than is provi ded on chip, up to 16 MBytes of external RAM and/or ROM can be connected to the microcontroller.

Data Sheet 13 V2.0, 2000-12

C165

External Bus Controller

All of the external memory accesses are performed by a particular on-chip External Bus Controller (EBC). It can be programmed either to Single Chi p Mode when no external memory is required, or to one of four different external memory access modes, which are as follows:

– 16-/18-/20-/24-bit Addresses, 16-bit Data, Demultiplexed – 16-/18-/20-/24-bit Addresses, 16-bit Data, Multiplexed – 16-/18-/20-/24-bit Addresses, 8-bit Data, Multiplexed – 16-/18-/20-/24-bit Addresses, 8-bit Data, Demultiplexed

In the demultiplexed bus modes, addresses are output on PORT1 and data is input/ output on PORT0 or P0L, respectively. In the mul tiplexed bus modes both addresses and data use PORT0 for input/output.

Important timing characteristics of the external bus interface (Memory Cycle Time, Memory Tri-State Time, Length of ALE and Read Write Delay) have been made programmable to allow the user the adaption of a wide range of different types of memories and external peripherals. In addition, up to 4 indepen dent address windows may be defined (via register pairs ADDRSELx / BUSCONx) which co ntrol the access to diff erent resources with different bus characteristics. These address windows are arranged hierarchically where BUSCON4 overrides BUSCON3 and BUSCON2 overrides BUSCON1. All accesses to locations not covered by these 4 address windows are controlled by BUSCON0.

Up to 5 external CS external glue logic. The C165 offers the possibility to switch the CS unlatched mode. In this m ode the intern al filter logic is switched o ff and the CS are directly genera ted from the address . The u nlatch ed CS

signals (4 windows plus de fault) can be generated in order to save

outputs to an

signals

mode is enabled by setting

CSCFG (SYSCON.6). Access to very sl ow m emories or me morie s wi th va ry ing a ccess times i s sup ported via

a particular ‘Ready’ function. A HOLD

/HLDA protocol is available for bus arbitration and allows to share external resources with other bus ma sters. The bus arbitration is en abled by setting bit HLDEN in register PSW. After setting HLDEN once, pins P6.7 … P6.5 (BREQ

, HLDA, HOLD) are automatically controlled by the EBC. In Master M ode (def ault after reset) the HLDA pin is an output. By setti ng bit DP6.7 to ‘1’ th e Sla ve Mod e is s elec ted w here pin HLD A is switched to input. This allows to directly connect the slave controller to another master controller without gl ue logic.

For applications which require less than 16 MBytes of external memory space, this address space can be restricted to 1 MByte, 256 KByte, or to 64 KByte. In this case Port 4 ou tputs four, two, or no address lines at all. It outputs all 8 address lines, if an address space of 16 MBytes is used.

Data Sheet 14 V2.0, 2000-12

C165

Central Processing Unit (CPU)

The main core of the C PU consis ts of a 4 -stage inst ructi on pipelin e, a 16-b it arithmetic and logic unit (ALU) and dedicated SFRs. Additional hardware has been spent for a separate multiply and divide unit, a bit-mask generator and a barrel shifter.

Based on these hardware prov isions, most of the C165’s instructions c an be executed in just one machine cycle which requires 80 ns at 25 MHz CPU clock. For example, shift and rotate instructions are al ways proce ssed du ring one m achine c ycle in dep endent of the number of bits to be shifted. All multiple-cycle instructio ns have been optimized so that they can be executed very fast as well: branches in 2 cycles, a 16×16 bit multiplication in 5 cycles and a 32-/16 bit division in 10 cycles. Another pipeline optimization, the so-called ‘Jump Cache’, allows reducing the execution time of repeatedly performed jumps in a loop from 2 cycles to 1 cycle.

ROM

CPU

SP STKOV STKUN

Exec. Unit

Instr. Ptr.

Instr. Reg.

4-Stage

Pipeline

PSW

SYSCON

BUSCON 0 BUSCON 1 BUSCON 2 BUSCON 3 BUSCON 4 ADDRSEL 4

Data Page Ptr. Code Seg. Ptr.

MDH

MDL

Mul/Div-HW

Bit-Mask Gen

ALU

(16-bit)

Barrel - Shifter

Context Ptr.

ADDRSEL 1 ADDRSEL 2 ADDRSEL 3

R15

General

Purpose

Registers

Internal

RAM

R15

MCB02147

Figure 5 CPU Block Diagram

Data Sheet 15 V2.0, 2000-12

C165

The CPU has a regis ter context consis ting of up to 16 wordwide GPRs at its disposal. These 16 GPRs are physically allocated within the on-chip RAM area. A Context Pointer (CP) register determines the base address of the active register bank to be accessed by the CPU at any time. The number of register banks is only rest ricted by the available internal RAM space. For easy parameter passing, a register bank may overlap others.

A system stack of up to 1024 words is provided as a storage for temporary data. The system stack is allocated in the on-chip RAM area, and it is accessed by the CPU via the stack pointer (SP) register. Two separate SFRs, STKOV and STKUN, are implicitly compared against the stack pointer value upon each stack access for the detection of a stack overflow or underflow.

The high performance offered by the hardware implementation of the CPU can efficiently be utilized by a programme r via the high ly efficient C165 instru ction set whic h includes the following instruction classes:

– Arithmetic Instructions – Logical Instructions – Boolean Bit Manipulation Instructions – Compare and Loop Control Instructions – Shift and Rotate Instructions – Prioritize Instruction – Data Movement Instructions – System Stack Instructions – Jump and Call Instructions – Return Instructions – System Control Instructions – Miscellaneous Instructions

The basic instruction length is either 2 or 4 bytes. Possible operand types are bits, bytes and words. A variety of direc t, indirect or i mmediate ad dressing mod es are provid ed to specify the required operands.

Data Sheet 16 V2.0, 2000-12

C165

Interrupt System

With an interrupt response tim e within a ran ge fro m just 5 to 12 CPU cl ock s (in case of internal program execution), the C165 is capable of reacting very fast to the occurrence of non-deterministic events.

The architecture of the C165 supports several mechanisms for fast and flexible response to service requests that can be generated from various sources internal or external to the microcontroller. Any of these interrupt requests can be programmed to being serviced by the Interrupt Controller or by the Peripheral Event Controller (PEC).

In contrast to a standard interrupt service where the current program execution is suspended and a branch to the interrupt vector table is performed, just one cycle is

‘stolen’ from the current CPU activity to perform a PEC service. A PEC service implies a single byte or word data transfer be tween any two memory location s with an additio nal increment of either the PEC source or the destination pointer. An individual PEC transfer counter is implici ty decremented for each PEC service except when performing in the continuous transfer mode. When this counter reaches zero, a standard interrupt is performed to the correspon ding source related vector loc ation. PEC services are very well suited, for example, for sup porting the transmissi on or reception of blocks of data. The C165 has 8 PEC channels each of which offers such fast interrupt-driven data transfer capabilities.

A separate control register which con tains an interrupt requ est flag, an interrupt ena ble flag and an interrupt priority bitfield exists for each of the possible interrupt sources. Via its related register, each sou rce can be progra mmed to one of six teen interrupt pri ority levels. Once having been accepted by the CPU, an interrupt service can only be interrupted by a higher prioritized service request. For the standard interrupt processing, each of the possible interrupt sources has a dedicated vector location.

Fast external interrupt inputs are provided to service external interrupts with high precision requirements. These fast interrupt inputs feature programmable edge detection (rising edge, falling edge or both edges).

Software interrupts are supported by means of the ‘TRAP’ instruction in combination with an individual trap (interrupt) number.

Table 3 shows all of the possible C165 interrupt sources and the corresponding

hardware-related interrupt flags, vectors, vector locations and trap (interrupt) numbers.

Note: Interrupt nodes which are not used by associated peripherals, may be used to

generate software controlled interrupt requests by setting the respective interrupt request bit (xIR).

Data Sheet 17 V2.0, 2000-12

Table 3 C165 Interrupt Nodes

C165

Source of Interrupt or PEC Service Request

Request Flag

Enable Flag

Interrupt Vector

Vector Location

External Interrupt 0 CC8IR CC8IE CC8INT 00’0060 External Interrupt 1 CC9IR CC9IE CC9INT 00’0064 External Interrupt 2 CC10IR CC10IE CC10INT 00’0068 External Interrupt 3 CC11IR CC11IE CC11INT 00’006C External Interrupt 4 CC12IR CC12IE CC12INT 00’0070 External Interrupt 5 CC13IR CC13IE CC13INT 00’0074 External Interrupt 6 CC14IR CC14IE CC14INT 00’0078 External Interrupt 7 CC15IR CC15IE CC15INT 00’007C GPT1 Timer 2 T2IR T2IE T2INT 00’0088 GPT1 Timer 3 T3IR T3IE T3INT 00’008C GPT1 Timer 4 T4IR T4IE T4INT 00’0090 GPT2 Timer 5 T5IR T5IE T5INT 00’0094 GPT2 Timer 6 T6IR T6IE T6INT 00’0098

H H H

H H H H

H H

H H H H

Trap Number

GPT2 CAPREL Reg. CRIR CRIE CRINT 00’009C ASC0 Transmit S0TIR S0TIE S0TINT 00’00A8 ASC0 Transmit Buffer S0TBIR S0TBIE S0TBINT 00’011C ASC0 Receive S0RIR S0RIE S0RINT 00’00AC ASC0 Error S0EIR S0EIE S0EINT 00’00B0 SSC Transmit SCTIR SCTIE SCTINT 00’00B4 SSC Receive SCRIR SCRIE SCRINT 00’00B8 SSC Error SCEIR SCEIE SCEINT 00’00BC Unassigned node XP0IR XP0IE XP0I NT 00’0100 Unassigned node XP1IR XP1IE XP1I NT 00’0104 Unassigned node XP2IR XP2IE XP2I NT 00’0108 Unassigned node XP3IR XP3IE XP3I NT 00’010C Unassigned node CC29IR CC29 IE CC29INT 00’0110 Unassigned node CC30IR CC30 IE CC30INT 00’0114 Unassigned node CC31IR CC31 IE CC31INT 00’0118

H H H H

H H H

H H H H

2A 47 2B 2C 2D 2E 2F 40 41 42 43 44 45 46

H H H

H H H H H H H H H

Data Sheet 18 V2.0, 2000-12

C165

The C165 also provide s an excellen t mechanis m to identif y and to proces s exceptions

or error conditions that arise during run-time, so-called ‘Hardware Traps’. Hardware traps cause immediate non-maskable system reaction which is similar to a standard interrupt service (b ranching to a dedicated vector table location). The occurence of a hardware trap is additio nally signified by a n i ndi vid ual bit in the trap fla g regis ter (TFR ). Except when another higher prioritized trap service is in progress, a hardware trap will interrupt any actual program execution. In turn, hardware trap services can normally not be interrupted by standard or PEC interrupts.

Table 4 shows all of the possible exceptions or error conditions that can arise during run-

time:

Table 4 Hardware Trap Summary Exception Condition Trap

Flag

Reset Functions:

– – Hardware Reset – Software Reset – W-dog Timer Overflow

Class A Hardware Traps: – Non-Maskable Interrupt – Stack Overflow – Stack Underflow

NMI

STKOF

STKUF Class B Hardware Traps:

– Undefined Opcode – Protected Instruction

UNDOPC

PRTFLT

Fault

– Illegal Word Operand

ILLOPA

Access

– Illegal Instruction

ILLINA

Access

– Illegal External Bus

ILLBUS

Access

Trap Vector

RESET RESET RESET

NMITRAP STOTRAP STUTRAP

BTRAP BTRAP

BTRAP BTRAP BTRAP

Vector Location

00’0000 00’0000 00’0000

00’0008 00’0010 00’0018

00’0028 00’0028

00’0028 00’0028 00’0028

H H H

H H

Trap Number

Trap Priority

III III III

II II II

I I

I I I

Reserved – – [2C

Software Traps – TRAP Instruction

– – Any

[00’0000 00’01FC

–

]

[0B

–

]

Any

–

]

[00 7F

–

]

–

Current CPU

Priority in steps of 4

Data Sheet 19 V2.0, 2000-12

C165

General Purpose Timer (GPT) Unit

The GPT unit represents a very flexible multifunctional timer/counter structure which may be used for many different tim e related tasks such as event timi ng and counting, pulse width and duty cycle measurements, pulse generation, or pulse multiplication.

The GPT unit incorporates five 16-bit timers which are organized in two separate modules, GPT1 and GPT2. Each timer in eac h mod ule may op erate inde pend ently in a number of different modes, or may be concatenated with another timer of the same module.

Each of the three timers T2 , T3, T4 o f module G PT1 c an be c onfigu red i ndiv iduall y for one of four basic modes of operation, which are Timer, Gated Timer, Counter, and Incremental Interface Mode. In Timer Mode, the input clock for a ti mer is derived from the CPU clock, divided by a programmable prescaler, while Counter Mode allows a timer to be clocked in reference to external events. Pulse width or duty cycle measurement is supporte d in Gated Timer Mode, where the

operation of a timer is controlled by the ‘g ate’ level on an external input pi n. For these purposes, each timer h as one a ssocia ted p ort pin (TxIN ) whic h serves as gate or clo ck input. The maximum resolution of the timers in module GPT1 is 16 TCL.

The count direction (up/down) for each timer is programmable by software or may additionally be altered dynamically by an external signal on a port pin (TxEUD) to facilitate e.g. position tracking.

In Incremental Interface Mod e the GPT1 timers (T2, T3, T4 ) can be directly co nnected to the incremental posi tion senso r signal s A and B via their respectiv e inputs Tx IN and TxEUD. Direction and count si gnals are internally derived from these two in put signa ls, so the contents of the re spe ctiv e ti mer Tx co rresp onds to the s en sor p osi tion . The third position sensor signal TOP0 can be connected to an interrupt input.

Timer T3 has an output toggle latch (T3OTL) which changes its state on each timer overflow/underflow. The state of this latch may be output on pin T3OUT e.g. for time out monitoring of external hardware com ponents, or may be used interna lly to clock ti mers T2 and T4 for measuring long time periods with high resolution.

In addition to their basic operating modes, timers T2 and T4 may be configured as reload or capture registers for timer T3. When used as capture or re load registers, timers T2 and T4 are stopped. The contents of timer T3 is captured into T2 or T4 in response to a signal at their associated input pins (TxIN). Timer T3 is reloaded with the contents of T2 or T4 triggered either by an external signal or by a selectable state transition of its toggle latch T3OTL. When bot h T2 a nd T 4 are configured to alternate ly re loa d T3 on opposite state transitions of T3OT L with the low and hig h tim es of a PWM sign al, th is signa l can be constantly generated without software intervention.

Data Sheet 20 V2.0, 2000-12

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