INFINEON C164CI, C164SI, C164CL User Manual

Data Sheet, V2.0, May 2001

C164CI/SI
C164CL/SL

16-Bit Single-Chip Microcontroller

Microcontrollers

Never stop thinking.

Edition 2001-05

Published by Infineon Technologies AG,
St.-Martin-Strasse 53,
D-81541 München, Germany

© Infineon Technologies AG 2001.

All Rights Reserved.

Attention please!

The information herein is given to describe certain components and shall not be considered as warranted
characteristics.

Terms of delivery and rights to technical change reserved.
We hereby disclaim any and all warranties, including but not limited to warranties of non-infringement, regarding

circuits, descriptions and charts stated herein.
Infineon Technologies is an approved CECC manufacturer.

Information

For further information on technology, delivery terms and conditions and prices please contact your nearest
Infineon Technologies Office in Germany or our Infineon Technologies Representatives worldwide.

Warnings

Due to technical requirements components may contain dangerous substances. For information on the types in
question please contact your nearest Infineon Technologies Office.

Infineon Technologies Components may only be used in life-support devices or systems with the express written
approval of Infineon Technologies, if a failure of such components can reasonably be expected to cause the failure
of that life-support device or system, or to affect the safety or effectiveness of that device or system. Life support
devices or systems are intended to be implanted in the human body, or to support and/or maintain and sustain
and/or protect human life. If they fail, it is reasonable to assume that the health of the user or other persons may
be endangered.

Data Sheet, V2.0, May 2001

C164CI/SI
C164CL/SL

16-Bit Single-Chip Microcontroller

Microcontrollers

Never stop thinking.

C164CI

Revision History: 2001-05 V2.0

Previous Version: 1999-08

1998-02 (Preliminary)

04.97 (Advance Information)

Page Subjects (major changes since last revision)

1)

All Converted to Infineon layout

1 Operating frequency up to 25 MHz

1 et al. References to Flash removed

1 Timer Unit with three timers

1, 12, 73 On-chip XRAM described

2 Derivative table updated

10 Supply voltage is 5 V

21 Functionality of reduced CAPCOM6 corrected

22f Timer description improved

29, 30 Sections “Oscillator Watchdog” and “Power Management” added

37 POCON reset values adjusted

41 to 73 Parameter section reworked

1)

These changes refer to the last two versions. Version 1998-02 covers OTP and ROM derivatives, while version
1999-08 ist the most recent one.

Controller Area Network (CAN): License of Robert Bosch GmbH

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Your feedback will help us to continuously improve the quality of this document.
Please send your proposal (including a reference to this document) to:

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C164CI16-Bit Single-Chip Microcontroller

C166 Family

C164CI/SI, C164CL/SL

• High Performance 16-bit CPU with 4-Stage Pipeline
– 80 ns Instruction Cycle Time at 25 MHz CPU Clock
– 400 ns Multiplication (16 × 16 bit), 800 ns Division (32 / 16 bit)
– Enhanced Boolean Bit Manipulation Facilities
– Additional Instructions to Support HLL and Operating Systems
– Register-Based Design with Multiple Variable Register Banks
– Single-Cycle Context Switching Support
– 16 MBytes Total Linear Address Space for Code and Data
– 1024 Bytes On-Chip Special Function Register Area

• 16-Priority-Level Interrupt System with 32 Sources, Sample-Rate down to 40 ns

• 8-Channel Interrupt-Driven Single-Cycle Data Transfer Facilities via
Peripheral Event Controller (PEC)

• Clock Generation via on-chip PLL (factors 1:1.5/2/2.5/3/4/5),
via prescaler or via direct clock input

• On-Chip Memory Modules
– 2 KBytes On-Chip Internal RAM (IRAM)
– 2 KBytes On-Chip Extension RAM (XRAM)
– up to 64 KBytes On-Chip Program Mask ROM or OTP Memory

• On-Chip Peripheral Modules
– 8-Channel 10-bit A/D Converter with Programmable Conversion Time

down to 7.8 µs
– 8-Channel General Purpose Capture/Compare Unit (CAPCOM2)
– Capture/Compare Unit for flexible PWM Signal Generation (CAPCOM6)

(3/6 Capture/Compare Channels and 1 Compare Channel)
– Multi-Functional General Purpose Timer Unit with 3 Timers
– Two Serial Channels (Synchronous/Asynchronous and High-Speed-Synchronous)
– On-Chip CAN Interface (Rev. 2.0B active) with 15 Message Objects

(Full CAN/Basic CAN)
– On-Chip Real Time Clock

• Up to 4 MBytes External Address Space for Code and Data
– Programmable External Bus Characteristics for Different Address Ranges
– Multiplexed or Demultiplexed External Address/Data Buses with 8-Bit or 16-Bit

Data Bus Width

– Four Optional Programmable Chip-Select Signals

• Idle, Sleep, and Power Down Modes with Flexible Power Management

• Programmable Watchdog Timer and Oscillator Watchdog

• Up to 59 General Purpose I/O Lines,
partly with Selectable Input Thresholds and Hysteresis

Data Sheet 1 V2.0, 2001-05

C164CI/SI

C164CL/SL

• Supported by a Large Range of Development Tools like C-Compilers,
Macro-Assembler Packages, Emulators, Evaluation Boards, HLL-Debuggers,
Simulators, Logic Analyzer Disassemblers, Programming Boards

• On-Chip Bootstrap Loader

• 80-Pin MQFP Package, 0.65 mm pitch

This document describes several derivatives of the C164 group. Table 1 enumerates
these derivatives and summarizes the differences. As this document refers to all of these
derivatives, some descriptions may not apply to a specific product.

Table 1 C164CI Derivative Synopsis

Derivative

1)

Program
Memory

CAPCOM6 CAN Interf. Operating

Frequency

SAK-C164CI-8R[25]M
SAF-C164CI-8R[25]M

SAK-C164SI-8R[25]M
SAF-C164SI-8R[25]M

SAK-C164CL-8R[25]M
SAF-C164CL-8R[25]M

SAK-C164SL-8R[25]M
SAF-C164SL-8R[25]M

SAK-C164CL-6R[25]M
SAF-C164CL-6R[25]M

SAK-C164SL-6R[25]M
SAF-C164SL-6R[25]M

SAK-C164CI-L[25]M
SAF-C164CI-L[25]M

SAK-C164CI-8EM

64 KByte ROM Full function CAN1 20 MHz,

[25 MHz]

64 KByte ROM Full function --- 20 MHz,

[25 MHz]

64 KByte ROM Reduced fct. CAN1 20 MHz,

[25 MHz]

64 KByte ROM Reduced fct. --- 20 MHz,

[25 MHz]

48 KByte ROM Reduced fct. CAN1 20 MHz,

[25 MHz]

48 KByte ROM Reduced fct. --- 20 MHz,

[25 MHz]

--- Full function CAN1 20 MHz,
[25 MHz]

64 KByte OTP Full function CAN1 20 MHz

SAF-C164CI-8EM

1)

This Data Sheet is valid for ROM(less) devices starting with and including design step AB, and for OTP devices
starting with and including design step DA.

For simplicity all versions are referred to by the term C164CI throughout this document.

Data Sheet 2 V2.0, 2001-05

C164CI/SI

C164CL/SL

Ordering Information

The ordering code for Infineon microcontrollers provides an exact reference to the
required product. This ordering code identifies:

• the derivative itself, i.e. its function set, the temperature range, and the supply voltage

• the package and the type of delivery.

For the available ordering codes for the C164CI please refer to the “Product Catalog
Microcontrollers”, which summarizes all available microcontroller variants.

Note: The ordering codes for Mask-ROM versions are defined for each product after

verification of the respective ROM code.

Introduction

The C164CI derivatives of the Infineon C166 Family of full featured single-chip CMOS
microcontrollers are especially suited for cost sensitive applications. They combine high
CPU performance (up to 12.5 million instructions per second) with high peripheral
functionality and enhanced IO-capabilities. They also provide clock generation via PLL
and various on-chip memory modules such as program ROM or OTP, internal RAM, and
extension RAM.

XTAL1

XTAL2

RSTIN

RSTOUT

NMI

EA

ALE

RD

WR/WRL

V

AREFVAGND

C164CI

V

DDVSS

Port 0
16 Bit

Port 1
16 Bit

Port 3
9 Bit

Port 4
6 Bit

Port 8
4 Bit

Port 5
8 Bit

MCL04869

Figure 1 Logic Symbol

Data Sheet 3 V2.0, 2001-05

Pin Configuration

(top view)

D
N
G
A

P5.3/AN3

V

P5.0/AN0

P5.2/AN2

P5.1/AN1

/*

/*

/*

/*

C16IO

P8.1/CC17IO

P8.3/CC19IO

P8.2/CC18IO

P8.0/C

I

NM

T

P1H.7/A15/CC27IO

RSTOU

RSTIN

P1H.6/A14/CC26IO

/EX2IN

/EX1IN

S2

S1
6PO
CC

CC6PO

D

P1H.3/A11/EXIN/T7IN

P1H.5/A13/CC25IO

P1H.4/A12/CC24IO

D

P1H.2/A10/

V

P1H.1/A9/

C164CI/SI

C164CL/SL

V

P5.4/AN4/T2EUD 2
P5.5/AN5/T4EUD

P5.6/AN6/T2IN
P5.7/AN7/T4IN

P3.4/T3EUD

P3.11/RxD0

P3.12/BHE/WRH

P3.13/SCLK

P3.15/CLKOUT/FOUT

P4.0/A16/CS3
P4.1/A17/CS2
P4.2/A18/CS1

AREF

V
V

P3.6/T3IN
P3.8/MRST
P3.9/MTSR

P3.10/TxD0

V

SS

DD

SS

1

3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20

80

21

V

797877

23

24

22

D
D

*/P4.5/A20

*/P4.6/A21

P4.3/A19/CS0

76

25

RD

75

26

RL

R/W
W

74

27

ALE

737271

C164CI

30

29

28

Vpp/EA

P0L.1/AD1

P0L.0/AD0

70

68

69

33

31

32

P0L.2/AD2

P0L.4/AD4

P0L.3/AD3

676665

34

36

35

P0L.5/AD5

P0L.7/AD7

P0L.6/AD6

646362

37

38

39

61

40

V

P0H.0/AD8

P0H.1/AD9

P0H.2/AD10

V

60

SS

P1H.0/A8/CC6POS0/EX0IN

59
58

P1L.7/A7/CTRAP
P1L.6/A6/COUT6357

V

56

SS

XTAL155
XTAL254

V

53

DD

P1L.5/A5/COUT6252
P1L.4/A4/CC6251
P1L.3/A3/COUT61

50

P1L.2/A2/CC6149
P1L.1/A1/COUT6048
P1L.0/A0/CC60

47

P0H.7/AD1546
P0H.6/AD1445
P0H.5/AD13

44
43

P0H.4/AD12
P0H.3/AD1142

V

41

SS

D
D

MCP04870

Figure 2

*) The marked pins of Port 4 and Port 8 can have CAN interface lines assigned to them.

Table 2 on the pages below lists the possible assignments.

The marked input signals are available only in devices with a full-function CAPCOM6.
They are not available in devices with a reduced-function CAPCOM6.

Data Sheet 4 V2.0, 2001-05

Table 2 Pin Definitions and Functions

C164CI/SI

C164CL/SL

Symbol Pin

No.

P5

P5.0
P5.1
P5.2
P5.3
P5.4
P5.5
P5.6

P5.7

P3

P3.4
P3.6
P3.8
P3.9
P3.10
P3.11
P3.12

P3.13
P3.15

76
77
78
79
2
3
4

5

8
9
10
11
12
13
14

15
16

Input
Outp.

I

I
I
I
I
I
I
I

I

IO

I
I
I/O
I/O
O
I/O
O
O
I/O
O
O

Function

Port 5 is an 8-bit input-only port with Schmitt-Trigger charact.
The pins of Port 5 also serve as analog input channels for the
A/D converter, or they serve as timer inputs:
AN0
AN1
AN2
AN3
AN4, T2EUD GPT1 Timer T2 Ext. Up/Down Ctrl. Inp.
AN5, T4EUD GPT1 Timer T4 Ext. Up/Down Ctrl. Inp.
AN6, T2IN GPT1 Timer T2 Input for

Count/Gate/Reload/Capture

AN7, T4IN GPT1 Timer T4 Input for

Count/Gate/Reload/Capture

Port 3 is a 9-bit bidirectional I/O port. It is bit-wise
programmable for input or output via direction bits. For a pin
configured as input, the output driver is put into high­impedance state. Port 3 outputs can be configured as push/
pull or open drain drivers. The input threshold of Port 3 is
selectable (TTL or special).
The following Port 3 pins also serve for alternate functions:
T3EUD GPT1 Timer T3 External Up/Down Control Input
T3IN GPT1 Timer T3 Count/Gate Input
MRST SSC Master-Receive/Slave-Transmit Inp./Outp.
MTSR SSC Master-Transmit/Slave-Receive Outp./Inp.
TxD0 ASC0 Clock/Data Output (Async./Sync.)
RxD0 ASC0 Data Input (Async.) or Inp./Outp. (Sync.)
BHE
WRH
SCLK SSC Master Clock Output / Slave Clock Input.
CLKOUT System Clock Output (= CPU Clock),
FOUT Programmable Frequency Output

External Memory High Byte Enable Signal,
External Memory High Byte Write Strobe

Data Sheet 5 V2.0, 2001-05

Table 2 Pin Definitions and Functions (cont’d)

C164CI/SI

C164CL/SL

Symbol Pin

No.

P4

P4.0

P4.1

P4.2

P4.3

P4.5

P4.6

17

18

19

22

23

24

Input
Outp.

IO

O
O
O
O
O
O
O
O
O
I
O
O

Function

Port 4 is a 6-bit bidirectional I/O port. It is bit-wise
programmable for input or output via direction bits. For a pin
configured as input, the output driver is put into high­impedance state. Port 4 outputs can be configured as push/
pull or open drain drivers. The input threshold of Port 4 is
selectable (TTL or special).
Port 4 can be used to output the segment address lines, the
optional chip select lines, and for serial interface lines:

1)

A16 Least Significant Segment Address Line,
CS3 Chip Select 3 Output
A17 Segment Address Line,
CS2

Chip Select 2 Output
A18 Segment Address Line,
CS1

Chip Select 1 Output
A19 Segment Address Line,
CS0

Chip Select 0 Output
A20 Segment Address Line,
CAN1_RxD CAN 1 Receive Data Input
A21 Most Significant Segment Address Line,
CAN1_TxD CAN 1 Transmit Data Output

RD

25 O External Memory Read Strobe. RD is activated for every

external instruction or data read access.

WR
WRL

/

26 O External Memory Write Strobe. In WR-mode this pin is

activated for every external data write access. In WRL

-mode
this pin is activated for low byte data write accesses on a
16-bit bus, and for every data write access on an 8-bit bus.
See WRCFG in register SYSCON for mode selection.

ALE 27 O Address Latch Enable Output. Can be used for latching the

address into external memory or an address latch in the
multiplexed bus modes.

Data Sheet 6 V2.0, 2001-05

Table 2 Pin Definitions and Functions (cont’d)

C164CI/SI

C164CL/SL

Symbol Pin

No.

EA/V

28 I External Access Enable pin.

PP

PORT0

P0L.0-7

29­36

P0H.0-7

37-39,
42-46

Input

Function

Outp.

A low level at this pin during and after Reset forces the

C164CI to latch the configuration from PORT0 and pin RD
and to begin instruction execution out of external memory.
A high level forces the C164CI to latch the configuration
from pins RD

and ALE, and to begin instruction execution out
of the internal program memory.
“ROMless” versions must have this pin tied to ‘0’.

Note: This pin also accepts the programming voltage for the

OTP derivatives.

IO PORT0 consists of the two 8-bit bidirectional I/O ports P0L

and P0H. It is bit-wise programmable for input or output via
direction bits. For a pin configured as input, the output driver
is put into high-impedance state.
In case of an external bus configuration, PORT0 serves as
the address (A) and address/data (AD) bus in multiplexed
bus modes and as the data (D) bus in demultiplexed bus
modes.

Demultiplexed bus modes:

Data Path Width: 8-bit 16-bit
P0L.0 – P0L.7: D0 – D7 D0 – D7
P0H.0 – P0H.7: I/O D8 – D15

Multiplexed bus modes:

Data Path Width: 8-bit 16-bit
P0L.0 – P0L.7: AD0 – AD7 AD0 – AD7
P0H.0 – P0H.7: A8 – A15 AD8 – AD15

,

Data Sheet 7 V2.0, 2001-05

Table 2 Pin Definitions and Functions (cont’d)

C164CI/SI

C164CL/SL

Symbol Pin

No.

PORT1

P1L.0-7

P1H.0-7

P1L.0
P1L.1
P1L.2
P1L.3
P1L.4
P1L.5
P1L.6
P1L.7

P1H.0

P1H.1

P1H.2

P1H.3

P1H.4
P1H.5
P1H.6
P1H.7

47-52,
57-59
59,
62-68

47
48
49
50
51
52
57
58

59

62

63

64

65
66
67
68

Input
Outp.

IO

I/O
O
I/O
O
I/O
O
O
I

I
I
I
I
I
I
I

I/O
I/O
I/O
I/O

Function

PORT1 consists of the two 8-bit bidirectional I/O ports P1L
and P1H. It is bit-wise programmable for input or output via
direction bits. For a pin configured as input, the output driver
is put into high-impedance state. PORT1 is used as the
16-bit address bus (A) in demultiplexed bus modes and also
after switching from a demultiplexed bus mode to a
multiplexed bus mode.
The following PORT1 pins also serve for alt. functions:
CC60 CAPCOM6: Input / Output of Channel 0
COUT60 CAPCOM6: Output of Channel 0
CC61 CAPCOM6: Input / Output of Channel 1
COUT61 CAPCOM6: Output of Channel 1
CC62 CAPCOM6: Input / Output of Channel 2
COUT62 CAPCOM6: Output of Channel 2
COUT63 Output of 10-bit Compare Channel
CTRAP
CTRAP
level on this pin switches the compare outputs of the
CAPCOM6 unit to the logic level defined by software.
CC6POS0
EX0IN Fast External Interrupt 0 Input
CC6POS1
EX1IN Fast External Interrupt 1 Input
CC6POS2
EX2IN Fast External Interrupt 2 Input
EX3IN Fast External Interrupt 3 Input,
T7IN CAPCOM2: Timer T7 Count Input
CC24IO CAPCOM2: CC24 Capture Inp./Compare Outp.
CC25IO CAPCOM2: CC25 Capture Inp./Compare Outp.
CC26IO CAPCOM2: CC26 Capture Inp./Compare Outp.
CC27IO CAPCOM2: CC27 Capture Inp./Compare Outp.

CAPCOM6: Trap Input

is an input pin with an internal pullup resistor. A low

CAPCOM6: Position 0 Input, **)

CAPCOM6: Position 1 Input, **)

CAPCOM6: Position 2 Input, **)

Note: The marked (**) input signals are available only in

devices with a full function CAPCOM6.

Data Sheet 8 V2.0, 2001-05

Table 2 Pin Definitions and Functions (cont’d)

C164CI/SI

C164CL/SL

Symbol Pin

No.

XTAL2
XTAL15455

RSTIN

69 I/O Reset Input with Schmitt-Trigger characteristics. A low level

Input
Outp.

O
I

Function

XTAL2: Output of the oscillator amplifier circuit.
XTAL1: Input to the oscillator amplifier and input to

the internal clock generator
To clock the device from an external source, drive XTAL1,
while leaving XTAL2 unconnected. Minimum and maximum
high/low and rise/fall times specified in the AC
Characteristics must be observed.

at this pin while the oscillator is running resets the C164CI.
An internal pullup resistor permits power-on reset using only

V

a capacitor connected to
A spike filter suppresses input pulses <10 ns. Input pulses
>100 ns safely pass the filter. The minimum duration for a
safe recognition should be 100 ns + 2 CPU clock cycles.
In bidirectional reset mode (enabled by setting bit BDRSTEN
in register SYSCON) the RSTIN
for the duration of the internal reset sequence upon any reset
(HW, SW, WDT). See note below this table.

.

SS

line is internally pulled low

RST
OUT

NMI

70 O Internal Reset Indication Output. This pin is set to a low level

when the part is executing either a hardware-, a software- or
a watchdog timer reset. RSTOUT
(end of initialization) instruction is executed.

71 I Non-Maskable Interrupt Input. A high to low transition at this

pin causes the CPU to vector to the NMI trap routine. When
the PWRDN (power down) instruction is executed, the NMI
pin must be low in order to force the C164CI to go into power
down mode. If NMI
part will continue to run in normal mode.
If not used, pin NMI

is high, when PWRDN is executed, the

should be pulled high externally.

remains low until the EINIT

Data Sheet 9 V2.0, 2001-05

Table 2 Pin Definitions and Functions (cont’d)

C164CI/SI

C164CL/SL

Symbol Pin

No.

P8

P8.0

P8.1

P8.2

P8.3

V

AREF

72

73

74

75

1 – Reference voltage for the A/D converter.

Input
Outp.

IO

I/O
I
I/O
O
I/O
I
I/O
O

Function

Port 8 is a 4-bit bidirectional I/O port. It is bit-wise
programmable for input or output via direction bits. For a pin
configured as input, the output driver is put into high­impedance state. Port 8 outputs can be configured as push/
pull or open drain drivers. The input threshold of Port 8 is
selectable (TTL or special). Port 8 pins provide inputs/
outputs for CAPCOM2 and serial interface lines.

1)

CC16IO CAPCOM2: CC16 Capture Inp./Compare Outp.,
CAN1_RxD CAN 1 Receive Data Input
CC17IO CAPCOM2: CC17 Capture Inp./Compare Outp.,
CAN1_TxD CAN 1 Transmit Data Output
CC18IO CAPCOM2: CC18 Capture Inp./Compare Outp.,
CAN1_RxD CAN 1 Receive Data Input
CC19IO CAPCOM2: CC19 Capture Inp./Compare Outp.,
CAN1_TxD CAN 1 Transmit Data Output

V

AGND

V

DD

V

SS

80 – Reference ground for the A/D converter.

7, 21,
40, 53,
61

6, 20,

– Digital Supply Voltage:

+5 V during normal operation and idle mode.
≥2.5 V during power down mode.

– Digital Ground.
41, 56,
60

1)

The CAN interface lines are assigned to ports P4 and P8 under software control. Within the CAN module
several assignments can be selected.

Note: The following behavioural differences must be observed when the bidirectional

reset is active:

• Bit BDRSTEN in register SYSCON cannot be changed after EINIT and is cleared
automatically after a reset.

• The reset indication flags always indicate a long hardware reset.

• The PORT0 configuration is treated as if it were a hardware reset. In particular, the

bootstrap loader may be activated when P0L.4 is low.

• Pin RSTIN

may only be connected to external reset devices with an open drain output

driver.

• A short hardware reset is extended to the duration of the internal reset sequence.

Data Sheet 10 V2.0, 2001-05

C164CI/SI

C164CL/SL

Functional Description

The architecture of the C164CI combines advantages of both RISC and CISC
processors and of advanced peripheral subsystems in a very well-balanced way. In
addition the on-chip memory blocks allow the design of compact systems with maximum
performance.
The following block diagram gives an overview of the different on-chip components and
of the advanced, high bandwidth internal bus structure of the C164CI.

Note: All time specifications refer to a CPU clock of 25 MHz

(see definition in the AC Characteristics section).

6

ProgMem

ROM: 48/64

OTP: 64

KByte

XRAM

2 KByte

CAN

Rev 2.0B active

EBC

XBUS Control

rt 4
o

External Bus

P

Control

Port 0

32

Instr. / Data

16

)
x
u

m
e

it D

-B

16

6
(1

S
U
B
X
ip
h

-C
n
O

16 8

ADC

10-Bit

8

Channels

Port 5 Port 3

External Instr. / Data

Interrupt Controller

ASC0

(USART)

BRGen

C166-Core

CPU

SSC

(SPI)

BRGen

PEC

16-Level

Priority

GPT1

T2

T3

T4

9

Interrupt Bus

Peripheral Data Bus

Data

Data

16

CCOM2

16

rt
o

l P

16

a
u

D

RTC WDT

CCOM6

T7

T8

Port 8

IRAM

Internal

RAM

2 KByte

Osc / PLL

T12

T13

4

MCB04323_4ci

rt 1
o
P

XTAL

16

Figure 3 Block Diagram

The program memory, the internal RAM (IRAM) and the set of generic peripherals are
connected to the CPU via separate buses. A fourth bus, the XBUS, connects external
resources as well as additional on-chip resoures, the X-Peripherals (see Figure 3).

The XBUS resources (XRAM, CAN) of the C164CI can be enabled or disabled during
initialization by setting the general X-Peripheral enable bit XPEN (SYSCON.2). Modules
that are disabled consume neither address space nor port pins.

Data Sheet 11 V2.0, 2001-05

C164CI/SI

C164CL/SL

Memory Organization

The memory space of the C164CI is configured in a Von Neumann architecture which
means that code memory, data memory, registers and I/O ports are organized within the
same linear address space which includes 16 MBytes. The entire memory space can be
accessed bytewise or wordwise. Particular portions of the on-chip memory have
additionally been made directly bitaddressable.

The C164CI incorporates 64 KBytes of on-chip OTP memory or 64/48 KBytes of on-chip
mask-programmable ROM (not in the ROM-less derivative, of course) for code or
constant data. The lower 32 KBytes of the on-chip ROM/OTP can be mapped either to
segment 0 or segment 1.
The OTP memory can be programmed by the CPU itself (in system, e.g. during booting)
or directly via an external interface (e.g. before assembly). The programming time is

V

approx. 100 µs per word. An external programming voltage
supplied for this purpose (via pin EA

/VPP).

=11.5V must be

PP

2 KBytes of on-chip Internal RAM (IRAM) are provided as a storage for user defined
variables, for the system stack, general purpose register banks and even for code. A
register bank can consist of up to 16 wordwide (R0 to R15) and/or bytewide (RL0, RH0,
…, RL7, RH7) so-called General Purpose Registers (GPRs).

1024 bytes (2 × 512 bytes) of the address space are reserved for the Special Function
Register areas (SFR space and ESFR space). SFRs are wordwide registers which are
used for controlling and monitoring functions of the different on-chip units. Unused SFR
addresses are reserved for future members of the C166 Family.

2 KBytes of on-chip Extension RAM (XRAM) are provided to store user data, user
stacks, or code. The XRAM is accessed like external memory and therefore cannot be
used for the system stack or for register banks and is not bitaddressable. The XRAM
permits 16-bit accesses with maximum speed.

In order to meet the needs of designs where more memory is required than is provided
on chip, up to 4 MBytes of external RAM and/or ROM can be connected to the
microcontroller.

Data Sheet 12 V2.0, 2001-05

C164CI/SI

C164CL/SL

External Bus Controller

All of the external memory accesses are performed by a particular on-chip External Bus
Controller (EBC). It can be programmed either to Single Chip Mode when no external
memory is required, or to one of four different external memory access modes, which are
as follows:

– 16-/18-/20-/22-bit Addresses, 16-bit Data, Demultiplexed
– 16-/18-/20-/22-bit Addresses, 16-bit Data, Multiplexed
– 16-/18-/20-/22-bit Addresses, 8-bit Data, Multiplexed
– 16-/18-/20-/22-bit Addresses, 8-bit Data, Demultiplexed

In the demultiplexed bus modes, addresses are output on PORT1 and data is input/
output on PORT0 or P0L, respectively. In the multiplexed bus modes both addresses
and data use PORT0 for input/output.

Important timing characteristics of the external bus interface (Memory Cycle Time,
Memory Tri-State Time, Length of ALE and Read Write Delay) have been made
programmable to allow the user the adaption of a wide range of different types of
memories and external peripherals.
In addition, up to 4 independent address windows may be defined (via register pairs
ADDRSELx / BUSCONx) which control the access to different resources with different
bus characteristics. These address windows are arranged hierarchically where
BUSCON4 overrides BUSCON3 and BUSCON2 overrides BUSCON1. All accesses to
locations not covered by these 4 address windows are controlled by BUSCON0.

Up to 4 external CS
external glue logic. The C164CI offers the possibility to switch the CS
unlatched mode. In this mode the internal filter logic is switched off and the CS
are directly generated from the address. The unlatched CS
CSCFG (SYSCON.6).

For applications which require less than 4 MBytes of external memory space, this
address space can be restricted to 1 MByte, 256 KByte, or to 64 KByte. In this case
Port 4 outputs four, two, or no address lines at all. It outputs all 6 address lines, if an
address space of 4 MBytes is used.

Note: When the on-chip CAN Module is used with the interface lines assigned to Port 4,

the CAN lines override the segment address lines and the segment address
output on Port 4 is therefore limited to 4 bits i.e. address lines A19 … A16.

signals (3 windows plus default) can be generated in order to save

outputs to an

signals

mode is enabled by setting

Data Sheet 13 V2.0, 2001-05

C164CI/SI

C164CL/SL

Central Processing Unit (CPU)

The main core of the CPU consists of a 4-stage instruction pipeline, a 16-bit arithmetic
and logic unit (ALU) and dedicated SFRs. Additional hardware has been spent for a
separate multiply and divide unit, a bit-mask generator and a barrel shifter.

Based on these hardware provisions, most of the C164CI’s instructions can be executed
in just one machine cycle which requires 2 CPU clocks (4 TCL). For example, shift and
rotate instructions are always processed during one machine cycle independent of the
number of bits to be shifted. All multiple-cycle instructions have been optimized so that
they can be executed very fast as well: branches in 2 cycles, a 16 × 16 bit multiplication
in 5 cycles and a 32-/16-bit division in 10 cycles. Another pipeline optimization, the so­called ‘Jump Cache’, reduces the execution time of repeatedly performed jumps in a loop
from 2 cycles to 1 cycle.

ROM

32

CPU

SP
STKOV
STKUN

Exec. Unit

Instr. Ptr.

Instr. Reg.

4-Stage
Pipeline

PSW

SYSCON

BUSCON 0
BUSCON 1
BUSCON 2
BUSCON 3
BUSCON 4 ADDRSEL 4

Data Page Ptr. Code Seg. Ptr.

MDH
MDL

Mul/Div-HW

Bit-Mask Gen

ALU

(16-bit)

Barrel - Shifter

Context Ptr.

ADDRSEL 1
ADDRSEL 2
ADDRSEL 3

R15

General

Purpose

Registers

R0

16

Internal

RAM

R15

R0

16

MCB02147

Figure 4 CPU Block Diagram

Data Sheet 14 V2.0, 2001-05

C164CI/SI

C164CL/SL

The CPU has a register context consisting of up to 16 wordwide GPRs at its disposal.
These 16 GPRs are physically allocated within the on-chip RAM area. A Context Pointer
(CP) register determines the base address of the active register bank to be accessed by
the CPU at any time. The number of register banks is only restricted by the available
internal RAM space. For easy parameter passing, a register bank may overlap others.

A system stack of up to 1024 words is provided as a storage for temporary data. The
system stack is allocated in the on-chip RAM area, and it is accessed by the CPU via the
stack pointer (SP) register. Two separate SFRs, STKOV and STKUN, are implicitly
compared against the stack pointer value upon each stack access for the detection of a
stack overflow or underflow.

The high performance offered by the hardware implementation of the CPU can efficiently
be utilized by a programmer via the highly efficient C164CI instruction set which includes
the following instruction classes:

– Arithmetic Instructions
– Logical Instructions
– Boolean Bit Manipulation Instructions
– Compare and Loop Control Instructions
– Shift and Rotate Instructions
– Prioritize Instruction
– Data Movement Instructions
– System Stack Instructions
– Jump and Call Instructions
– Return Instructions
– System Control Instructions
– Miscellaneous Instructions

The basic instruction length is either 2 or 4 bytes. Possible operand types are bits, bytes
and words. A variety of direct, indirect or immediate addressing modes are provided to
specify the required operands.

Data Sheet 15 V2.0, 2001-05

C164CI/SI

C164CL/SL

Interrupt System

With an interrupt response time within a range from just 5 to 12 CPU clocks (in case of
internal program execution), the C164CI is capable of reacting very fast to the
occurrence of non-deterministic events.

The architecture of the C164CI supports several mechanisms for fast and flexible
response to service requests that can be generated from various sources internal or
external to the microcontroller. Any of these interrupt requests can be programmed to
being serviced by the Interrupt Controller or by the Peripheral Event Controller (PEC).

In contrast to a standard interrupt service where the current program execution is
suspended and a branch to the interrupt vector table is performed, just one cycle is
‘stolen’ from the current CPU activity to perform a PEC service. A PEC service implies a
single byte or word data transfer between any two memory locations with an additional
increment of either the PEC source or the destination pointer. An individual PEC transfer
counter is implicity decremented for each PEC service except when performing in the
continuous transfer mode. When this counter reaches zero, a standard interrupt is
performed to the corresponding source related vector location. PEC services are very
well suited, for example, for supporting the transmission or reception of blocks of data.
The C164CI has 8 PEC channels each of which offers such fast interrupt-driven data
transfer capabilities.

A separate control register which contains an interrupt request flag, an interrupt enable
flag and an interrupt priority bitfield exists for each of the possible interrupt sources. Via
its related register, each source can be programmed to one of sixteen interrupt priority
levels. Once having been accepted by the CPU, an interrupt service can only be
interrupted by a higher prioritized service request. For the standard interrupt processing,
each of the possible interrupt sources has a dedicated vector location.

Fast external interrupt inputs are provided to service external interrupts with high
precision requirements. These fast interrupt inputs feature programmable edge
detection (rising edge, falling edge or both edges).

Software interrupts are supported by means of the ‘TRAP’ instruction in combination with
an individual trap (interrupt) number.

Table 3 shows all of the possible C164CI interrupt sources and the corresponding

hardware-related interrupt flags, vectors, vector locations and trap (interrupt) numbers.

Note: Interrupt nodes which are not used by associated peripherals, may be used to

generate software controlled interrupt requests by setting the respective interrupt
request bit (xIR).

Data Sheet 16 V2.0, 2001-05

Table 3 C164CI Interrupt Nodes

C164CI/SI

C164CL/SL

Source of Interrupt or
PEC Service Request

Request
Flag

Enable
Flag

Interrupt
Vector

Vector
Location

Fast External Interrupt 0 CC8IR CC8IE CC8INT 00’0060

Fast External Interrupt 1 CC9IR CC9IE CC9INT 00’0064

Fast External Interrupt 2 CC10IR CC10IE CC10INT 00’0068

Fast External Interrupt 3 CC11IR CC11IE CC11INT 00’006C

GPT1 Timer 2 T2IR T2IE T2INT 00’0088

GPT1 Timer 3 T3IR T3IE T3INT 00’008C

GPT1 Timer 4 T4IR T4IE T4INT 00’0090

A/D Conversion

ADCIR ADCIE ADCINT 00’00A0

Complete

A/D Overrun Error ADEIR ADEIE ADEINT 00’00A4

ASC0 Transmit S0TIR S0TIE S0TINT 00’00A8

ASC0 Transmit Buffer S0TBIR S0TBIE S0TBINT 00’011C

ASC0 Receive S0RIR S0RIE S0RINT 00’00AC

H

H

H

H

H

H

H

H

H

H

H

H

Trap
Number

18

H

19

H

1A

H

1B

H

22

H

23

H

24

H

28

H

29

H

2A

H

47

H

2B

H

ASC0 Error S0EIR S0EIE S0EINT 00’00B0

SSC Transmit SCTIR SCTIE SCTINT 00’00B4

SSC Receive SCRIR SCRIE SCRINT 00’00B8

SSC Error SCEIR SCEIE SCEINT 00’00BC

CAPCOM Register 16 CC16IR CC16IE CC16INT 00’00C0

CAPCOM Register 17 CC17IR CC17IE CC17INT 00’00C4

CAPCOM Register 18 CC18IR CC18IE CC18INT 00’00C8

CAPCOM Register 19 CC19IR CC19IE CC19INT 00’00CC

CAPCOM Register 24 CC24IR CC24IE CC24INT 00’00E0

CAPCOM Register 25 CC25IR CC25IE CC25INT 00’00E4

CAPCOM Register 26 CC26IR CC26IE CC26INT 00’00E8

CAPCOM Register 27 CC27IR CC27IE CC27INT 00’00EC

CAPCOM Timer 7 T7IR T7IE T7INT 00’00F4

CAPCOM Timer 8 T8IR T8IE T8INT 00’00F8

CAPCOM6 Interrupt CC6IR CC6IE CC6INT 00’00FC

2C

H

H

H

H

H

H

H

H

H

H

H

H

H

H

H

2D

2E

2F

30

31

32

33

38

39

3A

3B

3D

3E

3F

H

H

H

H

H

H

H

H

H

H

H

H

H

H

H

CAN Interface 1 XP0IR XP0IE XP0INT 00’0100

PLL/OWD and RTC XP3IR XP3IE XP3INT 00’010C

Data Sheet 17 V2.0, 2001-05

40

H

H

43

H

H

Table 3 C164CI Interrupt Nodes (cont’d)

C164CI/SI

C164CL/SL

Source of Interrupt or
PEC Service Request

Request
Flag

Enable
Flag

Interrupt
Vector

Vector
Location

CAPCOM 6 Timer 12 T12IR T12IE T12INT 00’0134

CAPCOM 6 Timer 13 T13IR T13IE T13INT 00’0138

CAPCOM 6 Emergency CC6EIR CC6EIE CC6EINT 00’013C

H

H

H

Trap
Number

4D

H

4E

H

4F

H

Data Sheet 18 V2.0, 2001-05

C164CI/SI

C164CL/SL

The C164CI also provides an excellent mechanism to identify and to process exceptions
or error conditions that arise during run-time, so-called ‘Hardware Traps’. Hardware
traps cause immediate non-maskable system reaction which is similar to a standard
interrupt service (branching to a dedicated vector table location). The occurence of a
hardware trap is additionally signified by an individual bit in the trap flag register (TFR).
Except when another higher prioritized trap service is in progress, a hardware trap will
interrupt any actual program execution. In turn, hardware trap services can normally not
be interrupted by standard or PEC interrupts.

Table 4 shows all of the possible exceptions or error conditions that can arise during run-

time:

Table 4 Hardware Trap Summary

Exception Condition Trap

Flag

Reset Functions:

–
– Hardware Reset
– Software Reset
– W-dog Timer Overflow

Class A Hardware Traps:

– Non-Maskable Interrupt
– Stack Overflow
– Stack Underflow

NMI

STKOF

STKUF

Class B Hardware Traps:

– Undefined Opcode
– Protected Instruction

UNDOPC

PRTFLT

Fault

– Illegal Word Operand

ILLOPA

Access

– Illegal Instruction

ILLINA

Access

– Illegal External Bus

ILLBUS

Access

Trap
Vector

RESET
RESET
RESET

NMITRAP
STOTRAP
STUTRAP

BTRAP
BTRAP

BTRAP

BTRAP

BTRAP

Vector
Location

00’0000
00’0000
00’0000

00’0008
00’0010
00’0018

00’0028
00’0028

00’0028

00’0028

00’0028

H

H

H

H

H

H

H

H

H

H

H

Trap
Number

00

H

00

H

00

H

02

H

04

H

06

H

0A

H

0A

H

0A

H

0A

H

0A

H

Trap
Priority

III
III
III

II
II
II

I
I

I

I

I

Reserved –– [2C

3CH]

Software Traps

– TRAP Instruction

–– Any

[00’0000
00’01FCH]

–

H

–

H

[0BH –
0FH]

Any

–

[00

H

7FH]

–

Current
CPU

Priority
in steps
of 4

H

Data Sheet 19 V2.0, 2001-05

C164CI/SI

C164CL/SL

The Capture/Compare Unit CAPCOM2

The general purpose CAPCOM2 unit supports generation and control of timing
sequences on up to 8 channels with a maximum resolution of 16 TCL. The CAPCOM
units are typically used to handle high speed I/O tasks such as pulse and waveform
generation, pulse width modulation (PMW), Digital to Analog (D/A) conversion, software
timing, or time recording relative to external events.
Two 16-bit timers (T7/T8) with reload registers provide two independent time bases for
the capture/compare register array.
Each dual purpose capture/compare register, which may be individually allocated to
either CAPCOM timer and programmed for capture or compare function, has one port
pin associated with it which serves as an input pin for triggering the capture function, or
as an output pin to indicate the occurrence of a compare event.

When a capture/compare register has been selected for capture mode, the current
contents of the allocated timer will be latched (‘capture’d) into the capture/compare
register in response to an external event at the port pin which is associated with this
register. In addition, a specific interrupt request for this capture/compare register is
generated. Either a positive, a negative, or both a positive and a negative external signal
transition at the pin can be selected as the triggering event. The contents of all registers
which have been selected for one of the five compare modes are continuously compared
with the contents of the allocated timers. When a match occurs between the timer value
and the value in a capture/compare register, specific actions will be taken based on the
selected compare mode.

Table 5 Compare Modes (CAPCOM2)

Compare Modes Function

Mode 0 Interrupt-only compare mode;

several compare interrupts per timer period are possible

Mode 1 Pin toggles on each compare match;

several compare events per timer period are possible

Mode 2 Interrupt-only compare mode;

only one compare interrupt per timer period is generated

Mode 3 Pin set ‘1’ on match; pin reset ‘0’ on compare time overflow;

only one compare event per timer period is generated

Double
Register Mode

Two registers operate on one pin; pin toggles on each compare
match;
several compare events per timer period are possible.
Registers CC16 & CC24 ➞ pin CC16IO
Registers CC17 & CC25 ➞ pin CC17IO
Registers CC18 & CC26 ➞ pin CC18IO
Registers CC19 & CC27 ➞ pin CC19IO

Data Sheet 20 V2.0, 2001-05