INFINEON C164CI, C164SI, C164CL User Manual

Data Sheet, V2.0, May 2001

C164CI/SI
C164CL/SL

16-Bit Single-Chip Microcontroller

Microcontrollers

Never stop thinking.

Edition 2001-05

Published by Infineon Technologies AG,
St.-Martin-Strasse 53,
D-81541 München, Germany

© Infineon Technologies AG 2001.

All Rights Reserved.

Attention please!

The information herein is given to describe certain components and shall not be considered as warranted
characteristics.

Terms of delivery and rights to technical change reserved.
We hereby disclaim any and all warranties, including but not limited to warranties of non-infringement, regarding

circuits, descriptions and charts stated herein.
Infineon Technologies is an approved CECC manufacturer.

Information

For further information on technology, delivery terms and conditions and prices please contact your nearest
Infineon Technologies Office in Germany or our Infineon Technologies Representatives worldwide.

Warnings

Due to technical requirements components may contain dangerous substances. For information on the types in
question please contact your nearest Infineon Technologies Office.

Infineon Technologies Components may only be used in life-support devices or systems with the express written
approval of Infineon Technologies, if a failure of such components can reasonably be expected to cause the failure
of that life-support device or system, or to affect the safety or effectiveness of that device or system. Life support
devices or systems are intended to be implanted in the human body, or to support and/or maintain and sustain
and/or protect human life. If they fail, it is reasonable to assume that the health of the user or other persons may
be endangered.

Data Sheet, V2.0, May 2001

C164CI/SI
C164CL/SL

16-Bit Single-Chip Microcontroller

Microcontrollers

Never stop thinking.

C164CI

Revision History: 2001-05 V2.0

Previous Version: 1999-08

1998-02 (Preliminary)

04.97 (Advance Information)

Page Subjects (major changes since last revision)

1)

All Converted to Infineon layout

1 Operating frequency up to 25 MHz

1 et al. References to Flash removed

1 Timer Unit with three timers

1, 12, 73 On-chip XRAM described

2 Derivative table updated

10 Supply voltage is 5 V

21 Functionality of reduced CAPCOM6 corrected

22f Timer description improved

29, 30 Sections “Oscillator Watchdog” and “Power Management” added

37 POCON reset values adjusted

41 to 73 Parameter section reworked

1)

These changes refer to the last two versions. Version 1998-02 covers OTP and ROM derivatives, while version
1999-08 ist the most recent one.

Controller Area Network (CAN): License of Robert Bosch GmbH

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Your feedback will help us to continuously improve the quality of this document.
Please send your proposal (including a reference to this document) to:

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C164CI16-Bit Single-Chip Microcontroller

C166 Family

C164CI/SI, C164CL/SL

• High Performance 16-bit CPU with 4-Stage Pipeline
– 80 ns Instruction Cycle Time at 25 MHz CPU Clock
– 400 ns Multiplication (16 × 16 bit), 800 ns Division (32 / 16 bit)
– Enhanced Boolean Bit Manipulation Facilities
– Additional Instructions to Support HLL and Operating Systems
– Register-Based Design with Multiple Variable Register Banks
– Single-Cycle Context Switching Support
– 16 MBytes Total Linear Address Space for Code and Data
– 1024 Bytes On-Chip Special Function Register Area

• 16-Priority-Level Interrupt System with 32 Sources, Sample-Rate down to 40 ns

• 8-Channel Interrupt-Driven Single-Cycle Data Transfer Facilities via
Peripheral Event Controller (PEC)

• Clock Generation via on-chip PLL (factors 1:1.5/2/2.5/3/4/5),
via prescaler or via direct clock input

• On-Chip Memory Modules
– 2 KBytes On-Chip Internal RAM (IRAM)
– 2 KBytes On-Chip Extension RAM (XRAM)
– up to 64 KBytes On-Chip Program Mask ROM or OTP Memory

• On-Chip Peripheral Modules
– 8-Channel 10-bit A/D Converter with Programmable Conversion Time

down to 7.8 µs
– 8-Channel General Purpose Capture/Compare Unit (CAPCOM2)
– Capture/Compare Unit for flexible PWM Signal Generation (CAPCOM6)

(3/6 Capture/Compare Channels and 1 Compare Channel)
– Multi-Functional General Purpose Timer Unit with 3 Timers
– Two Serial Channels (Synchronous/Asynchronous and High-Speed-Synchronous)
– On-Chip CAN Interface (Rev. 2.0B active) with 15 Message Objects

(Full CAN/Basic CAN)
– On-Chip Real Time Clock

• Up to 4 MBytes External Address Space for Code and Data
– Programmable External Bus Characteristics for Different Address Ranges
– Multiplexed or Demultiplexed External Address/Data Buses with 8-Bit or 16-Bit

Data Bus Width

– Four Optional Programmable Chip-Select Signals

• Idle, Sleep, and Power Down Modes with Flexible Power Management

• Programmable Watchdog Timer and Oscillator Watchdog

• Up to 59 General Purpose I/O Lines,
partly with Selectable Input Thresholds and Hysteresis

Data Sheet 1 V2.0, 2001-05

C164CI/SI

C164CL/SL

• Supported by a Large Range of Development Tools like C-Compilers,
Macro-Assembler Packages, Emulators, Evaluation Boards, HLL-Debuggers,
Simulators, Logic Analyzer Disassemblers, Programming Boards

• On-Chip Bootstrap Loader

• 80-Pin MQFP Package, 0.65 mm pitch

This document describes several derivatives of the C164 group. Table 1 enumerates
these derivatives and summarizes the differences. As this document refers to all of these
derivatives, some descriptions may not apply to a specific product.

Table 1 C164CI Derivative Synopsis

Derivative

1)

Program
Memory

CAPCOM6 CAN Interf. Operating

Frequency

SAK-C164CI-8R[25]M
SAF-C164CI-8R[25]M

SAK-C164SI-8R[25]M
SAF-C164SI-8R[25]M

SAK-C164CL-8R[25]M
SAF-C164CL-8R[25]M

SAK-C164SL-8R[25]M
SAF-C164SL-8R[25]M

SAK-C164CL-6R[25]M
SAF-C164CL-6R[25]M

SAK-C164SL-6R[25]M
SAF-C164SL-6R[25]M

SAK-C164CI-L[25]M
SAF-C164CI-L[25]M

SAK-C164CI-8EM

64 KByte ROM Full function CAN1 20 MHz,

[25 MHz]

64 KByte ROM Full function --- 20 MHz,

[25 MHz]

64 KByte ROM Reduced fct. CAN1 20 MHz,

[25 MHz]

64 KByte ROM Reduced fct. --- 20 MHz,

[25 MHz]

48 KByte ROM Reduced fct. CAN1 20 MHz,

[25 MHz]

48 KByte ROM Reduced fct. --- 20 MHz,

[25 MHz]

--- Full function CAN1 20 MHz,
[25 MHz]

64 KByte OTP Full function CAN1 20 MHz

SAF-C164CI-8EM

1)

This Data Sheet is valid for ROM(less) devices starting with and including design step AB, and for OTP devices
starting with and including design step DA.

For simplicity all versions are referred to by the term C164CI throughout this document.

Data Sheet 2 V2.0, 2001-05

C164CI/SI

C164CL/SL

Ordering Information

The ordering code for Infineon microcontrollers provides an exact reference to the
required product. This ordering code identifies:

• the derivative itself, i.e. its function set, the temperature range, and the supply voltage

• the package and the type of delivery.

For the available ordering codes for the C164CI please refer to the “Product Catalog
Microcontrollers”, which summarizes all available microcontroller variants.

Note: The ordering codes for Mask-ROM versions are defined for each product after

verification of the respective ROM code.

Introduction

The C164CI derivatives of the Infineon C166 Family of full featured single-chip CMOS
microcontrollers are especially suited for cost sensitive applications. They combine high
CPU performance (up to 12.5 million instructions per second) with high peripheral
functionality and enhanced IO-capabilities. They also provide clock generation via PLL
and various on-chip memory modules such as program ROM or OTP, internal RAM, and
extension RAM.

XTAL1

XTAL2

RSTIN

RSTOUT

NMI

EA

ALE

RD

WR/WRL

V

AREFVAGND

C164CI

V

DDVSS

Port 0
16 Bit

Port 1
16 Bit

Port 3
9 Bit

Port 4
6 Bit

Port 8
4 Bit

Port 5
8 Bit

MCL04869

Figure 1 Logic Symbol

Data Sheet 3 V2.0, 2001-05

Pin Configuration

(top view)

D
N
G
A

P5.3/AN3

V

P5.0/AN0

P5.2/AN2

P5.1/AN1

/*

/*

/*

/*

C16IO

P8.1/CC17IO

P8.3/CC19IO

P8.2/CC18IO

P8.0/C

I

NM

T

P1H.7/A15/CC27IO

RSTOU

RSTIN

P1H.6/A14/CC26IO

/EX2IN

/EX1IN

S2

S1
6PO
CC

CC6PO

D

P1H.3/A11/EXIN/T7IN

P1H.5/A13/CC25IO

P1H.4/A12/CC24IO

D

P1H.2/A10/

V

P1H.1/A9/

C164CI/SI

C164CL/SL

V

P5.4/AN4/T2EUD 2
P5.5/AN5/T4EUD

P5.6/AN6/T2IN
P5.7/AN7/T4IN

P3.4/T3EUD

P3.11/RxD0

P3.12/BHE/WRH

P3.13/SCLK

P3.15/CLKOUT/FOUT

P4.0/A16/CS3
P4.1/A17/CS2
P4.2/A18/CS1

AREF

V
V

P3.6/T3IN
P3.8/MRST
P3.9/MTSR

P3.10/TxD0

V

SS

DD

SS

1

3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20

80

21

V

797877

23

24

22

D
D

*/P4.5/A20

*/P4.6/A21

P4.3/A19/CS0

76

25

RD

75

26

RL

R/W
W

74

27

ALE

737271

C164CI

30

29

28

Vpp/EA

P0L.1/AD1

P0L.0/AD0

70

68

69

33

31

32

P0L.2/AD2

P0L.4/AD4

P0L.3/AD3

676665

34

36

35

P0L.5/AD5

P0L.7/AD7

P0L.6/AD6

646362

37

38

39

61

40

V

P0H.0/AD8

P0H.1/AD9

P0H.2/AD10

V

60

SS

P1H.0/A8/CC6POS0/EX0IN

59
58

P1L.7/A7/CTRAP
P1L.6/A6/COUT6357

V

56

SS

XTAL155
XTAL254

V

53

DD

P1L.5/A5/COUT6252
P1L.4/A4/CC6251
P1L.3/A3/COUT61

50

P1L.2/A2/CC6149
P1L.1/A1/COUT6048
P1L.0/A0/CC60

47

P0H.7/AD1546
P0H.6/AD1445
P0H.5/AD13

44
43

P0H.4/AD12
P0H.3/AD1142

V

41

SS

D
D

MCP04870

Figure 2

*) The marked pins of Port 4 and Port 8 can have CAN interface lines assigned to them.

Table 2 on the pages below lists the possible assignments.

The marked input signals are available only in devices with a full-function CAPCOM6.
They are not available in devices with a reduced-function CAPCOM6.

Data Sheet 4 V2.0, 2001-05

Table 2 Pin Definitions and Functions

C164CI/SI

C164CL/SL

Symbol Pin

No.

P5

P5.0
P5.1
P5.2
P5.3
P5.4
P5.5
P5.6

P5.7

P3

P3.4
P3.6
P3.8
P3.9
P3.10
P3.11
P3.12

P3.13
P3.15

76
77
78
79
2
3
4

5

8
9
10
11
12
13
14

15
16

Input
Outp.

I

I
I
I
I
I
I
I

I

IO

I
I
I/O
I/O
O
I/O
O
O
I/O
O
O

Function

Port 5 is an 8-bit input-only port with Schmitt-Trigger charact.
The pins of Port 5 also serve as analog input channels for the
A/D converter, or they serve as timer inputs:
AN0
AN1
AN2
AN3
AN4, T2EUD GPT1 Timer T2 Ext. Up/Down Ctrl. Inp.
AN5, T4EUD GPT1 Timer T4 Ext. Up/Down Ctrl. Inp.
AN6, T2IN GPT1 Timer T2 Input for

Count/Gate/Reload/Capture

AN7, T4IN GPT1 Timer T4 Input for

Count/Gate/Reload/Capture

Port 3 is a 9-bit bidirectional I/O port. It is bit-wise
programmable for input or output via direction bits. For a pin
configured as input, the output driver is put into high­impedance state. Port 3 outputs can be configured as push/
pull or open drain drivers. The input threshold of Port 3 is
selectable (TTL or special).
The following Port 3 pins also serve for alternate functions:
T3EUD GPT1 Timer T3 External Up/Down Control Input
T3IN GPT1 Timer T3 Count/Gate Input
MRST SSC Master-Receive/Slave-Transmit Inp./Outp.
MTSR SSC Master-Transmit/Slave-Receive Outp./Inp.
TxD0 ASC0 Clock/Data Output (Async./Sync.)
RxD0 ASC0 Data Input (Async.) or Inp./Outp. (Sync.)
BHE
WRH
SCLK SSC Master Clock Output / Slave Clock Input.
CLKOUT System Clock Output (= CPU Clock),
FOUT Programmable Frequency Output

External Memory High Byte Enable Signal,
External Memory High Byte Write Strobe

Data Sheet 5 V2.0, 2001-05

Table 2 Pin Definitions and Functions (cont’d)

C164CI/SI

C164CL/SL

Symbol Pin

No.

P4

P4.0

P4.1

P4.2

P4.3

P4.5

P4.6

17

18

19

22

23

24

Input
Outp.

IO

O
O
O
O
O
O
O
O
O
I
O
O

Function

Port 4 is a 6-bit bidirectional I/O port. It is bit-wise
programmable for input or output via direction bits. For a pin
configured as input, the output driver is put into high­impedance state. Port 4 outputs can be configured as push/
pull or open drain drivers. The input threshold of Port 4 is
selectable (TTL or special).
Port 4 can be used to output the segment address lines, the
optional chip select lines, and for serial interface lines:

1)

A16 Least Significant Segment Address Line,
CS3 Chip Select 3 Output
A17 Segment Address Line,
CS2

Chip Select 2 Output
A18 Segment Address Line,
CS1

Chip Select 1 Output
A19 Segment Address Line,
CS0

Chip Select 0 Output
A20 Segment Address Line,
CAN1_RxD CAN 1 Receive Data Input
A21 Most Significant Segment Address Line,
CAN1_TxD CAN 1 Transmit Data Output

RD

25 O External Memory Read Strobe. RD is activated for every

external instruction or data read access.

WR
WRL

/

26 O External Memory Write Strobe. In WR-mode this pin is

activated for every external data write access. In WRL

-mode
this pin is activated for low byte data write accesses on a
16-bit bus, and for every data write access on an 8-bit bus.
See WRCFG in register SYSCON for mode selection.

ALE 27 O Address Latch Enable Output. Can be used for latching the

address into external memory or an address latch in the
multiplexed bus modes.

Data Sheet 6 V2.0, 2001-05

Table 2 Pin Definitions and Functions (cont’d)

C164CI/SI

C164CL/SL

Symbol Pin

No.

EA/V

28 I External Access Enable pin.

PP

PORT0

P0L.0-7

29­36

P0H.0-7

37-39,
42-46

Input

Function

Outp.

A low level at this pin during and after Reset forces the

C164CI to latch the configuration from PORT0 and pin RD
and to begin instruction execution out of external memory.
A high level forces the C164CI to latch the configuration
from pins RD

and ALE, and to begin instruction execution out
of the internal program memory.
“ROMless” versions must have this pin tied to ‘0’.

Note: This pin also accepts the programming voltage for the

OTP derivatives.

IO PORT0 consists of the two 8-bit bidirectional I/O ports P0L

and P0H. It is bit-wise programmable for input or output via
direction bits. For a pin configured as input, the output driver
is put into high-impedance state.
In case of an external bus configuration, PORT0 serves as
the address (A) and address/data (AD) bus in multiplexed
bus modes and as the data (D) bus in demultiplexed bus
modes.

Demultiplexed bus modes:

Data Path Width: 8-bit 16-bit
P0L.0 – P0L.7: D0 – D7 D0 – D7
P0H.0 – P0H.7: I/O D8 – D15

Multiplexed bus modes:

Data Path Width: 8-bit 16-bit
P0L.0 – P0L.7: AD0 – AD7 AD0 – AD7
P0H.0 – P0H.7: A8 – A15 AD8 – AD15

,

Data Sheet 7 V2.0, 2001-05

Table 2 Pin Definitions and Functions (cont’d)

C164CI/SI

C164CL/SL

Symbol Pin

No.

PORT1

P1L.0-7

P1H.0-7

P1L.0
P1L.1
P1L.2
P1L.3
P1L.4
P1L.5
P1L.6
P1L.7

P1H.0

P1H.1

P1H.2

P1H.3

P1H.4
P1H.5
P1H.6
P1H.7

47-52,
57-59
59,
62-68

47
48
49
50
51
52
57
58

59

62

63

64

65
66
67
68

Input
Outp.

IO

I/O
O
I/O
O
I/O
O
O
I

I
I
I
I
I
I
I

I/O
I/O
I/O
I/O

Function

PORT1 consists of the two 8-bit bidirectional I/O ports P1L
and P1H. It is bit-wise programmable for input or output via
direction bits. For a pin configured as input, the output driver
is put into high-impedance state. PORT1 is used as the
16-bit address bus (A) in demultiplexed bus modes and also
after switching from a demultiplexed bus mode to a
multiplexed bus mode.
The following PORT1 pins also serve for alt. functions:
CC60 CAPCOM6: Input / Output of Channel 0
COUT60 CAPCOM6: Output of Channel 0
CC61 CAPCOM6: Input / Output of Channel 1
COUT61 CAPCOM6: Output of Channel 1
CC62 CAPCOM6: Input / Output of Channel 2
COUT62 CAPCOM6: Output of Channel 2
COUT63 Output of 10-bit Compare Channel
CTRAP
CTRAP
level on this pin switches the compare outputs of the
CAPCOM6 unit to the logic level defined by software.
CC6POS0
EX0IN Fast External Interrupt 0 Input
CC6POS1
EX1IN Fast External Interrupt 1 Input
CC6POS2
EX2IN Fast External Interrupt 2 Input
EX3IN Fast External Interrupt 3 Input,
T7IN CAPCOM2: Timer T7 Count Input
CC24IO CAPCOM2: CC24 Capture Inp./Compare Outp.
CC25IO CAPCOM2: CC25 Capture Inp./Compare Outp.
CC26IO CAPCOM2: CC26 Capture Inp./Compare Outp.
CC27IO CAPCOM2: CC27 Capture Inp./Compare Outp.

CAPCOM6: Trap Input

is an input pin with an internal pullup resistor. A low

CAPCOM6: Position 0 Input, **)

CAPCOM6: Position 1 Input, **)

CAPCOM6: Position 2 Input, **)

Note: The marked (**) input signals are available only in

devices with a full function CAPCOM6.

Data Sheet 8 V2.0, 2001-05

Table 2 Pin Definitions and Functions (cont’d)

C164CI/SI

C164CL/SL

Symbol Pin

No.

XTAL2
XTAL15455

RSTIN

69 I/O Reset Input with Schmitt-Trigger characteristics. A low level

Input
Outp.

O
I

Function

XTAL2: Output of the oscillator amplifier circuit.
XTAL1: Input to the oscillator amplifier and input to

the internal clock generator
To clock the device from an external source, drive XTAL1,
while leaving XTAL2 unconnected. Minimum and maximum
high/low and rise/fall times specified in the AC
Characteristics must be observed.

at this pin while the oscillator is running resets the C164CI.
An internal pullup resistor permits power-on reset using only

V

a capacitor connected to
A spike filter suppresses input pulses <10 ns. Input pulses
>100 ns safely pass the filter. The minimum duration for a
safe recognition should be 100 ns + 2 CPU clock cycles.
In bidirectional reset mode (enabled by setting bit BDRSTEN
in register SYSCON) the RSTIN
for the duration of the internal reset sequence upon any reset
(HW, SW, WDT). See note below this table.

.

SS

line is internally pulled low

RST
OUT

NMI

70 O Internal Reset Indication Output. This pin is set to a low level

when the part is executing either a hardware-, a software- or
a watchdog timer reset. RSTOUT
(end of initialization) instruction is executed.

71 I Non-Maskable Interrupt Input. A high to low transition at this

pin causes the CPU to vector to the NMI trap routine. When
the PWRDN (power down) instruction is executed, the NMI
pin must be low in order to force the C164CI to go into power
down mode. If NMI
part will continue to run in normal mode.
If not used, pin NMI

is high, when PWRDN is executed, the

should be pulled high externally.

remains low until the EINIT

Data Sheet 9 V2.0, 2001-05

Table 2 Pin Definitions and Functions (cont’d)

C164CI/SI

C164CL/SL

Symbol Pin

No.

P8

P8.0

P8.1

P8.2

P8.3

V

AREF

72

73

74

75

1 – Reference voltage for the A/D converter.

Input
Outp.

IO

I/O
I
I/O
O
I/O
I
I/O
O

Function

Port 8 is a 4-bit bidirectional I/O port. It is bit-wise
programmable for input or output via direction bits. For a pin
configured as input, the output driver is put into high­impedance state. Port 8 outputs can be configured as push/
pull or open drain drivers. The input threshold of Port 8 is
selectable (TTL or special). Port 8 pins provide inputs/
outputs for CAPCOM2 and serial interface lines.

1)

CC16IO CAPCOM2: CC16 Capture Inp./Compare Outp.,
CAN1_RxD CAN 1 Receive Data Input
CC17IO CAPCOM2: CC17 Capture Inp./Compare Outp.,
CAN1_TxD CAN 1 Transmit Data Output
CC18IO CAPCOM2: CC18 Capture Inp./Compare Outp.,
CAN1_RxD CAN 1 Receive Data Input
CC19IO CAPCOM2: CC19 Capture Inp./Compare Outp.,
CAN1_TxD CAN 1 Transmit Data Output

V

AGND

V

DD

V

SS

80 – Reference ground for the A/D converter.

7, 21,
40, 53,
61

6, 20,

– Digital Supply Voltage:

+5 V during normal operation and idle mode.
≥2.5 V during power down mode.

– Digital Ground.
41, 56,
60

1)

The CAN interface lines are assigned to ports P4 and P8 under software control. Within the CAN module
several assignments can be selected.

Note: The following behavioural differences must be observed when the bidirectional

reset is active:

• Bit BDRSTEN in register SYSCON cannot be changed after EINIT and is cleared
automatically after a reset.

• The reset indication flags always indicate a long hardware reset.

• The PORT0 configuration is treated as if it were a hardware reset. In particular, the

bootstrap loader may be activated when P0L.4 is low.

• Pin RSTIN

may only be connected to external reset devices with an open drain output

driver.

• A short hardware reset is extended to the duration of the internal reset sequence.

Data Sheet 10 V2.0, 2001-05

C164CI/SI

C164CL/SL

Functional Description

The architecture of the C164CI combines advantages of both RISC and CISC
processors and of advanced peripheral subsystems in a very well-balanced way. In
addition the on-chip memory blocks allow the design of compact systems with maximum
performance.
The following block diagram gives an overview of the different on-chip components and
of the advanced, high bandwidth internal bus structure of the C164CI.

Note: All time specifications refer to a CPU clock of 25 MHz

(see definition in the AC Characteristics section).

6

ProgMem

ROM: 48/64

OTP: 64

KByte

XRAM

2 KByte

CAN

Rev 2.0B active

EBC

XBUS Control

rt 4
o

External Bus

P

Control

Port 0

32

Instr. / Data

16

)
x
u

m
e

it D

-B

16

6
(1

S
U
B
X
ip
h

-C
n
O

16 8

ADC

10-Bit

8

Channels

Port 5 Port 3

External Instr. / Data

Interrupt Controller

ASC0

(USART)

BRGen

C166-Core

CPU

SSC

(SPI)

BRGen

PEC

16-Level

Priority

GPT1

T2

T3

T4

9

Interrupt Bus

Peripheral Data Bus

Data

Data

16

CCOM2

16

rt
o

l P

16

a
u

D

RTC WDT

CCOM6

T7

T8

Port 8

IRAM

Internal

RAM

2 KByte

Osc / PLL

T12

T13

4

MCB04323_4ci

rt 1
o
P

XTAL

16

Figure 3 Block Diagram

The program memory, the internal RAM (IRAM) and the set of generic peripherals are
connected to the CPU via separate buses. A fourth bus, the XBUS, connects external
resources as well as additional on-chip resoures, the X-Peripherals (see Figure 3).

The XBUS resources (XRAM, CAN) of the C164CI can be enabled or disabled during
initialization by setting the general X-Peripheral enable bit XPEN (SYSCON.2). Modules
that are disabled consume neither address space nor port pins.

Data Sheet 11 V2.0, 2001-05

C164CI/SI

C164CL/SL

Memory Organization

The memory space of the C164CI is configured in a Von Neumann architecture which
means that code memory, data memory, registers and I/O ports are organized within the
same linear address space which includes 16 MBytes. The entire memory space can be
accessed bytewise or wordwise. Particular portions of the on-chip memory have
additionally been made directly bitaddressable.

The C164CI incorporates 64 KBytes of on-chip OTP memory or 64/48 KBytes of on-chip
mask-programmable ROM (not in the ROM-less derivative, of course) for code or
constant data. The lower 32 KBytes of the on-chip ROM/OTP can be mapped either to
segment 0 or segment 1.
The OTP memory can be programmed by the CPU itself (in system, e.g. during booting)
or directly via an external interface (e.g. before assembly). The programming time is

V

approx. 100 µs per word. An external programming voltage
supplied for this purpose (via pin EA

/VPP).

=11.5V must be

PP

2 KBytes of on-chip Internal RAM (IRAM) are provided as a storage for user defined
variables, for the system stack, general purpose register banks and even for code. A
register bank can consist of up to 16 wordwide (R0 to R15) and/or bytewide (RL0, RH0,
…, RL7, RH7) so-called General Purpose Registers (GPRs).

1024 bytes (2 × 512 bytes) of the address space are reserved for the Special Function
Register areas (SFR space and ESFR space). SFRs are wordwide registers which are
used for controlling and monitoring functions of the different on-chip units. Unused SFR
addresses are reserved for future members of the C166 Family.

2 KBytes of on-chip Extension RAM (XRAM) are provided to store user data, user
stacks, or code. The XRAM is accessed like external memory and therefore cannot be
used for the system stack or for register banks and is not bitaddressable. The XRAM
permits 16-bit accesses with maximum speed.

In order to meet the needs of designs where more memory is required than is provided
on chip, up to 4 MBytes of external RAM and/or ROM can be connected to the
microcontroller.

Data Sheet 12 V2.0, 2001-05

C164CI/SI

C164CL/SL

External Bus Controller

All of the external memory accesses are performed by a particular on-chip External Bus
Controller (EBC). It can be programmed either to Single Chip Mode when no external
memory is required, or to one of four different external memory access modes, which are
as follows:

– 16-/18-/20-/22-bit Addresses, 16-bit Data, Demultiplexed
– 16-/18-/20-/22-bit Addresses, 16-bit Data, Multiplexed
– 16-/18-/20-/22-bit Addresses, 8-bit Data, Multiplexed
– 16-/18-/20-/22-bit Addresses, 8-bit Data, Demultiplexed

In the demultiplexed bus modes, addresses are output on PORT1 and data is input/
output on PORT0 or P0L, respectively. In the multiplexed bus modes both addresses
and data use PORT0 for input/output.

Important timing characteristics of the external bus interface (Memory Cycle Time,
Memory Tri-State Time, Length of ALE and Read Write Delay) have been made
programmable to allow the user the adaption of a wide range of different types of
memories and external peripherals.
In addition, up to 4 independent address windows may be defined (via register pairs
ADDRSELx / BUSCONx) which control the access to different resources with different
bus characteristics. These address windows are arranged hierarchically where
BUSCON4 overrides BUSCON3 and BUSCON2 overrides BUSCON1. All accesses to
locations not covered by these 4 address windows are controlled by BUSCON0.

Up to 4 external CS
external glue logic. The C164CI offers the possibility to switch the CS
unlatched mode. In this mode the internal filter logic is switched off and the CS
are directly generated from the address. The unlatched CS
CSCFG (SYSCON.6).

For applications which require less than 4 MBytes of external memory space, this
address space can be restricted to 1 MByte, 256 KByte, or to 64 KByte. In this case
Port 4 outputs four, two, or no address lines at all. It outputs all 6 address lines, if an
address space of 4 MBytes is used.

Note: When the on-chip CAN Module is used with the interface lines assigned to Port 4,

the CAN lines override the segment address lines and the segment address
output on Port 4 is therefore limited to 4 bits i.e. address lines A19 … A16.

signals (3 windows plus default) can be generated in order to save

outputs to an

signals

mode is enabled by setting

Data Sheet 13 V2.0, 2001-05

C164CI/SI

C164CL/SL

Central Processing Unit (CPU)

The main core of the CPU consists of a 4-stage instruction pipeline, a 16-bit arithmetic
and logic unit (ALU) and dedicated SFRs. Additional hardware has been spent for a
separate multiply and divide unit, a bit-mask generator and a barrel shifter.

Based on these hardware provisions, most of the C164CI’s instructions can be executed
in just one machine cycle which requires 2 CPU clocks (4 TCL). For example, shift and
rotate instructions are always processed during one machine cycle independent of the
number of bits to be shifted. All multiple-cycle instructions have been optimized so that
they can be executed very fast as well: branches in 2 cycles, a 16 × 16 bit multiplication
in 5 cycles and a 32-/16-bit division in 10 cycles. Another pipeline optimization, the so­called ‘Jump Cache’, reduces the execution time of repeatedly performed jumps in a loop
from 2 cycles to 1 cycle.

ROM

32

CPU

SP
STKOV
STKUN

Exec. Unit

Instr. Ptr.

Instr. Reg.

4-Stage
Pipeline

PSW

SYSCON

BUSCON 0
BUSCON 1
BUSCON 2
BUSCON 3
BUSCON 4 ADDRSEL 4

Data Page Ptr. Code Seg. Ptr.

MDH
MDL

Mul/Div-HW

Bit-Mask Gen

ALU

(16-bit)

Barrel - Shifter

Context Ptr.

ADDRSEL 1
ADDRSEL 2
ADDRSEL 3

R15

General

Purpose

Registers

R0

16

Internal

RAM

R15

R0

16

MCB02147

Figure 4 CPU Block Diagram

Data Sheet 14 V2.0, 2001-05

C164CI/SI

C164CL/SL

The CPU has a register context consisting of up to 16 wordwide GPRs at its disposal.
These 16 GPRs are physically allocated within the on-chip RAM area. A Context Pointer
(CP) register determines the base address of the active register bank to be accessed by
the CPU at any time. The number of register banks is only restricted by the available
internal RAM space. For easy parameter passing, a register bank may overlap others.

A system stack of up to 1024 words is provided as a storage for temporary data. The
system stack is allocated in the on-chip RAM area, and it is accessed by the CPU via the
stack pointer (SP) register. Two separate SFRs, STKOV and STKUN, are implicitly
compared against the stack pointer value upon each stack access for the detection of a
stack overflow or underflow.

The high performance offered by the hardware implementation of the CPU can efficiently
be utilized by a programmer via the highly efficient C164CI instruction set which includes
the following instruction classes:

– Arithmetic Instructions
– Logical Instructions
– Boolean Bit Manipulation Instructions
– Compare and Loop Control Instructions
– Shift and Rotate Instructions
– Prioritize Instruction
– Data Movement Instructions
– System Stack Instructions
– Jump and Call Instructions
– Return Instructions
– System Control Instructions
– Miscellaneous Instructions

The basic instruction length is either 2 or 4 bytes. Possible operand types are bits, bytes
and words. A variety of direct, indirect or immediate addressing modes are provided to
specify the required operands.

Data Sheet 15 V2.0, 2001-05

C164CI/SI

C164CL/SL

Interrupt System

With an interrupt response time within a range from just 5 to 12 CPU clocks (in case of
internal program execution), the C164CI is capable of reacting very fast to the
occurrence of non-deterministic events.

The architecture of the C164CI supports several mechanisms for fast and flexible
response to service requests that can be generated from various sources internal or
external to the microcontroller. Any of these interrupt requests can be programmed to
being serviced by the Interrupt Controller or by the Peripheral Event Controller (PEC).

In contrast to a standard interrupt service where the current program execution is
suspended and a branch to the interrupt vector table is performed, just one cycle is
‘stolen’ from the current CPU activity to perform a PEC service. A PEC service implies a
single byte or word data transfer between any two memory locations with an additional
increment of either the PEC source or the destination pointer. An individual PEC transfer
counter is implicity decremented for each PEC service except when performing in the
continuous transfer mode. When this counter reaches zero, a standard interrupt is
performed to the corresponding source related vector location. PEC services are very
well suited, for example, for supporting the transmission or reception of blocks of data.
The C164CI has 8 PEC channels each of which offers such fast interrupt-driven data
transfer capabilities.

A separate control register which contains an interrupt request flag, an interrupt enable
flag and an interrupt priority bitfield exists for each of the possible interrupt sources. Via
its related register, each source can be programmed to one of sixteen interrupt priority
levels. Once having been accepted by the CPU, an interrupt service can only be
interrupted by a higher prioritized service request. For the standard interrupt processing,
each of the possible interrupt sources has a dedicated vector location.

Fast external interrupt inputs are provided to service external interrupts with high
precision requirements. These fast interrupt inputs feature programmable edge
detection (rising edge, falling edge or both edges).

Software interrupts are supported by means of the ‘TRAP’ instruction in combination with
an individual trap (interrupt) number.

Table 3 shows all of the possible C164CI interrupt sources and the corresponding

hardware-related interrupt flags, vectors, vector locations and trap (interrupt) numbers.

Note: Interrupt nodes which are not used by associated peripherals, may be used to

generate software controlled interrupt requests by setting the respective interrupt
request bit (xIR).

Data Sheet 16 V2.0, 2001-05

Table 3 C164CI Interrupt Nodes

C164CI/SI

C164CL/SL

Source of Interrupt or
PEC Service Request

Request
Flag

Enable
Flag

Interrupt
Vector

Vector
Location

Fast External Interrupt 0 CC8IR CC8IE CC8INT 00’0060

Fast External Interrupt 1 CC9IR CC9IE CC9INT 00’0064

Fast External Interrupt 2 CC10IR CC10IE CC10INT 00’0068

Fast External Interrupt 3 CC11IR CC11IE CC11INT 00’006C

GPT1 Timer 2 T2IR T2IE T2INT 00’0088

GPT1 Timer 3 T3IR T3IE T3INT 00’008C

GPT1 Timer 4 T4IR T4IE T4INT 00’0090

A/D Conversion

ADCIR ADCIE ADCINT 00’00A0

Complete

A/D Overrun Error ADEIR ADEIE ADEINT 00’00A4

ASC0 Transmit S0TIR S0TIE S0TINT 00’00A8

ASC0 Transmit Buffer S0TBIR S0TBIE S0TBINT 00’011C

ASC0 Receive S0RIR S0RIE S0RINT 00’00AC

H

H

H

H

H

H

H

H

H

H

H

H

Trap
Number

18

H

19

H

1A

H

1B

H

22

H

23

H

24

H

28

H

29

H

2A

H

47

H

2B

H

ASC0 Error S0EIR S0EIE S0EINT 00’00B0

SSC Transmit SCTIR SCTIE SCTINT 00’00B4

SSC Receive SCRIR SCRIE SCRINT 00’00B8

SSC Error SCEIR SCEIE SCEINT 00’00BC

CAPCOM Register 16 CC16IR CC16IE CC16INT 00’00C0

CAPCOM Register 17 CC17IR CC17IE CC17INT 00’00C4

CAPCOM Register 18 CC18IR CC18IE CC18INT 00’00C8

CAPCOM Register 19 CC19IR CC19IE CC19INT 00’00CC

CAPCOM Register 24 CC24IR CC24IE CC24INT 00’00E0

CAPCOM Register 25 CC25IR CC25IE CC25INT 00’00E4

CAPCOM Register 26 CC26IR CC26IE CC26INT 00’00E8

CAPCOM Register 27 CC27IR CC27IE CC27INT 00’00EC

CAPCOM Timer 7 T7IR T7IE T7INT 00’00F4

CAPCOM Timer 8 T8IR T8IE T8INT 00’00F8

CAPCOM6 Interrupt CC6IR CC6IE CC6INT 00’00FC

2C

H

H

H

H

H

H

H

H

H

H

H

H

H

H

H

2D

2E

2F

30

31

32

33

38

39

3A

3B

3D

3E

3F

H

H

H

H

H

H

H

H

H

H

H

H

H

H

H

CAN Interface 1 XP0IR XP0IE XP0INT 00’0100

PLL/OWD and RTC XP3IR XP3IE XP3INT 00’010C

Data Sheet 17 V2.0, 2001-05

40

H

H

43

H

H

Table 3 C164CI Interrupt Nodes (cont’d)

C164CI/SI

C164CL/SL

Source of Interrupt or
PEC Service Request

Request
Flag

Enable
Flag

Interrupt
Vector

Vector
Location

CAPCOM 6 Timer 12 T12IR T12IE T12INT 00’0134

CAPCOM 6 Timer 13 T13IR T13IE T13INT 00’0138

CAPCOM 6 Emergency CC6EIR CC6EIE CC6EINT 00’013C

H

H

H

Trap
Number

4D

H

4E

H

4F

H

Data Sheet 18 V2.0, 2001-05

C164CI/SI

C164CL/SL

The C164CI also provides an excellent mechanism to identify and to process exceptions
or error conditions that arise during run-time, so-called ‘Hardware Traps’. Hardware
traps cause immediate non-maskable system reaction which is similar to a standard
interrupt service (branching to a dedicated vector table location). The occurence of a
hardware trap is additionally signified by an individual bit in the trap flag register (TFR).
Except when another higher prioritized trap service is in progress, a hardware trap will
interrupt any actual program execution. In turn, hardware trap services can normally not
be interrupted by standard or PEC interrupts.

Table 4 shows all of the possible exceptions or error conditions that can arise during run-

time:

Table 4 Hardware Trap Summary

Exception Condition Trap

Flag

Reset Functions:

–
– Hardware Reset
– Software Reset
– W-dog Timer Overflow

Class A Hardware Traps:

– Non-Maskable Interrupt
– Stack Overflow
– Stack Underflow

NMI

STKOF

STKUF

Class B Hardware Traps:

– Undefined Opcode
– Protected Instruction

UNDOPC

PRTFLT

Fault

– Illegal Word Operand

ILLOPA

Access

– Illegal Instruction

ILLINA

Access

– Illegal External Bus

ILLBUS

Access

Trap
Vector

RESET
RESET
RESET

NMITRAP
STOTRAP
STUTRAP

BTRAP
BTRAP

BTRAP

BTRAP

BTRAP

Vector
Location

00’0000
00’0000
00’0000

00’0008
00’0010
00’0018

00’0028
00’0028

00’0028

00’0028

00’0028

H

H

H

H

H

H

H

H

H

H

H

Trap
Number

00

H

00

H

00

H

02

H

04

H

06

H

0A

H

0A

H

0A

H

0A

H

0A

H

Trap
Priority

III
III
III

II
II
II

I
I

I

I

I

Reserved –– [2C

3CH]

Software Traps

– TRAP Instruction

–– Any

[00’0000
00’01FCH]

–

H

–

H

[0BH –
0FH]

Any

–

[00

H

7FH]

–

Current
CPU

Priority
in steps
of 4

H

Data Sheet 19 V2.0, 2001-05

C164CI/SI

C164CL/SL

The Capture/Compare Unit CAPCOM2

The general purpose CAPCOM2 unit supports generation and control of timing
sequences on up to 8 channels with a maximum resolution of 16 TCL. The CAPCOM
units are typically used to handle high speed I/O tasks such as pulse and waveform
generation, pulse width modulation (PMW), Digital to Analog (D/A) conversion, software
timing, or time recording relative to external events.
Two 16-bit timers (T7/T8) with reload registers provide two independent time bases for
the capture/compare register array.
Each dual purpose capture/compare register, which may be individually allocated to
either CAPCOM timer and programmed for capture or compare function, has one port
pin associated with it which serves as an input pin for triggering the capture function, or
as an output pin to indicate the occurrence of a compare event.

When a capture/compare register has been selected for capture mode, the current
contents of the allocated timer will be latched (‘capture’d) into the capture/compare
register in response to an external event at the port pin which is associated with this
register. In addition, a specific interrupt request for this capture/compare register is
generated. Either a positive, a negative, or both a positive and a negative external signal
transition at the pin can be selected as the triggering event. The contents of all registers
which have been selected for one of the five compare modes are continuously compared
with the contents of the allocated timers. When a match occurs between the timer value
and the value in a capture/compare register, specific actions will be taken based on the
selected compare mode.

Table 5 Compare Modes (CAPCOM2)

Compare Modes Function

Mode 0 Interrupt-only compare mode;

several compare interrupts per timer period are possible

Mode 1 Pin toggles on each compare match;

several compare events per timer period are possible

Mode 2 Interrupt-only compare mode;

only one compare interrupt per timer period is generated

Mode 3 Pin set ‘1’ on match; pin reset ‘0’ on compare time overflow;

only one compare event per timer period is generated

Double
Register Mode

Two registers operate on one pin; pin toggles on each compare
match;
several compare events per timer period are possible.
Registers CC16 & CC24 ➞ pin CC16IO
Registers CC17 & CC25 ➞ pin CC17IO
Registers CC18 & CC26 ➞ pin CC18IO
Registers CC19 & CC27 ➞ pin CC19IO

Data Sheet 20 V2.0, 2001-05

C164CI/SI

C164CL/SL

The Capture/Compare Unit CAPCOM6

The CAPCOM6 unit supports generation and control of timing sequences on up to three
16-bit capture/compare channels plus one 10-bit compare channel.
In compare mode the CAPCOM6 unit provides two output signals per channel which
have inverted polarity and non-overlapping pulse transitions. The compare channel can
generate a single PWM output signal and is further used to modulate the capture/
compare output signals.
In capture mode the contents of compare timer 12 is stored in the capture registers upon
a signal transition at pins CCx.

Compare timers T12 (16-bit) and T13 (10-bit) are free running timers which are clocked
by the prescaled CPU clock.

f

f

CPU

CPU

Period Register

T12P

Offset Register

T12OF

Compare

Timer T12

Prescaler

Prescaler

16-Bit

Control Register

CTCON

Compare

Timer T13

10-Bit

Period Register

T13P

Mode

Select Register

CC6MSEL

CC Channel 0

CC60

CC Channel 1

Control

CC61

CC Channel 2

CC62

Compare Register

CMP13

Trap Register

Port

Control

Logic

Block

Commutation

Control

CC6MCON.H

CTRAP

CC60
COUT60

CC61
COUT61

CC62
COUT62

COUT63

CC6POS0
CC6POS1
CC6POS2

The timer registers (T12, T13) are not directly accessible.
The period and offset registers are loading a value into the timer registers.
The shaded blocks are available in the full function module only.

MCB04109

Figure 5 CAPCOM6 Block Diagram

For motor control applications both subunits may generate versatile multichannel PWM
signals which are basically either controlled by compare timer 12 or by a typical hall
sensor pattern at the interrupt inputs (block commutation).

Note: Multichannel signal generation is provided only in devices with a full CAPCOM6.

Data Sheet 21 V2.0, 2001-05

C164CI/SI

C164CL/SL

General Purpose Timer (GPT) Unit

The GPT unit represents a very flexible multifunctional timer/counter structure which
may be used for many different time related tasks such as event timing and counting,
pulse width and duty cycle measurements, pulse generation, or pulse multiplication.

The GPT unit incorporates three 16-bit timers. Each timer may operate independently in
a number of different modes, or may be concatenated with another timer.

Each of the three timers T2, T3, T4 of module GPT1 can be configured individually for
one of four basic modes of operation, which are Timer, Gated Timer, Counter, and
Incremental Interface Mode. In Timer Mode, the input clock for a timer is derived from
the CPU clock, divided by a programmable prescaler, while Counter Mode allows a timer
to be clocked in reference to external events.
Pulse width or duty cycle measurement is supported in Gated Timer Mode, where the
operation of a timer is controlled by the ‘gate’ level on an external input pin. For these
purposes, each timer has one associated port pin (TxIN) which serves as gate or clock
input. The maximum resolution of the timers in module GPT1 is 16 TCL.

The count direction (up/down) for each timer is programmable by software or may
additionally be altered dynamically by an external signal on a port pin (TxEUD) to
facilitate e.g. position tracking.

In Incremental Interface Mode the GPT1 timers (T2, T3, T4) can be directly connected
to the incremental position sensor signals A and B via their respective inputs TxIN and
TxEUD. Direction and count signals are internally derived from these two input signals,
so the contents of the respective timer Tx corresponds to the sensor position. The third
position sensor signal TOP0 can be connected to an interrupt input.

Timer T3 has an output toggle latch (T3OTL) which changes its state on each timer over­flow/underflow. The state of this latch may be used internally to clock timers T2 and T4
for measuring long time periods with high resolution.

In addition to their basic operating modes, timers T2 and T4 may be configured as reload
or capture registers for timer T3. When used as capture or reload registers, timers T2
and T4 are stopped. The contents of timer T3 is captured into T2 or T4 in response to a
signal at their associated input pins (TxIN). Timer T3 is reloaded with the contents of T2
or T4 triggered either by an external signal or by a selectable state transition of its toggle
latch T3OTL.

Data Sheet 22 V2.0, 2001-05

C164CI/SI

C164CL/SL

T2EUD

T2IN

T3IN

T3EUD

T4IN

T4EUD

CPU

CPU

CPU

U/D

Interrupt

2n : 1f

2n : 1f

2n : 1f

T2

Mode

Control

T3

Mode

Control

T4

Mode

Control

GPT1 Timer T2

Reload

Capture

Toggle FF

GPT1 Timer T3 T3OTL

U/D

Capture

Reload

GPT1 Timer T4

U/D

Request
(T2IR)

Interrupt
Request
(T3IR)

Other
Timers

Interrupt
Request
(T4IR)

Mct04825_4.vsd

n = 3 … 10

Figure 6 Block Diagram of GPT1

Data Sheet 23 V2.0, 2001-05

C164CI/SI

C164CL/SL

Real Time Clock

The Real Time Clock (RTC) module of the C164CI consists of a chain of 3 divider blocks,
a fixed 8:1 divider, the reloadable 16-bit timer T14, and the 32-bit RTC timer (accessible
via registers RTCH and RTCL). The RTC module is directly clocked with the on-chip

f

oscillator frequency divided by 32 via a separate clock driver (

RTC

= f

therefore independent from the selected clock generation mode of the C164CI. All timers
count up.

The RTC module can be used for different purposes:

• System clock to determine the current time and date

• Cyclic time based interrupt

• 48-bit timer for long term measurements

/32) and is

OSC

T14REL

Reload

f

T14 8:1

RTCLRTCH

RTC

Interrupt
Request

MCD04432

Figure 7 RTC Block Diagram

Note: The registers associated with the RTC are not affected by a reset in order to

maintain the correct system time even when intermediate resets are executed.

Data Sheet 24 V2.0, 2001-05

C164CI/SI

C164CL/SL

A/D Converter

For analog signal measurement, a 10-bit A/D converter with 8 multiplexed input channels
and a sample and hold circuit has been integrated on-chip. It uses the method of
successive approximation. The sample time (for loading the capacitors) and the
conversion time is programmable and can so be adjusted to the external circuitry.

Overrun error detection/protection is provided for the conversion result register
(ADDAT): either an interrupt request will be generated when the result of a previous
conversion has not been read from the result register at the time the next conversion is
complete, or the next conversion is suspended in such a case until the previous result
has been read.

For applications which require less than 8 analog input channels, the remaining channel
inputs can be used as digital input port pins.

The A/D converter of the C164CI supports four different conversion modes. In the
standard Single Channel conversion mode, the analog level on a specified channel is
sampled once and converted to a digital result. In the Single Channel Continuous mode,
the analog level on a specified channel is repeatedly sampled and converted without
software intervention. In the Auto Scan mode, the analog levels on a prespecified
number of channels (standard or extension) are sequentially sampled and converted. In
the Auto Scan Continuous mode, the number of prespecified channels is repeatedly
sampled and converted. In addition, the conversion of a specific channel can be inserted
(injected) into a running sequence without disturbing this sequence. This is called
Channel Injection Mode.

The Peripheral Event Controller (PEC) may be used to automatically store the
conversion results into a table in memory for later evaluation, without requiring the
overhead of entering and exiting interrupt routines for each data transfer.

After each reset and also during normal operation the ADC automatically performs
calibration cycles. This automatic self-calibration constantly adjusts the converter to
changing operating conditions (e.g. temperature) and compensates process variations.

These calibration cycles are part of the conversion cycle, so they do not affect the normal
operation of the A/D converter.

In order to decouple analog inputs from digital noise and to avoid input trigger noise
those pins used for analog input can be disconnected from the digital IO or input stages
under software control. This can be selected for each pin separately via register P5DIDIS
(Port 5 Digital Input Disable).

Data Sheet 25 V2.0, 2001-05

C164CI/SI

C164CL/SL

Serial Channels

Serial communication with other microcontrollers, processors, terminals or external
peripheral components is provided by two serial interfaces with different functionality, an
Asynchronous/Synchronous Serial Channel (ASC0) and a High-Speed Synchronous
Serial Channel (SSC).

The ASC0 is upward compatible with the serial ports of the Infineon 8-bit microcontroller
families and supports full-duplex asynchronous communication at up to 781 Kbit/s and
half-duplex synchronous communication at up to 3.1 Mbit/s (@ 25 MHz CPU clock).
A dedicated baud rate generator allows to set up all standard baud rates without
oscillator tuning. For transmission, reception and error handling 4 separate interrupt
vectors are provided. In asynchronous mode, 8- or 9-bit data frames are transmitted or
received, preceded by a start bit and terminated by one or two stop bits. For
multiprocessor communication, a mechanism to distinguish address from data bytes has
been included (8-bit data plus wake up bit mode).
In synchronous mode, the ASC0 transmits or receives bytes (8 bits) synchronously to a
shift clock which is generated by the ASC0. The ASC0 always shifts the LSB first. A loop
back option is available for testing purposes.
A number of optional hardware error detection capabilities has been included to increase
the reliability of data transfers. A parity bit can automatically be generated on
transmission or be checked on reception. Framing error detection allows to recognize
data frames with missing stop bits. An overrun error will be generated, if the last
character received has not been read out of the receive buffer register at the time the
reception of a new character is complete.

The SSC supports full-duplex synchronous communication at up to 6.25 Mbit/s
(@ 25 MHz CPU clock). It may be configured so it interfaces with serially linked
peripheral components. A dedicated baud rate generator allows to set up all standard
baud rates without oscillator tuning. For transmission, reception and error handling
3 separate interrupt vectors are provided.
The SSC transmits or receives characters of 2 … 16 bits length synchronously to a shift
clock which can be generated by the SSC (master mode) or by an external master (slave
mode). The SSC can start shifting with the LSB or with the MSB and allows the selection
of shifting and latching clock edges as well as the clock polarity.
A number of optional hardware error detection capabilities has been included to increase
the reliability of data transfers. Transmit and receive error supervise the correct handling
of the data buffer. Phase and baudrate error detect incorrect serial data.

Data Sheet 26 V2.0, 2001-05

C164CI/SI

C164CL/SL

CAN-Module

The integrated CAN-Module handles the completely autonomous transmission and
reception of CAN frames in accordance with the CAN specification V2.0 part B (active),
i.e. the on-chip CAN-Modules can receive and transmit standard frames with 11-bit
identifiers as well as extended frames with 29-bit identifiers.

The module provides Full CAN functionality on up to 15 message objects. Message
object 15 may be configured for Basic CAN functionality. Both modes provide separate
masks for acceptance filtering which allows to accept a number of identifiers in Full CAN
mode and also allows to disregard a number of identifiers in Basic CAN mode. All
message objects can be updated independent from the other objects and are equipped
for the maximum message length of 8 bytes.

The bit timing is derived from the XCLK and is programmable up to a data rate of 1 Mbit/
s. Each CAN-Module uses two pins of Port 4 or Port 8 to interface to an external bus
transceiver. The interface pins are assigned via software.

Note: When the CAN interface is assigned to Port 4, the respective segment address

lines on Port 4 cannot be used. This will limit the external address space.

Watchdog Timer

The Watchdog Timer represents one of the fail-safe mechanisms which have been
implemented to prevent the controller from malfunctioning for longer periods of time.

The Watchdog Timer is always enabled after a reset of the chip, and can only be
disabled in the time interval until the EINIT (end of initialization) instruction has been
executed. Thus, the chip’s start-up procedure is always monitored. The software has to
be designed to service the Watchdog Timer before it overflows. If, due to hardware or
software related failures, the software fails to do so, the Watchdog Timer overflows and
generates an internal hardware reset and pulls the RSTOUT
external hardware components to be reset.

The Watchdog Timer is a 16-bit timer, clocked with the system clock divided by 2/4/128/

256. The high byte of the Watchdog Timer register can be set to a prespecified reload
value (stored in WDTREL) in order to allow further variation of the monitored time
interval. Each time it is serviced by the application software, the high byte of the
Watchdog Timer is reloaded. Thus, time intervals between 20 µs and 336 ms can be
monitored (@ 25 MHz).
The default Watchdog Timer interval after reset is 5.24 ms (@ 25 MHz).

pin low in order to allow

Data Sheet 27 V2.0, 2001-05

C164CI/SI

C164CL/SL

Parallel Ports

The C164CI provides up to 59 I/O lines which are organized into five input/output ports
and one input port. All port lines are bit-addressable, and all input/output lines are
individually (bit-wise) programmable as inputs or outputs via direction registers. The I/O
ports are true bidirectional ports which are switched to high impedance state when
configured as inputs. The output drivers of three I/O ports can be configured (pin by pin)
for push/pull operation or open-drain operation via control registers. During the internal
reset, all port pins are configured as inputs.

The input threshold of Port 3, Port 4, and Port 8 is selectable (TTL or CMOS like), where
the special CMOS like input threshold reduces noise sensitivity due to the input
hysteresis. The input threshold may be selected individually for each byte of the
respective ports.

All port lines have programmable alternate input or output functions associated with
them. All port lines that are not used for these alternate functions may be used as general
purpose IO lines.

PORT0 and PORT1 may be used as address and data lines when accessing external
memory, while Port 4 outputs the additional segment address bits A21/19/17 … A16 and
the optional chip select signals in systems where segmentation is enabled to access
more than 64 KBytes of memory.
Ports P1L, P1H, and P8 are associated with the capture inputs or compare outputs of
the CAPCOM units and/or serve as external interrupt inputs.
Port 3 includes alternate functions of timers, serial interfaces, the optional bus control
signal BHE
frequency output FOUT).
Port 5 is used for the analog input channels to the A/D converter or timer control signals.

The edge characteristics (transition time) and driver characteristics (output current) of
the C164CI’s port drivers can be selected via the Port Output Control registers
(POCONx).

/WRH, and the system clock output CLKOUT (or the programmable

Data Sheet 28 V2.0, 2001-05

C164CI/SI

C164CL/SL

Oscillator Watchdog

The Oscillator Watchdog (OWD) monitors the clock signal generated by the on-chip
oscillator (either with a crystal or via external clock drive). For this operation the PLL
provides a clock signal which is used to supervise transitions on the oscillator clock. This
PLL clock is independent from the XTAL1 clock. When the expected oscillator clock
transitions are missing the OWD activates the PLL Unlock/OWD interrupt node and
supplies the CPU with the PLL clock signal. Under these circumstances the PLL will
oscillate with its basic frequency.

f

In direct drive mode the PLL base frequency is used directly (
In prescaler mode the PLL base frequency is divided by 2 (

f

CPU

Note: The CPU clock source is only switched back to the oscillator clock after a

hardware reset.

The oscillator watchdog can be disabled by setting bit OWDDIS in register SYSCON.
In this case (OWDDIS = ‘1’) the PLL remains idle and provides no clock signal, while the
CPU clock signal is derived directly from the oscillator clock or via prescaler or SDD. Also
no interrupt request will be generated in case of a missing oscillator clock.

= 2 … 5 MHz).

CPU

= 1 … 2.5 MHz).

Note: At the end of a reset bit OWDDIS reflects the inverted level of pin RD

Thus the oscillator watchdog may also be disabled via hardware by (externally)
pulling the RD

line low upon a reset, similar to the standard reset configuration via

PORT0.

at that time.

Data Sheet 29 V2.0, 2001-05

C164CI/SI

C164CL/SL

Power Management

The C164CI provides several means to control the power it consumes either at a given
time or averaged over a certain timespan. Three mechanisms can be used (partly in
parallel):

• Power Saving Modes switch the C164CI into a special operating mode (control via
instructions).
Idle Mode stops the CPU while the peripherals can continue to operate.
Sleep Mode and Power Down Mode stop all clock signals and all operation (RTC may
optionally continue running). Sleep Mode can be terminated by external interrupt
signals.

• Clock Generation Management controls the distribution and the frequency of
internal and external clock signals (control via register SYSCON2).

f

Slow Down Mode lets the C164CI run at a CPU clock frequency of
for prescaler operation) which drastically reduces the consumed power. The PLL can
be optionally disabled while operating in Slow Down Mode.
External circuitry can be controlled via the programmable frequency output FOUT.

• Peripheral Management permits temporary disabling of peripheral modules (control
via register SYSCON3).
Each peripheral can separately be disabled/enabled. A group control option disables
a major part of the peripheral set by setting one single bit.

/1 … 32 (half

OSC

The on-chip RTC supports intermittend operation of the C164CI by generating cyclic
wakeup signals. This offers full performance to quickly react on action requests while the
intermittend sleep phases greatly reduce the average power consumption of the system.

Data Sheet 30 V2.0, 2001-05

C164CI/SI

C164CL/SL

Instruction Set Summary

Table 6 lists the instructions of the C164CI in a condensed way.

The various addressing modes that can be used with a specific instruction, the operation
of the instructions, parameters for conditional execution of instructions, and the opcodes
for each instruction can be found in the “C166 Family Instruction Set Manual”.

This document also provides a detailled description of each instruction.

Table 6 Instruction Set Summary

Mnemonic Description Bytes

ADD(B) Add word (byte) operands 2 / 4
ADDC(B) Add word (byte) operands with Carry 2 / 4
SUB(B) Subtract word (byte) operands 2 / 4
SUBC(B) Subtract word (byte) operands with Carry 2 / 4
MUL(U) (Un)Signed multiply direct GPR by direct GPR (16-16-bit) 2
DIV(U) (Un)Signed divide register MDL by direct GPR (16-/16-bit) 2
DIVL(U) (Un)Signed long divide reg. MD by direct GPR (32-/16-bit) 2
CPL(B) Complement direct word (byte) GPR 2
NEG(B) Negate direct word (byte) GPR 2
AND(B) Bitwise AND, (word/byte operands) 2 / 4
OR(B) Bitwise OR, (word/byte operands) 2 / 4
XOR(B) Bitwise XOR, (word/byte operands) 2 / 4
BCLR Clear direct bit 2
BSET Set direct bit 2
BMOV(N) Move (negated) direct bit to direct bit 4
BAND, BOR,

BXOR
BCMP Compare direct bit to direct bit 4
BFLDH/L Bitwise modify masked high/low byte of bit-addressable

CMP(B) Compare word (byte) operands 2 / 4

AND/OR/XOR direct bit with direct bit 4

4

direct word memory with immediate data

CMPD1/2 Compare word data to GPR and decrement GPR by 1/2 2 / 4
CMPI1/2 Compare word data to GPR and increment GPR by 1/2 2 / 4
PRIOR Determine number of shift cycles to normalize direct

word GPR and store result in direct word GPR
SHL / SHR Shift left/right direct word GPR 2
ROL / ROR Rotate left/right direct word GPR 2
ASHR Arithmetic (sign bit) shift right direct word GPR 2

Data Sheet 31 V2.0, 2001-05

2

C164CI/SI

C164CL/SL

Table 6 Instruction Set Summary (cont’d)

Mnemonic Description Bytes

MOV(B) Move word (byte) data 2 / 4
MOVBS Move byte operand to word operand with sign extension 2 / 4
MOVBZ 2 / 4
JMPA, JMPI,

JMPR
JMPS Jump absolute to a code segment 4
J(N)B Jump relative if direct bit is (not) set 4
JBC Jump relative and clear bit if direct bit is set 4
JNBS Jump relative and set bit if direct bit is not set 4
CALLA, CALLI,

CALLR
CALLS Call absolute subroutine in any code segment 4
PCALL Push direct word register onto system stack and call

TRAP Call interrupt service routine via immediate trap number 2
PUSH, POP Push/pop direct word register onto/from system stack 2
SCXT Push direct word register onto system stack und update

RET Return from intra-segment subroutine 2

Move byte operand to word operand with zero extension

Jump absolute/indirect/relative if condition is met 4

Call absolute/indirect/relative subroutine if condition is met 4

4

absolute subroutine

4

register with word operand

RETS Return from inter-segment subroutine 2
RETP Return from intra-segment subroutine and pop direct

word register from system stack
RETI Return from interrupt service subroutine 2
SRST Software Reset 4
IDLE Enter Idle Mode 4
PWRDN Enter Power Down Mode (supposes NMI
SRVWDT Service Watchdog Timer 4
DISWDT Disable Watchdog Timer 4
EINIT Signify End-of-Initialization on RSTOUT
ATOMIC Begin ATOMIC sequence 2
EXTR Begin EXTended Register sequence 2
EXTP(R) Begin EXTended Page (and Register) sequence 2 / 4
EXTS(R) Begin EXTended Segment (and Register) sequence 2 / 4
NOP Null operation 2

-pin being low) 4

-pin 4

2

Data Sheet 32 V2.0, 2001-05

C164CI/SI

C164CL/SL

Special Function Registers Overview

Table 7 lists all SFRs which are implemented in the C164CI in alphabetical order.

Bit-addressable SFRs are marked with the letter “b” in column “Name”. SFRs within the
Extended SFR-Space (ESFRs) are marked with the letter “E” in column “Physical

Address”. Registers within on-chip X-peripherals are marked with the letter “X” in column
“Physical Address”.

An SFR can be specified via its individual mnemonic name. Depending on the selected
addressing mode, an SFR can be accessed via its physical address (using the Data
Page Pointers), or via its short 8-bit address (without using the Data Page Pointers).

Table 7 C164CI Registers, Ordered by Name

Name Physical

Address

ADCIC b FF98

ADCON b FFA0

ADDAT FEA0

ADDAT2 F0A0

ADDRSEL1 FE18

ADDRSEL2 FE1A

ADDRSEL3 FE1C

ADDRSEL4 FE1E

ADEIC b FF9A

BUSCON0 b FF0C

BUSCON1 b FF14

BUSCON2 b FF16

H

H

H

H

H

H

H

H

H

H

H

H

8-Bit
Addr.

CC

D0

50

E 50

0C

0D

0E

0F

CD

86

8A

8B

Description Reset

A/D Converter End of Conversion

H

Interrupt Control Register

A/D Converter Control Register 0000

H

A/D Converter Result Register 0000

H

A/D Converter 2 Result Register 0000

H

Address Select Register 1 0000

H

Address Select Register 2 0000

H

Address Select Register 3 0000

H

Address Select Register 4 0000

H

A/D Converter Overrun Error Interrupt

H

Control Register

Bus Configuration Register 0 0000

H

Bus Configuration Register 1 0000

H

Bus Configuration Register 2 0000

H

Value

0000

0000

H

H

H

H

H

H

H

H

H

H

H

H

BUSCON3 b FF18

BUSCON4 b FF1A

C1BTR EF04

C1CSR EF00

C1GMS EF06

C1LARn EFn4

C1LGML EF0A

C1LMLM EF0E

Data Sheet 33 V2.0, 2001-05

H

H

H

H

H

H

H

H

8C

8D

Bus Configuration Register 3 0000

H

Bus Configuration Register 4 0000

H

X --- CAN1 Bit Timing Register UUUU

X --- CAN1 Control / Status Register XX01

X --- CAN1 Global Mask Short UFUU

X --- CAN Lower Arbitration Register (msg. n) UUUU

X --- CAN Lower Global Mask Long UUUU

X --- CAN Lower Mask of Last Message UUUU

H

H

H

H

H

H

H

H

Table 7 C164CI Registers, Ordered by Name (cont’d)

C164CI/SI

C164CL/SL

Name Physical

Address

C1MCFGn EFn6

C1MCRn EFn0

C1PCIR EF02

C1UARn EFn2

C1UGML EF08

C1UMLM EF0C

CC10IC b FF8C

CC11IC b FF8E

CC16 FE60

CC16IC b F160

CC17 FE62

CC17IC b F162

H

H

H

H

H

H

H

H

H

H

H

H

8-Bit
Addr.

X --- CAN Message Configuration Register

Description Reset

Value

UU

(msg. n)

X --- CAN Message Control Register (msg. n) UUUU

X --- CAN1 Port Control / Interrupt Register XXXX

X --- CAN Upper Arbitration Register (msg. n) UUUU

X --- CAN Upper Global Mask Long UUUU

X --- CAN Upper Mask of Last Message UUUU

C6

C7

30

E B0

31

E B1

External Interrupt 2 Control Register 0000

H

External Interrupt 3 Control Register 0000

H

CAPCOM Register 16 0000

H

CAPCOM Reg. 16 Interrupt Ctrl. Reg. 0000

H

CAPCOM Register 17 0000

H

CAPCOM Reg. 17 Interrupt Ctrl. Reg. 0000

H

H

H

H

H

H

H

H

H

H

H

H

H

CC18 FE64

CC18IC b F164

CC19 FE66

CC19IC b F166

CC20 FE68

CC20IC b F168

CC21 FE6A

CC21IC b F16A

CC22 FE6C

H

H

H

H

H

H

H

H

H

32

E B2

33

E B3

34

E B4

35

E B5

36

CC22IC b F16CHE B6

CC23 FE6E

CC23IC b F16E

CC24 FE70

CC24IC b F170

CC25 FE72

H

H

H

H

H

37

E B7

38

E B8

39

CAPCOM Register 18 0000

H

CAPCOM Reg. 18 Interrupt Ctrl. Reg. 0000

H

CAPCOM Register 19 0000

H

CAPCOM Reg. 19 Interrupt Ctrl. Reg. 0000

H

CAPCOM Register 20 0000

H

CAPCOM Reg. 20 Interrupt Ctrl. Reg. 0000

H

CAPCOM Register 21 0000

H

CAPCOM Reg. 21 Interrupt Ctrl. Reg. 0000

H

CAPCOM Register 22 0000

H

CAPCOM Reg. 22 Interrupt Ctrl. Reg. 0000

H

CAPCOM Register 23 0000

H

CAPCOM Reg. 23 Interrupt Ctrl. Reg. 0000

H

CAPCOM Register 24 0000

H

CAPCOM Reg. 24 Interrupt Ctrl. Reg. 0000

H

CAPCOM Register 25 0000

H

H

H

H

H

H

H

H

H

H

H

H

H

H

H

H

CC25IC b F172

CC26 FE74

Data Sheet 34 V2.0, 2001-05

H

H

E B9

3A

CAPCOM Reg. 25 Interrupt Ctrl. Reg. 0000

H

CAPCOM Register 26 0000

H

H

H

Table 7 C164CI Registers, Ordered by Name (cont’d)

C164CI/SI

C164CL/SL

Name Physical

Address

CC26IC b F174

CC27 FE76

CC27IC b F176

CC28 FE78

CC28IC b F178

CC29 FE7A

CC29IC b F184

CC30 FE7C

H

H

H

H

H

H

H

H

8-Bit
Addr.

E BA

3B

E BB

3C

E BC

3D

E C2

3E

CC30IC b F18CHE C6

CC31 FE7E

CC31IC b F194

CC60 FE30

CC61 FE32

H

H

H

H

3F

E CA

18

19

Description Reset

CAPCOM Reg. 26 Interrupt Ctrl. Reg. 0000

H

CAPCOM Register 27 0000

H

CAPCOM Reg. 27 Interrupt Ctrl. Reg. 0000

H

CAPCOM Register 28 0000

H

CAPCOM Reg. 28 Interrupt Ctrl. Reg. 0000

H

CAPCOM Register 29 0000

H

CAPCOM Reg. 29 Interrupt Ctrl. Reg. 0000

H

CAPCOM Register 30 0000

H

CAPCOM Reg. 30 Interrupt Ctrl. Reg. 0000

H

CAPCOM Register 31 0000

H

CAPCOM Reg. 31 Interrupt Ctrl. Reg. 0000

H

CAPCOM 6 Register 0 0000

H

CAPCOM 6 Register 1 0000

H

Value

H

H

H

H

H

H

H

H

H

H

H

H

H

CC62 FE34

CC6EIC b F188

CC6CIC b F17E

CC6MCON b FF32

CC6MIC b FF36

CC6MSEL F036

CC8IC b FF88

CC9IC b FF8A

CCM4 b FF22

CCM5 b FF24

CCM6 b FF26

CCM7 b FF28

CMP13 FE36

CP FE10

H

H

H

H

H

H

H

H

H

H

H

H

H

H

1A

E C4

E BF

99

9B

E 1B

C4

C5

91

92

93

94

1B

08

CAPCOM 6 Register 2 0000

H

CAPCOM 6 Emergency Interrrupt

H

Control Register

CAPCOM 6 Interrupt Control Register 0000

H

CAPCOM 6 Mode Control Register 00FF

H

CAPCOM 6 Mode Interrupt Ctrl. Reg. 0000

H

CAPCOM 6 Mode Select Register 0000

H

External Interrupt 0 Control Register 0000

H

External Interrupt 1 Control Register 0000

H

CAPCOM Mode Control Register 4 0000

H

CAPCOM Mode Control Register 5 0000

H

CAPCOM Mode Control Register 6 0000

H

CAPCOM Mode Control Register 7 0000

H

CAPCOM 6 Timer 13 Compare Reg. 0000

H

CPU Context Pointer Register FC00

H

0000

H

H

H

H

H

H

H

H

H

H

H

H

H

H

CSP FE08

H

04

CPU Code Segment Pointer Register

H

0000

H

(8 bits, not directly writeable)

Data Sheet 35 V2.0, 2001-05

Table 7 C164CI Registers, Ordered by Name (cont’d)

C164CI/SI

C164CL/SL

Name Physical

Address

CTCON b FF30

DP0H b F102

DP0L b F100

DP1H b F106

DP1L b F104

DP3 b FFC6

DP4 b FFCA

DP8 b FFD6

DPP0 FE00

DPP1 FE02

DPP2 FE04

DPP3 FE06

EXICON b F1C0

H

H

H

H

H

H

H

H

H

H

H

H

H

8-Bit
Addr.

98

E 81

E 80

E 83

E 82

E3

E5

EB

00

01

02

03

E E0

Description Reset

CAPCOM 6 Compare Timer Ctrl. Reg. 1010

H

P0H Direction Control Register 00

H

P0L Direction Control Register 00

H

P1H Direction Control Register 00

H

P1L Direction Control Register 00

H

Port 3 Direction Control Register 0000

H

Port 4 Direction Control Register 00

H

Port 8 Direction Control Register 00

H

CPU Data Page Pointer 0 Reg. (10 bits) 0000

H

CPU Data Page Pointer 1 Reg. (10 bits) 0001

H

CPU Data Page Pointer 2 Reg. (10 bits) 0002

H

CPU Data Page Pointer 3 Reg. (10 bits) 0003

H

External Interrupt Control Register 0000

H

Value

H

H

H

H

H

H

H

H

H

H

H

H

H

EXISEL b F1DAHE ED

FOCON b FFAA

IDCHIP F07C

IDMANUF F07E

IDMEM F07A

IDPROG F078

IDMEM2 F076

H

H

H

H

H

H

D5

E 3E

E 3F

E 3D

E 3C

E 3B

ISNC b F1DEHE EF

MDC b FF0E

MDH FE0C

MDL FE0E

ODP3 b F1C6

H

H

H

H

87

06

07

E E3

ODP4 b F1CAHE E5

ODP8 b F1D6

ONES b FF1E

H

H

E EB

8F

External Interrupt Source Select Reg. 0000

H

Frequency Output Control Register 0000

H

Identifier XXXX

H

Identifier 1820

H

Identifier XXXX

H

Identifier XXXX

H

Identifier XXXX

H

Interrupt Subnode Control Register 0000

H

CPU Multiply Divide Control Register 0000

H

CPU Multiply Divide Reg. – High Word 0000

H

CPU Multiply Divide Reg. – Low Word 0000

H

Port 3 Open Drain Control Register 0000

H

Port 4 Open Drain Control Register 00

H

Port 8 Open Drain Control Register 00

H

Constant Value 1’s Register (read only) FFFF

H

H

H

H

H

H

H

H

H

H

H

H

H

H

H

H

OPAD EDC2HX --- OTP Progr. Interface Address Register 0000

OPCTRL EDC0HX --- OTP Progr. Interface Control Register 0007

Data Sheet 36 V2.0, 2001-05

H

H

Table 7 C164CI Registers, Ordered by Name (cont’d)

C164CI/SI

C164CL/SL

Name Physical

Address

8-Bit
Addr.

Description Reset

Value

OPDAT EDC4HX --- OTP Progr. Interface Data Register 0000

P0H b FF02

P0L b FF00

P1H b FF06

P1L b FF04

P3 b FFC4

P4 b FFC8

P5 b FFA2

P5DIDIS b FFA4

P8 b FFD4

PECC0 FEC0

PECC1 FEC2

PECC2 FEC4

H

H

H

H

H

H

H

H

H

H

H

H

81

80

83

82

E2

E4

D1

D2

EA

60

61

62

Port 0 High Reg. (Upper half of PORT0) 00

H

Port 0 Low Reg. (Lower half of PORT0) 00

H

Port 1 High Reg. (Upper half of PORT1) 00

H

Port 1 Low Reg. (Lower half of PORT1) 00

H

Port 3 Register 0000

H

Port 4 Register (7 bits) 00

H

Port 5 Register (read only) XXXX

H

Port 5 Digital Input Disable Register 0000

H

Port 8 Register (8 bits) 00

H

PEC Channel 0 Control Register 0000

H

PEC Channel 1 Control Register 0000

H

PEC Channel 2 Control Register 0000

H

H

H

H

H

H

H

H

H

H

H

H

H

H

PECC3 FEC6

PECC4 FEC8

PECC5 FECA

PECC6 FECC

PECC7 FECE

PICON b F1C4

POCON0H F082

POCON0L F080

POCON1H F086

POCON1L F084

POCON20 F0AA

POCON3 F08A

POCON4 F08C

POCON8 F092

PSW b FF10

H

H

H

H

H

H

H

H

H

H

H

H

H

H

H

63

64

65

66

67

E E2

E 41

E 40

E 43

E 42

E 55

E 45

E 46

E 49

88

PEC Channel 3 Control Register 0000

H

PEC Channel 4 Control Register 0000

H

PEC Channel 5 Control Register 0000

H

PEC Channel 6 Control Register 0000

H

PEC Channel 7 Control Register 0000

H

Port Input Threshold Control Register 0000

H

Port P0H Output Control Register 0011

H

Port P0L Output Control Register 0011

H

Port P1H Output Control Register 0011

H

Port P1L Output Control Register 0011

H

Dedicated Pin Output Control Register 0000

H

Port P3 Output Control Register 2222

H

Port P4 Output Control Register 0010

H

Port P8 Output Control Register 0022

H

CPU Program Status Word 0000

H

H

H

H

H

H

H

H

H

H

H

H

H

H

H

H

RP0H b F108

RSTCON b F1E0Hm --- Reset Control Register 00XX

Data Sheet 37 V2.0, 2001-05

E 84

H

System Startup Config. Reg. (Rd. only) XX

H

H

H

Table 7 C164CI Registers, Ordered by Name (cont’d)

C164CI/SI

C164CL/SL

Name Physical

Address

RTCH F0D6

RTCL F0D4

S0BG FEB4

S0CON b FFB0

S0EIC b FF70

S0RBUF FEB2

S0RIC b FF6E

S0TBIC b F19C

S0TBUF FEB0

H

H

H

H

H

H

H

H

H

8-Bit
Addr.

E 6B

E 6A

5A

D8

B8

59

B7

E CE

58

Description Reset

RTC High Register no

H

RTC Low Register no

H

Serial Channel 0 Baud Rate Generator

H

Reload Register

Serial Channel 0 Control Register 0000

H

Serial Channel 0 Error Interrupt Ctrl.

H

Reg.

Serial Channel 0 Receive Buffer Reg.

H

(read only)

Serial Channel 0 Receive Interrupt

H

Control Register

Serial Channel 0 Transmit Buffer

H

Interrupt Control Register

Serial Channel 0 Transmit Buffer Reg.

H

(write only)

Value

0000

0000

XXXX

0000

0000

0000

H

H

H

H

H

H

H

S0TIC b FF6C

SP FE12

SSCBR F0B4

SSCCON b FFB2

SSCEIC b FF76

SSCRB F0B2

SSCRIC b FF74

SSCTB F0B0

SSCTIC b FF72

STKOV FE14

STKUN FE16

SYSCON b FF12

H

H

H

H

H

H

H

H

H

H

H

H

B6

09

E 5A

D9

BB

E 59

BA

E 58

B9

0A

0B

89

SYSCON1 b F1DCHE EE

SYSCON2 b F1D0

H

E E8

Serial Channel 0 Transmit Interrupt

H

Control Register

CPU System Stack Pointer Register FC00

H

SSC Baudrate Register 0000

H

SSC Control Register 0000

H

SSC Error Interrupt Control Register 0000

H

SSC Receive Buffer XXXX

H

SSC Receive Interrupt Control Register 0000

H

SSC Transmit Buffer 0000

H

SSC Transmit Interrupt Control Register 0000

H

CPU Stack Overflow Pointer Register FA00

H

CPU Stack Underflow Pointer Register FC00

H

CPU System Configuration Register

H

CPU System Configuration Register 1 0000

H

CPU System Configuration Register 2 0000

H

1)

0xx0

0000

H

H

H

H

H

H

H

H

H

H

H

H

H

H

SYSCON3 b F1D4

Data Sheet 38 V2.0, 2001-05

H

E EA

CPU System Configuration Register 3 0000

H

H

Table 7 C164CI Registers, Ordered by Name (cont’d)

C164CI/SI

C164CL/SL

Name Physical

Address

T12IC b F190

T12OF F034

T12P F030

T13IC b F198

T13P F032

T14 F0D2

T14REL F0D0

T2 FE40

T2CON b FF40

T2IC b FF60

T3 FE42

T3CON b FF42

T3IC b FF62

H

H

H

H

H

H

H

H

H

H

H

H

H

8-Bit
Addr.

E C8

E 1A

E 18

E CC

E 19

E 69

E 68

20

A0

B0

21

A1

B1

Description Reset

CAPCOM 6 Timer 12 Interrupt Ctrl. Reg. 0000

H

CAPCOM 6 Timer 12 Offset Register 0000

H

CAPCOM 6 Timer 12 Period Register 0000

H

CAPCOM 6 Timer 13 Interrupt Ctrl. Reg. 0000

H

CAPCOM 6 Timer 13 Period Register 0000

H

RTC Timer 14 Register no

H

RTC Timer 14 Reload Register no

H

GPT1 Timer 2 Register 0000

H

GPT1 Timer 2 Control Register 0000

H

GPT1 Timer 2 Interrupt Control Register 0000

H

GPT1 Timer 3 Register 0000

H

GPT1 Timer 3 Control Register 0000

H

GPT1 Timer 3 Interrupt Control Register 0000

H

Value

H

H

H

H

H

H

H

H

H

H

H

T4 FE44

T4CON b FF44

T4IC b FF64

T7 F050

T78CON b FF20

T7IC b F17A

T7REL F054

T8 F052

T8IC b F17C

T8REL F056

TFR b FFAC

TRCON b FF34

WDT FEAE

WDTCON FFAE

XP0IC b F186

H

H

H

H

H

H

H

H

H

H

H

H

H

H

H

22

A2

B2

E 28

90

E BD

E 2A

E 29

E BE

E 2B

D6

9A

57

D7

E C3

GPT1 Timer 4 Register 0000

H

GPT1 Timer 4 Control Register 0000

H

GPT1 Timer 4 Interrupt Control Register 0000

H

CAPCOM Timer 7 Register 0000

H

CAPCOM Timer 7 and 8 Ctrl. Reg. 0000

H

CAPCOM Timer 7 Interrupt Ctrl. Reg. 0000

H

CAPCOM Timer 7 Reload Register 0000

H

CAPCOM Timer 8 Register 0000

H

CAPCOM Timer 8 Interrupt Ctrl. Reg. 0000

H

CAPCOM Timer 8 Reload Register 0000

H

Trap Flag Register 0000

H

CAPCOM 6 Trap Enable Ctrl. Reg. 00XX

H

Watchdog Timer Register (read only) 0000

H

Watchdog Timer Control Register

H

CAN1 Module Interrupt Control Register 0000

H

2)

00xx

H

H

H

H

H

H

H

H

H

H

H

H

H

H

H

XP1IC b F18E

Data Sheet 39 V2.0, 2001-05

H

E C7

Unassigned Interrupt Control Reg. 0000

H

H

Table 7 C164CI Registers, Ordered by Name (cont’d)

C164CI/SI

C164CL/SL

Name Physical

Address

XP3IC b F19E

ZEROS b FF1C

1)

The system configuration is selected during reset.

2)

The reset value depends on the indicated reset source.

H

H

8-Bit
Addr.

E CF

8E

Description Reset

PLL/RTC Interrupt Control Register 0000

H

Constant Value 0’s Register (read only) 0000

H

Value

H

H

Note: The three registers of the OTP programming interface are, of course, only

implemented in the OTP versions of the C164CI.

Data Sheet 40 V2.0, 2001-05

C164CL/SL

Absolute Maximum Ratings

Table 8 Absolute Maximum Rating Parameters

Parameter Symbol Limit Values Unit Notes

min. max.

C164CI/SI

Storage temperature

Junction temperature

Voltage on
respect to ground (

V

pins with

DD

V

SS

)

Voltage on any pin with

V

respect to ground (

SS

)

Input current on any pin

T

ST

T

J

V

DD

V

IN

– -10 10 mA –

-65 150 °C –

-40 150 °C under bias

-0.5 6.5 V –

-0.5 VDD + 0.5 V –

during overload condition

Absolute sum of all input

–– |100| mA –
currents during overload
condition

Power dissipation

P

DISS

– 1.5 W –

Note: Stresses above those listed under “Absolute Maximum Ratings” may cause

permanent damage to the device. This is a stress rating only and functional
operation of the device at these or any other conditions above those indicated in
the operational sections of this specification is not implied. Exposure to absolute
maximum rating conditions for extended periods may affect device reliability.

V

During absolute maximum rating overload conditions (

V

voltage on

pins with respect to ground (VSS) must not exceed the values

DD

> VDD or VIN< VSS) the

IN

defined by the absolute maximum ratings.

Data Sheet 41 V2.0, 2001-05

C164CI/SI

C164CL/SL

Operating Conditions

The following operating conditions must not be exceeded in order to ensure correct
operation of the C164CI. All parameters specified in the following sections refer to these
operating conditions, unless otherwise noticed.

Table 9 Operating Condition Parameters

Parameter Symbol Limit Values Unit Notes

min. max.

Digital supply voltage

Digital ground voltage

Overload current

Absolute sum of overload

V

DD

V

SS

I

OV

Σ|IOV| – 50 mA

4.75 5.5 V Active mode,

2.5

1)

f

CPUmax

5.5 V PowerDown mode

= 25 MHz

0 V Reference voltage

– ±5 mA Per pin

3)

2)3)

currents

External Load
Capacitance

Ambient temperature T

C

L

– 100 pF Pin drivers in

default mode

A

070°C SAB-C164CI …

-40 85 °C SAF-C164CI …

-40 125 °C SAK-C164CI …

1)

Output voltages and output currents will be reduced when VDD leaves the range defined for active mode.

2)

Overload conditions occur if the standard operatings conditions are exceeded, i.e. the voltage on any pin
exceeds the specified range (i.e.
currents on all pins may not exceed 50 mA. The supply voltage must remain within the specified limits.
Proper operation is not guaranteed if overload conditions occur on functional pins line XTAL1, RD

3)

Not 100% tested, guaranteed by design and characterization.

4)

The timing is valid for pin drivers operating in default current mode (selected after reset). Reducing the output
current may lead to increased delays or reduced driving capability (

5)

The current ROM-version of the C164CI is equipped with port drivers, which provide reduced driving capability
and reduced control. Please refer to the actual errata sheet for details.

V

> VDD + 0.5 V or VOV< VSS - 0.5 V). The absolute sum of input overload

OV

C

).

L

, WR, etc.

4)5)

Data Sheet 42 V2.0, 2001-05

C164CI/SI

C164CL/SL

Parameter Interpretation

The parameters listed in the following partly represent the characteristics of the C164CI
and partly its demands on the system. To aid in interpreting the parameters right, when
evaluating them for a design, they are marked in column “Symbol”:

CC (Controller Characteristics):
The logic of the C164CI will provide signals with the respective characteristics.

SR (System Requirement):
The external system must provide signals with the respective characteristics to the
C164CI.

DC Characteristics

(Operating Conditions apply)

Parameter Symbol Limit Values Unit Test Conditions

1)

Input low voltage (TTL,
all except XTAL1)

Input low voltage XTAL1

Input low voltage
(Special Threshold)

Input high voltage (TTL,
all except RSTIN

, XTAL1)

Input high voltage RSTIN
(when operated as input)

Input high voltage XTAL1

Input high voltage
(Special Threshold)

Input Hysteresis
(Special Threshold)

Output low voltage

Output high voltage

2)

5)

min. max.

V

SR -0.5 0.2 V

IL

DD

V –

- 0.1

V

V

V

V

SR -0.5 0.3 V

IL2

SR -0.5 2.0 V –

ILS

SR 0.2 V

IH

DD

+ 0.9

SR 0.6 V

IH1

DDVDD

V

DD

0.5

DD

+

+

V –

V –

V –

0.5

V

IH2

SR 0.7 V

DDVDD

+

V –

0.5

V

IHS

SR 0.8 V

- 0.2

DD

V

DD

0.5

+

V –

HYS 400 – mV Series resistance

= 0 Ω

V

V

CC – 1.0 V IOL ≤ I

OL

– 0.45 V IOL ≤ I

CC VDD -

OH

– V IOH ≥ I

OLmax

OLnom

OHmax

3)

3)4)

3)

1.0

V

DD

-

– V IOH ≥ I

OHnom

3)4)

0.45

Input leakage current (Port 5) I

Data Sheet 43 V2.0, 2001-05

CC – ±200 nA 0 V < VIN < V

OZ1

DD

C164CI/SI

C164CL/SL

DC Characteristics (cont’d)

(Operating Conditions apply)

Parameter Symbol Limit Values Unit Test Conditions

1)

min. max.

Input leakage current (all other) I

9)

9)

9)

6)

9)

9)

9)

6)

10)

I

I

I

I

I

I

I

I

I

RSTIN inactive current

RSTIN active current

RD/WR inact. current

/WR active current

RD

ALE inactive current

ALE active current

Port 4 inactive current

Port 4 active current

PORT0 configuration current

I

XTAL1 input current I

Pin capacitance
(digital inputs/outputs)

1)

Keeping signal levels within the levels specified in this table, ensures operation without overload conditions.
For signal levels outside these specifications also refer to the specification of the overload current

2)

For pin RSTIN this specification is only valid in bidirectional reset mode.

3)

The maximum deliverable output current of a port driver depends on the selected output driver mode, see

Table 10, Current Limits for Port Output Drivers. The limit for pin groups must be respected.

4)

As a rule, with decreasing output current the output levels approach the respective supply level (V

V

→ V

OH

5)

This specification is not valid for outputs which are switched to open drain mode. In this case the respective
output will float and the voltage results from the external circuitry.

6)

These parameters describe the RSTIN pullup, which equals a resistance of ca. 50 to 250 kΩ.

7)

The maximum current may be drawn while the respective signal line remains inactive.

8)

The minimum current must be drawn in order to drive the respective signal line active.

9)

This specification is valid during Reset and during Adapt-mode. The Port 4 current values are only valid for
pins P4.3-0, which can act as CS

10)

This specification is valid during Reset if required for configuration, and during Adapt-mode.

11)

Not 100% tested, guaranteed by design and characterization.

DD

11)

). However, only the levels for nominal output currents are guaranteed.

outputs.

C

CC – ±500 nA 0.45 V < VIN <

OZ2

V

DD

7)

RSTH

RSTL

RWH

8)

RWL

ALEL

ALEH

7)

P4H

8)

P4L

7)

P0H

8)

P0L

IL

IO

– -10 µA VIN = V

8)

-100 – µA VIN = V

7)

– -40 µA V

-500 – µA V

7)

– 40 µA V

8)

500 – µA V

– -40 µA V

-500 – µA V

OUT

OUT

OUT

OUT

OUT

OUT

– -10 µA VIN = V

-100 – µA VIN = V

CC – ±20 µA0 V < VIN < V

CC – 10 pF f = 1 MHz

T

= 25 °C

A

IH1

IL

= 2.4 V

= V

OLmax

= V

OLmax

= 2.4 V

= 2.4 V

= V

OL1max

IHmin

ILmax

I

OV

OL

DD

.

→ V

SS

,

Data Sheet 44 V2.0, 2001-05

Table 10 Current Limits for Port Output Drivers

C164CI/SI

C164CL/SL

Port Output Driver
Mode

Maximum Output Current

I

(

OLmax

, -I

OHmax

1)

)

Nominal Output Current

I

(

OLnom

, -I

OHnom

2)

)

Strong driver 10 mA 2.5 mA

Medium driver 4.0 mA 1.0 mA

Weak driver 0.5 mA 0.1 mA

1)

An output current above |I
For any group of 16 neighboring port output pins the total output current in each direction (
must remain below 50 mA.

2)

The current ROM-version of the C164CI (step Ax) is equipped with port drivers, which provide reduced driving
capability and reduced control. Please refer to the actual errata sheet for details.

| may be drawn from up to three pins at the same time.

OXnom

ΣI

and Σ-IOH)

OL

Power Consumption C164CI (ROM)

(Operating Conditions apply)

Parameter Sym-

bol

Power supply current (active)

I

DD

with all peripherals active

Limit Values Unit Test

min. max.

– 1 +

2.5 ×

f

mA RSTIN = V

CPU

Conditions

f

in [MHz]

CPU

IL

1)

Idle mode supply current
with all peripherals active

Idle mode supply current
with all peripherals deactivated,

I

IDX

I

IDO

– 1 +

2)

– 500 +

1.1 × f

50 ×

CPU

f

OSC

mA RSTIN = V

f

in [MHz]

CPU

µARSTIN = V

f

in [MHz]

OSC

PLL off, SDD factor = 32

Sleep and Power-down mode
supply current with RTC running

Sleep and Power-down mode

I

PDR

I

PDO

2)

– 200 +

25 ×

f

OSC

µA VDD = V

f

– 50 µA VDD = V

OSC

DDmax

in [MHz]

DDmax

supply current with RTC disabled

1)

The supply current is a function of the operating frequency. This dependency is illustrated in Figure 9.
These parameters are tested at
at

V

or VIH.

IL

2)

This parameter is determined mainly by the current consumed by the oscillator (see Figure 8). This current,
however, is influenced by the external oscillator circuitry (crystal, capacitors). The values given refer to a typical
circuitry and may change in case of a not optimized external oscillator circuitry.

3)

This parameter is tested including leakage currents. All inputs (including pins configured as inputs) at 0 V to

0.1 V or at

V

- 0.1 V to VDD, V

DD

V

REF

and maximum CPU clock with all outputs disconnected and all inputs

DDmax

= 0 V, all outputs (including pins configured as outputs) disconnected.

IH1

IH1

1)

1)

3)

3)

Data Sheet 45 V2.0, 2001-05

Power Consumption C164CI (OTP)

(Operating Conditions apply)

C164CI/SI

C164CL/SL

Parameter Sym-

bol

Power supply current (active)

I

DD

with all peripherals active

Idle mode supply current

I

IDX

with all peripherals active

Idle mode supply current

I

IDO

2)

with all peripherals deactivated,

Limit Values Unit Test

min. max.

– 10 +

3.5 ×

– 5 +

1.25 ×

– 500 +

50 ×

f

CPU

f

OSC

f

mA RSTIN = V

mA RSTIN = V

CPU

µARSTIN = V

Conditions

f

in [MHz]

CPU

f

in [MHz]

CPU

f

in [MHz]

OSC

PLL off, SDD factor = 32

Sleep and Power-down mode
supply current with RTC running

Sleep and Power-down mode

I

PDR

I

PDO

2)

– 200 +

25 ×

f

OSC

µA VDD = V

f

– 50 µA VDD = V

OSC

DDmax

in [MHz]

DDmax

supply current with RTC disabled

1)

The supply current is a function of the operating frequency. This dependency is illustrated in Figure 10.
These parameters are tested at
at

V

or VIH.

IL

2)

This parameter is determined mainly by the current consumed by the oscillator (see Figure 8). This current,
however, is influenced by the external oscillator circuitry (crystal, capacitors). The values given refer to a typical
circuitry and may change in case of a not optimized external oscillator circuitry.

3)

This parameter is tested including leakage currents. All inputs (including pins configured as inputs) at 0 V to

0.1 V or at

V

- 0.1 V to VDD, V

DD

V

REF

and maximum CPU clock with all outputs disconnected and all inputs

DDmax

= 0 V, all outputs (including pins configured as outputs) disconnected.

IL

IH1

IH1

1)

1)

1)

3)

3)

Data Sheet 46 V2.0, 2001-05

C164CI/SI

C164CL/SL

Ι

µA

1500

1250

1000

750

500

250

0

0

4 8 12 16

I

IDOmax

I

IDOtyp

I

PDRmax

I

PDOmax

MHz

MCD04433

f

OSC

Figure 8 Idle and Power Down Supply Current as a Function of Oscillator

Frequency

Data Sheet 47 V2.0, 2001-05

I [mA]

100

80

60

C164CI/SI

C164CL/SL

I

DD5max

I

DD5typ

40

20

10 15 20 25

f

CPU

Figure 9 Supply/Idle Current as a Function of Operating Frequency

for ROM Derivatives

I

IDX5max

I

IDX5typ

[MHz]

Data Sheet 48 V2.0, 2001-05

C164CI/SI

C164CL/SL

I [mA]

100

80

60

40

I

DD5max

I

DD5typ

I

IDX5max

I

IDX5typ

20

10 15 20 25

f

CPU

Figure 10 Supply/Idle Current as a Function of Operating Frequency

for OTP Derivatives

[MHz]

Data Sheet 49 V2.0, 2001-05

C164CI/SI

C164CL/SL

AC Characteristics Definition of Internal Timing

f

The internal operation of the C164CI is controlled by the internal CPU clock
edges of the CPU clock can trigger internal (e.g. pipeline) or external (e.g. bus cycles)
operations.

The specification of the external timing (AC Characteristics) therefore depends on the
time between two consecutive edges of the CPU clock, called “TCL” (see Figure 11).

Phase Locked Loop Operation

f

OSC

TCL

f

CPU

CPU

. Both

TCL

Direct Clock Drive

f

OSC

TCL

f

CPU

TCL

Prescaler Operation

f

OSC

TCL

f

CPU

TCL

MCT04338

Figure 11 Generation Mechanisms for the CPU Clock

The CPU clock signal

f

can be generated from the oscillator clock signal f

CPU

OSC

via

different mechanisms. The duration of TCLs and their variation (and also the derived

f

external timing) depends on the used mechanism to generate

. This influence must

CPU

be regarded when calculating the timings for the C164CI.

Note: The example for PLL operation shown in Figure 11 refers to a PLL factor of 4.

The used mechanism to generate the basic CPU clock is selected by bitfield CLKCFG
in register RP0H.7-5.
Upon a long hardware reset register RP0H is loaded with the logic levels present on the
upper half of PORT0 (P0H), i.e. bitfield CLKCFG represents the logic levels on pins

Data Sheet 50 V2.0, 2001-05

C164CI/SI

C164CL/SL

P0.15-13 (P0H.7-5). Register RP0H can be loaded from the upper half of register
RSTCON under software control.

Table 11 associates the combinations of these three bits with the respective clock

generation mode.

Table 11 C164CI Clock Generation Modes

1)

CLKCFG
(RP0H.7-5)

11 1

CPU Frequency

f

= f

CPU

f

× 4 2.5 to 6.25 MHz Default configuration

OSC

OSC

× F

External Clock
Input Range

2)

Notes

110

101

100

011

010 f

001

000

1)

Please note that pin P0.15 (corresponding to RP0H.7) is inverted in emulation mode, and thus also in EHM.

2)

The external clock input range refers to a CPU clock range of 10 … 25 MHz.

3)

The maximum frequency depends on the duty cycle of the external clock signal.

f

× 3 3.33 to 8.33 MHz –

OSC

f

× 2 5 to 12.5 MHz –

OSC

f

× 5 2 to 5 MHz –

OSC

f

× 1 1 to 25 MHz Direct drive

OSC

× 1.5 6.66 to 16.66 MHz –

OSC

f

/ 2 2 to 50 MHz CPU clock via prescaler

OSC

f

× 2.5 4 to 10 MHz –

OSC

3)

Prescaler Operation

When prescaler operation is configured (CLKCFG = 001

) the CPU clock is derived from

B

the internal oscillator (input clock signal) by a 2:1 prescaler.

f

The frequency of

is half the frequency of f

CPU

the duration of an individual TCL) is defined by the period of the input clock

and the high and low time of f

OSC

f

OSC

CPU

.

(i.e.

The timings listed in the AC Characteristics that refer to TCLs therefore can be
calculated using the period of f

for any TCL.

OSC

Phase Locked Loop

When PLL operation is configured (via CLKCFG) the on-chip phase locked loop is
enabled and provides the CPU clock (see Table 11). The PLL multiplies the input
frequency by the factor F which is selected via the combination of pins P0.15-13 (i.e.

f

CPU

= f

× F). With every F’th transition of f

OSC

the PLL circuit synchronizes the CPU

OSC

clock to the input clock. This synchronization is done smoothly, i.e. the CPU clock
frequency does not change abruptly.

Data Sheet 51 V2.0, 2001-05

C164CI/SI

C164CL/SL

Due to this adaptation to the input clock the frequency of f

f

it is locked to

. The slight variation causes a jitter of f

OSC

is constantly adjusted so

CPU

which also effects the

CPU

duration of individual TCLs.

The timings listed in the AC Characteristics that refer to TCLs therefore must be
calculated using the minimum TCL that is possible under the respective circumstances.
The actual minimum value for TCL depends on the jitter of the PLL. As the PLL is
constantly adjusting its output frequency so it corresponds to the applied input frequency
(crystal or oscillator) the relative deviation for periods of more than one TCL is lower than
for one single TCL (see formula and Figure 12).
For a period of
deviation D

(

N × TCL)

where

N

N = number of consecutive TCLs and 1 ≤ N ≤ 40.

So for a period of 3 TCLs @ 25 MHz (i.e.
and (3TCL)

min

N × TCL the minimum value is computed using the corresponding

:

= N × TCL

min

= 3TCL

- 1.288 ns = 58.7 ns (@ f

NOM

- DN; DN [ns] = ±(13.3 + N × 6.3)/f

NOM

N = 3): D

= (13.3 + 3 × 6.3)/25 = 1.288 ns,

3

= 25 MHz).

CPU

CPU

[MHz],

This is especially important for bus cycles using waitstates and e.g. for the operation of
timers, serial interfaces, etc. For all slower operations and longer periods (e.g. pulse train
generation or measurement, lower baudrates, etc.) the deviation caused by the PLL jitter
is neglectible.

Note: For all periods longer than 40 TCL the N = 40 value can be used (see Figure 12).

Max. jitter D

ns

±30

±26.5

±20

±10

±1

N

This approximated formula is valid for

<

<

N 40 and 10 MHz f

1

–

–

110 20 40

<

–

CPU

<

25 MHz.

–

30

10 MHz

16 MHz

20 MHz

25 MHz

N

MCD04455

Figure 12 Approximated Maximum Accumulated PLL Jitter

Data Sheet 52 V2.0, 2001-05

Direct Drive

C164CI/SI

C164CL/SL

When direct drive is configured (CLKCFG = 011

) the on-chip phase locked loop is

B

disabled and the CPU clock is directly driven from the internal oscillator with the input
clock signal.

f

The frequency of

f

(i.e. the duration of an individual TCL) is defined by the duty cycle of the input clock

CPU

f

.

OSC

directly follows the frequency of f

CPU

so the high and low time of

OSC

The timings listed below that refer to TCLs therefore must be calculated using the
minimum TCL that is possible under the respective circumstances. This minimum value
can be calculated via the following formula:

min

= 1/f

TCL

For two consecutive TCLs the deviation caused by the duty cycle of
so the duration of 2TCL is always 1/

OSC

× DC

min

(DC = duty cycle)

f

. The minimum value TCL

OSC

f

is compensated

OSC

therefore has to

min

be used only once for timings that require an odd number of TCLs (1, 3, …). Timings that

f

require an even number of TCLs (2, 4, …) may use the formula 2TCL = 1/

OSC

.

Data Sheet 53 V2.0, 2001-05

AC Characteristics External Clock Drive XTAL1

(Operating Conditions apply)

Table 12 External Clock Drive Characteristics

C164CI/SI

C164CL/SL

Parameter Symbol Direct Drive

1:1

Prescaler

2:1

PLL

1:N

Unit

min. max. min. max. min. max.

Oscillator period

High time

Low time

Rise time

Fall time

1)

The minimum and maximum oscillator periods for PLL operation depend on the selected CPU clock generation
mode. Please see respective table above.

2)

The clock input signal must reach the defined levels V

3)

The minimum high and low time refers to a duty cycle of 50%. The maximum operating freqency (f
drive mode depends on the duty cycle of the clock input signal.

2)

2)

2)

2)

t

OSC

t

1

t

2

t

3

t

4

SR 40 – 20 – 60

SR 20

SR 20

3)

3)

– 6 – 10 – ns

– 6 – 10 – ns

SR – 8 – 5 – 10 ns

SR – 8 – 5 – 10 ns

and V

IL2

t

1

t

IH2

3

.

1)

t

4

500

1)

CPU

ns

) in direct

V

VDD0.5

t

2

t

OSC

IH2

V

IL

MCT02534

Figure 13 External Clock Drive XTAL1

Note: If the on-chip oscillator is used together with a crystal, the oscillator frequency is

limited to a range of 4 MHz to 16 MHz.
It is strongly recommended to measure the oscillation allowance (or margin) in the
final target system (layout) to determine the optimum parameters for the oscillator
operation. Please refer to the limits specified by the crystal supplier.
When driven by an external clock signal it will accept the specified frequency
range. Operation at lower input frequencies is possible but is guaranteed by
design only (not 100% tested).

Data Sheet 54 V2.0, 2001-05

C164CL/SL

A/D Converter Characteristics

(Operating Conditions apply)

Table 13 A/D Converter Characteristics

Parameter Symbol Limit Values Unit Test

Conditions

1)

Analog reference supply V

AREF

min. max.

SR 4.0 VDD + 0.1 V

C164CI/SI

Analog reference ground V

Analog input voltage range

Basic clock frequency f

Conversion time t

Calibration time after reset t

V

BC

C

CAL

Total unadjusted error TUE CC – ±2LSB

Internal resistance of

R

reference voltage source

Internal resistance of analog

R

source

ADC input capacitance C

1)

TUE is tested at V
within the defined voltage range.
If the analog reference supply voltage exceeds the power supply voltage by up to 0.2 V
(i.e.

V

= VDD= +0.2 V) the maximum TUE is increased to ±3 LSB. This range is not 100% tested.

AREF

The specified TUE is guaranteed only if the absolute sum of input overload currents on Port 5 pins (see
specification) does not exceed 10 mA.
During the reset calibration sequence the maximum TUE may be

2)

V

may exceed V

AIN

these cases will be X000

3)

The limit values for f

4)

This parameter includes the sample time tS, the time for determining the digital result and the time to load the
result register with the conversion result.
Values for the basic clock
This parameter depends on the ADC control logic. It is not a real maximum value, but rather a fixum.

5)

During the reset calibration conversions can be executed (with the current accuracy). The time required for
these conversions is added to the total reset calibration time.

6)

During the conversion the ADC’s capacitance must be repeatedly charged or discharged. The internal
resistance of the reference voltage source must allow the capacitance to reach its respective voltage level
within each conversion step. The maximum internal resistance results from the programmed conversion
timing.

7)

Not 100% tested, guaranteed by design and characterization.

=5.0V, V

AREF

or V

AGND

or X3FFH, respectively.

H

must not be exceeded when selecting the CPU frequency and the ADCTC setting.

BC

t

BC

AGND

up to the absolute maximum ratings. However, the conversion result in

AREF

depend on programming and can be taken from Table 14.

SR VSS - 0.1 VSS + 0.2 V –

AGND

SR V

AIN

AGND

0.5 6.25 MHz

CC – 40 tBC +

CC – 3328 t

SR – tBC / 60

AREF

V

AREF

t

S

+ 2t

V

–

CPU

–

BC

kΩ tBC in [ns]

2)

3)

4)

t

CPU

5)

1)

= 1 / f

- 0.25

SR – tS / 450

ASRC

kΩ tS in [ns]

7)8)

- 0.25

CC – 33 pF

AIN

=0V, VDD= 4.9 V. It is guaranteed by design for all other voltages

±4 LSB.

7)

CPU

6)7)

I

OV

Data Sheet 55 V2.0, 2001-05

C164CI/SI

C164CL/SL

8)

During the sample time the input capacitance C
internal resistance of the analog source must allow the capacitance to reach its final voltage level within
After the end of the sample time
Values for the sample time

t

, changes of the analog input voltage have no effect on the conversion result.

S

t

depend on programming and can be taken from Table 14.

S

Sample time and conversion time of the C164CI’s A/D Converter are programmable.

Table 14 should be used to calculate the above timings.

f

The limit values for

must not be exceeded when selecting ADCTC.

BC

Table 14 A/D Converter Computation Table

can be charged/discharged by the external source. The

AIN

t

S

.

ADCON.15|14
(ADCTC)

00 f

01

10

11

A/D Converter
Basic Clock

/ 4 00 tBC × 8

CPU

f

/ 2 01 tBC × 16

CPU

f

/ 16 10 tBC × 32

CPU

f

/ 8 11 tBC × 64

CPU

Converter Timing Example:

Assumptions:

Basic clock
Sample time
Conversion time

f

CPU

f

BC

t

S

t

C

= 25 MHz (i.e. t

= f
= tBC × 8 = 1280 ns.
= tS + 40 tBC + 2 t

ADCON.13|12

f

BC

/4 = 6.25 MHz, i.e. tBC = 160 ns.

CPU

(ADSTC)

= 40 ns), ADCTC = ‘00’, ADSTC = ‘00’.

CPU

= (1280 + 6400 + 80) ns = 7.8 µs.

CPU

Sample time

t

S

Data Sheet 56 V2.0, 2001-05

Testing Waveforms

C164CI/SI

C164CL/SL

2.4 V

1.8 V

0.8 V

0.45 V

AC inputs during testing are driven at 2.4 V for a logic ’1’ and 0.45 V for a logic ’0’.

V

Timing measurements are made at

min for a logic ’1’ and

IH

Figure 14 Input Output Waveforms

+ 0.1 V

V

Load

- 0.1 V

V

Load

Test Points

Timing

Reference

Points

1.8 V

0.8 V

V

max for a logic ’0’.

IL

V

OH

V

OL

MCA04414

- 0.1 V

+ 0.1 V

For timing purposes a port pin is no longer floating when a 100 mV change from load voltage occurs,
but begins to float when a 100 mV change from the loaded

V

/

V

OH

level occurs (

OL

I

I

/ = 20 mA).

OH OL

MCA00763

Figure 15 Float Waveforms

Data Sheet 57 V2.0, 2001-05

C164CI/SI

C164CL/SL

Memory Cycle Variables

The timing tables below use three variables which are derived from the BUSCONx
registers and represent the special characteristics of the programmed memory cycle.
The following table describes, how these variables are to be computed.

Table 15 Memory Cycle Variables

Description Symbol Values

ALE Extension

Memory Cycle Time Waitstates

Memory Tristate Time

t

A

t

C

t

F

TCL × <ALECTL>

2TCL × (15 - <MCTC>)

2TCL × (1 - <MTTC>)

Note: Please respect the maximum operating frequency of the respective derivative.

AC Characteristics

Multiplexed Bus

(Operating Conditions apply)

t

ALE cycle time = 6 TCL + 2

Parameter Symbol Max. CPU Clock

+ tC + tF (120 ns at 25 MHz CPU clock without waitstates)

A

= 25 MHz

Variable CPU Clock

1 / 2TCL = 1 to 25 MHz

Unit

min. max. min. max.

t

ALE high time

Address setup to ALE

CC 10 + t

5

t

CC 4 + t

6

A

– TCL - 10

A

– TCL - 16

t

+

+ t

– ns

A

– ns

A

Address hold after ALE

ALE falling edge to RD

(with RW-delay)

WR

ALE falling edge to RD

(no RW-delay)

WR

Address float after RD

CC 10 + t

7

,

t

CC 10 + t

8

,

t

CC -10 + tA– -10 + t

9

,

t

CC – 6 – 6ns

10

– TCL - 10

A

– TCL - 10

A

– ns

t

+

A

– ns

t

+

A

A

– ns

t

WR (with RW-delay)

,

t

Address float after RD

(no RW-delay)

WR

, WR low time

RD
(with RW-delay)

Data Sheet 58 V2.0, 2001-05

CC – 26 – TCL + 6 ns

11

t

CC 30 + t

12

– 2TCL - 10

C

+

– ns

t

C

Multiplexed Bus (cont’d)
(Operating Conditions apply)
ALE cycle time = 6 TCL + 2

t

C164CI/SI

C164CL/SL

+ tC + tF (120 ns at 25 MHz CPU clock without waitstates)

A

Parameter Symbol Max. CPU Clock

= 25 MHz

min. max. min. max.

RD, WR low time

t

CC 50 + t

13

– 3TCL - 10

C

(no RW-delay)

to valid data in

RD

t

SR – 20 + t

14

C

(with RW-delay)

to valid data in

RD

t

SR – 40 + t

15

C

(no RW-delay)

t

ALE low to valid data in

Address to valid data in

Data hold after RD

SR – 40 + t

16

+ t

t

SR – 50 + 2tA

17

+

t

SR 0 – 0 – ns

18

A

C

t

C

rising edge

t

Data float after RD

SR – 26 + t

19

F

Variable CPU Clock

1 / 2TCL = 1 to 25 MHz

– ns

t

+

C

– 2TCL - 20

t

+

C

– 3TCL - 20

+ t

C

– 3TCL - 20

t

+ t

+

A

C

– 4TCL - 30

2t

+ t

+

A

C

– 2TCL - 14

+ t

F

Unit

ns

ns

ns

ns

ns

Data valid to WR

Data hold after WR

ALE rising edge after RD
WR

Address hold after RD

,

WR

ALE falling edge to CS

CS

low to Valid Data In

hold after RD, WR

CS

1)

1)

ALE fall. edge to RdCS
WrCS (with RW delay)

1)

,

t

CC 20 + t

22

t

CC 26 + t

23

,

t

CC 26 + t

25

t

CC 26 + t

27

t

CC -4 - t

38

t

SR – 40

39

t

CC 46 + t

40

t

CC 16 + t

42

– 2TCL - 20

C

– 2TCL - 14

F

– 2TCL - 14

F

– 2TCL - 14

F

10 - t

A

F

A

A

t

+

C

+ 2t

A

– 3TCL - 14

– TCL - 4

– ns

t

+

C

– ns

t

+

F

– ns

t

+

F

– ns

+ t

F

-4 - t

A

10 - t

A

– 3TCL - 20

t

+ 2t

+

C

A

– ns

t

+

F

– ns

+ t

A

ns

ns

Data Sheet 59 V2.0, 2001-05

Multiplexed Bus (cont’d)
(Operating Conditions apply)
ALE cycle time = 6 TCL + 2

t

C164CI/SI

C164CL/SL

+ tC + tF (120 ns at 25 MHz CPU clock without waitstates)

A

Parameter Symbol Max. CPU Clock

= 25 MHz

min. max. min. max.

ALE fall. edge to RdCS,
WrCS

(no RW delay)

Address float after RdCS
WrCS

(with RW delay)

Address float after RdCS

t

CC -4 + t

43

,

t

CC – 0 – 0ns

44

,

t

CC – 20 – TCL ns

45

– -4

A

WrCS (no RW delay)

RdCS

to Valid Data In

t

SR – 16 + t

46

C

(with RW delay)

RdCS

to Valid Data In

t

SR – 36 + t

47

C

(no RW delay)

RdCS

, WrCS Low Time

t

CC 30 + t

48

– 2TCL - 10

C

(with RW delay)

RdCS

, WrCS Low Time

t

CC 50 + t

49

– 3TCL - 10

C

(no RW delay)

Variable CPU Clock

1 / 2TCL = 1 to 25 MHz

– ns

t

+

A

– 2TCL - 24

t

+

C

– 3TCL - 24

t

+

C

– ns

t

+

C

– ns

+ t

C

Unit

ns

ns

t

Data valid to WrCS

Data hold after RdCS

Data float after RdCS

Address hold after
RdCS

, WrCS

Data hold after WrCS

1)

These parameters refer to the latched chip select signals (CSxL). The early chip select signals (CSxE) are
specified together with the address and signal BHE

CC 26 + t

50

t

SR 0 – 0 – ns

51

t

SR – 20 + t

52

t

CC 20 + t

54

t

CC 20 + t

56

– 2TCL - 14

C

F

– 2TCL - 20

F

– 2TCL - 20

F

(see figures below).

– ns

t

+

C

– 2TCL - 20

t

+

F

– ns

t

+

F

– ns

t

+

F

ns

Data Sheet 60 V2.0, 2001-05

C164CI/SI

C164CL/SL

ALE

CSxL

A21-A16

(A15-A8)

, CSxE

BHE

Read Cycle

BUS

RD

t

5

t

6

Address

t

16

t

38

t

39

t

17

t

25

t

40

t

27

Address

t

7

t

54

t

19

t

18

Data In

t

t

8

10

t

14

RdCSx

Write Cycle

BUS

WR,

,

WRL

WRH

WrCSx

t

44

12

t

46

t

48

t

t

42

t

51

t

52

t

23

Data OutAddress

t

t

t

8

t

42

10

t

44

t

22

t

12

t

50

t

48

56

Figure 16 External Memory Cycle:

Multiplexed Bus, With Read/Write Delay, Normal ALE

Data Sheet 61 V2.0, 2001-05

C164CI/SI

C164CL/SL

ALE

CSxL

A21-A16

(A15-A8)

, CSxE

BHE

Read Cycle

BUS

RD

t

5

t

38

t

16

t

39

t

17

t

25

t

40

t

27

Address

t

6

t

7

t

54

t

19

t

18

Data InAddress

t

t

8

10

t

14

RdCSx

Write Cycle

BUS

WR,

,

WRL

WRH

WrCSx

t

t

t

42

4

12

t

46

t

48

t

51

t

52

t

23

Data OutAddress

t

t

t

8

t

42

10

t

44

t

22

t

12

t

50

t

48

56

Figure 17 External Memory Cycle:

Multiplexed Bus, With Read/Write Delay, Extended ALE

Data Sheet 62 V2.0, 2001-05

C164CI/SI

C164CL/SL

ALE

CSxL

A21-A16

(A15-A8)

, CSxE

BHE

Read Cycle

BUS

RD

t

5

t

38

t

16

t

39

t

17

Address

t

6

t

7

Address Data In

t

9

t

11

t

15

t

25

t

40

t

27

t

54

t

19

t

18

RdCSx

Write Cycle

BUS

WR,

,

WRL

WRH

WrCSx

t

t

43

t

45

13

t

47

t

49

t

51

t

52

t

23

Data OutAddress

t

t

9

t

43

t

11

t

45

t

22

t

13

t

50

t

49

56

Figure 18 External Memory Cycle:

Multiplexed Bus, No Read/Write Delay, Normal ALE

Data Sheet 63 V2.0, 2001-05

C164CI/SI

C164CL/SL

ALE

CSxL

A21-A16

(A15-A8)

, CSxE

BHE

Read Cycle

BUS

RD

t

5

t

38

t

16

t

39

t

17

t

25

t

40

t

27

Address

t

6

t

7

t

54

t

19

t

18

Data InAddress

t

9

t

11

t

15

RdCSx

Write Cycle

BUS

WR,

,

WRL

WRH

WrCSx

t

t

t

43

9

43

t

13

t

45

t

47

t

49

t

51

t

52

t

23

Data OutAddress

t

56

t

11

t

45

t

22

t

13

t

50

t

49

Figure 19 External Memory Cycle:

Multiplexed Bus, No Read/Write Delay, Extended ALE

Data Sheet 64 V2.0, 2001-05

AC Characteristics

Demultiplexed Bus

(Operating Conditions apply)
ALE cycle time = 4 TCL + 2

C164CI/SI

C164CL/SL

t

+ tC + tF (80 ns at 25 MHz CPU clock without waitstates)

A

Parameter Symbol Max. CPU Clock

= 25 MHz

min. max. min. max.

ALE high time

Address setup to ALE

ALE falling edge to RD

(with RW-delay)

WR

ALE falling edge to RD

t

CC 10 + t

5

t

CC 4 + t

6

,

t

CC 10 + t

8

,

t

CC -10 + tA– -10

9

A

– TCL - 10

A

– TCL - 16

– TCL - 10

A

WR (no RW-delay)

, WR low time

RD

t

CC 30 + t

12

– 2TCL - 10

C

(with RW-delay)

, WR low time

RD

t

CC 50 + t

13

– 3TCL - 10

C

(no RW-delay)

to valid data in

RD

t

SR – 20 + t

14

C

(with RW-delay)

Variable CPU Clock

1 / 2TCL = 1 to 25 MHz

– ns

t

+

A

– ns

t

+

A

– ns

t

+

A

– ns

+ t

A

– ns

t

+

C

– ns

t

+

C

– 2TCL - 20

t

+

C

Unit

ns

to valid data in

RD
(no RW-delay)

ALE low to valid data in

Address to valid data in

Data hold after RD

t

SR – 40 + t

15

t

SR – 40 +

16

t

+ t

A

t

SR – 50 +

17

t

+ t

2

A

t

SR 0 – 0 – ns

18

– 3TCL - 20

C

– 3TCL - 20

C

– 4TCL - 30

C

t

+

C

t

+ t

+

A

2t

+

A

+ t

ns

ns

C

ns

C

rising edge

Data float after RD

rising

edge (with RW-delay1))

Data float after RD
edge (no RW-delay

Data Sheet 65 V2.0, 2001-05

rising

1)

)

t

SR – 26 +

20

t

SR – 10 +

21

2tA + t

t

+ t

2

A

– 2TCL - 14

1)

F

+ 22t
+ t

– TCL - 10

1)

F

+
+ t

F

22t

F

1)

1)

ns

A

ns

A

Demultiplexed Bus (cont’d)
(Operating Conditions apply)
ALE cycle time = 4 TCL + 2

C164CI/SI

C164CL/SL

t

+ tC + tF (80 ns at 25 MHz CPU clock without waitstates)

A

Parameter Symbol Max. CPU Clock

= 25 MHz

min. max. min. max.

Data valid to WR t

Data hold after WR

ALE rising edge after RD

,

CC 20 + t

22

t

CC 10 + t

24

t

CC -10 + tF– -10 + t

26

– 2TCL - 20

C

– TCL - 10

F

WR

2)

t

Address hold after WR

ALE falling edge to CS

low to Valid Data In

CS

hold after RD, WR

CS

3)

3)

3)

ALE falling edge to RdCS
WrCS

(with RW-delay)

CC 0 + t

28

t

CC -4 - t

38

t

SR – 40 +

39

t

CC 6 + t

41

,

t

CC 16 + t

42

F

F

– 0 + t

10 - t

A

tC + 2t

A

A

– TCL - 14

– TCL - 4

A

Variable CPU Clock

1 / 2TCL = 1 to 25 MHz

– ns

t

+

C

– ns

t

+

F

– ns

– ns

10 - t

A

-4 - t

F

F

A

– 3TCL - 20

+ tC + 2t

A

– ns

t

+

F

– ns

t

+

A

Unit

ns

ns

ALE falling edge to RdCS
WrCS

RdCS

(no RW-delay)

to Valid Data In

(with RW-delay)

RdCS

to Valid Data In

(no RW-delay)

RdCS

, WrCS Low Time

(with RW-delay)

RdCS

, WrCS Low Time

(no RW-delay)

Data valid to WrCS

Data hold after RdCS

Data float after RdCS
(with RW-delay)

1)

,

t

CC -4 + t

43

t

SR – 16 + t

46

t

SR – 36 + t

47

t

CC 30 + t

48

t

CC 50 + t

49

t

CC 26 + t

50

t

SR 0 – 0 – ns

51

t

SR – 20 + t

53

– -4

A

C

C

– 2TCL - 10

C

– 3TCL - 10

C

– 2TCL - 14

C

F

– ns

t

+

A

– 2TCL - 24

+ t

C

– 3TCL - 24

t

+

C

– ns

t

+

C

– ns

t

+

C

– ns

+ t

C

– 2TCL - 20

2t

+ t

+

A

F

ns

ns

ns

1)

Data Sheet 66 V2.0, 2001-05

Demultiplexed Bus (cont’d)
(Operating Conditions apply)
ALE cycle time = 4 TCL + 2

C164CI/SI

C164CL/SL

t

+ tC + tF (80 ns at 25 MHz CPU clock without waitstates)

A

Parameter Symbol Max. CPU Clock

= 25 MHz

Variable CPU Clock

1 / 2TCL = 1 to 25 MHz

min. max. min. max.

Data float after RdCS
(no RW-delay)

1)

Address hold after
RdCS

, WrCS

Data hold after WrCS

1)

RW-delay and tA refer to the next following bus cycle (including an access to an on-chip X-Peripheral).

2)

Read data are latched with the same clock edge that triggers the address change and the rising RD edge.
Therefore address changes before the end of RD

3)

These parameters refer to the latched chip select signals (CSxL). The early chip select signals (CSxE) are
specified together with the address and signal BHE

t

SR – 0 + t

68

t

CC -6 + t

55

t

CC 6 + t

57

have no impact on read cycles.

F

– -6 + t

F

F

– TCL - 14 +

(see figures below).

– TCL - 20

2t

+ t

+

A

F

– ns

– ns

t

F

1)

F

Unit

ns

Data Sheet 67 V2.0, 2001-05

C164CI/SI

C164CL/SL

ALE

CSxL

A21-A16

A15-A0

, CSxE

BHE

Read Cycle

BUS

(D15-D8)

D7-D0

RD

t

5

t

38

t

16

t

39

t

17

t

t

26

28

t

41

Address

t

6

t

55

t

20

t

18

Data In

t

8

t

14

RdCSx

Write Cycle

BUS

(D15-D8)

D7-D0

WR,

WRL

WRH

WrCSx

t

12

t

42

t

46

t

48

t

51

t

53

t

24

Data Out

t

57

t

8

t

22

,

t

12

t

42

t

50

t

48

Figure 20 External Memory Cycle:

Demultiplexed Bus, With Read/Write Delay, Normal ALE

Data Sheet 68 V2.0, 2001-05

C164CI/SI

C164CL/SL

ALE

CSxL

A21-A16

A15-A0

,

BHE

CSxE

Read Cycle

BUS

(D15-D8)

D7-D0

RD

t

5

t

38

t

16

t

39

t

17

t

26

t

41

t

28

Address

t

6

t

55

t

20

t

18

Data In

t

8

t

14

RdCSx

Write Cycle

BUS

(D15-D8)

D7-D0

WR,

,

WRL

WRH

WrCSx

t

12

t

42

t

46

t

48

t

51

t

53

t

24

Data Out

t

57

t

8

t

42

t

22

t

12

t

50

t

48

Figure 21 External Memory Cycle:

Demultiplexed Bus, With Read/Write Delay, Extended ALE

Data Sheet 69 V2.0, 2001-05

C164CI/SI

C164CL/SL

ALE

CSxL

A21-A16

A15-A0

, CSxE

BHE

Read Cycle

BUS

(D15-D8)

D7-D0

RD

t

5

t

38

t

16

t

39

t

17

t

t

26

28

t

41

Address

t

6

t

55

t

21

t

18

Data In

t

9

t

15

RdCSx

Write Cycle

BUS

(D15-D8)

D7-D0

WR,

,WRH

WRL

WrCSx

t

t

43

13

t

47

t

49

t

51

t

68

t

24

Data Out

t

t

9

t

43

t

22

t

13

t

50

t

49

57

Figure 22 External Memory Cycle:

Demultiplexed Bus, No Read/Write Delay, Normal ALE

Data Sheet 70 V2.0, 2001-05

C164CI/SI

C164CL/SL

ALE

CSxL

A21-A16

A15-A0

, CSxE

BHE

Read Cycle

BUS

(D15-D8)

D7-D0

RD

t

5

t

38

t

16

t

39

t

17

t

26

t

41

t

28

Address

t

6

t

55

t

21

t

18

Data In

t

9

t

15

RdCSx

Write Cycle

BUS

(D15-D8)

D7-D0

WR,

, WRH

WRL

WrCSx

t

13

t

43

t

47

t

49

t

51

t

68

t

24

Data Out

t

57

t

t

13

49

t

22

t

50

t

9

t

43

Figure 23 External Memory Cycle:

Demultiplexed Bus, No Read/Write Delay, Extended ALE

Data Sheet 71 V2.0, 2001-05

AC Characteristics

CLKOUT

(Operating Conditions apply)

C164CI/SI

C164CL/SL

Parameter Symbol Max. CPU Clock

= 25 MHz

min. max. min. max.

t

CLKOUT cycle time

CLKOUT high time

CLKOUT low time

CLKOUT rise time

CLKOUT fall time

CLKOUT rising edge to

CC 40 40 2TCL 2TCL ns

29

t

CC 14 – TCL - 6 – ns

30

t

CC 10 – TCL - 10 – ns

31

t

CC – 4 – 4ns

32

t

CC – 4 – 4ns

33

t

CC 0 + t

34

A

10 + t

A

ALE falling edge

1)

t

29

CLKOUT

Running cycle

t

32

t

30

t

34

t

33

t

31

Variable CPU Clock

1 / 2TCL = 1 to 25 MHz

0 + t

A

MUX/Tristate

10 + t

3)

Unit

A

ns

ALE

Command

, WR

RD

2)

4)

Figure 24 CLKOUT Timing

Notes

1)

Cycle as programmed, including MCTC waitstates (Example shows 0 MCTC WS).

2)

The leading edge of the respective command depends on RW-delay.

3)

Multiplexed bus modes have a MUX waitstate added after a bus cycle, and an additional MTTC waitstate may
be inserted here.
For a multiplexed bus with MTTC waitstate this delay is 2 CLKOUT cycles, for a demultiplexed bus without
MTTC waitstate this delay is zero.

4)

The next external bus cycle may start here.

Data Sheet 72 V2.0, 2001-05

C164CI/SI

C164CL/SL

External XRAM Access

If XPER-Share mode is enabled the on-chip XRAM of the C164CI can be accessed
(during hold states) by an external master like an asynchronous SRAM.

Table 16 XRAM Access Timing (Operating Conditions apply)

Parameter Symbol Limit Values Unit

min. max.

Address setup time before RD

Address hold time after RD

Data turn on delay after RD

/WR falling edge t

/WR rising edge t

falling edge

Data output valid delay after address latched

Data turn off delay after RD

Write data setup time before WR

Write data hold time after WR

pulse width t

WR

WR

signal recovery time t

Address

Command
(RD, WR)

rising edge t

rising edge

rising edge t

t

40

SR 4 – ns

40

SR 0 – ns

41

t

CC 2 – ns

42

t

CC – 37 ns

43

Read

CC 0 10 ns

44

t

SR 10 – ns

45

SR 1 – ns

46

Write

t

47

SR 18 – ns

47

48

SR t

t

45

40

t

41

t

48

t

46

– ns

Write Data

t

43

Read Data

t

42

t

44

MCT04423

Figure 25 External Access to the XRAM

Data Sheet 73 V2.0, 2001-05

Package Outlines

P-MQFP-80-7

(Plastic Metric Quad Flat Package)

C164CI/SI

C164CL/SL

Sorts of Packing

Package outlines for tubes, trays etc. are contained in our
Data Book “Package Information”.

SMD = Surface Mounted Device

Data Sheet 74 V2.0, 2001-05

Dimensions in mm

GPM05249

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